dhd_sdio.c 122 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/types.h>
  17. #include <linux/kernel.h>
  18. #include <linux/kthread.h>
  19. #include <linux/printk.h>
  20. #include <linux/pci_ids.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/sched.h>
  24. #include <linux/mmc/sdio.h>
  25. #include <linux/mmc/sdio_func.h>
  26. #include <linux/mmc/card.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/firmware.h>
  29. #include <linux/module.h>
  30. #include <asm/unaligned.h>
  31. #include <defs.h>
  32. #include <brcmu_wifi.h>
  33. #include <brcmu_utils.h>
  34. #include <brcm_hw_ids.h>
  35. #include <soc.h>
  36. #include "sdio_host.h"
  37. #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
  38. #ifdef BCMDBG
  39. #define BRCMF_TRAP_INFO_SIZE 80
  40. #define CBUF_LEN (128)
  41. struct rte_log_le {
  42. __le32 buf; /* Can't be pointer on (64-bit) hosts */
  43. __le32 buf_size;
  44. __le32 idx;
  45. char *_buf_compat; /* Redundant pointer for backward compat. */
  46. };
  47. struct rte_console {
  48. /* Virtual UART
  49. * When there is no UART (e.g. Quickturn),
  50. * the host should write a complete
  51. * input line directly into cbuf and then write
  52. * the length into vcons_in.
  53. * This may also be used when there is a real UART
  54. * (at risk of conflicting with
  55. * the real UART). vcons_out is currently unused.
  56. */
  57. uint vcons_in;
  58. uint vcons_out;
  59. /* Output (logging) buffer
  60. * Console output is written to a ring buffer log_buf at index log_idx.
  61. * The host may read the output when it sees log_idx advance.
  62. * Output will be lost if the output wraps around faster than the host
  63. * polls.
  64. */
  65. struct rte_log_le log_le;
  66. /* Console input line buffer
  67. * Characters are read one at a time into cbuf
  68. * until <CR> is received, then
  69. * the buffer is processed as a command line.
  70. * Also used for virtual UART.
  71. */
  72. uint cbuf_idx;
  73. char cbuf[CBUF_LEN];
  74. };
  75. #endif /* BCMDBG */
  76. #include <chipcommon.h>
  77. #include "dhd.h"
  78. #include "dhd_bus.h"
  79. #include "dhd_proto.h"
  80. #include "dhd_dbg.h"
  81. #include <bcmchip.h>
  82. #define TXQLEN 2048 /* bulk tx queue length */
  83. #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
  84. #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
  85. #define PRIOMASK 7
  86. #define TXRETRIES 2 /* # of retries for tx frames */
  87. #define BRCMF_RXBOUND 50 /* Default for max rx frames in
  88. one scheduling */
  89. #define BRCMF_TXBOUND 20 /* Default for max tx frames in
  90. one scheduling */
  91. #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
  92. #define MEMBLOCK 2048 /* Block size used for downloading
  93. of dongle image */
  94. #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
  95. biggest possible glom */
  96. #define BRCMF_FIRSTREAD (1 << 6)
  97. /* SBSDIO_DEVICE_CTL */
  98. /* 1: device will assert busy signal when receiving CMD53 */
  99. #define SBSDIO_DEVCTL_SETBUSY 0x01
  100. /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
  101. #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
  102. /* 1: mask all interrupts to host except the chipActive (rev 8) */
  103. #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
  104. /* 1: isolate internal sdio signals, put external pads in tri-state; requires
  105. * sdio bus power cycle to clear (rev 9) */
  106. #define SBSDIO_DEVCTL_PADS_ISO 0x08
  107. /* Force SD->SB reset mapping (rev 11) */
  108. #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
  109. /* Determined by CoreControl bit */
  110. #define SBSDIO_DEVCTL_RST_CORECTL 0x00
  111. /* Force backplane reset */
  112. #define SBSDIO_DEVCTL_RST_BPRESET 0x10
  113. /* Force no backplane reset */
  114. #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
  115. /* SBSDIO_FUNC1_CHIPCLKCSR */
  116. /* Force ALP request to backplane */
  117. #define SBSDIO_FORCE_ALP 0x01
  118. /* Force HT request to backplane */
  119. #define SBSDIO_FORCE_HT 0x02
  120. /* Force ILP request to backplane */
  121. #define SBSDIO_FORCE_ILP 0x04
  122. /* Make ALP ready (power up xtal) */
  123. #define SBSDIO_ALP_AVAIL_REQ 0x08
  124. /* Make HT ready (power up PLL) */
  125. #define SBSDIO_HT_AVAIL_REQ 0x10
  126. /* Squelch clock requests from HW */
  127. #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
  128. /* Status: ALP is ready */
  129. #define SBSDIO_ALP_AVAIL 0x40
  130. /* Status: HT is ready */
  131. #define SBSDIO_HT_AVAIL 0x80
  132. #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
  133. #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
  134. #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
  135. #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
  136. #define SBSDIO_CLKAV(regval, alponly) \
  137. (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
  138. /* direct(mapped) cis space */
  139. /* MAPPED common CIS address */
  140. #define SBSDIO_CIS_BASE_COMMON 0x1000
  141. /* maximum bytes in one CIS */
  142. #define SBSDIO_CIS_SIZE_LIMIT 0x200
  143. /* cis offset addr is < 17 bits */
  144. #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
  145. /* manfid tuple length, include tuple, link bytes */
  146. #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
  147. /* intstatus */
  148. #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
  149. #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
  150. #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
  151. #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
  152. #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
  153. #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
  154. #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
  155. #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
  156. #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
  157. #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
  158. #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
  159. #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
  160. #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
  161. #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
  162. #define I_PC (1 << 10) /* descriptor error */
  163. #define I_PD (1 << 11) /* data error */
  164. #define I_DE (1 << 12) /* Descriptor protocol Error */
  165. #define I_RU (1 << 13) /* Receive descriptor Underflow */
  166. #define I_RO (1 << 14) /* Receive fifo Overflow */
  167. #define I_XU (1 << 15) /* Transmit fifo Underflow */
  168. #define I_RI (1 << 16) /* Receive Interrupt */
  169. #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
  170. #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
  171. #define I_XI (1 << 24) /* Transmit Interrupt */
  172. #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
  173. #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
  174. #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
  175. #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
  176. #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
  177. #define I_SRESET (1 << 30) /* CCCR RES interrupt */
  178. #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
  179. #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
  180. #define I_DMA (I_RI | I_XI | I_ERRORS)
  181. /* corecontrol */
  182. #define CC_CISRDY (1 << 0) /* CIS Ready */
  183. #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
  184. #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
  185. #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
  186. #define CC_XMTDATAAVAIL_MODE (1 << 4)
  187. #define CC_XMTDATAAVAIL_CTRL (1 << 5)
  188. /* SDA_FRAMECTRL */
  189. #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
  190. #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
  191. #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
  192. #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
  193. /* HW frame tag */
  194. #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
  195. /* Total length of frame header for dongle protocol */
  196. #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
  197. #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
  198. /*
  199. * Software allocation of To SB Mailbox resources
  200. */
  201. /* tosbmailbox bits corresponding to intstatus bits */
  202. #define SMB_NAK (1 << 0) /* Frame NAK */
  203. #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
  204. #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
  205. #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
  206. /* tosbmailboxdata */
  207. #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
  208. /*
  209. * Software allocation of To Host Mailbox resources
  210. */
  211. /* intstatus bits */
  212. #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
  213. #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
  214. #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
  215. #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
  216. /* tohostmailboxdata */
  217. #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
  218. #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
  219. #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
  220. #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
  221. #define HMB_DATA_FCDATA_MASK 0xff000000
  222. #define HMB_DATA_FCDATA_SHIFT 24
  223. #define HMB_DATA_VERSION_MASK 0x00ff0000
  224. #define HMB_DATA_VERSION_SHIFT 16
  225. /*
  226. * Software-defined protocol header
  227. */
  228. /* Current protocol version */
  229. #define SDPCM_PROT_VERSION 4
  230. /* SW frame header */
  231. #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
  232. #define SDPCM_CHANNEL_MASK 0x00000f00
  233. #define SDPCM_CHANNEL_SHIFT 8
  234. #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
  235. #define SDPCM_NEXTLEN_OFFSET 2
  236. /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
  237. #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
  238. #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
  239. #define SDPCM_DOFFSET_MASK 0xff000000
  240. #define SDPCM_DOFFSET_SHIFT 24
  241. #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
  242. #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
  243. #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
  244. #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
  245. #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
  246. /* logical channel numbers */
  247. #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
  248. #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
  249. #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
  250. #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
  251. #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
  252. #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
  253. #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
  254. /*
  255. * Shared structure between dongle and the host.
  256. * The structure contains pointers to trap or assert information.
  257. */
  258. #define SDPCM_SHARED_VERSION 0x0002
  259. #define SDPCM_SHARED_VERSION_MASK 0x00FF
  260. #define SDPCM_SHARED_ASSERT_BUILT 0x0100
  261. #define SDPCM_SHARED_ASSERT 0x0200
  262. #define SDPCM_SHARED_TRAP 0x0400
  263. /* Space for header read, limit for data packets */
  264. #define MAX_HDR_READ (1 << 6)
  265. #define MAX_RX_DATASZ 2048
  266. /* Maximum milliseconds to wait for F2 to come up */
  267. #define BRCMF_WAIT_F2RDY 3000
  268. /* Bump up limit on waiting for HT to account for first startup;
  269. * if the image is doing a CRC calculation before programming the PMU
  270. * for HT availability, it could take a couple hundred ms more, so
  271. * max out at a 1 second (1000000us).
  272. */
  273. #undef PMU_MAX_TRANSITION_DLY
  274. #define PMU_MAX_TRANSITION_DLY 1000000
  275. /* Value for ChipClockCSR during initial setup */
  276. #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
  277. SBSDIO_ALP_AVAIL_REQ)
  278. /* Flags for SDH calls */
  279. #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
  280. /* sbimstate */
  281. #define SBIM_IBE 0x20000 /* inbanderror */
  282. #define SBIM_TO 0x40000 /* timeout */
  283. #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
  284. #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
  285. /* sbtmstatelow */
  286. /* reset */
  287. #define SBTML_RESET 0x0001
  288. /* reject field */
  289. #define SBTML_REJ_MASK 0x0006
  290. /* reject */
  291. #define SBTML_REJ 0x0002
  292. /* temporary reject, for error recovery */
  293. #define SBTML_TMPREJ 0x0004
  294. /* Shift to locate the SI control flags in sbtml */
  295. #define SBTML_SICF_SHIFT 16
  296. /* sbtmstatehigh */
  297. #define SBTMH_SERR 0x0001 /* serror */
  298. #define SBTMH_INT 0x0002 /* interrupt */
  299. #define SBTMH_BUSY 0x0004 /* busy */
  300. #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
  301. /* Shift to locate the SI status flags in sbtmh */
  302. #define SBTMH_SISF_SHIFT 16
  303. /* sbidlow */
  304. #define SBIDL_INIT 0x80 /* initiator */
  305. /* sbidhigh */
  306. #define SBIDH_RC_MASK 0x000f /* revision code */
  307. #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
  308. #define SBIDH_RCE_SHIFT 8
  309. #define SBCOREREV(sbidh) \
  310. ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
  311. ((sbidh) & SBIDH_RC_MASK))
  312. #define SBIDH_CC_MASK 0x8ff0 /* core code */
  313. #define SBIDH_CC_SHIFT 4
  314. #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
  315. #define SBIDH_VC_SHIFT 16
  316. /*
  317. * Conversion of 802.1D priority to precedence level
  318. */
  319. static uint prio2prec(u32 prio)
  320. {
  321. return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
  322. (prio^2) : prio;
  323. }
  324. /*
  325. * Core reg address translation.
  326. * Both macro's returns a 32 bits byte address on the backplane bus.
  327. */
  328. #define CORE_CC_REG(base, field) \
  329. (base + offsetof(struct chipcregs, field))
  330. #define CORE_BUS_REG(base, field) \
  331. (base + offsetof(struct sdpcmd_regs, field))
  332. #define CORE_SB(base, field) \
  333. (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
  334. /* core registers */
  335. struct sdpcmd_regs {
  336. u32 corecontrol; /* 0x00, rev8 */
  337. u32 corestatus; /* rev8 */
  338. u32 PAD[1];
  339. u32 biststatus; /* rev8 */
  340. /* PCMCIA access */
  341. u16 pcmciamesportaladdr; /* 0x010, rev8 */
  342. u16 PAD[1];
  343. u16 pcmciamesportalmask; /* rev8 */
  344. u16 PAD[1];
  345. u16 pcmciawrframebc; /* rev8 */
  346. u16 PAD[1];
  347. u16 pcmciaunderflowtimer; /* rev8 */
  348. u16 PAD[1];
  349. /* interrupt */
  350. u32 intstatus; /* 0x020, rev8 */
  351. u32 hostintmask; /* rev8 */
  352. u32 intmask; /* rev8 */
  353. u32 sbintstatus; /* rev8 */
  354. u32 sbintmask; /* rev8 */
  355. u32 funcintmask; /* rev4 */
  356. u32 PAD[2];
  357. u32 tosbmailbox; /* 0x040, rev8 */
  358. u32 tohostmailbox; /* rev8 */
  359. u32 tosbmailboxdata; /* rev8 */
  360. u32 tohostmailboxdata; /* rev8 */
  361. /* synchronized access to registers in SDIO clock domain */
  362. u32 sdioaccess; /* 0x050, rev8 */
  363. u32 PAD[3];
  364. /* PCMCIA frame control */
  365. u8 pcmciaframectrl; /* 0x060, rev8 */
  366. u8 PAD[3];
  367. u8 pcmciawatermark; /* rev8 */
  368. u8 PAD[155];
  369. /* interrupt batching control */
  370. u32 intrcvlazy; /* 0x100, rev8 */
  371. u32 PAD[3];
  372. /* counters */
  373. u32 cmd52rd; /* 0x110, rev8 */
  374. u32 cmd52wr; /* rev8 */
  375. u32 cmd53rd; /* rev8 */
  376. u32 cmd53wr; /* rev8 */
  377. u32 abort; /* rev8 */
  378. u32 datacrcerror; /* rev8 */
  379. u32 rdoutofsync; /* rev8 */
  380. u32 wroutofsync; /* rev8 */
  381. u32 writebusy; /* rev8 */
  382. u32 readwait; /* rev8 */
  383. u32 readterm; /* rev8 */
  384. u32 writeterm; /* rev8 */
  385. u32 PAD[40];
  386. u32 clockctlstatus; /* rev8 */
  387. u32 PAD[7];
  388. u32 PAD[128]; /* DMA engines */
  389. /* SDIO/PCMCIA CIS region */
  390. char cis[512]; /* 0x400-0x5ff, rev6 */
  391. /* PCMCIA function control registers */
  392. char pcmciafcr[256]; /* 0x600-6ff, rev6 */
  393. u16 PAD[55];
  394. /* PCMCIA backplane access */
  395. u16 backplanecsr; /* 0x76E, rev6 */
  396. u16 backplaneaddr0; /* rev6 */
  397. u16 backplaneaddr1; /* rev6 */
  398. u16 backplaneaddr2; /* rev6 */
  399. u16 backplaneaddr3; /* rev6 */
  400. u16 backplanedata0; /* rev6 */
  401. u16 backplanedata1; /* rev6 */
  402. u16 backplanedata2; /* rev6 */
  403. u16 backplanedata3; /* rev6 */
  404. u16 PAD[31];
  405. /* sprom "size" & "blank" info */
  406. u16 spromstatus; /* 0x7BE, rev2 */
  407. u32 PAD[464];
  408. u16 PAD[0x80];
  409. };
  410. #ifdef BCMDBG
  411. /* Device console log buffer state */
  412. struct brcmf_console {
  413. uint count; /* Poll interval msec counter */
  414. uint log_addr; /* Log struct address (fixed) */
  415. struct rte_log_le log_le; /* Log struct (host copy) */
  416. uint bufsize; /* Size of log buffer */
  417. u8 *buf; /* Log buffer (host copy) */
  418. uint last; /* Last buffer read index */
  419. };
  420. #endif /* BCMDBG */
  421. struct sdpcm_shared {
  422. u32 flags;
  423. u32 trap_addr;
  424. u32 assert_exp_addr;
  425. u32 assert_file_addr;
  426. u32 assert_line;
  427. u32 console_addr; /* Address of struct rte_console */
  428. u32 msgtrace_addr;
  429. u8 tag[32];
  430. };
  431. struct sdpcm_shared_le {
  432. __le32 flags;
  433. __le32 trap_addr;
  434. __le32 assert_exp_addr;
  435. __le32 assert_file_addr;
  436. __le32 assert_line;
  437. __le32 console_addr; /* Address of struct rte_console */
  438. __le32 msgtrace_addr;
  439. u8 tag[32];
  440. };
  441. /* misc chip info needed by some of the routines */
  442. struct chip_info {
  443. u32 chip;
  444. u32 chiprev;
  445. u32 cccorebase;
  446. u32 ccrev;
  447. u32 cccaps;
  448. u32 buscorebase; /* 32 bits backplane bus address */
  449. u32 buscorerev;
  450. u32 buscoretype;
  451. u32 ramcorebase;
  452. u32 armcorebase;
  453. u32 pmurev;
  454. u32 ramsize;
  455. };
  456. /* Private data for SDIO bus interaction */
  457. struct brcmf_bus {
  458. struct brcmf_pub *drvr;
  459. struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
  460. struct chip_info *ci; /* Chip info struct */
  461. char *vars; /* Variables (from CIS and/or other) */
  462. uint varsz; /* Size of variables buffer */
  463. u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
  464. u32 hostintmask; /* Copy of Host Interrupt Mask */
  465. u32 intstatus; /* Intstatus bits (events) pending */
  466. bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
  467. bool fcstate; /* State of dongle flow-control */
  468. uint blocksize; /* Block size of SDIO transfers */
  469. uint roundup; /* Max roundup limit */
  470. struct pktq txq; /* Queue length used for flow-control */
  471. u8 flowcontrol; /* per prio flow control bitmask */
  472. u8 tx_seq; /* Transmit sequence number (next) */
  473. u8 tx_max; /* Maximum transmit sequence allowed */
  474. u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
  475. u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
  476. u16 nextlen; /* Next Read Len from last header */
  477. u8 rx_seq; /* Receive sequence number (expected) */
  478. bool rxskip; /* Skip receive (awaiting NAK ACK) */
  479. uint rxbound; /* Rx frames to read before resched */
  480. uint txbound; /* Tx frames to send before resched */
  481. uint txminmax;
  482. struct sk_buff *glomd; /* Packet containing glomming descriptor */
  483. struct sk_buff_head glom; /* Packet list for glommed superframe */
  484. uint glomerr; /* Glom packet read errors */
  485. u8 *rxbuf; /* Buffer for receiving control packets */
  486. uint rxblen; /* Allocated length of rxbuf */
  487. u8 *rxctl; /* Aligned pointer into rxbuf */
  488. u8 *databuf; /* Buffer for receiving big glom packet */
  489. u8 *dataptr; /* Aligned pointer into databuf */
  490. uint rxlen; /* Length of valid data in buffer */
  491. u8 sdpcm_ver; /* Bus protocol reported by dongle */
  492. bool intr; /* Use interrupts */
  493. bool poll; /* Use polling */
  494. bool ipend; /* Device interrupt is pending */
  495. uint intrcount; /* Count of device interrupt callbacks */
  496. uint lastintrs; /* Count as of last watchdog timer */
  497. uint spurious; /* Count of spurious interrupts */
  498. uint pollrate; /* Ticks between device polls */
  499. uint polltick; /* Tick counter */
  500. uint pollcnt; /* Count of active polls */
  501. #ifdef BCMDBG
  502. uint console_interval;
  503. struct brcmf_console console; /* Console output polling support */
  504. uint console_addr; /* Console address from shared struct */
  505. #endif /* BCMDBG */
  506. uint regfails; /* Count of R_REG failures */
  507. uint clkstate; /* State of sd and backplane clock(s) */
  508. bool activity; /* Activity flag for clock down */
  509. s32 idletime; /* Control for activity timeout */
  510. s32 idlecount; /* Activity timeout counter */
  511. s32 idleclock; /* How to set bus driver when idle */
  512. s32 sd_rxchain;
  513. bool use_rxchain; /* If brcmf should use PKT chains */
  514. bool sleeping; /* Is SDIO bus sleeping? */
  515. bool rxflow_mode; /* Rx flow control mode */
  516. bool rxflow; /* Is rx flow control on */
  517. bool alp_only; /* Don't use HT clock (ALP only) */
  518. /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
  519. bool usebufpool;
  520. /* Some additional counters */
  521. uint tx_sderrs; /* Count of tx attempts with sd errors */
  522. uint fcqueued; /* Tx packets that got queued */
  523. uint rxrtx; /* Count of rtx requests (NAK to dongle) */
  524. uint rx_toolong; /* Receive frames too long to receive */
  525. uint rxc_errors; /* SDIO errors when reading control frames */
  526. uint rx_hdrfail; /* SDIO errors on header reads */
  527. uint rx_badhdr; /* Bad received headers (roosync?) */
  528. uint rx_badseq; /* Mismatched rx sequence number */
  529. uint fc_rcvd; /* Number of flow-control events received */
  530. uint fc_xoff; /* Number which turned on flow-control */
  531. uint fc_xon; /* Number which turned off flow-control */
  532. uint rxglomfail; /* Failed deglom attempts */
  533. uint rxglomframes; /* Number of glom frames (superframes) */
  534. uint rxglompkts; /* Number of packets from glom frames */
  535. uint f2rxhdrs; /* Number of header reads */
  536. uint f2rxdata; /* Number of frame data reads */
  537. uint f2txdata; /* Number of f2 frame writes */
  538. uint f1regdata; /* Number of f1 register accesses */
  539. u8 *ctrl_frame_buf;
  540. u32 ctrl_frame_len;
  541. bool ctrl_frame_stat;
  542. spinlock_t txqlock;
  543. wait_queue_head_t ctrl_wait;
  544. wait_queue_head_t dcmd_resp_wait;
  545. struct timer_list timer;
  546. struct completion watchdog_wait;
  547. struct task_struct *watchdog_tsk;
  548. bool wd_timer_valid;
  549. uint save_ms;
  550. struct task_struct *dpc_tsk;
  551. struct completion dpc_wait;
  552. struct semaphore sdsem;
  553. const char *fw_name;
  554. const struct firmware *firmware;
  555. const char *nv_name;
  556. u32 fw_ptr;
  557. };
  558. struct sbconfig {
  559. u32 PAD[2];
  560. u32 sbipsflag; /* initiator port ocp slave flag */
  561. u32 PAD[3];
  562. u32 sbtpsflag; /* target port ocp slave flag */
  563. u32 PAD[11];
  564. u32 sbtmerrloga; /* (sonics >= 2.3) */
  565. u32 PAD;
  566. u32 sbtmerrlog; /* (sonics >= 2.3) */
  567. u32 PAD[3];
  568. u32 sbadmatch3; /* address match3 */
  569. u32 PAD;
  570. u32 sbadmatch2; /* address match2 */
  571. u32 PAD;
  572. u32 sbadmatch1; /* address match1 */
  573. u32 PAD[7];
  574. u32 sbimstate; /* initiator agent state */
  575. u32 sbintvec; /* interrupt mask */
  576. u32 sbtmstatelow; /* target state */
  577. u32 sbtmstatehigh; /* target state */
  578. u32 sbbwa0; /* bandwidth allocation table0 */
  579. u32 PAD;
  580. u32 sbimconfiglow; /* initiator configuration */
  581. u32 sbimconfighigh; /* initiator configuration */
  582. u32 sbadmatch0; /* address match0 */
  583. u32 PAD;
  584. u32 sbtmconfiglow; /* target configuration */
  585. u32 sbtmconfighigh; /* target configuration */
  586. u32 sbbconfig; /* broadcast configuration */
  587. u32 PAD;
  588. u32 sbbstate; /* broadcast state */
  589. u32 PAD[3];
  590. u32 sbactcnfg; /* activate configuration */
  591. u32 PAD[3];
  592. u32 sbflagst; /* current sbflags */
  593. u32 PAD[3];
  594. u32 sbidlow; /* identification */
  595. u32 sbidhigh; /* identification */
  596. };
  597. /* clkstate */
  598. #define CLK_NONE 0
  599. #define CLK_SDONLY 1
  600. #define CLK_PENDING 2 /* Not used yet */
  601. #define CLK_AVAIL 3
  602. #ifdef BCMDBG
  603. static int qcount[NUMPRIO];
  604. static int tx_packets[NUMPRIO];
  605. #endif /* BCMDBG */
  606. #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
  607. #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
  608. /* Retry count for register access failures */
  609. static const uint retry_limit = 2;
  610. /* Limit on rounding up frames */
  611. static const uint max_roundup = 512;
  612. #define ALIGNMENT 4
  613. static void pkt_align(struct sk_buff *p, int len, int align)
  614. {
  615. uint datalign;
  616. datalign = (unsigned long)(p->data);
  617. datalign = roundup(datalign, (align)) - datalign;
  618. if (datalign)
  619. skb_pull(p, datalign);
  620. __skb_trim(p, len);
  621. }
  622. /* To check if there's window offered */
  623. static bool data_ok(struct brcmf_bus *bus)
  624. {
  625. return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
  626. ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
  627. }
  628. /*
  629. * Reads a register in the SDIO hardware block. This block occupies a series of
  630. * adresses on the 32 bit backplane bus.
  631. */
  632. static void
  633. r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
  634. {
  635. *retryvar = 0;
  636. do {
  637. *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
  638. bus->ci->buscorebase + reg_offset, sizeof(u32));
  639. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  640. (++(*retryvar) <= retry_limit));
  641. if (*retryvar) {
  642. bus->regfails += (*retryvar-1);
  643. if (*retryvar > retry_limit) {
  644. brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
  645. *regvar = 0;
  646. }
  647. }
  648. }
  649. static void
  650. w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
  651. {
  652. *retryvar = 0;
  653. do {
  654. brcmf_sdcard_reg_write(bus->sdiodev,
  655. bus->ci->buscorebase + reg_offset,
  656. sizeof(u32), regval);
  657. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  658. (++(*retryvar) <= retry_limit));
  659. if (*retryvar) {
  660. bus->regfails += (*retryvar-1);
  661. if (*retryvar > retry_limit)
  662. brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
  663. reg_offset);
  664. }
  665. }
  666. #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
  667. #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
  668. /* Packet free applicable unconditionally for sdio and sdspi.
  669. * Conditional if bufpool was present for gspi bus.
  670. */
  671. static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
  672. {
  673. if (bus->usebufpool)
  674. brcmu_pkt_buf_free_skb(pkt);
  675. }
  676. /* Turn backplane clock on or off */
  677. static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
  678. {
  679. int err;
  680. u8 clkctl, clkreq, devctl;
  681. unsigned long timeout;
  682. brcmf_dbg(TRACE, "Enter\n");
  683. clkctl = 0;
  684. if (on) {
  685. /* Request HT Avail */
  686. clkreq =
  687. bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
  688. if ((bus->ci->chip == BCM4329_CHIP_ID)
  689. && (bus->ci->chiprev == 0))
  690. clkreq |= SBSDIO_FORCE_ALP;
  691. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  692. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  693. if (err) {
  694. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  695. return -EBADE;
  696. }
  697. if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
  698. && (bus->ci->buscorerev == 9))) {
  699. u32 dummy, retries;
  700. r_sdreg32(bus, &dummy,
  701. offsetof(struct sdpcmd_regs, clockctlstatus),
  702. &retries);
  703. }
  704. /* Check current status */
  705. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  706. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  707. if (err) {
  708. brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
  709. return -EBADE;
  710. }
  711. /* Go to pending and await interrupt if appropriate */
  712. if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
  713. /* Allow only clock-available interrupt */
  714. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  715. SDIO_FUNC_1,
  716. SBSDIO_DEVICE_CTL, &err);
  717. if (err) {
  718. brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
  719. err);
  720. return -EBADE;
  721. }
  722. devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
  723. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  724. SBSDIO_DEVICE_CTL, devctl, &err);
  725. brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
  726. bus->clkstate = CLK_PENDING;
  727. return 0;
  728. } else if (bus->clkstate == CLK_PENDING) {
  729. /* Cancel CA-only interrupt filter */
  730. devctl =
  731. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  732. SBSDIO_DEVICE_CTL, &err);
  733. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  734. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  735. SBSDIO_DEVICE_CTL, devctl, &err);
  736. }
  737. /* Otherwise, wait here (polling) for HT Avail */
  738. timeout = jiffies +
  739. msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
  740. while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  741. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  742. SDIO_FUNC_1,
  743. SBSDIO_FUNC1_CHIPCLKCSR,
  744. &err);
  745. if (time_after(jiffies, timeout))
  746. break;
  747. else
  748. usleep_range(5000, 10000);
  749. }
  750. if (err) {
  751. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  752. return -EBADE;
  753. }
  754. if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  755. brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
  756. PMU_MAX_TRANSITION_DLY, clkctl);
  757. return -EBADE;
  758. }
  759. /* Mark clock available */
  760. bus->clkstate = CLK_AVAIL;
  761. brcmf_dbg(INFO, "CLKCTL: turned ON\n");
  762. #if defined(BCMDBG)
  763. if (bus->alp_only != true) {
  764. if (SBSDIO_ALPONLY(clkctl))
  765. brcmf_dbg(ERROR, "HT Clock should be on\n");
  766. }
  767. #endif /* defined (BCMDBG) */
  768. bus->activity = true;
  769. } else {
  770. clkreq = 0;
  771. if (bus->clkstate == CLK_PENDING) {
  772. /* Cancel CA-only interrupt filter */
  773. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  774. SDIO_FUNC_1,
  775. SBSDIO_DEVICE_CTL, &err);
  776. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  777. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  778. SBSDIO_DEVICE_CTL, devctl, &err);
  779. }
  780. bus->clkstate = CLK_SDONLY;
  781. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  782. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  783. brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
  784. if (err) {
  785. brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
  786. err);
  787. return -EBADE;
  788. }
  789. }
  790. return 0;
  791. }
  792. /* Change idle/active SD state */
  793. static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
  794. {
  795. brcmf_dbg(TRACE, "Enter\n");
  796. if (on)
  797. bus->clkstate = CLK_SDONLY;
  798. else
  799. bus->clkstate = CLK_NONE;
  800. return 0;
  801. }
  802. /* Transition SD and backplane clock readiness */
  803. static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
  804. {
  805. #ifdef BCMDBG
  806. uint oldstate = bus->clkstate;
  807. #endif /* BCMDBG */
  808. brcmf_dbg(TRACE, "Enter\n");
  809. /* Early exit if we're already there */
  810. if (bus->clkstate == target) {
  811. if (target == CLK_AVAIL) {
  812. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  813. bus->activity = true;
  814. }
  815. return 0;
  816. }
  817. switch (target) {
  818. case CLK_AVAIL:
  819. /* Make sure SD clock is available */
  820. if (bus->clkstate == CLK_NONE)
  821. brcmf_sdbrcm_sdclk(bus, true);
  822. /* Now request HT Avail on the backplane */
  823. brcmf_sdbrcm_htclk(bus, true, pendok);
  824. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  825. bus->activity = true;
  826. break;
  827. case CLK_SDONLY:
  828. /* Remove HT request, or bring up SD clock */
  829. if (bus->clkstate == CLK_NONE)
  830. brcmf_sdbrcm_sdclk(bus, true);
  831. else if (bus->clkstate == CLK_AVAIL)
  832. brcmf_sdbrcm_htclk(bus, false, false);
  833. else
  834. brcmf_dbg(ERROR, "request for %d -> %d\n",
  835. bus->clkstate, target);
  836. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  837. break;
  838. case CLK_NONE:
  839. /* Make sure to remove HT request */
  840. if (bus->clkstate == CLK_AVAIL)
  841. brcmf_sdbrcm_htclk(bus, false, false);
  842. /* Now remove the SD clock */
  843. brcmf_sdbrcm_sdclk(bus, false);
  844. brcmf_sdbrcm_wd_timer(bus, 0);
  845. break;
  846. }
  847. #ifdef BCMDBG
  848. brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
  849. #endif /* BCMDBG */
  850. return 0;
  851. }
  852. static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
  853. {
  854. uint retries = 0;
  855. brcmf_dbg(INFO, "request %s (currently %s)\n",
  856. sleep ? "SLEEP" : "WAKE",
  857. bus->sleeping ? "SLEEP" : "WAKE");
  858. /* Done if we're already in the requested state */
  859. if (sleep == bus->sleeping)
  860. return 0;
  861. /* Going to sleep: set the alarm and turn off the lights... */
  862. if (sleep) {
  863. /* Don't sleep if something is pending */
  864. if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
  865. return -EBUSY;
  866. /* Make sure the controller has the bus up */
  867. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  868. /* Tell device to start using OOB wakeup */
  869. w_sdreg32(bus, SMB_USE_OOB,
  870. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  871. if (retries > retry_limit)
  872. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
  873. /* Turn off our contribution to the HT clock request */
  874. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  875. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  876. SBSDIO_FUNC1_CHIPCLKCSR,
  877. SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
  878. /* Isolate the bus */
  879. if (bus->ci->chip != BCM4329_CHIP_ID) {
  880. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  881. SBSDIO_DEVICE_CTL,
  882. SBSDIO_DEVCTL_PADS_ISO, NULL);
  883. }
  884. /* Change state */
  885. bus->sleeping = true;
  886. } else {
  887. /* Waking up: bus power up is ok, set local state */
  888. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  889. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  890. /* Force pad isolation off if possible
  891. (in case power never toggled) */
  892. if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
  893. && (bus->ci->buscorerev >= 10))
  894. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  895. SBSDIO_DEVICE_CTL, 0, NULL);
  896. /* Make sure the controller has the bus up */
  897. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  898. /* Send misc interrupt to indicate OOB not needed */
  899. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
  900. &retries);
  901. if (retries <= retry_limit)
  902. w_sdreg32(bus, SMB_DEV_INT,
  903. offsetof(struct sdpcmd_regs, tosbmailbox),
  904. &retries);
  905. if (retries > retry_limit)
  906. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
  907. /* Make sure we have SD bus access */
  908. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  909. /* Change state */
  910. bus->sleeping = false;
  911. }
  912. return 0;
  913. }
  914. static void bus_wake(struct brcmf_bus *bus)
  915. {
  916. if (bus->sleeping)
  917. brcmf_sdbrcm_bussleep(bus, false);
  918. }
  919. static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
  920. {
  921. u32 intstatus = 0;
  922. u32 hmb_data;
  923. u8 fcbits;
  924. uint retries = 0;
  925. brcmf_dbg(TRACE, "Enter\n");
  926. /* Read mailbox data and ack that we did so */
  927. r_sdreg32(bus, &hmb_data,
  928. offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
  929. if (retries <= retry_limit)
  930. w_sdreg32(bus, SMB_INT_ACK,
  931. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  932. bus->f1regdata += 2;
  933. /* Dongle recomposed rx frames, accept them again */
  934. if (hmb_data & HMB_DATA_NAKHANDLED) {
  935. brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
  936. bus->rx_seq);
  937. if (!bus->rxskip)
  938. brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
  939. bus->rxskip = false;
  940. intstatus |= I_HMB_FRAME_IND;
  941. }
  942. /*
  943. * DEVREADY does not occur with gSPI.
  944. */
  945. if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
  946. bus->sdpcm_ver =
  947. (hmb_data & HMB_DATA_VERSION_MASK) >>
  948. HMB_DATA_VERSION_SHIFT;
  949. if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
  950. brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
  951. "expecting %d\n",
  952. bus->sdpcm_ver, SDPCM_PROT_VERSION);
  953. else
  954. brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
  955. bus->sdpcm_ver);
  956. }
  957. /*
  958. * Flow Control has been moved into the RX headers and this out of band
  959. * method isn't used any more.
  960. * remaining backward compatible with older dongles.
  961. */
  962. if (hmb_data & HMB_DATA_FC) {
  963. fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
  964. HMB_DATA_FCDATA_SHIFT;
  965. if (fcbits & ~bus->flowcontrol)
  966. bus->fc_xoff++;
  967. if (bus->flowcontrol & ~fcbits)
  968. bus->fc_xon++;
  969. bus->fc_rcvd++;
  970. bus->flowcontrol = fcbits;
  971. }
  972. /* Shouldn't be any others */
  973. if (hmb_data & ~(HMB_DATA_DEVREADY |
  974. HMB_DATA_NAKHANDLED |
  975. HMB_DATA_FC |
  976. HMB_DATA_FWREADY |
  977. HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
  978. brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
  979. hmb_data);
  980. return intstatus;
  981. }
  982. static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
  983. {
  984. uint retries = 0;
  985. u16 lastrbc;
  986. u8 hi, lo;
  987. int err;
  988. brcmf_dbg(ERROR, "%sterminate frame%s\n",
  989. abort ? "abort command, " : "",
  990. rtx ? ", send NAK" : "");
  991. if (abort)
  992. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  993. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  994. SBSDIO_FUNC1_FRAMECTRL,
  995. SFC_RF_TERM, &err);
  996. bus->f1regdata++;
  997. /* Wait until the packet has been flushed (device/FIFO stable) */
  998. for (lastrbc = retries = 0xffff; retries > 0; retries--) {
  999. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  1000. SBSDIO_FUNC1_RFRAMEBCHI, NULL);
  1001. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  1002. SBSDIO_FUNC1_RFRAMEBCLO, NULL);
  1003. bus->f1regdata += 2;
  1004. if ((hi == 0) && (lo == 0))
  1005. break;
  1006. if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
  1007. brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
  1008. lastrbc, (hi << 8) + lo);
  1009. }
  1010. lastrbc = (hi << 8) + lo;
  1011. }
  1012. if (!retries)
  1013. brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
  1014. else
  1015. brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
  1016. if (rtx) {
  1017. bus->rxrtx++;
  1018. w_sdreg32(bus, SMB_NAK,
  1019. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  1020. bus->f1regdata++;
  1021. if (retries <= retry_limit)
  1022. bus->rxskip = true;
  1023. }
  1024. /* Clear partial in any case */
  1025. bus->nextlen = 0;
  1026. /* If we can't reach the device, signal failure */
  1027. if (err || brcmf_sdcard_regfail(bus->sdiodev))
  1028. bus->drvr->busstate = BRCMF_BUS_DOWN;
  1029. }
  1030. /* copy a buffer into a pkt buffer chain */
  1031. static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_bus *bus, uint len)
  1032. {
  1033. uint n, ret = 0;
  1034. struct sk_buff *p;
  1035. u8 *buf;
  1036. buf = bus->dataptr;
  1037. /* copy the data */
  1038. skb_queue_walk(&bus->glom, p) {
  1039. n = min_t(uint, p->len, len);
  1040. memcpy(p->data, buf, n);
  1041. buf += n;
  1042. len -= n;
  1043. ret += n;
  1044. if (!len)
  1045. break;
  1046. }
  1047. return ret;
  1048. }
  1049. static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
  1050. {
  1051. u16 dlen, totlen;
  1052. u8 *dptr, num = 0;
  1053. u16 sublen, check;
  1054. struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
  1055. int errcode;
  1056. u8 chan, seq, doff, sfdoff;
  1057. u8 txmax;
  1058. int ifidx = 0;
  1059. bool usechain = bus->use_rxchain;
  1060. /* If packets, issue read(s) and send up packet chain */
  1061. /* Return sequence numbers consumed? */
  1062. brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
  1063. bus->glomd, skb_peek(&bus->glom));
  1064. /* If there's a descriptor, generate the packet chain */
  1065. if (bus->glomd) {
  1066. pfirst = plast = pnext = NULL;
  1067. dlen = (u16) (bus->glomd->len);
  1068. dptr = bus->glomd->data;
  1069. if (!dlen || (dlen & 1)) {
  1070. brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
  1071. dlen);
  1072. dlen = 0;
  1073. }
  1074. for (totlen = num = 0; dlen; num++) {
  1075. /* Get (and move past) next length */
  1076. sublen = get_unaligned_le16(dptr);
  1077. dlen -= sizeof(u16);
  1078. dptr += sizeof(u16);
  1079. if ((sublen < SDPCM_HDRLEN) ||
  1080. ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
  1081. brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
  1082. num, sublen);
  1083. pnext = NULL;
  1084. break;
  1085. }
  1086. if (sublen % BRCMF_SDALIGN) {
  1087. brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
  1088. sublen, BRCMF_SDALIGN);
  1089. usechain = false;
  1090. }
  1091. totlen += sublen;
  1092. /* For last frame, adjust read len so total
  1093. is a block multiple */
  1094. if (!dlen) {
  1095. sublen +=
  1096. (roundup(totlen, bus->blocksize) - totlen);
  1097. totlen = roundup(totlen, bus->blocksize);
  1098. }
  1099. /* Allocate/chain packet for next subframe */
  1100. pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
  1101. if (pnext == NULL) {
  1102. brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
  1103. num, sublen);
  1104. break;
  1105. }
  1106. skb_queue_tail(&bus->glom, pnext);
  1107. /* Adhere to start alignment requirements */
  1108. pkt_align(pnext, sublen, BRCMF_SDALIGN);
  1109. }
  1110. /* If all allocations succeeded, save packet chain
  1111. in bus structure */
  1112. if (pnext) {
  1113. brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
  1114. totlen, num);
  1115. if (BRCMF_GLOM_ON() && bus->nextlen &&
  1116. totlen != bus->nextlen) {
  1117. brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
  1118. bus->nextlen, totlen, rxseq);
  1119. }
  1120. pfirst = pnext = NULL;
  1121. } else {
  1122. if (!skb_queue_empty(&bus->glom))
  1123. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1124. skb_unlink(pfirst, &bus->glom);
  1125. brcmu_pkt_buf_free_skb(pfirst);
  1126. }
  1127. num = 0;
  1128. }
  1129. /* Done with descriptor packet */
  1130. brcmu_pkt_buf_free_skb(bus->glomd);
  1131. bus->glomd = NULL;
  1132. bus->nextlen = 0;
  1133. }
  1134. /* Ok -- either we just generated a packet chain,
  1135. or had one from before */
  1136. if (!skb_queue_empty(&bus->glom)) {
  1137. if (BRCMF_GLOM_ON()) {
  1138. brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
  1139. skb_queue_walk(&bus->glom, pnext) {
  1140. brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
  1141. pnext, (u8 *) (pnext->data),
  1142. pnext->len, pnext->len);
  1143. }
  1144. }
  1145. pfirst = skb_peek(&bus->glom);
  1146. dlen = (u16) brcmu_pkttotlen(pfirst);
  1147. /* Do an SDIO read for the superframe. Configurable iovar to
  1148. * read directly into the chained packet, or allocate a large
  1149. * packet and and copy into the chain.
  1150. */
  1151. if (usechain) {
  1152. errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
  1153. bus->sdiodev->sbwad,
  1154. SDIO_FUNC_2,
  1155. F2SYNC, (u8 *) pfirst->data, dlen,
  1156. pfirst);
  1157. } else if (bus->dataptr) {
  1158. errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
  1159. bus->sdiodev->sbwad,
  1160. SDIO_FUNC_2,
  1161. F2SYNC, bus->dataptr, dlen,
  1162. NULL);
  1163. sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
  1164. if (sublen != dlen) {
  1165. brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
  1166. dlen, sublen);
  1167. errcode = -1;
  1168. }
  1169. pnext = NULL;
  1170. } else {
  1171. brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
  1172. dlen);
  1173. errcode = -1;
  1174. }
  1175. bus->f2rxdata++;
  1176. /* On failure, kill the superframe, allow a couple retries */
  1177. if (errcode < 0) {
  1178. brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
  1179. dlen, errcode);
  1180. bus->drvr->rx_errors++;
  1181. if (bus->glomerr++ < 3) {
  1182. brcmf_sdbrcm_rxfail(bus, true, true);
  1183. } else {
  1184. bus->glomerr = 0;
  1185. brcmf_sdbrcm_rxfail(bus, true, false);
  1186. bus->rxglomfail++;
  1187. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1188. skb_unlink(pfirst, &bus->glom);
  1189. brcmu_pkt_buf_free_skb(pfirst);
  1190. }
  1191. }
  1192. return 0;
  1193. }
  1194. #ifdef BCMDBG
  1195. if (BRCMF_GLOM_ON()) {
  1196. printk(KERN_DEBUG "SUPERFRAME:\n");
  1197. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1198. pfirst->data, min_t(int, pfirst->len, 48));
  1199. }
  1200. #endif
  1201. /* Validate the superframe header */
  1202. dptr = (u8 *) (pfirst->data);
  1203. sublen = get_unaligned_le16(dptr);
  1204. check = get_unaligned_le16(dptr + sizeof(u16));
  1205. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1206. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1207. bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1208. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1209. brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
  1210. bus->nextlen, seq);
  1211. bus->nextlen = 0;
  1212. }
  1213. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1214. txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1215. errcode = 0;
  1216. if ((u16)~(sublen ^ check)) {
  1217. brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
  1218. sublen, check);
  1219. errcode = -1;
  1220. } else if (roundup(sublen, bus->blocksize) != dlen) {
  1221. brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
  1222. sublen, roundup(sublen, bus->blocksize),
  1223. dlen);
  1224. errcode = -1;
  1225. } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
  1226. SDPCM_GLOM_CHANNEL) {
  1227. brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
  1228. SDPCM_PACKET_CHANNEL(
  1229. &dptr[SDPCM_FRAMETAG_LEN]));
  1230. errcode = -1;
  1231. } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
  1232. brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
  1233. errcode = -1;
  1234. } else if ((doff < SDPCM_HDRLEN) ||
  1235. (doff > (pfirst->len - SDPCM_HDRLEN))) {
  1236. brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
  1237. doff, sublen, pfirst->len, SDPCM_HDRLEN);
  1238. errcode = -1;
  1239. }
  1240. /* Check sequence number of superframe SW header */
  1241. if (rxseq != seq) {
  1242. brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
  1243. seq, rxseq);
  1244. bus->rx_badseq++;
  1245. rxseq = seq;
  1246. }
  1247. /* Check window for sanity */
  1248. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1249. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1250. txmax, bus->tx_seq);
  1251. txmax = bus->tx_seq + 2;
  1252. }
  1253. bus->tx_max = txmax;
  1254. /* Remove superframe header, remember offset */
  1255. skb_pull(pfirst, doff);
  1256. sfdoff = doff;
  1257. /* Validate all the subframe headers */
  1258. for (num = 0, pnext = pfirst; pnext && !errcode;
  1259. num++, pnext = pnext->next) {
  1260. dptr = (u8 *) (pnext->data);
  1261. dlen = (u16) (pnext->len);
  1262. sublen = get_unaligned_le16(dptr);
  1263. check = get_unaligned_le16(dptr + sizeof(u16));
  1264. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1265. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1266. #ifdef BCMDBG
  1267. if (BRCMF_GLOM_ON()) {
  1268. printk(KERN_DEBUG "subframe:\n");
  1269. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1270. dptr, 32);
  1271. }
  1272. #endif
  1273. if ((u16)~(sublen ^ check)) {
  1274. brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
  1275. num, sublen, check);
  1276. errcode = -1;
  1277. } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
  1278. brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
  1279. num, sublen, dlen);
  1280. errcode = -1;
  1281. } else if ((chan != SDPCM_DATA_CHANNEL) &&
  1282. (chan != SDPCM_EVENT_CHANNEL)) {
  1283. brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
  1284. num, chan);
  1285. errcode = -1;
  1286. } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
  1287. brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
  1288. num, doff, sublen, SDPCM_HDRLEN);
  1289. errcode = -1;
  1290. }
  1291. }
  1292. if (errcode) {
  1293. /* Terminate frame on error, request
  1294. a couple retries */
  1295. if (bus->glomerr++ < 3) {
  1296. /* Restore superframe header space */
  1297. skb_push(pfirst, sfdoff);
  1298. brcmf_sdbrcm_rxfail(bus, true, true);
  1299. } else {
  1300. bus->glomerr = 0;
  1301. brcmf_sdbrcm_rxfail(bus, true, false);
  1302. bus->rxglomfail++;
  1303. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1304. skb_unlink(pfirst, &bus->glom);
  1305. brcmu_pkt_buf_free_skb(pfirst);
  1306. }
  1307. }
  1308. bus->nextlen = 0;
  1309. return 0;
  1310. }
  1311. /* Basic SD framing looks ok - process each packet (header) */
  1312. save_pfirst = pfirst;
  1313. plast = NULL;
  1314. for (num = 0; pfirst; rxseq++, pfirst = pnext) {
  1315. pnext = pfirst->next;
  1316. pfirst->next = NULL;
  1317. dptr = (u8 *) (pfirst->data);
  1318. sublen = get_unaligned_le16(dptr);
  1319. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1320. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1321. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1322. brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
  1323. num, pfirst, pfirst->data,
  1324. pfirst->len, sublen, chan, seq);
  1325. /* precondition: chan == SDPCM_DATA_CHANNEL ||
  1326. chan == SDPCM_EVENT_CHANNEL */
  1327. if (rxseq != seq) {
  1328. brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
  1329. seq, rxseq);
  1330. bus->rx_badseq++;
  1331. rxseq = seq;
  1332. }
  1333. #ifdef BCMDBG
  1334. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1335. printk(KERN_DEBUG "Rx Subframe Data:\n");
  1336. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1337. dptr, dlen);
  1338. }
  1339. #endif
  1340. __skb_trim(pfirst, sublen);
  1341. skb_pull(pfirst, doff);
  1342. if (pfirst->len == 0) {
  1343. brcmu_pkt_buf_free_skb(pfirst);
  1344. if (plast)
  1345. plast->next = pnext;
  1346. else
  1347. save_pfirst = pnext;
  1348. continue;
  1349. } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
  1350. pfirst) != 0) {
  1351. brcmf_dbg(ERROR, "rx protocol error\n");
  1352. bus->drvr->rx_errors++;
  1353. brcmu_pkt_buf_free_skb(pfirst);
  1354. if (plast)
  1355. plast->next = pnext;
  1356. else
  1357. save_pfirst = pnext;
  1358. continue;
  1359. }
  1360. /* this packet will go up, link back into
  1361. chain and count it */
  1362. pfirst->next = pnext;
  1363. plast = pfirst;
  1364. num++;
  1365. #ifdef BCMDBG
  1366. if (BRCMF_GLOM_ON()) {
  1367. brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
  1368. num, pfirst, pfirst->data,
  1369. pfirst->len, pfirst->next,
  1370. pfirst->prev);
  1371. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1372. pfirst->data,
  1373. min_t(int, pfirst->len, 32));
  1374. }
  1375. #endif /* BCMDBG */
  1376. }
  1377. if (num) {
  1378. up(&bus->sdsem);
  1379. brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
  1380. down(&bus->sdsem);
  1381. }
  1382. bus->rxglomframes++;
  1383. bus->rxglompkts += num;
  1384. }
  1385. return num;
  1386. }
  1387. static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
  1388. bool *pending)
  1389. {
  1390. DECLARE_WAITQUEUE(wait, current);
  1391. int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
  1392. /* Wait until control frame is available */
  1393. add_wait_queue(&bus->dcmd_resp_wait, &wait);
  1394. set_current_state(TASK_INTERRUPTIBLE);
  1395. while (!(*condition) && (!signal_pending(current) && timeout))
  1396. timeout = schedule_timeout(timeout);
  1397. if (signal_pending(current))
  1398. *pending = true;
  1399. set_current_state(TASK_RUNNING);
  1400. remove_wait_queue(&bus->dcmd_resp_wait, &wait);
  1401. return timeout;
  1402. }
  1403. static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
  1404. {
  1405. if (waitqueue_active(&bus->dcmd_resp_wait))
  1406. wake_up_interruptible(&bus->dcmd_resp_wait);
  1407. return 0;
  1408. }
  1409. static void
  1410. brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
  1411. {
  1412. uint rdlen, pad;
  1413. int sdret;
  1414. brcmf_dbg(TRACE, "Enter\n");
  1415. /* Set rxctl for frame (w/optional alignment) */
  1416. bus->rxctl = bus->rxbuf;
  1417. bus->rxctl += BRCMF_FIRSTREAD;
  1418. pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
  1419. if (pad)
  1420. bus->rxctl += (BRCMF_SDALIGN - pad);
  1421. bus->rxctl -= BRCMF_FIRSTREAD;
  1422. /* Copy the already-read portion over */
  1423. memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
  1424. if (len <= BRCMF_FIRSTREAD)
  1425. goto gotpkt;
  1426. /* Raise rdlen to next SDIO block to avoid tail command */
  1427. rdlen = len - BRCMF_FIRSTREAD;
  1428. if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
  1429. pad = bus->blocksize - (rdlen % bus->blocksize);
  1430. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1431. ((len + pad) < bus->drvr->maxctl))
  1432. rdlen += pad;
  1433. } else if (rdlen % BRCMF_SDALIGN) {
  1434. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1435. }
  1436. /* Satisfy length-alignment requirements */
  1437. if (rdlen & (ALIGNMENT - 1))
  1438. rdlen = roundup(rdlen, ALIGNMENT);
  1439. /* Drop if the read is too big or it exceeds our maximum */
  1440. if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
  1441. brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
  1442. rdlen, bus->drvr->maxctl);
  1443. bus->drvr->rx_errors++;
  1444. brcmf_sdbrcm_rxfail(bus, false, false);
  1445. goto done;
  1446. }
  1447. if ((len - doff) > bus->drvr->maxctl) {
  1448. brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
  1449. len, len - doff, bus->drvr->maxctl);
  1450. bus->drvr->rx_errors++;
  1451. bus->rx_toolong++;
  1452. brcmf_sdbrcm_rxfail(bus, false, false);
  1453. goto done;
  1454. }
  1455. /* Read remainder of frame body into the rxctl buffer */
  1456. sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
  1457. bus->sdiodev->sbwad,
  1458. SDIO_FUNC_2,
  1459. F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen,
  1460. NULL);
  1461. bus->f2rxdata++;
  1462. /* Control frame failures need retransmission */
  1463. if (sdret < 0) {
  1464. brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
  1465. rdlen, sdret);
  1466. bus->rxc_errors++;
  1467. brcmf_sdbrcm_rxfail(bus, true, true);
  1468. goto done;
  1469. }
  1470. gotpkt:
  1471. #ifdef BCMDBG
  1472. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  1473. printk(KERN_DEBUG "RxCtrl:\n");
  1474. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
  1475. }
  1476. #endif
  1477. /* Point to valid data and indicate its length */
  1478. bus->rxctl += doff;
  1479. bus->rxlen = len - doff;
  1480. done:
  1481. /* Awake any waiters */
  1482. brcmf_sdbrcm_dcmd_resp_wake(bus);
  1483. }
  1484. /* Pad read to blocksize for efficiency */
  1485. static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
  1486. {
  1487. if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
  1488. *pad = bus->blocksize - (*rdlen % bus->blocksize);
  1489. if (*pad <= bus->roundup && *pad < bus->blocksize &&
  1490. *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
  1491. *rdlen += *pad;
  1492. } else if (*rdlen % BRCMF_SDALIGN) {
  1493. *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
  1494. }
  1495. }
  1496. static void
  1497. brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
  1498. struct sk_buff **pkt, u8 **rxbuf)
  1499. {
  1500. int sdret; /* Return code from calls */
  1501. *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
  1502. if (*pkt == NULL)
  1503. return;
  1504. pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
  1505. *rxbuf = (u8 *) ((*pkt)->data);
  1506. /* Read the entire frame */
  1507. sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
  1508. SDIO_FUNC_2, F2SYNC,
  1509. *rxbuf, rdlen, *pkt);
  1510. bus->f2rxdata++;
  1511. if (sdret < 0) {
  1512. brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
  1513. rdlen, sdret);
  1514. brcmu_pkt_buf_free_skb(*pkt);
  1515. bus->drvr->rx_errors++;
  1516. /* Force retry w/normal header read.
  1517. * Don't attempt NAK for
  1518. * gSPI
  1519. */
  1520. brcmf_sdbrcm_rxfail(bus, true, true);
  1521. *pkt = NULL;
  1522. }
  1523. }
  1524. /* Checks the header */
  1525. static int
  1526. brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
  1527. u8 rxseq, u16 nextlen, u16 *len)
  1528. {
  1529. u16 check;
  1530. bool len_consistent; /* Result of comparing readahead len and
  1531. len from hw-hdr */
  1532. memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
  1533. /* Extract hardware header fields */
  1534. *len = get_unaligned_le16(bus->rxhdr);
  1535. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1536. /* All zeros means readahead info was bad */
  1537. if (!(*len | check)) {
  1538. brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
  1539. goto fail;
  1540. }
  1541. /* Validate check bytes */
  1542. if ((u16)~(*len ^ check)) {
  1543. brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
  1544. nextlen, *len, check);
  1545. bus->rx_badhdr++;
  1546. brcmf_sdbrcm_rxfail(bus, false, false);
  1547. goto fail;
  1548. }
  1549. /* Validate frame length */
  1550. if (*len < SDPCM_HDRLEN) {
  1551. brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
  1552. *len);
  1553. goto fail;
  1554. }
  1555. /* Check for consistency with readahead info */
  1556. len_consistent = (nextlen != (roundup(*len, 16) >> 4));
  1557. if (len_consistent) {
  1558. /* Mismatch, force retry w/normal
  1559. header (may be >4K) */
  1560. brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
  1561. nextlen, *len, roundup(*len, 16),
  1562. rxseq);
  1563. brcmf_sdbrcm_rxfail(bus, true, true);
  1564. goto fail;
  1565. }
  1566. return 0;
  1567. fail:
  1568. brcmf_sdbrcm_pktfree2(bus, pkt);
  1569. return -EINVAL;
  1570. }
  1571. /* Return true if there may be more frames to read */
  1572. static uint
  1573. brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
  1574. {
  1575. u16 len, check; /* Extracted hardware header fields */
  1576. u8 chan, seq, doff; /* Extracted software header fields */
  1577. u8 fcbits; /* Extracted fcbits from software header */
  1578. struct sk_buff *pkt; /* Packet for event or data frames */
  1579. u16 pad; /* Number of pad bytes to read */
  1580. u16 rdlen; /* Total number of bytes to read */
  1581. u8 rxseq; /* Next sequence number to expect */
  1582. uint rxleft = 0; /* Remaining number of frames allowed */
  1583. int sdret; /* Return code from calls */
  1584. u8 txmax; /* Maximum tx sequence offered */
  1585. u8 *rxbuf;
  1586. int ifidx = 0;
  1587. uint rxcount = 0; /* Total frames read */
  1588. brcmf_dbg(TRACE, "Enter\n");
  1589. /* Not finished unless we encounter no more frames indication */
  1590. *finished = false;
  1591. for (rxseq = bus->rx_seq, rxleft = maxframes;
  1592. !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
  1593. rxseq++, rxleft--) {
  1594. /* Handle glomming separately */
  1595. if (bus->glomd || !skb_queue_empty(&bus->glom)) {
  1596. u8 cnt;
  1597. brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
  1598. bus->glomd, skb_peek(&bus->glom));
  1599. cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
  1600. brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
  1601. rxseq += cnt - 1;
  1602. rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
  1603. continue;
  1604. }
  1605. /* Try doing single read if we can */
  1606. if (bus->nextlen) {
  1607. u16 nextlen = bus->nextlen;
  1608. bus->nextlen = 0;
  1609. rdlen = len = nextlen << 4;
  1610. brcmf_pad(bus, &pad, &rdlen);
  1611. /*
  1612. * After the frame is received we have to
  1613. * distinguish whether it is data
  1614. * or non-data frame.
  1615. */
  1616. brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
  1617. if (pkt == NULL) {
  1618. /* Give up on data, request rtx of events */
  1619. brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
  1620. len, rdlen, rxseq);
  1621. continue;
  1622. }
  1623. if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
  1624. &len) < 0)
  1625. continue;
  1626. /* Extract software header fields */
  1627. chan = SDPCM_PACKET_CHANNEL(
  1628. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1629. seq = SDPCM_PACKET_SEQUENCE(
  1630. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1631. doff = SDPCM_DOFFSET_VALUE(
  1632. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1633. txmax = SDPCM_WINDOW_VALUE(
  1634. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1635. bus->nextlen =
  1636. bus->rxhdr[SDPCM_FRAMETAG_LEN +
  1637. SDPCM_NEXTLEN_OFFSET];
  1638. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1639. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1640. bus->nextlen, seq);
  1641. bus->nextlen = 0;
  1642. }
  1643. bus->drvr->rx_readahead_cnt++;
  1644. /* Handle Flow Control */
  1645. fcbits = SDPCM_FCMASK_VALUE(
  1646. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1647. if (bus->flowcontrol != fcbits) {
  1648. if (~bus->flowcontrol & fcbits)
  1649. bus->fc_xoff++;
  1650. if (bus->flowcontrol & ~fcbits)
  1651. bus->fc_xon++;
  1652. bus->fc_rcvd++;
  1653. bus->flowcontrol = fcbits;
  1654. }
  1655. /* Check and update sequence number */
  1656. if (rxseq != seq) {
  1657. brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
  1658. seq, rxseq);
  1659. bus->rx_badseq++;
  1660. rxseq = seq;
  1661. }
  1662. /* Check window for sanity */
  1663. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1664. brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
  1665. txmax, bus->tx_seq);
  1666. txmax = bus->tx_seq + 2;
  1667. }
  1668. bus->tx_max = txmax;
  1669. #ifdef BCMDBG
  1670. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1671. printk(KERN_DEBUG "Rx Data:\n");
  1672. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1673. rxbuf, len);
  1674. } else if (BRCMF_HDRS_ON()) {
  1675. printk(KERN_DEBUG "RxHdr:\n");
  1676. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1677. bus->rxhdr, SDPCM_HDRLEN);
  1678. }
  1679. #endif
  1680. if (chan == SDPCM_CONTROL_CHANNEL) {
  1681. brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
  1682. seq);
  1683. /* Force retry w/normal header read */
  1684. bus->nextlen = 0;
  1685. brcmf_sdbrcm_rxfail(bus, false, true);
  1686. brcmf_sdbrcm_pktfree2(bus, pkt);
  1687. continue;
  1688. }
  1689. /* Validate data offset */
  1690. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1691. brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
  1692. doff, len, SDPCM_HDRLEN);
  1693. brcmf_sdbrcm_rxfail(bus, false, false);
  1694. brcmf_sdbrcm_pktfree2(bus, pkt);
  1695. continue;
  1696. }
  1697. /* All done with this one -- now deliver the packet */
  1698. goto deliver;
  1699. }
  1700. /* Read frame header (hardware and software) */
  1701. sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
  1702. SDIO_FUNC_2, F2SYNC, bus->rxhdr,
  1703. BRCMF_FIRSTREAD, NULL);
  1704. bus->f2rxhdrs++;
  1705. if (sdret < 0) {
  1706. brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
  1707. bus->rx_hdrfail++;
  1708. brcmf_sdbrcm_rxfail(bus, true, true);
  1709. continue;
  1710. }
  1711. #ifdef BCMDBG
  1712. if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
  1713. printk(KERN_DEBUG "RxHdr:\n");
  1714. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1715. bus->rxhdr, SDPCM_HDRLEN);
  1716. }
  1717. #endif
  1718. /* Extract hardware header fields */
  1719. len = get_unaligned_le16(bus->rxhdr);
  1720. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1721. /* All zeros means no more frames */
  1722. if (!(len | check)) {
  1723. *finished = true;
  1724. break;
  1725. }
  1726. /* Validate check bytes */
  1727. if ((u16) ~(len ^ check)) {
  1728. brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
  1729. len, check);
  1730. bus->rx_badhdr++;
  1731. brcmf_sdbrcm_rxfail(bus, false, false);
  1732. continue;
  1733. }
  1734. /* Validate frame length */
  1735. if (len < SDPCM_HDRLEN) {
  1736. brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
  1737. continue;
  1738. }
  1739. /* Extract software header fields */
  1740. chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1741. seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1742. doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1743. txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1744. /* Validate data offset */
  1745. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1746. brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
  1747. doff, len, SDPCM_HDRLEN, seq);
  1748. bus->rx_badhdr++;
  1749. brcmf_sdbrcm_rxfail(bus, false, false);
  1750. continue;
  1751. }
  1752. /* Save the readahead length if there is one */
  1753. bus->nextlen =
  1754. bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1755. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1756. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1757. bus->nextlen, seq);
  1758. bus->nextlen = 0;
  1759. }
  1760. /* Handle Flow Control */
  1761. fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1762. if (bus->flowcontrol != fcbits) {
  1763. if (~bus->flowcontrol & fcbits)
  1764. bus->fc_xoff++;
  1765. if (bus->flowcontrol & ~fcbits)
  1766. bus->fc_xon++;
  1767. bus->fc_rcvd++;
  1768. bus->flowcontrol = fcbits;
  1769. }
  1770. /* Check and update sequence number */
  1771. if (rxseq != seq) {
  1772. brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
  1773. bus->rx_badseq++;
  1774. rxseq = seq;
  1775. }
  1776. /* Check window for sanity */
  1777. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1778. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1779. txmax, bus->tx_seq);
  1780. txmax = bus->tx_seq + 2;
  1781. }
  1782. bus->tx_max = txmax;
  1783. /* Call a separate function for control frames */
  1784. if (chan == SDPCM_CONTROL_CHANNEL) {
  1785. brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
  1786. continue;
  1787. }
  1788. /* precondition: chan is either SDPCM_DATA_CHANNEL,
  1789. SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
  1790. SDPCM_GLOM_CHANNEL */
  1791. /* Length to read */
  1792. rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
  1793. /* May pad read to blocksize for efficiency */
  1794. if (bus->roundup && bus->blocksize &&
  1795. (rdlen > bus->blocksize)) {
  1796. pad = bus->blocksize - (rdlen % bus->blocksize);
  1797. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1798. ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
  1799. rdlen += pad;
  1800. } else if (rdlen % BRCMF_SDALIGN) {
  1801. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1802. }
  1803. /* Satisfy length-alignment requirements */
  1804. if (rdlen & (ALIGNMENT - 1))
  1805. rdlen = roundup(rdlen, ALIGNMENT);
  1806. if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
  1807. /* Too long -- skip this frame */
  1808. brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
  1809. len, rdlen);
  1810. bus->drvr->rx_errors++;
  1811. bus->rx_toolong++;
  1812. brcmf_sdbrcm_rxfail(bus, false, false);
  1813. continue;
  1814. }
  1815. pkt = brcmu_pkt_buf_get_skb(rdlen +
  1816. BRCMF_FIRSTREAD + BRCMF_SDALIGN);
  1817. if (!pkt) {
  1818. /* Give up on data, request rtx of events */
  1819. brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
  1820. rdlen, chan);
  1821. bus->drvr->rx_dropped++;
  1822. brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
  1823. continue;
  1824. }
  1825. /* Leave room for what we already read, and align remainder */
  1826. skb_pull(pkt, BRCMF_FIRSTREAD);
  1827. pkt_align(pkt, rdlen, BRCMF_SDALIGN);
  1828. /* Read the remaining frame data */
  1829. sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
  1830. SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
  1831. rdlen, pkt);
  1832. bus->f2rxdata++;
  1833. if (sdret < 0) {
  1834. brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
  1835. ((chan == SDPCM_EVENT_CHANNEL) ? "event"
  1836. : ((chan == SDPCM_DATA_CHANNEL) ? "data"
  1837. : "test")), sdret);
  1838. brcmu_pkt_buf_free_skb(pkt);
  1839. bus->drvr->rx_errors++;
  1840. brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
  1841. continue;
  1842. }
  1843. /* Copy the already-read portion */
  1844. skb_push(pkt, BRCMF_FIRSTREAD);
  1845. memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
  1846. #ifdef BCMDBG
  1847. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1848. printk(KERN_DEBUG "Rx Data:\n");
  1849. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1850. pkt->data, len);
  1851. }
  1852. #endif
  1853. deliver:
  1854. /* Save superframe descriptor and allocate packet frame */
  1855. if (chan == SDPCM_GLOM_CHANNEL) {
  1856. if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
  1857. brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
  1858. len);
  1859. #ifdef BCMDBG
  1860. if (BRCMF_GLOM_ON()) {
  1861. printk(KERN_DEBUG "Glom Data:\n");
  1862. print_hex_dump_bytes("",
  1863. DUMP_PREFIX_OFFSET,
  1864. pkt->data, len);
  1865. }
  1866. #endif
  1867. __skb_trim(pkt, len);
  1868. skb_pull(pkt, SDPCM_HDRLEN);
  1869. bus->glomd = pkt;
  1870. } else {
  1871. brcmf_dbg(ERROR, "%s: glom superframe w/o "
  1872. "descriptor!\n", __func__);
  1873. brcmf_sdbrcm_rxfail(bus, false, false);
  1874. }
  1875. continue;
  1876. }
  1877. /* Fill in packet len and prio, deliver upward */
  1878. __skb_trim(pkt, len);
  1879. skb_pull(pkt, doff);
  1880. if (pkt->len == 0) {
  1881. brcmu_pkt_buf_free_skb(pkt);
  1882. continue;
  1883. } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
  1884. brcmf_dbg(ERROR, "rx protocol error\n");
  1885. brcmu_pkt_buf_free_skb(pkt);
  1886. bus->drvr->rx_errors++;
  1887. continue;
  1888. }
  1889. /* Unlock during rx call */
  1890. up(&bus->sdsem);
  1891. brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
  1892. down(&bus->sdsem);
  1893. }
  1894. rxcount = maxframes - rxleft;
  1895. #ifdef BCMDBG
  1896. /* Message if we hit the limit */
  1897. if (!rxleft)
  1898. brcmf_dbg(DATA, "hit rx limit of %d frames\n",
  1899. maxframes);
  1900. else
  1901. #endif /* BCMDBG */
  1902. brcmf_dbg(DATA, "processed %d frames\n", rxcount);
  1903. /* Back off rxseq if awaiting rtx, update rx_seq */
  1904. if (bus->rxskip)
  1905. rxseq--;
  1906. bus->rx_seq = rxseq;
  1907. return rxcount;
  1908. }
  1909. static int
  1910. brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
  1911. u8 *buf, uint nbytes, struct sk_buff *pkt)
  1912. {
  1913. return brcmf_sdcard_send_buf
  1914. (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
  1915. }
  1916. static void
  1917. brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
  1918. {
  1919. up(&bus->sdsem);
  1920. wait_event_interruptible_timeout(bus->ctrl_wait,
  1921. (*lockvar == false), HZ * 2);
  1922. down(&bus->sdsem);
  1923. return;
  1924. }
  1925. static void
  1926. brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
  1927. {
  1928. if (waitqueue_active(&bus->ctrl_wait))
  1929. wake_up_interruptible(&bus->ctrl_wait);
  1930. return;
  1931. }
  1932. /* Writes a HW/SW header into the packet and sends it. */
  1933. /* Assumes: (a) header space already there, (b) caller holds lock */
  1934. static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
  1935. uint chan, bool free_pkt)
  1936. {
  1937. int ret;
  1938. u8 *frame;
  1939. u16 len, pad = 0;
  1940. u32 swheader;
  1941. struct sk_buff *new;
  1942. int i;
  1943. brcmf_dbg(TRACE, "Enter\n");
  1944. frame = (u8 *) (pkt->data);
  1945. /* Add alignment padding, allocate new packet if needed */
  1946. pad = ((unsigned long)frame % BRCMF_SDALIGN);
  1947. if (pad) {
  1948. if (skb_headroom(pkt) < pad) {
  1949. brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
  1950. skb_headroom(pkt), pad);
  1951. bus->drvr->tx_realloc++;
  1952. new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
  1953. if (!new) {
  1954. brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
  1955. pkt->len + BRCMF_SDALIGN);
  1956. ret = -ENOMEM;
  1957. goto done;
  1958. }
  1959. pkt_align(new, pkt->len, BRCMF_SDALIGN);
  1960. memcpy(new->data, pkt->data, pkt->len);
  1961. if (free_pkt)
  1962. brcmu_pkt_buf_free_skb(pkt);
  1963. /* free the pkt if canned one is not used */
  1964. free_pkt = true;
  1965. pkt = new;
  1966. frame = (u8 *) (pkt->data);
  1967. /* precondition: (frame % BRCMF_SDALIGN) == 0) */
  1968. pad = 0;
  1969. } else {
  1970. skb_push(pkt, pad);
  1971. frame = (u8 *) (pkt->data);
  1972. /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
  1973. memset(frame, 0, pad + SDPCM_HDRLEN);
  1974. }
  1975. }
  1976. /* precondition: pad < BRCMF_SDALIGN */
  1977. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  1978. len = (u16) (pkt->len);
  1979. *(__le16 *) frame = cpu_to_le16(len);
  1980. *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
  1981. /* Software tag: channel, sequence number, data offset */
  1982. swheader =
  1983. ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
  1984. (((pad +
  1985. SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
  1986. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  1987. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  1988. #ifdef BCMDBG
  1989. tx_packets[pkt->priority]++;
  1990. if (BRCMF_BYTES_ON() &&
  1991. (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
  1992. (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
  1993. printk(KERN_DEBUG "Tx Frame:\n");
  1994. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
  1995. } else if (BRCMF_HDRS_ON()) {
  1996. printk(KERN_DEBUG "TxHdr:\n");
  1997. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1998. frame, min_t(u16, len, 16));
  1999. }
  2000. #endif
  2001. /* Raise len to next SDIO block to eliminate tail command */
  2002. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  2003. u16 pad = bus->blocksize - (len % bus->blocksize);
  2004. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  2005. len += pad;
  2006. } else if (len % BRCMF_SDALIGN) {
  2007. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  2008. }
  2009. /* Some controllers have trouble with odd bytes -- round to even */
  2010. if (len & (ALIGNMENT - 1))
  2011. len = roundup(len, ALIGNMENT);
  2012. ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
  2013. SDIO_FUNC_2, F2SYNC, frame,
  2014. len, pkt);
  2015. bus->f2txdata++;
  2016. if (ret < 0) {
  2017. /* On failure, abort the command and terminate the frame */
  2018. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2019. ret);
  2020. bus->tx_sderrs++;
  2021. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2022. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2023. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  2024. NULL);
  2025. bus->f1regdata++;
  2026. for (i = 0; i < 3; i++) {
  2027. u8 hi, lo;
  2028. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  2029. SDIO_FUNC_1,
  2030. SBSDIO_FUNC1_WFRAMEBCHI,
  2031. NULL);
  2032. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  2033. SDIO_FUNC_1,
  2034. SBSDIO_FUNC1_WFRAMEBCLO,
  2035. NULL);
  2036. bus->f1regdata += 2;
  2037. if ((hi == 0) && (lo == 0))
  2038. break;
  2039. }
  2040. }
  2041. if (ret == 0)
  2042. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2043. done:
  2044. /* restore pkt buffer pointer before calling tx complete routine */
  2045. skb_pull(pkt, SDPCM_HDRLEN + pad);
  2046. up(&bus->sdsem);
  2047. brcmf_txcomplete(bus->drvr, pkt, ret != 0);
  2048. down(&bus->sdsem);
  2049. if (free_pkt)
  2050. brcmu_pkt_buf_free_skb(pkt);
  2051. return ret;
  2052. }
  2053. static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
  2054. {
  2055. struct sk_buff *pkt;
  2056. u32 intstatus = 0;
  2057. uint retries = 0;
  2058. int ret = 0, prec_out;
  2059. uint cnt = 0;
  2060. uint datalen;
  2061. u8 tx_prec_map;
  2062. struct brcmf_pub *drvr = bus->drvr;
  2063. brcmf_dbg(TRACE, "Enter\n");
  2064. tx_prec_map = ~bus->flowcontrol;
  2065. /* Send frames until the limit or some other event */
  2066. for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
  2067. spin_lock_bh(&bus->txqlock);
  2068. pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
  2069. if (pkt == NULL) {
  2070. spin_unlock_bh(&bus->txqlock);
  2071. break;
  2072. }
  2073. spin_unlock_bh(&bus->txqlock);
  2074. datalen = pkt->len - SDPCM_HDRLEN;
  2075. ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
  2076. if (ret)
  2077. bus->drvr->tx_errors++;
  2078. else
  2079. bus->drvr->dstats.tx_bytes += datalen;
  2080. /* In poll mode, need to check for other events */
  2081. if (!bus->intr && cnt) {
  2082. /* Check device status, signal pending interrupt */
  2083. r_sdreg32(bus, &intstatus,
  2084. offsetof(struct sdpcmd_regs, intstatus),
  2085. &retries);
  2086. bus->f2txdata++;
  2087. if (brcmf_sdcard_regfail(bus->sdiodev))
  2088. break;
  2089. if (intstatus & bus->hostintmask)
  2090. bus->ipend = true;
  2091. }
  2092. }
  2093. /* Deflow-control stack if needed */
  2094. if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
  2095. drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
  2096. brcmf_txflowcontrol(drvr, 0, OFF);
  2097. return cnt;
  2098. }
  2099. static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
  2100. {
  2101. u32 intstatus, newstatus = 0;
  2102. uint retries = 0;
  2103. uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
  2104. uint txlimit = bus->txbound; /* Tx frames to send before resched */
  2105. uint framecnt = 0; /* Temporary counter of tx/rx frames */
  2106. bool rxdone = true; /* Flag for no more read data */
  2107. bool resched = false; /* Flag indicating resched wanted */
  2108. brcmf_dbg(TRACE, "Enter\n");
  2109. /* Start with leftover status bits */
  2110. intstatus = bus->intstatus;
  2111. down(&bus->sdsem);
  2112. /* If waiting for HTAVAIL, check status */
  2113. if (bus->clkstate == CLK_PENDING) {
  2114. int err;
  2115. u8 clkctl, devctl = 0;
  2116. #ifdef BCMDBG
  2117. /* Check for inconsistent device control */
  2118. devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2119. SBSDIO_DEVICE_CTL, &err);
  2120. if (err) {
  2121. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
  2122. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2123. }
  2124. #endif /* BCMDBG */
  2125. /* Read CSR, if clock on switch to AVAIL, else ignore */
  2126. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2127. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2128. if (err) {
  2129. brcmf_dbg(ERROR, "error reading CSR: %d\n",
  2130. err);
  2131. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2132. }
  2133. brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
  2134. devctl, clkctl);
  2135. if (SBSDIO_HTAV(clkctl)) {
  2136. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  2137. SDIO_FUNC_1,
  2138. SBSDIO_DEVICE_CTL, &err);
  2139. if (err) {
  2140. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
  2141. err);
  2142. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2143. }
  2144. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  2145. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2146. SBSDIO_DEVICE_CTL, devctl, &err);
  2147. if (err) {
  2148. brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
  2149. err);
  2150. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2151. }
  2152. bus->clkstate = CLK_AVAIL;
  2153. } else {
  2154. goto clkwait;
  2155. }
  2156. }
  2157. bus_wake(bus);
  2158. /* Make sure backplane clock is on */
  2159. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
  2160. if (bus->clkstate == CLK_PENDING)
  2161. goto clkwait;
  2162. /* Pending interrupt indicates new device status */
  2163. if (bus->ipend) {
  2164. bus->ipend = false;
  2165. r_sdreg32(bus, &newstatus,
  2166. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2167. bus->f1regdata++;
  2168. if (brcmf_sdcard_regfail(bus->sdiodev))
  2169. newstatus = 0;
  2170. newstatus &= bus->hostintmask;
  2171. bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
  2172. if (newstatus) {
  2173. w_sdreg32(bus, newstatus,
  2174. offsetof(struct sdpcmd_regs, intstatus),
  2175. &retries);
  2176. bus->f1regdata++;
  2177. }
  2178. }
  2179. /* Merge new bits with previous */
  2180. intstatus |= newstatus;
  2181. bus->intstatus = 0;
  2182. /* Handle flow-control change: read new state in case our ack
  2183. * crossed another change interrupt. If change still set, assume
  2184. * FC ON for safety, let next loop through do the debounce.
  2185. */
  2186. if (intstatus & I_HMB_FC_CHANGE) {
  2187. intstatus &= ~I_HMB_FC_CHANGE;
  2188. w_sdreg32(bus, I_HMB_FC_CHANGE,
  2189. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2190. r_sdreg32(bus, &newstatus,
  2191. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2192. bus->f1regdata += 2;
  2193. bus->fcstate =
  2194. !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
  2195. intstatus |= (newstatus & bus->hostintmask);
  2196. }
  2197. /* Handle host mailbox indication */
  2198. if (intstatus & I_HMB_HOST_INT) {
  2199. intstatus &= ~I_HMB_HOST_INT;
  2200. intstatus |= brcmf_sdbrcm_hostmail(bus);
  2201. }
  2202. /* Generally don't ask for these, can get CRC errors... */
  2203. if (intstatus & I_WR_OOSYNC) {
  2204. brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
  2205. intstatus &= ~I_WR_OOSYNC;
  2206. }
  2207. if (intstatus & I_RD_OOSYNC) {
  2208. brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
  2209. intstatus &= ~I_RD_OOSYNC;
  2210. }
  2211. if (intstatus & I_SBINT) {
  2212. brcmf_dbg(ERROR, "Dongle reports SBINT\n");
  2213. intstatus &= ~I_SBINT;
  2214. }
  2215. /* Would be active due to wake-wlan in gSPI */
  2216. if (intstatus & I_CHIPACTIVE) {
  2217. brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
  2218. intstatus &= ~I_CHIPACTIVE;
  2219. }
  2220. /* Ignore frame indications if rxskip is set */
  2221. if (bus->rxskip)
  2222. intstatus &= ~I_HMB_FRAME_IND;
  2223. /* On frame indication, read available frames */
  2224. if (PKT_AVAILABLE()) {
  2225. framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
  2226. if (rxdone || bus->rxskip)
  2227. intstatus &= ~I_HMB_FRAME_IND;
  2228. rxlimit -= min(framecnt, rxlimit);
  2229. }
  2230. /* Keep still-pending events for next scheduling */
  2231. bus->intstatus = intstatus;
  2232. clkwait:
  2233. if (data_ok(bus) && bus->ctrl_frame_stat &&
  2234. (bus->clkstate == CLK_AVAIL)) {
  2235. int ret, i;
  2236. ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
  2237. SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
  2238. (u32) bus->ctrl_frame_len, NULL);
  2239. if (ret < 0) {
  2240. /* On failure, abort the command and
  2241. terminate the frame */
  2242. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2243. ret);
  2244. bus->tx_sderrs++;
  2245. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2246. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2247. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  2248. NULL);
  2249. bus->f1regdata++;
  2250. for (i = 0; i < 3; i++) {
  2251. u8 hi, lo;
  2252. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  2253. SDIO_FUNC_1,
  2254. SBSDIO_FUNC1_WFRAMEBCHI,
  2255. NULL);
  2256. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  2257. SDIO_FUNC_1,
  2258. SBSDIO_FUNC1_WFRAMEBCLO,
  2259. NULL);
  2260. bus->f1regdata += 2;
  2261. if ((hi == 0) && (lo == 0))
  2262. break;
  2263. }
  2264. }
  2265. if (ret == 0)
  2266. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2267. brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
  2268. bus->ctrl_frame_stat = false;
  2269. brcmf_sdbrcm_wait_event_wakeup(bus);
  2270. }
  2271. /* Send queued frames (limit 1 if rx may still be pending) */
  2272. else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
  2273. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
  2274. && data_ok(bus)) {
  2275. framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
  2276. framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
  2277. txlimit -= framecnt;
  2278. }
  2279. /* Resched if events or tx frames are pending,
  2280. else await next interrupt */
  2281. /* On failed register access, all bets are off:
  2282. no resched or interrupts */
  2283. if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
  2284. brcmf_sdcard_regfail(bus->sdiodev)) {
  2285. brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
  2286. brcmf_sdcard_regfail(bus->sdiodev));
  2287. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2288. bus->intstatus = 0;
  2289. } else if (bus->clkstate == CLK_PENDING) {
  2290. brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
  2291. resched = true;
  2292. } else if (bus->intstatus || bus->ipend ||
  2293. (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
  2294. && data_ok(bus)) || PKT_AVAILABLE()) {
  2295. resched = true;
  2296. }
  2297. bus->dpc_sched = resched;
  2298. /* If we're done for now, turn off clock request. */
  2299. if ((bus->clkstate != CLK_PENDING)
  2300. && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
  2301. bus->activity = false;
  2302. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  2303. }
  2304. up(&bus->sdsem);
  2305. return resched;
  2306. }
  2307. static int brcmf_sdbrcm_dpc_thread(void *data)
  2308. {
  2309. struct brcmf_bus *bus = (struct brcmf_bus *) data;
  2310. allow_signal(SIGTERM);
  2311. /* Run until signal received */
  2312. while (1) {
  2313. if (kthread_should_stop())
  2314. break;
  2315. if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
  2316. /* Call bus dpc unless it indicated down
  2317. (then clean stop) */
  2318. if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
  2319. if (brcmf_sdbrcm_dpc(bus))
  2320. complete(&bus->dpc_wait);
  2321. } else {
  2322. /* after stopping the bus, exit thread */
  2323. brcmf_sdbrcm_bus_stop(bus);
  2324. bus->dpc_tsk = NULL;
  2325. break;
  2326. }
  2327. } else
  2328. break;
  2329. }
  2330. return 0;
  2331. }
  2332. int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
  2333. {
  2334. int ret = -EBADE;
  2335. uint datalen, prec;
  2336. brcmf_dbg(TRACE, "Enter\n");
  2337. datalen = pkt->len;
  2338. /* Add space for the header */
  2339. skb_push(pkt, SDPCM_HDRLEN);
  2340. /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
  2341. prec = prio2prec((pkt->priority & PRIOMASK));
  2342. /* Check for existing queue, current flow-control,
  2343. pending event, or pending clock */
  2344. brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
  2345. bus->fcqueued++;
  2346. /* Priority based enq */
  2347. spin_lock_bh(&bus->txqlock);
  2348. if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
  2349. skb_pull(pkt, SDPCM_HDRLEN);
  2350. brcmf_txcomplete(bus->drvr, pkt, false);
  2351. brcmu_pkt_buf_free_skb(pkt);
  2352. brcmf_dbg(ERROR, "out of bus->txq !!!\n");
  2353. ret = -ENOSR;
  2354. } else {
  2355. ret = 0;
  2356. }
  2357. spin_unlock_bh(&bus->txqlock);
  2358. if (pktq_len(&bus->txq) >= TXHI)
  2359. brcmf_txflowcontrol(bus->drvr, 0, ON);
  2360. #ifdef BCMDBG
  2361. if (pktq_plen(&bus->txq, prec) > qcount[prec])
  2362. qcount[prec] = pktq_plen(&bus->txq, prec);
  2363. #endif
  2364. /* Schedule DPC if needed to send queued packet(s) */
  2365. if (!bus->dpc_sched) {
  2366. bus->dpc_sched = true;
  2367. if (bus->dpc_tsk)
  2368. complete(&bus->dpc_wait);
  2369. }
  2370. return ret;
  2371. }
  2372. static int
  2373. brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
  2374. uint size)
  2375. {
  2376. int bcmerror = 0;
  2377. u32 sdaddr;
  2378. uint dsize;
  2379. /* Determine initial transfer parameters */
  2380. sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
  2381. if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
  2382. dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
  2383. else
  2384. dsize = size;
  2385. /* Set the backplane window to include the start address */
  2386. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
  2387. if (bcmerror) {
  2388. brcmf_dbg(ERROR, "window change failed\n");
  2389. goto xfer_done;
  2390. }
  2391. /* Do the transfer(s) */
  2392. while (size) {
  2393. brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
  2394. write ? "write" : "read", dsize,
  2395. sdaddr, address & SBSDIO_SBWINDOW_MASK);
  2396. bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
  2397. sdaddr, data, dsize);
  2398. if (bcmerror) {
  2399. brcmf_dbg(ERROR, "membytes transfer failed\n");
  2400. break;
  2401. }
  2402. /* Adjust for next transfer (if any) */
  2403. size -= dsize;
  2404. if (size) {
  2405. data += dsize;
  2406. address += dsize;
  2407. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
  2408. address);
  2409. if (bcmerror) {
  2410. brcmf_dbg(ERROR, "window change failed\n");
  2411. break;
  2412. }
  2413. sdaddr = 0;
  2414. dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
  2415. }
  2416. }
  2417. xfer_done:
  2418. /* Return the window to backplane enumeration space for core access */
  2419. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
  2420. brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
  2421. bus->sdiodev->sbwad);
  2422. return bcmerror;
  2423. }
  2424. #ifdef BCMDBG
  2425. #define CONSOLE_LINE_MAX 192
  2426. static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
  2427. {
  2428. struct brcmf_console *c = &bus->console;
  2429. u8 line[CONSOLE_LINE_MAX], ch;
  2430. u32 n, idx, addr;
  2431. int rv;
  2432. /* Don't do anything until FWREADY updates console address */
  2433. if (bus->console_addr == 0)
  2434. return 0;
  2435. /* Read console log struct */
  2436. addr = bus->console_addr + offsetof(struct rte_console, log_le);
  2437. rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
  2438. sizeof(c->log_le));
  2439. if (rv < 0)
  2440. return rv;
  2441. /* Allocate console buffer (one time only) */
  2442. if (c->buf == NULL) {
  2443. c->bufsize = le32_to_cpu(c->log_le.buf_size);
  2444. c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
  2445. if (c->buf == NULL)
  2446. return -ENOMEM;
  2447. }
  2448. idx = le32_to_cpu(c->log_le.idx);
  2449. /* Protect against corrupt value */
  2450. if (idx > c->bufsize)
  2451. return -EBADE;
  2452. /* Skip reading the console buffer if the index pointer
  2453. has not moved */
  2454. if (idx == c->last)
  2455. return 0;
  2456. /* Read the console buffer */
  2457. addr = le32_to_cpu(c->log_le.buf);
  2458. rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
  2459. if (rv < 0)
  2460. return rv;
  2461. while (c->last != idx) {
  2462. for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
  2463. if (c->last == idx) {
  2464. /* This would output a partial line.
  2465. * Instead, back up
  2466. * the buffer pointer and output this
  2467. * line next time around.
  2468. */
  2469. if (c->last >= n)
  2470. c->last -= n;
  2471. else
  2472. c->last = c->bufsize - n;
  2473. goto break2;
  2474. }
  2475. ch = c->buf[c->last];
  2476. c->last = (c->last + 1) % c->bufsize;
  2477. if (ch == '\n')
  2478. break;
  2479. line[n] = ch;
  2480. }
  2481. if (n > 0) {
  2482. if (line[n - 1] == '\r')
  2483. n--;
  2484. line[n] = 0;
  2485. printk(KERN_DEBUG "CONSOLE: %s\n", line);
  2486. }
  2487. }
  2488. break2:
  2489. return 0;
  2490. }
  2491. #endif /* BCMDBG */
  2492. static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
  2493. {
  2494. int i;
  2495. int ret;
  2496. bus->ctrl_frame_stat = false;
  2497. ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
  2498. SDIO_FUNC_2, F2SYNC, frame, len, NULL);
  2499. if (ret < 0) {
  2500. /* On failure, abort the command and terminate the frame */
  2501. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2502. ret);
  2503. bus->tx_sderrs++;
  2504. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2505. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2506. SBSDIO_FUNC1_FRAMECTRL,
  2507. SFC_WF_TERM, NULL);
  2508. bus->f1regdata++;
  2509. for (i = 0; i < 3; i++) {
  2510. u8 hi, lo;
  2511. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2512. SBSDIO_FUNC1_WFRAMEBCHI,
  2513. NULL);
  2514. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2515. SBSDIO_FUNC1_WFRAMEBCLO,
  2516. NULL);
  2517. bus->f1regdata += 2;
  2518. if (hi == 0 && lo == 0)
  2519. break;
  2520. }
  2521. return ret;
  2522. }
  2523. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2524. return ret;
  2525. }
  2526. int
  2527. brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
  2528. {
  2529. u8 *frame;
  2530. u16 len;
  2531. u32 swheader;
  2532. uint retries = 0;
  2533. u8 doff = 0;
  2534. int ret = -1;
  2535. brcmf_dbg(TRACE, "Enter\n");
  2536. /* Back the pointer to make a room for bus header */
  2537. frame = msg - SDPCM_HDRLEN;
  2538. len = (msglen += SDPCM_HDRLEN);
  2539. /* Add alignment padding (optional for ctl frames) */
  2540. doff = ((unsigned long)frame % BRCMF_SDALIGN);
  2541. if (doff) {
  2542. frame -= doff;
  2543. len += doff;
  2544. msglen += doff;
  2545. memset(frame, 0, doff + SDPCM_HDRLEN);
  2546. }
  2547. /* precondition: doff < BRCMF_SDALIGN */
  2548. doff += SDPCM_HDRLEN;
  2549. /* Round send length to next SDIO block */
  2550. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  2551. u16 pad = bus->blocksize - (len % bus->blocksize);
  2552. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  2553. len += pad;
  2554. } else if (len % BRCMF_SDALIGN) {
  2555. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  2556. }
  2557. /* Satisfy length-alignment requirements */
  2558. if (len & (ALIGNMENT - 1))
  2559. len = roundup(len, ALIGNMENT);
  2560. /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
  2561. /* Need to lock here to protect txseq and SDIO tx calls */
  2562. down(&bus->sdsem);
  2563. bus_wake(bus);
  2564. /* Make sure backplane clock is on */
  2565. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2566. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  2567. *(__le16 *) frame = cpu_to_le16((u16) msglen);
  2568. *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
  2569. /* Software tag: channel, sequence number, data offset */
  2570. swheader =
  2571. ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
  2572. SDPCM_CHANNEL_MASK)
  2573. | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
  2574. SDPCM_DOFFSET_MASK);
  2575. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  2576. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  2577. if (!data_ok(bus)) {
  2578. brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
  2579. bus->tx_max, bus->tx_seq);
  2580. bus->ctrl_frame_stat = true;
  2581. /* Send from dpc */
  2582. bus->ctrl_frame_buf = frame;
  2583. bus->ctrl_frame_len = len;
  2584. brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
  2585. if (bus->ctrl_frame_stat == false) {
  2586. brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
  2587. ret = 0;
  2588. } else {
  2589. brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
  2590. ret = -1;
  2591. }
  2592. }
  2593. if (ret == -1) {
  2594. #ifdef BCMDBG
  2595. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  2596. printk(KERN_DEBUG "Tx Frame:\n");
  2597. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2598. frame, len);
  2599. } else if (BRCMF_HDRS_ON()) {
  2600. printk(KERN_DEBUG "TxHdr:\n");
  2601. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2602. frame, min_t(u16, len, 16));
  2603. }
  2604. #endif
  2605. do {
  2606. ret = brcmf_tx_frame(bus, frame, len);
  2607. } while (ret < 0 && retries++ < TXRETRIES);
  2608. }
  2609. if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
  2610. bus->activity = false;
  2611. brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
  2612. }
  2613. up(&bus->sdsem);
  2614. if (ret)
  2615. bus->drvr->tx_ctlerrs++;
  2616. else
  2617. bus->drvr->tx_ctlpkts++;
  2618. return ret ? -EIO : 0;
  2619. }
  2620. int
  2621. brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
  2622. {
  2623. int timeleft;
  2624. uint rxlen = 0;
  2625. bool pending;
  2626. brcmf_dbg(TRACE, "Enter\n");
  2627. /* Wait until control frame is available */
  2628. timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
  2629. down(&bus->sdsem);
  2630. rxlen = bus->rxlen;
  2631. memcpy(msg, bus->rxctl, min(msglen, rxlen));
  2632. bus->rxlen = 0;
  2633. up(&bus->sdsem);
  2634. if (rxlen) {
  2635. brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
  2636. rxlen, msglen);
  2637. } else if (timeleft == 0) {
  2638. brcmf_dbg(ERROR, "resumed on timeout\n");
  2639. } else if (pending == true) {
  2640. brcmf_dbg(CTL, "cancelled\n");
  2641. return -ERESTARTSYS;
  2642. } else {
  2643. brcmf_dbg(CTL, "resumed for unknown reason?\n");
  2644. }
  2645. if (rxlen)
  2646. bus->drvr->rx_ctlpkts++;
  2647. else
  2648. bus->drvr->rx_ctlerrs++;
  2649. return rxlen ? (int)rxlen : -ETIMEDOUT;
  2650. }
  2651. static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
  2652. {
  2653. int bcmerror = 0;
  2654. brcmf_dbg(TRACE, "Enter\n");
  2655. /* Basic sanity checks */
  2656. if (bus->drvr->up) {
  2657. bcmerror = -EISCONN;
  2658. goto err;
  2659. }
  2660. if (!len) {
  2661. bcmerror = -EOVERFLOW;
  2662. goto err;
  2663. }
  2664. /* Free the old ones and replace with passed variables */
  2665. kfree(bus->vars);
  2666. bus->vars = kmalloc(len, GFP_ATOMIC);
  2667. bus->varsz = bus->vars ? len : 0;
  2668. if (bus->vars == NULL) {
  2669. bcmerror = -ENOMEM;
  2670. goto err;
  2671. }
  2672. /* Copy the passed variables, which should include the
  2673. terminating double-null */
  2674. memcpy(bus->vars, arg, bus->varsz);
  2675. err:
  2676. return bcmerror;
  2677. }
  2678. static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
  2679. {
  2680. int bcmerror = 0;
  2681. u32 varsize;
  2682. u32 varaddr;
  2683. u8 *vbuffer;
  2684. u32 varsizew;
  2685. __le32 varsizew_le;
  2686. #ifdef BCMDBG
  2687. char *nvram_ularray;
  2688. #endif /* BCMDBG */
  2689. /* Even if there are no vars are to be written, we still
  2690. need to set the ramsize. */
  2691. varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
  2692. varaddr = (bus->ramsize - 4) - varsize;
  2693. if (bus->vars) {
  2694. vbuffer = kzalloc(varsize, GFP_ATOMIC);
  2695. if (!vbuffer)
  2696. return -ENOMEM;
  2697. memcpy(vbuffer, bus->vars, bus->varsz);
  2698. /* Write the vars list */
  2699. bcmerror =
  2700. brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
  2701. #ifdef BCMDBG
  2702. /* Verify NVRAM bytes */
  2703. brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
  2704. nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
  2705. if (!nvram_ularray)
  2706. return -ENOMEM;
  2707. /* Upload image to verify downloaded contents. */
  2708. memset(nvram_ularray, 0xaa, varsize);
  2709. /* Read the vars list to temp buffer for comparison */
  2710. bcmerror =
  2711. brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
  2712. varsize);
  2713. if (bcmerror) {
  2714. brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
  2715. bcmerror, varsize, varaddr);
  2716. }
  2717. /* Compare the org NVRAM with the one read from RAM */
  2718. if (memcmp(vbuffer, nvram_ularray, varsize))
  2719. brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
  2720. else
  2721. brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
  2722. kfree(nvram_ularray);
  2723. #endif /* BCMDBG */
  2724. kfree(vbuffer);
  2725. }
  2726. /* adjust to the user specified RAM */
  2727. brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
  2728. brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
  2729. varaddr, varsize);
  2730. varsize = ((bus->ramsize - 4) - varaddr);
  2731. /*
  2732. * Determine the length token:
  2733. * Varsize, converted to words, in lower 16-bits, checksum
  2734. * in upper 16-bits.
  2735. */
  2736. if (bcmerror) {
  2737. varsizew = 0;
  2738. varsizew_le = cpu_to_le32(0);
  2739. } else {
  2740. varsizew = varsize / 4;
  2741. varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
  2742. varsizew_le = cpu_to_le32(varsizew);
  2743. }
  2744. brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
  2745. varsize, varsizew);
  2746. /* Write the length token to the last word */
  2747. bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
  2748. (u8 *)&varsizew_le, 4);
  2749. return bcmerror;
  2750. }
  2751. static void
  2752. brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
  2753. {
  2754. u32 regdata;
  2755. regdata = brcmf_sdcard_reg_read(sdiodev,
  2756. CORE_SB(corebase, sbtmstatelow), 4);
  2757. if (regdata & SBTML_RESET)
  2758. return;
  2759. regdata = brcmf_sdcard_reg_read(sdiodev,
  2760. CORE_SB(corebase, sbtmstatelow), 4);
  2761. if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
  2762. /*
  2763. * set target reject and spin until busy is clear
  2764. * (preserve core-specific bits)
  2765. */
  2766. regdata = brcmf_sdcard_reg_read(sdiodev,
  2767. CORE_SB(corebase, sbtmstatelow), 4);
  2768. brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
  2769. 4, regdata | SBTML_REJ);
  2770. regdata = brcmf_sdcard_reg_read(sdiodev,
  2771. CORE_SB(corebase, sbtmstatelow), 4);
  2772. udelay(1);
  2773. SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
  2774. CORE_SB(corebase, sbtmstatehigh), 4) &
  2775. SBTMH_BUSY), 100000);
  2776. regdata = brcmf_sdcard_reg_read(sdiodev,
  2777. CORE_SB(corebase, sbtmstatehigh), 4);
  2778. if (regdata & SBTMH_BUSY)
  2779. brcmf_dbg(ERROR, "ARM core still busy\n");
  2780. regdata = brcmf_sdcard_reg_read(sdiodev,
  2781. CORE_SB(corebase, sbidlow), 4);
  2782. if (regdata & SBIDL_INIT) {
  2783. regdata = brcmf_sdcard_reg_read(sdiodev,
  2784. CORE_SB(corebase, sbimstate), 4) |
  2785. SBIM_RJ;
  2786. brcmf_sdcard_reg_write(sdiodev,
  2787. CORE_SB(corebase, sbimstate), 4,
  2788. regdata);
  2789. regdata = brcmf_sdcard_reg_read(sdiodev,
  2790. CORE_SB(corebase, sbimstate), 4);
  2791. udelay(1);
  2792. SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
  2793. CORE_SB(corebase, sbimstate), 4) &
  2794. SBIM_BY), 100000);
  2795. }
  2796. /* set reset and reject while enabling the clocks */
  2797. brcmf_sdcard_reg_write(sdiodev,
  2798. CORE_SB(corebase, sbtmstatelow), 4,
  2799. (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
  2800. SBTML_REJ | SBTML_RESET));
  2801. regdata = brcmf_sdcard_reg_read(sdiodev,
  2802. CORE_SB(corebase, sbtmstatelow), 4);
  2803. udelay(10);
  2804. /* clear the initiator reject bit */
  2805. regdata = brcmf_sdcard_reg_read(sdiodev,
  2806. CORE_SB(corebase, sbidlow), 4);
  2807. if (regdata & SBIDL_INIT) {
  2808. regdata = brcmf_sdcard_reg_read(sdiodev,
  2809. CORE_SB(corebase, sbimstate), 4) &
  2810. ~SBIM_RJ;
  2811. brcmf_sdcard_reg_write(sdiodev,
  2812. CORE_SB(corebase, sbimstate), 4,
  2813. regdata);
  2814. }
  2815. }
  2816. /* leave reset and reject asserted */
  2817. brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
  2818. (SBTML_REJ | SBTML_RESET));
  2819. udelay(1);
  2820. }
  2821. static void
  2822. brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
  2823. {
  2824. u32 regdata;
  2825. /*
  2826. * Must do the disable sequence first to work for
  2827. * arbitrary current core state.
  2828. */
  2829. brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
  2830. /*
  2831. * Now do the initialization sequence.
  2832. * set reset while enabling the clock and
  2833. * forcing them on throughout the core
  2834. */
  2835. brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
  2836. ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
  2837. SBTML_RESET);
  2838. udelay(1);
  2839. regdata = brcmf_sdcard_reg_read(sdiodev,
  2840. CORE_SB(corebase, sbtmstatehigh), 4);
  2841. if (regdata & SBTMH_SERR)
  2842. brcmf_sdcard_reg_write(sdiodev,
  2843. CORE_SB(corebase, sbtmstatehigh), 4, 0);
  2844. regdata = brcmf_sdcard_reg_read(sdiodev,
  2845. CORE_SB(corebase, sbimstate), 4);
  2846. if (regdata & (SBIM_IBE | SBIM_TO))
  2847. brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
  2848. regdata & ~(SBIM_IBE | SBIM_TO));
  2849. /* clear reset and allow it to propagate throughout the core */
  2850. brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
  2851. (SICF_FGC << SBTML_SICF_SHIFT) |
  2852. (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
  2853. udelay(1);
  2854. /* leave clock enabled */
  2855. brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
  2856. (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
  2857. udelay(1);
  2858. }
  2859. static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
  2860. {
  2861. uint retries;
  2862. u32 regdata;
  2863. int bcmerror = 0;
  2864. /* To enter download state, disable ARM and reset SOCRAM.
  2865. * To exit download state, simply reset ARM (default is RAM boot).
  2866. */
  2867. if (enter) {
  2868. bus->alp_only = true;
  2869. brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
  2870. bus->ci->armcorebase);
  2871. brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
  2872. /* Clear the top bit of memory */
  2873. if (bus->ramsize) {
  2874. u32 zeros = 0;
  2875. brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
  2876. (u8 *)&zeros, 4);
  2877. }
  2878. } else {
  2879. regdata = brcmf_sdcard_reg_read(bus->sdiodev,
  2880. CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
  2881. regdata &= (SBTML_RESET | SBTML_REJ_MASK |
  2882. (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
  2883. if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
  2884. brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
  2885. bcmerror = -EBADE;
  2886. goto fail;
  2887. }
  2888. bcmerror = brcmf_sdbrcm_write_vars(bus);
  2889. if (bcmerror) {
  2890. brcmf_dbg(ERROR, "no vars written to RAM\n");
  2891. bcmerror = 0;
  2892. }
  2893. w_sdreg32(bus, 0xFFFFFFFF,
  2894. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2895. brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
  2896. /* Allow HT Clock now that the ARM is running. */
  2897. bus->alp_only = false;
  2898. bus->drvr->busstate = BRCMF_BUS_LOAD;
  2899. }
  2900. fail:
  2901. return bcmerror;
  2902. }
  2903. static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
  2904. {
  2905. if (bus->firmware->size < bus->fw_ptr + len)
  2906. len = bus->firmware->size - bus->fw_ptr;
  2907. memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
  2908. bus->fw_ptr += len;
  2909. return len;
  2910. }
  2911. MODULE_FIRMWARE(BCM4329_FW_NAME);
  2912. MODULE_FIRMWARE(BCM4329_NV_NAME);
  2913. static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
  2914. {
  2915. int offset = 0;
  2916. uint len;
  2917. u8 *memblock = NULL, *memptr;
  2918. int ret;
  2919. brcmf_dbg(INFO, "Enter\n");
  2920. bus->fw_name = BCM4329_FW_NAME;
  2921. ret = request_firmware(&bus->firmware, bus->fw_name,
  2922. &bus->sdiodev->func[2]->dev);
  2923. if (ret) {
  2924. brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
  2925. return ret;
  2926. }
  2927. bus->fw_ptr = 0;
  2928. memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
  2929. if (memblock == NULL) {
  2930. ret = -ENOMEM;
  2931. goto err;
  2932. }
  2933. if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
  2934. memptr += (BRCMF_SDALIGN -
  2935. ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
  2936. /* Download image */
  2937. while ((len =
  2938. brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
  2939. ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
  2940. if (ret) {
  2941. brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
  2942. ret, MEMBLOCK, offset);
  2943. goto err;
  2944. }
  2945. offset += MEMBLOCK;
  2946. }
  2947. err:
  2948. kfree(memblock);
  2949. release_firmware(bus->firmware);
  2950. bus->fw_ptr = 0;
  2951. return ret;
  2952. }
  2953. /*
  2954. * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
  2955. * and ending in a NUL.
  2956. * Removes carriage returns, empty lines, comment lines, and converts
  2957. * newlines to NULs.
  2958. * Shortens buffer as needed and pads with NULs. End of buffer is marked
  2959. * by two NULs.
  2960. */
  2961. static uint brcmf_process_nvram_vars(char *varbuf, uint len)
  2962. {
  2963. char *dp;
  2964. bool findNewline;
  2965. int column;
  2966. uint buf_len, n;
  2967. dp = varbuf;
  2968. findNewline = false;
  2969. column = 0;
  2970. for (n = 0; n < len; n++) {
  2971. if (varbuf[n] == 0)
  2972. break;
  2973. if (varbuf[n] == '\r')
  2974. continue;
  2975. if (findNewline && varbuf[n] != '\n')
  2976. continue;
  2977. findNewline = false;
  2978. if (varbuf[n] == '#') {
  2979. findNewline = true;
  2980. continue;
  2981. }
  2982. if (varbuf[n] == '\n') {
  2983. if (column == 0)
  2984. continue;
  2985. *dp++ = 0;
  2986. column = 0;
  2987. continue;
  2988. }
  2989. *dp++ = varbuf[n];
  2990. column++;
  2991. }
  2992. buf_len = dp - varbuf;
  2993. while (dp < varbuf + n)
  2994. *dp++ = 0;
  2995. return buf_len;
  2996. }
  2997. static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
  2998. {
  2999. uint len;
  3000. char *memblock = NULL;
  3001. char *bufp;
  3002. int ret;
  3003. bus->nv_name = BCM4329_NV_NAME;
  3004. ret = request_firmware(&bus->firmware, bus->nv_name,
  3005. &bus->sdiodev->func[2]->dev);
  3006. if (ret) {
  3007. brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
  3008. return ret;
  3009. }
  3010. bus->fw_ptr = 0;
  3011. memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
  3012. if (memblock == NULL) {
  3013. ret = -ENOMEM;
  3014. goto err;
  3015. }
  3016. len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
  3017. if (len > 0 && len < MEMBLOCK) {
  3018. bufp = (char *)memblock;
  3019. bufp[len] = 0;
  3020. len = brcmf_process_nvram_vars(bufp, len);
  3021. bufp += len;
  3022. *bufp++ = 0;
  3023. if (len)
  3024. ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
  3025. if (ret)
  3026. brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
  3027. } else {
  3028. brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
  3029. ret = -EIO;
  3030. }
  3031. err:
  3032. kfree(memblock);
  3033. release_firmware(bus->firmware);
  3034. bus->fw_ptr = 0;
  3035. return ret;
  3036. }
  3037. static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
  3038. {
  3039. int bcmerror = -1;
  3040. /* Keep arm in reset */
  3041. if (brcmf_sdbrcm_download_state(bus, true)) {
  3042. brcmf_dbg(ERROR, "error placing ARM core in reset\n");
  3043. goto err;
  3044. }
  3045. /* External image takes precedence if specified */
  3046. if (brcmf_sdbrcm_download_code_file(bus)) {
  3047. brcmf_dbg(ERROR, "dongle image file download failed\n");
  3048. goto err;
  3049. }
  3050. /* External nvram takes precedence if specified */
  3051. if (brcmf_sdbrcm_download_nvram(bus))
  3052. brcmf_dbg(ERROR, "dongle nvram file download failed\n");
  3053. /* Take arm out of reset */
  3054. if (brcmf_sdbrcm_download_state(bus, false)) {
  3055. brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
  3056. goto err;
  3057. }
  3058. bcmerror = 0;
  3059. err:
  3060. return bcmerror;
  3061. }
  3062. static bool
  3063. brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
  3064. {
  3065. bool ret;
  3066. /* Download the firmware */
  3067. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3068. ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
  3069. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  3070. return ret;
  3071. }
  3072. void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
  3073. {
  3074. u32 local_hostintmask;
  3075. u8 saveclk;
  3076. uint retries;
  3077. int err;
  3078. struct sk_buff *cur;
  3079. struct sk_buff *next;
  3080. brcmf_dbg(TRACE, "Enter\n");
  3081. if (bus->watchdog_tsk) {
  3082. send_sig(SIGTERM, bus->watchdog_tsk, 1);
  3083. kthread_stop(bus->watchdog_tsk);
  3084. bus->watchdog_tsk = NULL;
  3085. }
  3086. if (bus->dpc_tsk && bus->dpc_tsk != current) {
  3087. send_sig(SIGTERM, bus->dpc_tsk, 1);
  3088. kthread_stop(bus->dpc_tsk);
  3089. bus->dpc_tsk = NULL;
  3090. }
  3091. down(&bus->sdsem);
  3092. bus_wake(bus);
  3093. /* Enable clock for device interrupts */
  3094. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3095. /* Disable and clear interrupts at the chip level also */
  3096. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
  3097. local_hostintmask = bus->hostintmask;
  3098. bus->hostintmask = 0;
  3099. /* Change our idea of bus state */
  3100. bus->drvr->busstate = BRCMF_BUS_DOWN;
  3101. /* Force clocks on backplane to be sure F2 interrupt propagates */
  3102. saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3103. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3104. if (!err) {
  3105. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3106. SBSDIO_FUNC1_CHIPCLKCSR,
  3107. (saveclk | SBSDIO_FORCE_HT), &err);
  3108. }
  3109. if (err)
  3110. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  3111. /* Turn off the bus (F2), free any pending packets */
  3112. brcmf_dbg(INTR, "disable SDIO interrupts\n");
  3113. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  3114. SDIO_FUNC_ENABLE_1, NULL);
  3115. /* Clear any pending interrupts now that F2 is disabled */
  3116. w_sdreg32(bus, local_hostintmask,
  3117. offsetof(struct sdpcmd_regs, intstatus), &retries);
  3118. /* Turn off the backplane clock (only) */
  3119. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  3120. /* Clear the data packet queues */
  3121. brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
  3122. /* Clear any held glomming stuff */
  3123. if (bus->glomd)
  3124. brcmu_pkt_buf_free_skb(bus->glomd);
  3125. if (!skb_queue_empty(&bus->glom))
  3126. skb_queue_walk_safe(&bus->glom, cur, next) {
  3127. skb_unlink(cur, &bus->glom);
  3128. brcmu_pkt_buf_free_skb(cur);
  3129. }
  3130. /* Clear rx control and wake any waiters */
  3131. bus->rxlen = 0;
  3132. brcmf_sdbrcm_dcmd_resp_wake(bus);
  3133. /* Reset some F2 state stuff */
  3134. bus->rxskip = false;
  3135. bus->tx_seq = bus->rx_seq = 0;
  3136. up(&bus->sdsem);
  3137. }
  3138. int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
  3139. {
  3140. struct brcmf_bus *bus = drvr->bus;
  3141. unsigned long timeout;
  3142. uint retries = 0;
  3143. u8 ready, enable;
  3144. int err, ret = 0;
  3145. u8 saveclk;
  3146. brcmf_dbg(TRACE, "Enter\n");
  3147. /* try to download image and nvram to the dongle */
  3148. if (drvr->busstate == BRCMF_BUS_DOWN) {
  3149. if (!(brcmf_sdbrcm_download_firmware(bus)))
  3150. return -1;
  3151. }
  3152. if (!bus->drvr)
  3153. return 0;
  3154. /* Start the watchdog timer */
  3155. bus->drvr->tickcnt = 0;
  3156. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  3157. down(&bus->sdsem);
  3158. /* Make sure backplane clock is on, needed to generate F2 interrupt */
  3159. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3160. if (bus->clkstate != CLK_AVAIL)
  3161. goto exit;
  3162. /* Force clocks on backplane to be sure F2 interrupt propagates */
  3163. saveclk =
  3164. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3165. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3166. if (!err) {
  3167. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3168. SBSDIO_FUNC1_CHIPCLKCSR,
  3169. (saveclk | SBSDIO_FORCE_HT), &err);
  3170. }
  3171. if (err) {
  3172. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  3173. goto exit;
  3174. }
  3175. /* Enable function 2 (frame transfers) */
  3176. w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
  3177. offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
  3178. enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
  3179. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  3180. enable, NULL);
  3181. timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
  3182. ready = 0;
  3183. while (enable != ready) {
  3184. ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
  3185. SDIO_CCCR_IORx, NULL);
  3186. if (time_after(jiffies, timeout))
  3187. break;
  3188. else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
  3189. /* prevent busy waiting if it takes too long */
  3190. msleep_interruptible(20);
  3191. }
  3192. brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
  3193. /* If F2 successfully enabled, set core and enable interrupts */
  3194. if (ready == enable) {
  3195. /* Set up the interrupt mask and enable interrupts */
  3196. bus->hostintmask = HOSTINTMASK;
  3197. w_sdreg32(bus, bus->hostintmask,
  3198. offsetof(struct sdpcmd_regs, hostintmask), &retries);
  3199. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3200. SBSDIO_WATERMARK, 8, &err);
  3201. /* Set bus state according to enable result */
  3202. drvr->busstate = BRCMF_BUS_DATA;
  3203. }
  3204. else {
  3205. /* Disable F2 again */
  3206. enable = SDIO_FUNC_ENABLE_1;
  3207. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
  3208. SDIO_CCCR_IOEx, enable, NULL);
  3209. }
  3210. /* Restore previous clock setting */
  3211. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3212. SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
  3213. /* If we didn't come up, turn off backplane clock */
  3214. if (drvr->busstate != BRCMF_BUS_DATA)
  3215. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3216. exit:
  3217. up(&bus->sdsem);
  3218. return ret;
  3219. }
  3220. void brcmf_sdbrcm_isr(void *arg)
  3221. {
  3222. struct brcmf_bus *bus = (struct brcmf_bus *) arg;
  3223. brcmf_dbg(TRACE, "Enter\n");
  3224. if (!bus) {
  3225. brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
  3226. return;
  3227. }
  3228. if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
  3229. brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
  3230. return;
  3231. }
  3232. /* Count the interrupt call */
  3233. bus->intrcount++;
  3234. bus->ipend = true;
  3235. /* Shouldn't get this interrupt if we're sleeping? */
  3236. if (bus->sleeping) {
  3237. brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
  3238. return;
  3239. }
  3240. /* Disable additional interrupts (is this needed now)? */
  3241. if (!bus->intr)
  3242. brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
  3243. bus->dpc_sched = true;
  3244. if (bus->dpc_tsk)
  3245. complete(&bus->dpc_wait);
  3246. }
  3247. static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
  3248. {
  3249. struct brcmf_bus *bus;
  3250. brcmf_dbg(TIMER, "Enter\n");
  3251. bus = drvr->bus;
  3252. /* Ignore the timer if simulating bus down */
  3253. if (bus->sleeping)
  3254. return false;
  3255. down(&bus->sdsem);
  3256. /* Poll period: check device if appropriate. */
  3257. if (bus->poll && (++bus->polltick >= bus->pollrate)) {
  3258. u32 intstatus = 0;
  3259. /* Reset poll tick */
  3260. bus->polltick = 0;
  3261. /* Check device if no interrupts */
  3262. if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
  3263. if (!bus->dpc_sched) {
  3264. u8 devpend;
  3265. devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
  3266. SDIO_FUNC_0, SDIO_CCCR_INTx,
  3267. NULL);
  3268. intstatus =
  3269. devpend & (INTR_STATUS_FUNC1 |
  3270. INTR_STATUS_FUNC2);
  3271. }
  3272. /* If there is something, make like the ISR and
  3273. schedule the DPC */
  3274. if (intstatus) {
  3275. bus->pollcnt++;
  3276. bus->ipend = true;
  3277. bus->dpc_sched = true;
  3278. if (bus->dpc_tsk)
  3279. complete(&bus->dpc_wait);
  3280. }
  3281. }
  3282. /* Update interrupt tracking */
  3283. bus->lastintrs = bus->intrcount;
  3284. }
  3285. #ifdef BCMDBG
  3286. /* Poll for console output periodically */
  3287. if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
  3288. bus->console.count += BRCMF_WD_POLL_MS;
  3289. if (bus->console.count >= bus->console_interval) {
  3290. bus->console.count -= bus->console_interval;
  3291. /* Make sure backplane clock is on */
  3292. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3293. if (brcmf_sdbrcm_readconsole(bus) < 0)
  3294. /* stop on error */
  3295. bus->console_interval = 0;
  3296. }
  3297. }
  3298. #endif /* BCMDBG */
  3299. /* On idle timeout clear activity flag and/or turn off clock */
  3300. if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
  3301. if (++bus->idlecount >= bus->idletime) {
  3302. bus->idlecount = 0;
  3303. if (bus->activity) {
  3304. bus->activity = false;
  3305. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  3306. } else {
  3307. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3308. }
  3309. }
  3310. }
  3311. up(&bus->sdsem);
  3312. return bus->ipend;
  3313. }
  3314. static bool brcmf_sdbrcm_chipmatch(u16 chipid)
  3315. {
  3316. if (chipid == BCM4329_CHIP_ID)
  3317. return true;
  3318. return false;
  3319. }
  3320. static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
  3321. {
  3322. brcmf_dbg(TRACE, "Enter\n");
  3323. kfree(bus->rxbuf);
  3324. bus->rxctl = bus->rxbuf = NULL;
  3325. bus->rxlen = 0;
  3326. kfree(bus->databuf);
  3327. bus->databuf = NULL;
  3328. }
  3329. static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
  3330. {
  3331. brcmf_dbg(TRACE, "Enter\n");
  3332. if (bus->drvr->maxctl) {
  3333. bus->rxblen =
  3334. roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
  3335. ALIGNMENT) + BRCMF_SDALIGN;
  3336. bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
  3337. if (!(bus->rxbuf))
  3338. goto fail;
  3339. }
  3340. /* Allocate buffer to receive glomed packet */
  3341. bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
  3342. if (!(bus->databuf)) {
  3343. /* release rxbuf which was already located as above */
  3344. if (!bus->rxblen)
  3345. kfree(bus->rxbuf);
  3346. goto fail;
  3347. }
  3348. /* Align the buffer */
  3349. if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
  3350. bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
  3351. ((unsigned long)bus->databuf % BRCMF_SDALIGN));
  3352. else
  3353. bus->dataptr = bus->databuf;
  3354. return true;
  3355. fail:
  3356. return false;
  3357. }
  3358. /* SDIO Pad drive strength to select value mappings */
  3359. struct sdiod_drive_str {
  3360. u8 strength; /* Pad Drive Strength in mA */
  3361. u8 sel; /* Chip-specific select value */
  3362. };
  3363. /* SDIO Drive Strength to sel value table for PMU Rev 1 */
  3364. static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
  3365. {
  3366. 4, 0x2}, {
  3367. 2, 0x3}, {
  3368. 1, 0x0}, {
  3369. 0, 0x0}
  3370. };
  3371. /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
  3372. static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
  3373. {
  3374. 12, 0x7}, {
  3375. 10, 0x6}, {
  3376. 8, 0x5}, {
  3377. 6, 0x4}, {
  3378. 4, 0x2}, {
  3379. 2, 0x1}, {
  3380. 0, 0x0}
  3381. };
  3382. /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
  3383. static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
  3384. {
  3385. 32, 0x7}, {
  3386. 26, 0x6}, {
  3387. 22, 0x5}, {
  3388. 16, 0x4}, {
  3389. 12, 0x3}, {
  3390. 8, 0x2}, {
  3391. 4, 0x1}, {
  3392. 0, 0x0}
  3393. };
  3394. #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
  3395. static char *brcmf_chipname(uint chipid, char *buf, uint len)
  3396. {
  3397. const char *fmt;
  3398. fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
  3399. snprintf(buf, len, fmt, chipid);
  3400. return buf;
  3401. }
  3402. static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
  3403. u32 drivestrength) {
  3404. struct sdiod_drive_str *str_tab = NULL;
  3405. u32 str_mask = 0;
  3406. u32 str_shift = 0;
  3407. char chn[8];
  3408. if (!(bus->ci->cccaps & CC_CAP_PMU))
  3409. return;
  3410. switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
  3411. case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
  3412. str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
  3413. str_mask = 0x30000000;
  3414. str_shift = 28;
  3415. break;
  3416. case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
  3417. case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
  3418. str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
  3419. str_mask = 0x00003800;
  3420. str_shift = 11;
  3421. break;
  3422. case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
  3423. str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
  3424. str_mask = 0x00003800;
  3425. str_shift = 11;
  3426. break;
  3427. default:
  3428. brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
  3429. brcmf_chipname(bus->ci->chip, chn, 8),
  3430. bus->ci->chiprev, bus->ci->pmurev);
  3431. break;
  3432. }
  3433. if (str_tab != NULL) {
  3434. u32 drivestrength_sel = 0;
  3435. u32 cc_data_temp;
  3436. int i;
  3437. for (i = 0; str_tab[i].strength != 0; i++) {
  3438. if (drivestrength >= str_tab[i].strength) {
  3439. drivestrength_sel = str_tab[i].sel;
  3440. break;
  3441. }
  3442. }
  3443. brcmf_sdcard_reg_write(bus->sdiodev,
  3444. CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
  3445. 4, 1);
  3446. cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
  3447. CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
  3448. cc_data_temp &= ~str_mask;
  3449. drivestrength_sel <<= str_shift;
  3450. cc_data_temp |= drivestrength_sel;
  3451. brcmf_sdcard_reg_write(bus->sdiodev,
  3452. CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
  3453. 4, cc_data_temp);
  3454. brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
  3455. drivestrength, cc_data_temp);
  3456. }
  3457. }
  3458. static int
  3459. brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
  3460. struct chip_info *ci, u32 regs)
  3461. {
  3462. u32 regdata;
  3463. /*
  3464. * Get CC core rev
  3465. * Chipid is assume to be at offset 0 from regs arg
  3466. * For different chiptypes or old sdio hosts w/o chipcommon,
  3467. * other ways of recognition should be added here.
  3468. */
  3469. ci->cccorebase = regs;
  3470. regdata = brcmf_sdcard_reg_read(sdiodev,
  3471. CORE_CC_REG(ci->cccorebase, chipid), 4);
  3472. ci->chip = regdata & CID_ID_MASK;
  3473. ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
  3474. brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
  3475. /* Address of cores for new chips should be added here */
  3476. switch (ci->chip) {
  3477. case BCM4329_CHIP_ID:
  3478. ci->buscorebase = BCM4329_CORE_BUS_BASE;
  3479. ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
  3480. ci->armcorebase = BCM4329_CORE_ARM_BASE;
  3481. ci->ramsize = BCM4329_RAMSIZE;
  3482. break;
  3483. default:
  3484. brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
  3485. return -ENODEV;
  3486. }
  3487. regdata = brcmf_sdcard_reg_read(sdiodev,
  3488. CORE_SB(ci->cccorebase, sbidhigh), 4);
  3489. ci->ccrev = SBCOREREV(regdata);
  3490. regdata = brcmf_sdcard_reg_read(sdiodev,
  3491. CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
  3492. ci->pmurev = regdata & PCAP_REV_MASK;
  3493. regdata = brcmf_sdcard_reg_read(sdiodev,
  3494. CORE_SB(ci->buscorebase, sbidhigh), 4);
  3495. ci->buscorerev = SBCOREREV(regdata);
  3496. ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
  3497. brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
  3498. ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
  3499. /* get chipcommon capabilites */
  3500. ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
  3501. CORE_CC_REG(ci->cccorebase, capabilities), 4);
  3502. return 0;
  3503. }
  3504. static int
  3505. brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
  3506. {
  3507. struct chip_info *ci;
  3508. int err;
  3509. u8 clkval, clkset;
  3510. brcmf_dbg(TRACE, "Enter\n");
  3511. /* alloc chip_info_t */
  3512. ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
  3513. if (NULL == ci)
  3514. return -ENOMEM;
  3515. /* bus/core/clk setup for register access */
  3516. /* Try forcing SDIO core to do ALPAvail request only */
  3517. clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
  3518. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3519. SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
  3520. if (err) {
  3521. brcmf_dbg(ERROR, "error writing for HT off\n");
  3522. goto fail;
  3523. }
  3524. /* If register supported, wait for ALPAvail and then force ALP */
  3525. /* This may take up to 15 milliseconds */
  3526. clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3527. SBSDIO_FUNC1_CHIPCLKCSR, NULL);
  3528. if ((clkval & ~SBSDIO_AVBITS) == clkset) {
  3529. SPINWAIT(((clkval =
  3530. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3531. SBSDIO_FUNC1_CHIPCLKCSR,
  3532. NULL)),
  3533. !SBSDIO_ALPAV(clkval)),
  3534. PMU_MAX_TRANSITION_DLY);
  3535. if (!SBSDIO_ALPAV(clkval)) {
  3536. brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
  3537. clkval);
  3538. err = -EBUSY;
  3539. goto fail;
  3540. }
  3541. clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
  3542. SBSDIO_FORCE_ALP;
  3543. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3544. SBSDIO_FUNC1_CHIPCLKCSR,
  3545. clkset, &err);
  3546. udelay(65);
  3547. } else {
  3548. brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
  3549. clkset, clkval);
  3550. err = -EACCES;
  3551. goto fail;
  3552. }
  3553. /* Also, disable the extra SDIO pull-ups */
  3554. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3555. SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
  3556. err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
  3557. if (err)
  3558. goto fail;
  3559. /*
  3560. * Make sure any on-chip ARM is off (in case strapping is wrong),
  3561. * or downloaded code was already running.
  3562. */
  3563. brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
  3564. brcmf_sdcard_reg_write(bus->sdiodev,
  3565. CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
  3566. brcmf_sdcard_reg_write(bus->sdiodev,
  3567. CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
  3568. /* Disable F2 to clear any intermediate frame state on the dongle */
  3569. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  3570. SDIO_FUNC_ENABLE_1, NULL);
  3571. /* WAR: cmd52 backplane read so core HW will drop ALPReq */
  3572. clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3573. 0, NULL);
  3574. /* Done with backplane-dependent accesses, can drop clock... */
  3575. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3576. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  3577. bus->ci = ci;
  3578. return 0;
  3579. fail:
  3580. bus->ci = NULL;
  3581. kfree(ci);
  3582. return err;
  3583. }
  3584. static bool
  3585. brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
  3586. {
  3587. u8 clkctl = 0;
  3588. int err = 0;
  3589. int reg_addr;
  3590. u32 reg_val;
  3591. bus->alp_only = true;
  3592. /* Return the window to backplane enumeration space for core access */
  3593. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
  3594. brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
  3595. #ifdef BCMDBG
  3596. printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
  3597. brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
  3598. #endif /* BCMDBG */
  3599. /*
  3600. * Force PLL off until brcmf_sdbrcm_chip_attach()
  3601. * programs PLL control regs
  3602. */
  3603. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3604. SBSDIO_FUNC1_CHIPCLKCSR,
  3605. BRCMF_INIT_CLKCTL1, &err);
  3606. if (!err)
  3607. clkctl =
  3608. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3609. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3610. if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
  3611. brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
  3612. err, BRCMF_INIT_CLKCTL1, clkctl);
  3613. goto fail;
  3614. }
  3615. if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
  3616. brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
  3617. goto fail;
  3618. }
  3619. if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
  3620. brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
  3621. goto fail;
  3622. }
  3623. brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH);
  3624. /* Get info on the ARM and SOCRAM cores... */
  3625. brcmf_sdcard_reg_read(bus->sdiodev,
  3626. CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
  3627. bus->ramsize = bus->ci->ramsize;
  3628. if (!(bus->ramsize)) {
  3629. brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
  3630. goto fail;
  3631. }
  3632. /* Set core control so an SDIO reset does a backplane reset */
  3633. reg_addr = bus->ci->buscorebase +
  3634. offsetof(struct sdpcmd_regs, corecontrol);
  3635. reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
  3636. brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
  3637. reg_val | CC_BPRESEN);
  3638. brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
  3639. /* Locate an appropriately-aligned portion of hdrbuf */
  3640. bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
  3641. BRCMF_SDALIGN);
  3642. /* Set the poll and/or interrupt flags */
  3643. bus->intr = true;
  3644. bus->poll = false;
  3645. if (bus->poll)
  3646. bus->pollrate = 1;
  3647. return true;
  3648. fail:
  3649. return false;
  3650. }
  3651. static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
  3652. {
  3653. brcmf_dbg(TRACE, "Enter\n");
  3654. /* Disable F2 to clear any intermediate frame state on the dongle */
  3655. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  3656. SDIO_FUNC_ENABLE_1, NULL);
  3657. bus->drvr->busstate = BRCMF_BUS_DOWN;
  3658. bus->sleeping = false;
  3659. bus->rxflow = false;
  3660. /* Done with backplane-dependent accesses, can drop clock... */
  3661. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3662. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  3663. /* ...and initialize clock/power states */
  3664. bus->clkstate = CLK_SDONLY;
  3665. bus->idletime = BRCMF_IDLE_INTERVAL;
  3666. bus->idleclock = BRCMF_IDLE_ACTIVE;
  3667. /* Query the F2 block size, set roundup accordingly */
  3668. bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
  3669. bus->roundup = min(max_roundup, bus->blocksize);
  3670. /* bus module does not support packet chaining */
  3671. bus->use_rxchain = false;
  3672. bus->sd_rxchain = false;
  3673. return true;
  3674. }
  3675. static int
  3676. brcmf_sdbrcm_watchdog_thread(void *data)
  3677. {
  3678. struct brcmf_bus *bus = (struct brcmf_bus *)data;
  3679. allow_signal(SIGTERM);
  3680. /* Run until signal received */
  3681. while (1) {
  3682. if (kthread_should_stop())
  3683. break;
  3684. if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
  3685. brcmf_sdbrcm_bus_watchdog(bus->drvr);
  3686. /* Count the tick for reference */
  3687. bus->drvr->tickcnt++;
  3688. } else
  3689. break;
  3690. }
  3691. return 0;
  3692. }
  3693. static void
  3694. brcmf_sdbrcm_watchdog(unsigned long data)
  3695. {
  3696. struct brcmf_bus *bus = (struct brcmf_bus *)data;
  3697. if (bus->watchdog_tsk) {
  3698. complete(&bus->watchdog_wait);
  3699. /* Reschedule the watchdog */
  3700. if (bus->wd_timer_valid)
  3701. mod_timer(&bus->timer,
  3702. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3703. }
  3704. }
  3705. static void
  3706. brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
  3707. {
  3708. brcmf_dbg(TRACE, "Enter\n");
  3709. kfree(bus->ci);
  3710. bus->ci = NULL;
  3711. }
  3712. static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
  3713. {
  3714. brcmf_dbg(TRACE, "Enter\n");
  3715. if (bus->ci) {
  3716. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3717. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3718. brcmf_sdbrcm_chip_detach(bus);
  3719. if (bus->vars && bus->varsz)
  3720. kfree(bus->vars);
  3721. bus->vars = NULL;
  3722. }
  3723. brcmf_dbg(TRACE, "Disconnected\n");
  3724. }
  3725. /* Detach and free everything */
  3726. static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
  3727. {
  3728. brcmf_dbg(TRACE, "Enter\n");
  3729. if (bus) {
  3730. /* De-register interrupt handler */
  3731. brcmf_sdcard_intr_dereg(bus->sdiodev);
  3732. if (bus->drvr) {
  3733. brcmf_detach(bus->drvr);
  3734. brcmf_sdbrcm_release_dongle(bus);
  3735. bus->drvr = NULL;
  3736. }
  3737. brcmf_sdbrcm_release_malloc(bus);
  3738. kfree(bus);
  3739. }
  3740. brcmf_dbg(TRACE, "Disconnected\n");
  3741. }
  3742. void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
  3743. u32 regsva, struct brcmf_sdio_dev *sdiodev)
  3744. {
  3745. int ret;
  3746. struct brcmf_bus *bus;
  3747. /* Init global variables at run-time, not as part of the declaration.
  3748. * This is required to support init/de-init of the driver.
  3749. * Initialization
  3750. * of globals as part of the declaration results in non-deterministic
  3751. * behavior since the value of the globals may be different on the
  3752. * first time that the driver is initialized vs subsequent
  3753. * initializations.
  3754. */
  3755. brcmf_c_init();
  3756. brcmf_dbg(TRACE, "Enter\n");
  3757. /* We make an assumption about address window mappings:
  3758. * regsva == SI_ENUM_BASE*/
  3759. /* Allocate private bus interface state */
  3760. bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
  3761. if (!bus)
  3762. goto fail;
  3763. bus->sdiodev = sdiodev;
  3764. sdiodev->bus = bus;
  3765. skb_queue_head_init(&bus->glom);
  3766. bus->txbound = BRCMF_TXBOUND;
  3767. bus->rxbound = BRCMF_RXBOUND;
  3768. bus->txminmax = BRCMF_TXMINMAX;
  3769. bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
  3770. bus->usebufpool = false; /* Use bufpool if allocated,
  3771. else use locally malloced rxbuf */
  3772. /* attempt to attach to the dongle */
  3773. if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
  3774. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
  3775. goto fail;
  3776. }
  3777. spin_lock_init(&bus->txqlock);
  3778. init_waitqueue_head(&bus->ctrl_wait);
  3779. init_waitqueue_head(&bus->dcmd_resp_wait);
  3780. /* Set up the watchdog timer */
  3781. init_timer(&bus->timer);
  3782. bus->timer.data = (unsigned long)bus;
  3783. bus->timer.function = brcmf_sdbrcm_watchdog;
  3784. /* Initialize thread based operation and lock */
  3785. sema_init(&bus->sdsem, 1);
  3786. /* Initialize watchdog thread */
  3787. init_completion(&bus->watchdog_wait);
  3788. bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
  3789. bus, "brcmf_watchdog");
  3790. if (IS_ERR(bus->watchdog_tsk)) {
  3791. printk(KERN_WARNING
  3792. "brcmf_watchdog thread failed to start\n");
  3793. bus->watchdog_tsk = NULL;
  3794. }
  3795. /* Initialize DPC thread */
  3796. init_completion(&bus->dpc_wait);
  3797. bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
  3798. bus, "brcmf_dpc");
  3799. if (IS_ERR(bus->dpc_tsk)) {
  3800. printk(KERN_WARNING
  3801. "brcmf_dpc thread failed to start\n");
  3802. bus->dpc_tsk = NULL;
  3803. }
  3804. /* Attach to the brcmf/OS/network interface */
  3805. bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
  3806. if (!bus->drvr) {
  3807. brcmf_dbg(ERROR, "brcmf_attach failed\n");
  3808. goto fail;
  3809. }
  3810. /* Allocate buffers */
  3811. if (!(brcmf_sdbrcm_probe_malloc(bus))) {
  3812. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
  3813. goto fail;
  3814. }
  3815. if (!(brcmf_sdbrcm_probe_init(bus))) {
  3816. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
  3817. goto fail;
  3818. }
  3819. /* Register interrupt callback, but mask it (not operational yet). */
  3820. brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
  3821. ret = brcmf_sdcard_intr_reg(bus->sdiodev);
  3822. if (ret != 0) {
  3823. brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
  3824. goto fail;
  3825. }
  3826. brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
  3827. brcmf_dbg(INFO, "completed!!\n");
  3828. /* if firmware path present try to download and bring up bus */
  3829. ret = brcmf_bus_start(bus->drvr);
  3830. if (ret != 0) {
  3831. if (ret == -ENOLINK) {
  3832. brcmf_dbg(ERROR, "dongle is not responding\n");
  3833. goto fail;
  3834. }
  3835. }
  3836. /* add interface and open for business */
  3837. if (brcmf_add_if((struct brcmf_info *)bus->drvr, 0, "wlan%d", NULL)) {
  3838. brcmf_dbg(ERROR, "Add primary net device interface failed!!\n");
  3839. goto fail;
  3840. }
  3841. return bus;
  3842. fail:
  3843. brcmf_sdbrcm_release(bus);
  3844. return NULL;
  3845. }
  3846. void brcmf_sdbrcm_disconnect(void *ptr)
  3847. {
  3848. struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
  3849. brcmf_dbg(TRACE, "Enter\n");
  3850. if (bus)
  3851. brcmf_sdbrcm_release(bus);
  3852. brcmf_dbg(TRACE, "Disconnected\n");
  3853. }
  3854. struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
  3855. {
  3856. return &bus->sdiodev->func[2]->dev;
  3857. }
  3858. void
  3859. brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
  3860. {
  3861. /* Totally stop the timer */
  3862. if (!wdtick && bus->wd_timer_valid == true) {
  3863. del_timer_sync(&bus->timer);
  3864. bus->wd_timer_valid = false;
  3865. bus->save_ms = wdtick;
  3866. return;
  3867. }
  3868. /* don't start the wd until fw is loaded */
  3869. if (bus->drvr->busstate == BRCMF_BUS_DOWN)
  3870. return;
  3871. if (wdtick) {
  3872. if (bus->save_ms != BRCMF_WD_POLL_MS) {
  3873. if (bus->wd_timer_valid == true)
  3874. /* Stop timer and restart at new value */
  3875. del_timer_sync(&bus->timer);
  3876. /* Create timer again when watchdog period is
  3877. dynamically changed or in the first instance
  3878. */
  3879. bus->timer.expires =
  3880. jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
  3881. add_timer(&bus->timer);
  3882. } else {
  3883. /* Re arm the timer, at last watchdog period */
  3884. mod_timer(&bus->timer,
  3885. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3886. }
  3887. bus->wd_timer_valid = true;
  3888. bus->save_ms = wdtick;
  3889. }
  3890. }