smp.c 10.0 KB

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  1. /* smp.c: Sparc SMP support.
  2. *
  3. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  4. * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  5. * Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org)
  6. */
  7. #include <asm/head.h>
  8. #include <linux/kernel.h>
  9. #include <linux/sched.h>
  10. #include <linux/threads.h>
  11. #include <linux/smp.h>
  12. #include <linux/smp_lock.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/kernel_stat.h>
  15. #include <linux/init.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/mm.h>
  18. #include <linux/fs.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/cache.h>
  21. #include <linux/delay.h>
  22. #include <asm/ptrace.h>
  23. #include <asm/atomic.h>
  24. #include <asm/irq.h>
  25. #include <asm/page.h>
  26. #include <asm/pgalloc.h>
  27. #include <asm/pgtable.h>
  28. #include <asm/oplib.h>
  29. #include <asm/cacheflush.h>
  30. #include <asm/tlbflush.h>
  31. #include <asm/cpudata.h>
  32. volatile int smp_processors_ready = 0;
  33. int smp_num_cpus = 1;
  34. volatile unsigned long cpu_callin_map[NR_CPUS] __initdata = {0,};
  35. unsigned char boot_cpu_id = 0;
  36. unsigned char boot_cpu_id4 = 0; /* boot_cpu_id << 2 */
  37. int smp_activated = 0;
  38. volatile int __cpu_number_map[NR_CPUS];
  39. volatile int __cpu_logical_map[NR_CPUS];
  40. cpumask_t cpu_online_map = CPU_MASK_NONE;
  41. cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
  42. cpumask_t smp_commenced_mask = CPU_MASK_NONE;
  43. /* The only guaranteed locking primitive available on all Sparc
  44. * processors is 'ldstub [%reg + immediate], %dest_reg' which atomically
  45. * places the current byte at the effective address into dest_reg and
  46. * places 0xff there afterwards. Pretty lame locking primitive
  47. * compared to the Alpha and the Intel no? Most Sparcs have 'swap'
  48. * instruction which is much better...
  49. */
  50. /* Used to make bitops atomic */
  51. unsigned char bitops_spinlock = 0;
  52. void __cpuinit smp_store_cpu_info(int id)
  53. {
  54. int cpu_node;
  55. cpu_data(id).udelay_val = loops_per_jiffy;
  56. cpu_find_by_mid(id, &cpu_node);
  57. cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
  58. "clock-frequency", 0);
  59. cpu_data(id).prom_node = cpu_node;
  60. cpu_data(id).mid = cpu_get_hwmid(cpu_node);
  61. /* this is required to tune the scheduler correctly */
  62. /* is it possible to have CPUs with different cache sizes? */
  63. if (id == boot_cpu_id) {
  64. int cache_line,cache_nlines;
  65. cache_line = 0x20;
  66. cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line);
  67. cache_nlines = 0x8000;
  68. cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines);
  69. max_cache_size = cache_line * cache_nlines;
  70. }
  71. if (cpu_data(id).mid < 0)
  72. panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);
  73. }
  74. void __init smp_cpus_done(unsigned int max_cpus)
  75. {
  76. extern void smp4m_smp_done(void);
  77. extern void smp4d_smp_done(void);
  78. unsigned long bogosum = 0;
  79. int cpu, num;
  80. for (cpu = 0, num = 0; cpu < NR_CPUS; cpu++)
  81. if (cpu_online(cpu)) {
  82. num++;
  83. bogosum += cpu_data(cpu).udelay_val;
  84. }
  85. printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
  86. num, bogosum/(500000/HZ),
  87. (bogosum/(5000/HZ))%100);
  88. switch(sparc_cpu_model) {
  89. case sun4:
  90. printk("SUN4\n");
  91. BUG();
  92. break;
  93. case sun4c:
  94. printk("SUN4C\n");
  95. BUG();
  96. break;
  97. case sun4m:
  98. smp4m_smp_done();
  99. break;
  100. case sun4d:
  101. smp4d_smp_done();
  102. break;
  103. case sun4e:
  104. printk("SUN4E\n");
  105. BUG();
  106. break;
  107. case sun4u:
  108. printk("SUN4U\n");
  109. BUG();
  110. break;
  111. default:
  112. printk("UNKNOWN!\n");
  113. BUG();
  114. break;
  115. };
  116. }
  117. void cpu_panic(void)
  118. {
  119. printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
  120. panic("SMP bolixed\n");
  121. }
  122. struct linux_prom_registers smp_penguin_ctable __initdata = { 0 };
  123. void smp_send_reschedule(int cpu)
  124. {
  125. /* See sparc64 */
  126. }
  127. void smp_send_stop(void)
  128. {
  129. }
  130. void smp_flush_cache_all(void)
  131. {
  132. xc0((smpfunc_t) BTFIXUP_CALL(local_flush_cache_all));
  133. local_flush_cache_all();
  134. }
  135. void smp_flush_tlb_all(void)
  136. {
  137. xc0((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_all));
  138. local_flush_tlb_all();
  139. }
  140. void smp_flush_cache_mm(struct mm_struct *mm)
  141. {
  142. if(mm->context != NO_CONTEXT) {
  143. cpumask_t cpu_mask = mm->cpu_vm_mask;
  144. cpu_clear(smp_processor_id(), cpu_mask);
  145. if (!cpus_empty(cpu_mask))
  146. xc1((smpfunc_t) BTFIXUP_CALL(local_flush_cache_mm), (unsigned long) mm);
  147. local_flush_cache_mm(mm);
  148. }
  149. }
  150. void smp_flush_tlb_mm(struct mm_struct *mm)
  151. {
  152. if(mm->context != NO_CONTEXT) {
  153. cpumask_t cpu_mask = mm->cpu_vm_mask;
  154. cpu_clear(smp_processor_id(), cpu_mask);
  155. if (!cpus_empty(cpu_mask)) {
  156. xc1((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_mm), (unsigned long) mm);
  157. if(atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
  158. mm->cpu_vm_mask = cpumask_of_cpu(smp_processor_id());
  159. }
  160. local_flush_tlb_mm(mm);
  161. }
  162. }
  163. void smp_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
  164. unsigned long end)
  165. {
  166. struct mm_struct *mm = vma->vm_mm;
  167. if (mm->context != NO_CONTEXT) {
  168. cpumask_t cpu_mask = mm->cpu_vm_mask;
  169. cpu_clear(smp_processor_id(), cpu_mask);
  170. if (!cpus_empty(cpu_mask))
  171. xc3((smpfunc_t) BTFIXUP_CALL(local_flush_cache_range), (unsigned long) vma, start, end);
  172. local_flush_cache_range(vma, start, end);
  173. }
  174. }
  175. void smp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
  176. unsigned long end)
  177. {
  178. struct mm_struct *mm = vma->vm_mm;
  179. if (mm->context != NO_CONTEXT) {
  180. cpumask_t cpu_mask = mm->cpu_vm_mask;
  181. cpu_clear(smp_processor_id(), cpu_mask);
  182. if (!cpus_empty(cpu_mask))
  183. xc3((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_range), (unsigned long) vma, start, end);
  184. local_flush_tlb_range(vma, start, end);
  185. }
  186. }
  187. void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
  188. {
  189. struct mm_struct *mm = vma->vm_mm;
  190. if(mm->context != NO_CONTEXT) {
  191. cpumask_t cpu_mask = mm->cpu_vm_mask;
  192. cpu_clear(smp_processor_id(), cpu_mask);
  193. if (!cpus_empty(cpu_mask))
  194. xc2((smpfunc_t) BTFIXUP_CALL(local_flush_cache_page), (unsigned long) vma, page);
  195. local_flush_cache_page(vma, page);
  196. }
  197. }
  198. void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
  199. {
  200. struct mm_struct *mm = vma->vm_mm;
  201. if(mm->context != NO_CONTEXT) {
  202. cpumask_t cpu_mask = mm->cpu_vm_mask;
  203. cpu_clear(smp_processor_id(), cpu_mask);
  204. if (!cpus_empty(cpu_mask))
  205. xc2((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_page), (unsigned long) vma, page);
  206. local_flush_tlb_page(vma, page);
  207. }
  208. }
  209. void smp_reschedule_irq(void)
  210. {
  211. set_need_resched();
  212. }
  213. void smp_flush_page_to_ram(unsigned long page)
  214. {
  215. /* Current theory is that those who call this are the one's
  216. * who have just dirtied their cache with the pages contents
  217. * in kernel space, therefore we only run this on local cpu.
  218. *
  219. * XXX This experiment failed, research further... -DaveM
  220. */
  221. #if 1
  222. xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_to_ram), page);
  223. #endif
  224. local_flush_page_to_ram(page);
  225. }
  226. void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
  227. {
  228. cpumask_t cpu_mask = mm->cpu_vm_mask;
  229. cpu_clear(smp_processor_id(), cpu_mask);
  230. if (!cpus_empty(cpu_mask))
  231. xc2((smpfunc_t) BTFIXUP_CALL(local_flush_sig_insns), (unsigned long) mm, insn_addr);
  232. local_flush_sig_insns(mm, insn_addr);
  233. }
  234. extern unsigned int lvl14_resolution;
  235. /* /proc/profile writes can call this, don't __init it please. */
  236. static DEFINE_SPINLOCK(prof_setup_lock);
  237. int setup_profiling_timer(unsigned int multiplier)
  238. {
  239. int i;
  240. unsigned long flags;
  241. /* Prevent level14 ticker IRQ flooding. */
  242. if((!multiplier) || (lvl14_resolution / multiplier) < 500)
  243. return -EINVAL;
  244. spin_lock_irqsave(&prof_setup_lock, flags);
  245. for_each_possible_cpu(i) {
  246. load_profile_irq(i, lvl14_resolution / multiplier);
  247. prof_multiplier(i) = multiplier;
  248. }
  249. spin_unlock_irqrestore(&prof_setup_lock, flags);
  250. return 0;
  251. }
  252. void __init smp_prepare_cpus(unsigned int max_cpus)
  253. {
  254. extern void smp4m_boot_cpus(void);
  255. extern void smp4d_boot_cpus(void);
  256. int i, cpuid, extra;
  257. printk("Entering SMP Mode...\n");
  258. extra = 0;
  259. for (i = 0; !cpu_find_by_instance(i, NULL, &cpuid); i++) {
  260. if (cpuid >= NR_CPUS)
  261. extra++;
  262. }
  263. /* i = number of cpus */
  264. if (extra && max_cpus > i - extra)
  265. printk("Warning: NR_CPUS is too low to start all cpus\n");
  266. smp_store_cpu_info(boot_cpu_id);
  267. switch(sparc_cpu_model) {
  268. case sun4:
  269. printk("SUN4\n");
  270. BUG();
  271. break;
  272. case sun4c:
  273. printk("SUN4C\n");
  274. BUG();
  275. break;
  276. case sun4m:
  277. smp4m_boot_cpus();
  278. break;
  279. case sun4d:
  280. smp4d_boot_cpus();
  281. break;
  282. case sun4e:
  283. printk("SUN4E\n");
  284. BUG();
  285. break;
  286. case sun4u:
  287. printk("SUN4U\n");
  288. BUG();
  289. break;
  290. default:
  291. printk("UNKNOWN!\n");
  292. BUG();
  293. break;
  294. };
  295. }
  296. /* Set this up early so that things like the scheduler can init
  297. * properly. We use the same cpu mask for both the present and
  298. * possible cpu map.
  299. */
  300. void __init smp_setup_cpu_possible_map(void)
  301. {
  302. int instance, mid;
  303. instance = 0;
  304. while (!cpu_find_by_instance(instance, NULL, &mid)) {
  305. if (mid < NR_CPUS) {
  306. cpu_set(mid, phys_cpu_present_map);
  307. cpu_set(mid, cpu_present_map);
  308. }
  309. instance++;
  310. }
  311. }
  312. void __init smp_prepare_boot_cpu(void)
  313. {
  314. int cpuid = hard_smp_processor_id();
  315. if (cpuid >= NR_CPUS) {
  316. prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
  317. prom_halt();
  318. }
  319. if (cpuid != 0)
  320. printk("boot cpu id != 0, this could work but is untested\n");
  321. current_thread_info()->cpu = cpuid;
  322. cpu_set(cpuid, cpu_online_map);
  323. cpu_set(cpuid, phys_cpu_present_map);
  324. }
  325. int __cpuinit __cpu_up(unsigned int cpu)
  326. {
  327. extern int smp4m_boot_one_cpu(int);
  328. extern int smp4d_boot_one_cpu(int);
  329. int ret=0;
  330. switch(sparc_cpu_model) {
  331. case sun4:
  332. printk("SUN4\n");
  333. BUG();
  334. break;
  335. case sun4c:
  336. printk("SUN4C\n");
  337. BUG();
  338. break;
  339. case sun4m:
  340. ret = smp4m_boot_one_cpu(cpu);
  341. break;
  342. case sun4d:
  343. ret = smp4d_boot_one_cpu(cpu);
  344. break;
  345. case sun4e:
  346. printk("SUN4E\n");
  347. BUG();
  348. break;
  349. case sun4u:
  350. printk("SUN4U\n");
  351. BUG();
  352. break;
  353. default:
  354. printk("UNKNOWN!\n");
  355. BUG();
  356. break;
  357. };
  358. if (!ret) {
  359. cpu_set(cpu, smp_commenced_mask);
  360. while (!cpu_online(cpu))
  361. mb();
  362. }
  363. return ret;
  364. }
  365. void smp_bogo(struct seq_file *m)
  366. {
  367. int i;
  368. for_each_online_cpu(i) {
  369. seq_printf(m,
  370. "Cpu%dBogo\t: %lu.%02lu\n",
  371. i,
  372. cpu_data(i).udelay_val/(500000/HZ),
  373. (cpu_data(i).udelay_val/(5000/HZ))%100);
  374. }
  375. }
  376. void smp_info(struct seq_file *m)
  377. {
  378. int i;
  379. seq_printf(m, "State:\n");
  380. for_each_online_cpu(i)
  381. seq_printf(m, "CPU%d\t\t: online\n", i);
  382. }