iwl-rx.c 35 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <net/mac80211.h>
  31. #include <asm/unaligned.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-sta.h"
  36. #include "iwl-io.h"
  37. #include "iwl-calib.h"
  38. #include "iwl-helpers.h"
  39. /************************** RX-FUNCTIONS ****************************/
  40. /*
  41. * Rx theory of operation
  42. *
  43. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  44. * each of which point to Receive Buffers to be filled by the NIC. These get
  45. * used not only for Rx frames, but for any command response or notification
  46. * from the NIC. The driver and NIC manage the Rx buffers by means
  47. * of indexes into the circular buffer.
  48. *
  49. * Rx Queue Indexes
  50. * The host/firmware share two index registers for managing the Rx buffers.
  51. *
  52. * The READ index maps to the first position that the firmware may be writing
  53. * to -- the driver can read up to (but not including) this position and get
  54. * good data.
  55. * The READ index is managed by the firmware once the card is enabled.
  56. *
  57. * The WRITE index maps to the last position the driver has read from -- the
  58. * position preceding WRITE is the last slot the firmware can place a packet.
  59. *
  60. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  61. * WRITE = READ.
  62. *
  63. * During initialization, the host sets up the READ queue position to the first
  64. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  65. *
  66. * When the firmware places a packet in a buffer, it will advance the READ index
  67. * and fire the RX interrupt. The driver can then query the READ index and
  68. * process as many packets as possible, moving the WRITE index forward as it
  69. * resets the Rx queue buffers with new memory.
  70. *
  71. * The management in the driver is as follows:
  72. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  73. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  74. * to replenish the iwl->rxq->rx_free.
  75. * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  76. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  77. * 'processed' and 'read' driver indexes as well)
  78. * + A received packet is processed and handed to the kernel network stack,
  79. * detached from the iwl->rxq. The driver 'processed' index is updated.
  80. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  81. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  82. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  83. * were enough free buffers and RX_STALLED is set it is cleared.
  84. *
  85. *
  86. * Driver sequence:
  87. *
  88. * iwl_rx_queue_alloc() Allocates rx_free
  89. * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
  90. * iwl_rx_queue_restock
  91. * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  92. * queue, updates firmware pointers, and updates
  93. * the WRITE index. If insufficient rx_free buffers
  94. * are available, schedules iwl_rx_replenish
  95. *
  96. * -- enable interrupts --
  97. * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
  98. * READ INDEX, detaching the SKB from the pool.
  99. * Moves the packet buffer from queue to rx_used.
  100. * Calls iwl_rx_queue_restock to refill any empty
  101. * slots.
  102. * ...
  103. *
  104. */
  105. /**
  106. * iwl_rx_queue_space - Return number of free slots available in queue.
  107. */
  108. int iwl_rx_queue_space(const struct iwl_rx_queue *q)
  109. {
  110. int s = q->read - q->write;
  111. if (s <= 0)
  112. s += RX_QUEUE_SIZE;
  113. /* keep some buffer to not confuse full and empty queue */
  114. s -= 2;
  115. if (s < 0)
  116. s = 0;
  117. return s;
  118. }
  119. EXPORT_SYMBOL(iwl_rx_queue_space);
  120. /**
  121. * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  122. */
  123. int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  124. {
  125. u32 reg = 0;
  126. int ret = 0;
  127. unsigned long flags;
  128. spin_lock_irqsave(&q->lock, flags);
  129. if (q->need_update == 0)
  130. goto exit_unlock;
  131. /* If power-saving is in use, make sure device is awake */
  132. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  133. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  134. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  135. iwl_set_bit(priv, CSR_GP_CNTRL,
  136. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  137. goto exit_unlock;
  138. }
  139. ret = iwl_grab_nic_access(priv);
  140. if (ret)
  141. goto exit_unlock;
  142. /* Device expects a multiple of 8 */
  143. iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  144. q->write & ~0x7);
  145. iwl_release_nic_access(priv);
  146. /* Else device is assumed to be awake */
  147. } else
  148. /* Device expects a multiple of 8 */
  149. iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  150. q->need_update = 0;
  151. exit_unlock:
  152. spin_unlock_irqrestore(&q->lock, flags);
  153. return ret;
  154. }
  155. EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
  156. /**
  157. * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  158. */
  159. static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
  160. dma_addr_t dma_addr)
  161. {
  162. return cpu_to_le32((u32)(dma_addr >> 8));
  163. }
  164. /**
  165. * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
  166. *
  167. * If there are slots in the RX queue that need to be restocked,
  168. * and we have free pre-allocated buffers, fill the ranks as much
  169. * as we can, pulling from rx_free.
  170. *
  171. * This moves the 'write' index forward to catch up with 'processed', and
  172. * also updates the memory address in the firmware to reference the new
  173. * target buffer.
  174. */
  175. int iwl_rx_queue_restock(struct iwl_priv *priv)
  176. {
  177. struct iwl_rx_queue *rxq = &priv->rxq;
  178. struct list_head *element;
  179. struct iwl_rx_mem_buffer *rxb;
  180. unsigned long flags;
  181. int write;
  182. int ret = 0;
  183. spin_lock_irqsave(&rxq->lock, flags);
  184. write = rxq->write & ~0x7;
  185. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  186. /* Get next free Rx buffer, remove from free list */
  187. element = rxq->rx_free.next;
  188. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  189. list_del(element);
  190. /* Point to Rx buffer via next RBD in circular buffer */
  191. rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->aligned_dma_addr);
  192. rxq->queue[rxq->write] = rxb;
  193. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  194. rxq->free_count--;
  195. }
  196. spin_unlock_irqrestore(&rxq->lock, flags);
  197. /* If the pre-allocated buffer pool is dropping low, schedule to
  198. * refill it */
  199. if (rxq->free_count <= RX_LOW_WATERMARK)
  200. queue_work(priv->workqueue, &priv->rx_replenish);
  201. /* If we've added more space for the firmware to place data, tell it.
  202. * Increment device's write pointer in multiples of 8. */
  203. if (write != (rxq->write & ~0x7)) {
  204. spin_lock_irqsave(&rxq->lock, flags);
  205. rxq->need_update = 1;
  206. spin_unlock_irqrestore(&rxq->lock, flags);
  207. ret = iwl_rx_queue_update_write_ptr(priv, rxq);
  208. }
  209. return ret;
  210. }
  211. EXPORT_SYMBOL(iwl_rx_queue_restock);
  212. /**
  213. * iwl_rx_replenish - Move all used packet from rx_used to rx_free
  214. *
  215. * When moving to rx_free an SKB is allocated for the slot.
  216. *
  217. * Also restock the Rx queue via iwl_rx_queue_restock.
  218. * This is called as a scheduled work item (except for during initialization)
  219. */
  220. void iwl_rx_allocate(struct iwl_priv *priv)
  221. {
  222. struct iwl_rx_queue *rxq = &priv->rxq;
  223. struct list_head *element;
  224. struct iwl_rx_mem_buffer *rxb;
  225. unsigned long flags;
  226. while (1) {
  227. spin_lock_irqsave(&rxq->lock, flags);
  228. if (list_empty(&rxq->rx_used)) {
  229. spin_unlock_irqrestore(&rxq->lock, flags);
  230. return;
  231. }
  232. element = rxq->rx_used.next;
  233. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  234. list_del(element);
  235. spin_unlock_irqrestore(&rxq->lock, flags);
  236. /* Alloc a new receive buffer */
  237. rxb->skb = alloc_skb(priv->hw_params.rx_buf_size + 256,
  238. GFP_KERNEL);
  239. if (!rxb->skb) {
  240. IWL_CRIT(priv, "Can not allocate SKB buffers\n");
  241. /* We don't reschedule replenish work here -- we will
  242. * call the restock method and if it still needs
  243. * more buffers it will schedule replenish */
  244. break;
  245. }
  246. /* Get physical address of RB/SKB */
  247. rxb->real_dma_addr = pci_map_single(
  248. priv->pci_dev,
  249. rxb->skb->data,
  250. priv->hw_params.rx_buf_size + 256,
  251. PCI_DMA_FROMDEVICE);
  252. /* dma address must be no more than 36 bits */
  253. BUG_ON(rxb->real_dma_addr & ~DMA_BIT_MASK(36));
  254. /* and also 256 byte aligned! */
  255. rxb->aligned_dma_addr = ALIGN(rxb->real_dma_addr, 256);
  256. skb_reserve(rxb->skb, rxb->aligned_dma_addr - rxb->real_dma_addr);
  257. spin_lock_irqsave(&rxq->lock, flags);
  258. list_add_tail(&rxb->list, &rxq->rx_free);
  259. rxq->free_count++;
  260. priv->alloc_rxb_skb++;
  261. spin_unlock_irqrestore(&rxq->lock, flags);
  262. }
  263. }
  264. void iwl_rx_replenish(struct iwl_priv *priv)
  265. {
  266. unsigned long flags;
  267. iwl_rx_allocate(priv);
  268. spin_lock_irqsave(&priv->lock, flags);
  269. iwl_rx_queue_restock(priv);
  270. spin_unlock_irqrestore(&priv->lock, flags);
  271. }
  272. EXPORT_SYMBOL(iwl_rx_replenish);
  273. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  274. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  275. * This free routine walks the list of POOL entries and if SKB is set to
  276. * non NULL it is unmapped and freed
  277. */
  278. void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  279. {
  280. int i;
  281. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  282. if (rxq->pool[i].skb != NULL) {
  283. pci_unmap_single(priv->pci_dev,
  284. rxq->pool[i].real_dma_addr,
  285. priv->hw_params.rx_buf_size + 256,
  286. PCI_DMA_FROMDEVICE);
  287. dev_kfree_skb(rxq->pool[i].skb);
  288. }
  289. }
  290. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  291. rxq->dma_addr);
  292. pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
  293. rxq->rb_stts, rxq->rb_stts_dma);
  294. rxq->bd = NULL;
  295. rxq->rb_stts = NULL;
  296. }
  297. EXPORT_SYMBOL(iwl_rx_queue_free);
  298. int iwl_rx_queue_alloc(struct iwl_priv *priv)
  299. {
  300. struct iwl_rx_queue *rxq = &priv->rxq;
  301. struct pci_dev *dev = priv->pci_dev;
  302. int i;
  303. spin_lock_init(&rxq->lock);
  304. INIT_LIST_HEAD(&rxq->rx_free);
  305. INIT_LIST_HEAD(&rxq->rx_used);
  306. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  307. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  308. if (!rxq->bd)
  309. goto err_bd;
  310. rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status),
  311. &rxq->rb_stts_dma);
  312. if (!rxq->rb_stts)
  313. goto err_rb;
  314. /* Fill the rx_used queue with _all_ of the Rx buffers */
  315. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  316. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  317. /* Set us so that we have processed and used all buffers, but have
  318. * not restocked the Rx queue with fresh buffers */
  319. rxq->read = rxq->write = 0;
  320. rxq->free_count = 0;
  321. rxq->need_update = 0;
  322. return 0;
  323. err_rb:
  324. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  325. rxq->dma_addr);
  326. err_bd:
  327. return -ENOMEM;
  328. }
  329. EXPORT_SYMBOL(iwl_rx_queue_alloc);
  330. void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  331. {
  332. unsigned long flags;
  333. int i;
  334. spin_lock_irqsave(&rxq->lock, flags);
  335. INIT_LIST_HEAD(&rxq->rx_free);
  336. INIT_LIST_HEAD(&rxq->rx_used);
  337. /* Fill the rx_used queue with _all_ of the Rx buffers */
  338. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  339. /* In the reset function, these buffers may have been allocated
  340. * to an SKB, so we need to unmap and free potential storage */
  341. if (rxq->pool[i].skb != NULL) {
  342. pci_unmap_single(priv->pci_dev,
  343. rxq->pool[i].real_dma_addr,
  344. priv->hw_params.rx_buf_size + 256,
  345. PCI_DMA_FROMDEVICE);
  346. priv->alloc_rxb_skb--;
  347. dev_kfree_skb(rxq->pool[i].skb);
  348. rxq->pool[i].skb = NULL;
  349. }
  350. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  351. }
  352. /* Set us so that we have processed and used all buffers, but have
  353. * not restocked the Rx queue with fresh buffers */
  354. rxq->read = rxq->write = 0;
  355. rxq->free_count = 0;
  356. spin_unlock_irqrestore(&rxq->lock, flags);
  357. }
  358. EXPORT_SYMBOL(iwl_rx_queue_reset);
  359. int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  360. {
  361. int ret;
  362. unsigned long flags;
  363. u32 rb_size;
  364. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  365. const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */
  366. spin_lock_irqsave(&priv->lock, flags);
  367. ret = iwl_grab_nic_access(priv);
  368. if (ret) {
  369. spin_unlock_irqrestore(&priv->lock, flags);
  370. return ret;
  371. }
  372. if (priv->cfg->mod_params->amsdu_size_8K)
  373. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  374. else
  375. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  376. /* Stop Rx DMA */
  377. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  378. /* Reset driver's Rx queue write index */
  379. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  380. /* Tell device where to find RBD circular buffer in DRAM */
  381. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  382. (u32)(rxq->dma_addr >> 8));
  383. /* Tell device where in DRAM to update its Rx status */
  384. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  385. rxq->rb_stts_dma >> 4);
  386. /* Enable Rx DMA
  387. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  388. * the credit mechanism in 5000 HW RX FIFO
  389. * Direct rx interrupts to hosts
  390. * Rx buffer size 4 or 8k
  391. * RB timeout 0x10
  392. * 256 RBDs
  393. */
  394. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  395. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  396. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  397. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  398. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  399. rb_size|
  400. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  401. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  402. iwl_release_nic_access(priv);
  403. iwl_write32(priv, CSR_INT_COALESCING, 0x40);
  404. spin_unlock_irqrestore(&priv->lock, flags);
  405. return 0;
  406. }
  407. int iwl_rxq_stop(struct iwl_priv *priv)
  408. {
  409. int ret;
  410. unsigned long flags;
  411. spin_lock_irqsave(&priv->lock, flags);
  412. ret = iwl_grab_nic_access(priv);
  413. if (unlikely(ret)) {
  414. spin_unlock_irqrestore(&priv->lock, flags);
  415. return ret;
  416. }
  417. /* stop Rx DMA */
  418. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  419. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  420. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  421. iwl_release_nic_access(priv);
  422. spin_unlock_irqrestore(&priv->lock, flags);
  423. return 0;
  424. }
  425. EXPORT_SYMBOL(iwl_rxq_stop);
  426. void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
  427. struct iwl_rx_mem_buffer *rxb)
  428. {
  429. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  430. struct iwl_missed_beacon_notif *missed_beacon;
  431. missed_beacon = &pkt->u.missed_beacon;
  432. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  433. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  434. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  435. le32_to_cpu(missed_beacon->total_missed_becons),
  436. le32_to_cpu(missed_beacon->num_recvd_beacons),
  437. le32_to_cpu(missed_beacon->num_expected_beacons));
  438. if (!test_bit(STATUS_SCANNING, &priv->status))
  439. iwl_init_sensitivity(priv);
  440. }
  441. }
  442. EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
  443. /* Calculate noise level, based on measurements during network silence just
  444. * before arriving beacon. This measurement can be done only if we know
  445. * exactly when to expect beacons, therefore only when we're associated. */
  446. static void iwl_rx_calc_noise(struct iwl_priv *priv)
  447. {
  448. struct statistics_rx_non_phy *rx_info
  449. = &(priv->statistics.rx.general);
  450. int num_active_rx = 0;
  451. int total_silence = 0;
  452. int bcn_silence_a =
  453. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  454. int bcn_silence_b =
  455. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  456. int bcn_silence_c =
  457. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  458. if (bcn_silence_a) {
  459. total_silence += bcn_silence_a;
  460. num_active_rx++;
  461. }
  462. if (bcn_silence_b) {
  463. total_silence += bcn_silence_b;
  464. num_active_rx++;
  465. }
  466. if (bcn_silence_c) {
  467. total_silence += bcn_silence_c;
  468. num_active_rx++;
  469. }
  470. /* Average among active antennas */
  471. if (num_active_rx)
  472. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  473. else
  474. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  475. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  476. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  477. priv->last_rx_noise);
  478. }
  479. #define REG_RECALIB_PERIOD (60)
  480. void iwl_rx_statistics(struct iwl_priv *priv,
  481. struct iwl_rx_mem_buffer *rxb)
  482. {
  483. int change;
  484. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  485. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  486. (int)sizeof(priv->statistics), pkt->len);
  487. change = ((priv->statistics.general.temperature !=
  488. pkt->u.stats.general.temperature) ||
  489. ((priv->statistics.flag &
  490. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  491. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  492. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  493. set_bit(STATUS_STATISTICS, &priv->status);
  494. /* Reschedule the statistics timer to occur in
  495. * REG_RECALIB_PERIOD seconds to ensure we get a
  496. * thermal update even if the uCode doesn't give
  497. * us one */
  498. mod_timer(&priv->statistics_periodic, jiffies +
  499. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  500. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  501. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  502. iwl_rx_calc_noise(priv);
  503. queue_work(priv->workqueue, &priv->run_time_calib_work);
  504. }
  505. iwl_leds_background(priv);
  506. if (priv->cfg->ops->lib->temperature && change)
  507. priv->cfg->ops->lib->temperature(priv);
  508. }
  509. EXPORT_SYMBOL(iwl_rx_statistics);
  510. #define PERFECT_RSSI (-20) /* dBm */
  511. #define WORST_RSSI (-95) /* dBm */
  512. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  513. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  514. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  515. * about formulas used below. */
  516. static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm)
  517. {
  518. int sig_qual;
  519. int degradation = PERFECT_RSSI - rssi_dbm;
  520. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  521. * as indicator; formula is (signal dbm - noise dbm).
  522. * SNR at or above 40 is a great signal (100%).
  523. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  524. * Weakest usable signal is usually 10 - 15 dB SNR. */
  525. if (noise_dbm) {
  526. if (rssi_dbm - noise_dbm >= 40)
  527. return 100;
  528. else if (rssi_dbm < noise_dbm)
  529. return 0;
  530. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  531. /* Else use just the signal level.
  532. * This formula is a least squares fit of data points collected and
  533. * compared with a reference system that had a percentage (%) display
  534. * for signal quality. */
  535. } else
  536. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  537. (15 * RSSI_RANGE + 62 * degradation)) /
  538. (RSSI_RANGE * RSSI_RANGE);
  539. if (sig_qual > 100)
  540. sig_qual = 100;
  541. else if (sig_qual < 1)
  542. sig_qual = 0;
  543. return sig_qual;
  544. }
  545. /* Calc max signal level (dBm) among 3 possible receivers */
  546. static inline int iwl_calc_rssi(struct iwl_priv *priv,
  547. struct iwl_rx_phy_res *rx_resp)
  548. {
  549. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  550. }
  551. #ifdef CONFIG_IWLWIFI_DEBUG
  552. /**
  553. * iwl_dbg_report_frame - dump frame to syslog during debug sessions
  554. *
  555. * You may hack this function to show different aspects of received frames,
  556. * including selective frame dumps.
  557. * group100 parameter selects whether to show 1 out of 100 good data frames.
  558. * All beacon and probe response frames are printed.
  559. */
  560. static void iwl_dbg_report_frame(struct iwl_priv *priv,
  561. struct iwl_rx_phy_res *phy_res, u16 length,
  562. struct ieee80211_hdr *header, int group100)
  563. {
  564. u32 to_us;
  565. u32 print_summary = 0;
  566. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  567. u32 hundred = 0;
  568. u32 dataframe = 0;
  569. __le16 fc;
  570. u16 seq_ctl;
  571. u16 channel;
  572. u16 phy_flags;
  573. u32 rate_n_flags;
  574. u32 tsf_low;
  575. int rssi;
  576. if (likely(!(priv->debug_level & IWL_DL_RX)))
  577. return;
  578. /* MAC header */
  579. fc = header->frame_control;
  580. seq_ctl = le16_to_cpu(header->seq_ctrl);
  581. /* metadata */
  582. channel = le16_to_cpu(phy_res->channel);
  583. phy_flags = le16_to_cpu(phy_res->phy_flags);
  584. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  585. /* signal statistics */
  586. rssi = iwl_calc_rssi(priv, phy_res);
  587. tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff;
  588. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  589. /* if data frame is to us and all is good,
  590. * (optionally) print summary for only 1 out of every 100 */
  591. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  592. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  593. dataframe = 1;
  594. if (!group100)
  595. print_summary = 1; /* print each frame */
  596. else if (priv->framecnt_to_us < 100) {
  597. priv->framecnt_to_us++;
  598. print_summary = 0;
  599. } else {
  600. priv->framecnt_to_us = 0;
  601. print_summary = 1;
  602. hundred = 1;
  603. }
  604. } else {
  605. /* print summary for all other frames */
  606. print_summary = 1;
  607. }
  608. if (print_summary) {
  609. char *title;
  610. int rate_idx;
  611. u32 bitrate;
  612. if (hundred)
  613. title = "100Frames";
  614. else if (ieee80211_has_retry(fc))
  615. title = "Retry";
  616. else if (ieee80211_is_assoc_resp(fc))
  617. title = "AscRsp";
  618. else if (ieee80211_is_reassoc_resp(fc))
  619. title = "RasRsp";
  620. else if (ieee80211_is_probe_resp(fc)) {
  621. title = "PrbRsp";
  622. print_dump = 1; /* dump frame contents */
  623. } else if (ieee80211_is_beacon(fc)) {
  624. title = "Beacon";
  625. print_dump = 1; /* dump frame contents */
  626. } else if (ieee80211_is_atim(fc))
  627. title = "ATIM";
  628. else if (ieee80211_is_auth(fc))
  629. title = "Auth";
  630. else if (ieee80211_is_deauth(fc))
  631. title = "DeAuth";
  632. else if (ieee80211_is_disassoc(fc))
  633. title = "DisAssoc";
  634. else
  635. title = "Frame";
  636. rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
  637. if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) {
  638. bitrate = 0;
  639. WARN_ON_ONCE(1);
  640. } else {
  641. bitrate = iwl_rates[rate_idx].ieee / 2;
  642. }
  643. /* print frame summary.
  644. * MAC addresses show just the last byte (for brevity),
  645. * but you can hack it to show more, if you'd like to. */
  646. if (dataframe)
  647. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  648. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  649. title, le16_to_cpu(fc), header->addr1[5],
  650. length, rssi, channel, bitrate);
  651. else {
  652. /* src/dst addresses assume managed mode */
  653. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, src=0x%02x, "
  654. "len=%u, rssi=%d, tim=%lu usec, "
  655. "phy=0x%02x, chnl=%d\n",
  656. title, le16_to_cpu(fc), header->addr1[5],
  657. header->addr3[5], length, rssi,
  658. tsf_low - priv->scan_start_tsf,
  659. phy_flags, channel);
  660. }
  661. }
  662. if (print_dump)
  663. iwl_print_hex_dump(priv, IWL_DL_RX, header, length);
  664. }
  665. #endif
  666. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  667. {
  668. /* 0 - mgmt, 1 - cnt, 2 - data */
  669. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  670. priv->rx_stats[idx].cnt++;
  671. priv->rx_stats[idx].bytes += len;
  672. }
  673. /*
  674. * returns non-zero if packet should be dropped
  675. */
  676. static int iwl_set_decrypted_flag(struct iwl_priv *priv,
  677. struct ieee80211_hdr *hdr,
  678. u32 decrypt_res,
  679. struct ieee80211_rx_status *stats)
  680. {
  681. u16 fc = le16_to_cpu(hdr->frame_control);
  682. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  683. return 0;
  684. if (!(fc & IEEE80211_FCTL_PROTECTED))
  685. return 0;
  686. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  687. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  688. case RX_RES_STATUS_SEC_TYPE_TKIP:
  689. /* The uCode has got a bad phase 1 Key, pushes the packet.
  690. * Decryption will be done in SW. */
  691. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  692. RX_RES_STATUS_BAD_KEY_TTAK)
  693. break;
  694. case RX_RES_STATUS_SEC_TYPE_WEP:
  695. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  696. RX_RES_STATUS_BAD_ICV_MIC) {
  697. /* bad ICV, the packet is destroyed since the
  698. * decryption is inplace, drop it */
  699. IWL_DEBUG_RX("Packet destroyed\n");
  700. return -1;
  701. }
  702. case RX_RES_STATUS_SEC_TYPE_CCMP:
  703. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  704. RX_RES_STATUS_DECRYPT_OK) {
  705. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  706. stats->flag |= RX_FLAG_DECRYPTED;
  707. }
  708. break;
  709. default:
  710. break;
  711. }
  712. return 0;
  713. }
  714. static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  715. {
  716. u32 decrypt_out = 0;
  717. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  718. RX_RES_STATUS_STATION_FOUND)
  719. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  720. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  721. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  722. /* packet was not encrypted */
  723. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  724. RX_RES_STATUS_SEC_TYPE_NONE)
  725. return decrypt_out;
  726. /* packet was encrypted with unknown alg */
  727. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  728. RX_RES_STATUS_SEC_TYPE_ERR)
  729. return decrypt_out;
  730. /* decryption was not done in HW */
  731. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  732. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  733. return decrypt_out;
  734. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  735. case RX_RES_STATUS_SEC_TYPE_CCMP:
  736. /* alg is CCM: check MIC only */
  737. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  738. /* Bad MIC */
  739. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  740. else
  741. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  742. break;
  743. case RX_RES_STATUS_SEC_TYPE_TKIP:
  744. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  745. /* Bad TTAK */
  746. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  747. break;
  748. }
  749. /* fall through if TTAK OK */
  750. default:
  751. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  752. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  753. else
  754. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  755. break;
  756. };
  757. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  758. decrypt_in, decrypt_out);
  759. return decrypt_out;
  760. }
  761. static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
  762. int include_phy,
  763. struct iwl_rx_mem_buffer *rxb,
  764. struct ieee80211_rx_status *stats)
  765. {
  766. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  767. struct iwl_rx_phy_res *rx_start = (include_phy) ?
  768. (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  769. struct ieee80211_hdr *hdr;
  770. u16 len;
  771. __le32 *rx_end;
  772. unsigned int skblen;
  773. u32 ampdu_status;
  774. u32 ampdu_status_legacy;
  775. if (!include_phy && priv->last_phy_res[0])
  776. rx_start = (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  777. if (!rx_start) {
  778. IWL_ERR(priv, "MPDU frame without a PHY data\n");
  779. return;
  780. }
  781. if (include_phy) {
  782. hdr = (struct ieee80211_hdr *)((u8 *) &rx_start[1] +
  783. rx_start->cfg_phy_cnt);
  784. len = le16_to_cpu(rx_start->byte_count);
  785. rx_end = (__le32 *)((u8 *) &pkt->u.raw[0] +
  786. sizeof(struct iwl_rx_phy_res) +
  787. rx_start->cfg_phy_cnt + len);
  788. } else {
  789. struct iwl4965_rx_mpdu_res_start *amsdu =
  790. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  791. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  792. sizeof(struct iwl4965_rx_mpdu_res_start));
  793. len = le16_to_cpu(amsdu->byte_count);
  794. rx_start->byte_count = amsdu->byte_count;
  795. rx_end = (__le32 *) (((u8 *) hdr) + len);
  796. }
  797. ampdu_status = le32_to_cpu(*rx_end);
  798. skblen = ((u8 *) rx_end - (u8 *) &pkt->u.raw[0]) + sizeof(u32);
  799. if (!include_phy) {
  800. /* New status scheme, need to translate */
  801. ampdu_status_legacy = ampdu_status;
  802. ampdu_status = iwl_translate_rx_status(priv, ampdu_status);
  803. }
  804. /* start from MAC */
  805. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  806. skb_put(rxb->skb, len); /* end where data ends */
  807. /* We only process data packets if the interface is open */
  808. if (unlikely(!priv->is_open)) {
  809. IWL_DEBUG_DROP_LIMIT
  810. ("Dropping packet while interface is not open.\n");
  811. return;
  812. }
  813. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  814. /* in case of HW accelerated crypto and bad decryption, drop */
  815. if (!priv->hw_params.sw_crypto &&
  816. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  817. return;
  818. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  819. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  820. priv->alloc_rxb_skb--;
  821. rxb->skb = NULL;
  822. }
  823. /* This is necessary only for a number of statistics, see the caller. */
  824. static int iwl_is_network_packet(struct iwl_priv *priv,
  825. struct ieee80211_hdr *header)
  826. {
  827. /* Filter incoming packets to determine if they are targeted toward
  828. * this network, discarding packets coming from ourselves */
  829. switch (priv->iw_mode) {
  830. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  831. /* packets to our IBSS update information */
  832. return !compare_ether_addr(header->addr3, priv->bssid);
  833. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  834. /* packets to our IBSS update information */
  835. return !compare_ether_addr(header->addr2, priv->bssid);
  836. default:
  837. return 1;
  838. }
  839. }
  840. /* Called for REPLY_RX (legacy ABG frames), or
  841. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  842. void iwl_rx_reply_rx(struct iwl_priv *priv,
  843. struct iwl_rx_mem_buffer *rxb)
  844. {
  845. struct ieee80211_hdr *header;
  846. struct ieee80211_rx_status rx_status;
  847. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  848. /* Use phy data (Rx signal strength, etc.) contained within
  849. * this rx packet for legacy frames,
  850. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  851. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  852. struct iwl_rx_phy_res *rx_start = (include_phy) ?
  853. (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) :
  854. (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  855. __le32 *rx_end;
  856. unsigned int len = 0;
  857. u16 fc;
  858. u8 network_packet;
  859. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  860. rx_status.freq =
  861. ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
  862. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  863. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  864. rx_status.rate_idx =
  865. iwl_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  866. if (rx_status.band == IEEE80211_BAND_5GHZ)
  867. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  868. rx_status.flag = 0;
  869. /* TSF isn't reliable. In order to allow smooth user experience,
  870. * this W/A doesn't propagate it to the mac80211 */
  871. /*rx_status.flag |= RX_FLAG_TSFT;*/
  872. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  873. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  874. rx_start->cfg_phy_cnt);
  875. return;
  876. }
  877. if (!include_phy) {
  878. if (priv->last_phy_res[0])
  879. rx_start = (struct iwl_rx_phy_res *)
  880. &priv->last_phy_res[1];
  881. else
  882. rx_start = NULL;
  883. }
  884. if (!rx_start) {
  885. IWL_ERR(priv, "MPDU frame without a PHY data\n");
  886. return;
  887. }
  888. if (include_phy) {
  889. header = (struct ieee80211_hdr *)((u8 *) &rx_start[1]
  890. + rx_start->cfg_phy_cnt);
  891. len = le16_to_cpu(rx_start->byte_count);
  892. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  893. sizeof(struct iwl_rx_phy_res) + len);
  894. } else {
  895. struct iwl4965_rx_mpdu_res_start *amsdu =
  896. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  897. header = (void *)(pkt->u.raw +
  898. sizeof(struct iwl4965_rx_mpdu_res_start));
  899. len = le16_to_cpu(amsdu->byte_count);
  900. rx_end = (__le32 *) (pkt->u.raw +
  901. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  902. }
  903. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  904. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  905. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  906. le32_to_cpu(*rx_end));
  907. return;
  908. }
  909. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  910. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  911. rx_status.signal = iwl_calc_rssi(priv, rx_start);
  912. /* Meaningful noise values are available only from beacon statistics,
  913. * which are gathered only when associated, and indicate noise
  914. * only for the associated network channel ...
  915. * Ignore these noise values while scanning (other channels) */
  916. if (iwl_is_associated(priv) &&
  917. !test_bit(STATUS_SCANNING, &priv->status)) {
  918. rx_status.noise = priv->last_rx_noise;
  919. rx_status.qual = iwl_calc_sig_qual(rx_status.signal,
  920. rx_status.noise);
  921. } else {
  922. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  923. rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0);
  924. }
  925. /* Reset beacon noise level if not associated. */
  926. if (!iwl_is_associated(priv))
  927. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  928. /* Set "1" to report good data frames in groups of 100 */
  929. #ifdef CONFIG_IWLWIFI_DEBUG
  930. if (unlikely(priv->debug_level & IWL_DL_RX))
  931. iwl_dbg_report_frame(priv, rx_start, len, header, 1);
  932. #endif
  933. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  934. rx_status.signal, rx_status.noise, rx_status.signal,
  935. (unsigned long long)rx_status.mactime);
  936. /*
  937. * "antenna number"
  938. *
  939. * It seems that the antenna field in the phy flags value
  940. * is actually a bit field. This is undefined by radiotap,
  941. * it wants an actual antenna number but I always get "7"
  942. * for most legacy frames I receive indicating that the
  943. * same frame was received on all three RX chains.
  944. *
  945. * I think this field should be removed in favor of a
  946. * new 802.11n radiotap field "RX chains" that is defined
  947. * as a bitmask.
  948. */
  949. rx_status.antenna = le16_to_cpu(rx_start->phy_flags &
  950. RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  951. /* set the preamble flag if appropriate */
  952. if (rx_start->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  953. rx_status.flag |= RX_FLAG_SHORTPRE;
  954. /* Take shortcut when only in monitor mode */
  955. if (priv->iw_mode == NL80211_IFTYPE_MONITOR) {
  956. iwl_pass_packet_to_mac80211(priv, include_phy,
  957. rxb, &rx_status);
  958. return;
  959. }
  960. network_packet = iwl_is_network_packet(priv, header);
  961. if (network_packet) {
  962. priv->last_rx_rssi = rx_status.signal;
  963. priv->last_beacon_time = priv->ucode_beacon_time;
  964. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  965. }
  966. fc = le16_to_cpu(header->frame_control);
  967. switch (fc & IEEE80211_FCTL_FTYPE) {
  968. case IEEE80211_FTYPE_MGMT:
  969. case IEEE80211_FTYPE_DATA:
  970. if (priv->iw_mode == NL80211_IFTYPE_AP)
  971. iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  972. header->addr2);
  973. /* fall through */
  974. default:
  975. iwl_pass_packet_to_mac80211(priv, include_phy, rxb,
  976. &rx_status);
  977. break;
  978. }
  979. }
  980. EXPORT_SYMBOL(iwl_rx_reply_rx);
  981. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  982. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  983. void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
  984. struct iwl_rx_mem_buffer *rxb)
  985. {
  986. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  987. priv->last_phy_res[0] = 1;
  988. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  989. sizeof(struct iwl_rx_phy_res));
  990. }
  991. EXPORT_SYMBOL(iwl_rx_reply_rx_phy);