dice.c 27 KB

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  1. /*
  2. * TC Applied Technologies Digital Interface Communications Engine driver
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. * Licensed under the terms of the GNU General Public License, version 2.
  6. */
  7. #include <linux/compat.h>
  8. #include <linux/completion.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/firewire.h>
  12. #include <linux/firewire-constants.h>
  13. #include <linux/jiffies.h>
  14. #include <linux/module.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/mutex.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/wait.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/firewire.h>
  23. #include <sound/hwdep.h>
  24. #include <sound/initval.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include "amdtp.h"
  28. #include "iso-resources.h"
  29. #include "lib.h"
  30. #include "dice-interface.h"
  31. struct dice {
  32. struct snd_card *card;
  33. struct fw_unit *unit;
  34. spinlock_t lock;
  35. struct mutex mutex;
  36. unsigned int global_offset;
  37. unsigned int rx_offset;
  38. unsigned int clock_caps;
  39. unsigned int rx_channels[3];
  40. unsigned int rx_midi_ports[3];
  41. struct fw_address_handler notification_handler;
  42. int owner_generation;
  43. int dev_lock_count; /* > 0 driver, < 0 userspace */
  44. bool dev_lock_changed;
  45. bool global_enabled;
  46. struct completion clock_accepted;
  47. wait_queue_head_t hwdep_wait;
  48. u32 notification_bits;
  49. struct fw_iso_resources resources;
  50. struct amdtp_out_stream stream;
  51. };
  52. MODULE_DESCRIPTION("DICE driver");
  53. MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  54. MODULE_LICENSE("GPL v2");
  55. static const unsigned int dice_rates[] = {
  56. /* mode 0 */
  57. [0] = 32000,
  58. [1] = 44100,
  59. [2] = 48000,
  60. /* mode 1 */
  61. [3] = 88200,
  62. [4] = 96000,
  63. /* mode 2 */
  64. [5] = 176400,
  65. [6] = 192000,
  66. };
  67. static unsigned int rate_index_to_mode(unsigned int rate_index)
  68. {
  69. return ((int)rate_index - 1) / 2;
  70. }
  71. static void dice_lock_changed(struct dice *dice)
  72. {
  73. dice->dev_lock_changed = true;
  74. wake_up(&dice->hwdep_wait);
  75. }
  76. static int dice_try_lock(struct dice *dice)
  77. {
  78. int err;
  79. spin_lock_irq(&dice->lock);
  80. if (dice->dev_lock_count < 0) {
  81. err = -EBUSY;
  82. goto out;
  83. }
  84. if (dice->dev_lock_count++ == 0)
  85. dice_lock_changed(dice);
  86. err = 0;
  87. out:
  88. spin_unlock_irq(&dice->lock);
  89. return err;
  90. }
  91. static void dice_unlock(struct dice *dice)
  92. {
  93. spin_lock_irq(&dice->lock);
  94. if (WARN_ON(dice->dev_lock_count <= 0))
  95. goto out;
  96. if (--dice->dev_lock_count == 0)
  97. dice_lock_changed(dice);
  98. out:
  99. spin_unlock_irq(&dice->lock);
  100. }
  101. static inline u64 global_address(struct dice *dice, unsigned int offset)
  102. {
  103. return DICE_PRIVATE_SPACE + dice->global_offset + offset;
  104. }
  105. // TODO: rx index
  106. static inline u64 rx_address(struct dice *dice, unsigned int offset)
  107. {
  108. return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
  109. }
  110. static int dice_owner_set(struct dice *dice)
  111. {
  112. struct fw_device *device = fw_parent_device(dice->unit);
  113. __be64 *buffer;
  114. int err, errors = 0;
  115. buffer = kmalloc(2 * 8, GFP_KERNEL);
  116. if (!buffer)
  117. return -ENOMEM;
  118. for (;;) {
  119. buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
  120. buffer[1] = cpu_to_be64(
  121. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  122. dice->notification_handler.offset);
  123. dice->owner_generation = device->generation;
  124. smp_rmb(); /* node_id vs. generation */
  125. err = snd_fw_transaction(dice->unit,
  126. TCODE_LOCK_COMPARE_SWAP,
  127. global_address(dice, GLOBAL_OWNER),
  128. buffer, 2 * 8,
  129. FW_FIXED_GENERATION |
  130. dice->owner_generation);
  131. if (err == 0) {
  132. if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
  133. dev_err(&dice->unit->device,
  134. "device is already in use\n");
  135. err = -EBUSY;
  136. }
  137. break;
  138. }
  139. if (err != -EAGAIN || ++errors >= 3)
  140. break;
  141. msleep(20);
  142. }
  143. kfree(buffer);
  144. return err;
  145. }
  146. static int dice_owner_update(struct dice *dice)
  147. {
  148. struct fw_device *device = fw_parent_device(dice->unit);
  149. __be64 *buffer;
  150. int err;
  151. if (dice->owner_generation == -1)
  152. return 0;
  153. buffer = kmalloc(2 * 8, GFP_KERNEL);
  154. if (!buffer)
  155. return -ENOMEM;
  156. buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
  157. buffer[1] = cpu_to_be64(
  158. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  159. dice->notification_handler.offset);
  160. dice->owner_generation = device->generation;
  161. smp_rmb(); /* node_id vs. generation */
  162. err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
  163. global_address(dice, GLOBAL_OWNER),
  164. buffer, 2 * 8,
  165. FW_FIXED_GENERATION | dice->owner_generation);
  166. if (err == 0) {
  167. if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
  168. dev_err(&dice->unit->device,
  169. "device is already in use\n");
  170. err = -EBUSY;
  171. }
  172. } else if (err == -EAGAIN) {
  173. err = 0; /* try again later */
  174. }
  175. kfree(buffer);
  176. if (err < 0)
  177. dice->owner_generation = -1;
  178. return err;
  179. }
  180. static void dice_owner_clear(struct dice *dice)
  181. {
  182. struct fw_device *device = fw_parent_device(dice->unit);
  183. __be64 *buffer;
  184. buffer = kmalloc(2 * 8, GFP_KERNEL);
  185. if (!buffer)
  186. return;
  187. buffer[0] = cpu_to_be64(
  188. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  189. dice->notification_handler.offset);
  190. buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
  191. snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
  192. global_address(dice, GLOBAL_OWNER),
  193. buffer, 2 * 8, FW_QUIET |
  194. FW_FIXED_GENERATION | dice->owner_generation);
  195. kfree(buffer);
  196. dice->owner_generation = -1;
  197. }
  198. static int dice_enable_set(struct dice *dice)
  199. {
  200. __be32 value;
  201. int err;
  202. value = cpu_to_be32(1);
  203. err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  204. global_address(dice, GLOBAL_ENABLE),
  205. &value, 4,
  206. FW_FIXED_GENERATION | dice->owner_generation);
  207. if (err < 0)
  208. return err;
  209. dice->global_enabled = true;
  210. return 0;
  211. }
  212. static void dice_enable_clear(struct dice *dice)
  213. {
  214. __be32 value;
  215. if (!dice->global_enabled)
  216. return;
  217. value = 0;
  218. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  219. global_address(dice, GLOBAL_ENABLE),
  220. &value, 4, FW_QUIET |
  221. FW_FIXED_GENERATION | dice->owner_generation);
  222. dice->global_enabled = false;
  223. }
  224. static void dice_notification(struct fw_card *card, struct fw_request *request,
  225. int tcode, int destination, int source,
  226. int generation, unsigned long long offset,
  227. void *data, size_t length, void *callback_data)
  228. {
  229. struct dice *dice = callback_data;
  230. u32 bits;
  231. unsigned long flags;
  232. if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
  233. fw_send_response(card, request, RCODE_TYPE_ERROR);
  234. return;
  235. }
  236. if ((offset & 3) != 0) {
  237. fw_send_response(card, request, RCODE_ADDRESS_ERROR);
  238. return;
  239. }
  240. bits = be32_to_cpup(data);
  241. spin_lock_irqsave(&dice->lock, flags);
  242. dice->notification_bits |= bits;
  243. spin_unlock_irqrestore(&dice->lock, flags);
  244. fw_send_response(card, request, RCODE_COMPLETE);
  245. if (bits & NOTIFY_CLOCK_ACCEPTED)
  246. complete(&dice->clock_accepted);
  247. wake_up(&dice->hwdep_wait);
  248. }
  249. static int dice_open(struct snd_pcm_substream *substream)
  250. {
  251. static const struct snd_pcm_hardware hardware = {
  252. .info = SNDRV_PCM_INFO_MMAP |
  253. SNDRV_PCM_INFO_MMAP_VALID |
  254. SNDRV_PCM_INFO_BATCH |
  255. SNDRV_PCM_INFO_INTERLEAVED |
  256. SNDRV_PCM_INFO_BLOCK_TRANSFER,
  257. .formats = AMDTP_OUT_PCM_FORMAT_BITS,
  258. .buffer_bytes_max = 16 * 1024 * 1024,
  259. .period_bytes_min = 1,
  260. .period_bytes_max = UINT_MAX,
  261. .periods_min = 1,
  262. .periods_max = UINT_MAX,
  263. };
  264. struct dice *dice = substream->private_data;
  265. struct snd_pcm_runtime *runtime = substream->runtime;
  266. __be32 clock_sel, data[2];
  267. unsigned int rate_index, number_audio, number_midi;
  268. int err;
  269. err = dice_try_lock(dice);
  270. if (err < 0)
  271. goto error;
  272. err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
  273. global_address(dice, GLOBAL_CLOCK_SELECT),
  274. &clock_sel, 4, 0);
  275. if (err < 0)
  276. goto err_lock;
  277. rate_index = (be32_to_cpu(clock_sel) & CLOCK_RATE_MASK)
  278. >> CLOCK_RATE_SHIFT;
  279. if (rate_index >= ARRAY_SIZE(dice_rates)) {
  280. err = -ENXIO;
  281. goto err_lock;
  282. }
  283. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  284. rx_address(dice, RX_NUMBER_AUDIO),
  285. data, 2 * 4, 0);
  286. if (err < 0)
  287. goto err_lock;
  288. number_audio = be32_to_cpu(data[0]);
  289. number_midi = be32_to_cpu(data[1]);
  290. runtime->hw = hardware;
  291. runtime->hw.rates = snd_pcm_rate_to_rate_bit(dice_rates[rate_index]);
  292. snd_pcm_limit_hw_rates(runtime);
  293. runtime->hw.channels_min = number_audio;
  294. runtime->hw.channels_max = number_audio;
  295. amdtp_out_stream_set_parameters(&dice->stream, dice_rates[rate_index],
  296. number_audio, number_midi);
  297. err = snd_pcm_hw_constraint_step(runtime, 0,
  298. SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
  299. amdtp_syt_intervals[rate_index]);
  300. if (err < 0)
  301. goto err_lock;
  302. err = snd_pcm_hw_constraint_step(runtime, 0,
  303. SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
  304. amdtp_syt_intervals[rate_index]);
  305. if (err < 0)
  306. goto err_lock;
  307. err = snd_pcm_hw_constraint_minmax(runtime,
  308. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  309. 5000, UINT_MAX);
  310. if (err < 0)
  311. goto err_lock;
  312. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  313. if (err < 0)
  314. goto err_lock;
  315. return 0;
  316. err_lock:
  317. dice_unlock(dice);
  318. error:
  319. return err;
  320. }
  321. static int dice_close(struct snd_pcm_substream *substream)
  322. {
  323. struct dice *dice = substream->private_data;
  324. dice_unlock(dice);
  325. return 0;
  326. }
  327. static int dice_stream_start_packets(struct dice *dice)
  328. {
  329. int err;
  330. if (amdtp_out_stream_running(&dice->stream))
  331. return 0;
  332. err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
  333. fw_parent_device(dice->unit)->max_speed);
  334. if (err < 0)
  335. return err;
  336. err = dice_enable_set(dice);
  337. if (err < 0) {
  338. amdtp_out_stream_stop(&dice->stream);
  339. return err;
  340. }
  341. return 0;
  342. }
  343. static int dice_stream_start(struct dice *dice)
  344. {
  345. __be32 channel;
  346. int err;
  347. if (!dice->resources.allocated) {
  348. err = fw_iso_resources_allocate(&dice->resources,
  349. amdtp_out_stream_get_max_payload(&dice->stream),
  350. fw_parent_device(dice->unit)->max_speed);
  351. if (err < 0)
  352. goto error;
  353. channel = cpu_to_be32(dice->resources.channel);
  354. err = snd_fw_transaction(dice->unit,
  355. TCODE_WRITE_QUADLET_REQUEST,
  356. rx_address(dice, RX_ISOCHRONOUS),
  357. &channel, 4, 0);
  358. if (err < 0)
  359. goto err_resources;
  360. }
  361. err = dice_stream_start_packets(dice);
  362. if (err < 0)
  363. goto err_rx_channel;
  364. return 0;
  365. err_rx_channel:
  366. channel = cpu_to_be32((u32)-1);
  367. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  368. rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
  369. err_resources:
  370. fw_iso_resources_free(&dice->resources);
  371. error:
  372. return err;
  373. }
  374. static void dice_stream_stop_packets(struct dice *dice)
  375. {
  376. if (amdtp_out_stream_running(&dice->stream)) {
  377. dice_enable_clear(dice);
  378. amdtp_out_stream_stop(&dice->stream);
  379. }
  380. }
  381. static void dice_stream_stop(struct dice *dice)
  382. {
  383. __be32 channel;
  384. dice_stream_stop_packets(dice);
  385. if (!dice->resources.allocated)
  386. return;
  387. channel = cpu_to_be32((u32)-1);
  388. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  389. rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
  390. fw_iso_resources_free(&dice->resources);
  391. }
  392. static int dice_change_rate(struct dice *dice, unsigned int clock_rate)
  393. {
  394. __be32 value;
  395. int err;
  396. INIT_COMPLETION(dice->clock_accepted);
  397. value = cpu_to_be32(clock_rate | CLOCK_SOURCE_ARX1);
  398. err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  399. global_address(dice, GLOBAL_CLOCK_SELECT),
  400. &value, 4, 0);
  401. if (err < 0)
  402. return err;
  403. wait_for_completion_timeout(&dice->clock_accepted,
  404. msecs_to_jiffies(100));
  405. return 0;
  406. }
  407. static int dice_hw_params(struct snd_pcm_substream *substream,
  408. struct snd_pcm_hw_params *hw_params)
  409. {
  410. struct dice *dice = substream->private_data;
  411. int err;
  412. mutex_lock(&dice->mutex);
  413. dice_stream_stop(dice);
  414. mutex_unlock(&dice->mutex);
  415. err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
  416. params_buffer_bytes(hw_params));
  417. if (err < 0)
  418. goto error;
  419. amdtp_out_stream_set_pcm_format(&dice->stream,
  420. params_format(hw_params));
  421. return 0;
  422. error:
  423. return err;
  424. }
  425. static int dice_hw_free(struct snd_pcm_substream *substream)
  426. {
  427. struct dice *dice = substream->private_data;
  428. mutex_lock(&dice->mutex);
  429. dice_stream_stop(dice);
  430. mutex_unlock(&dice->mutex);
  431. return snd_pcm_lib_free_vmalloc_buffer(substream);
  432. }
  433. static int dice_prepare(struct snd_pcm_substream *substream)
  434. {
  435. struct dice *dice = substream->private_data;
  436. int err;
  437. mutex_lock(&dice->mutex);
  438. if (amdtp_out_streaming_error(&dice->stream))
  439. dice_stream_stop_packets(dice);
  440. err = dice_stream_start(dice);
  441. if (err < 0) {
  442. mutex_unlock(&dice->mutex);
  443. return err;
  444. }
  445. mutex_unlock(&dice->mutex);
  446. amdtp_out_stream_pcm_prepare(&dice->stream);
  447. return 0;
  448. }
  449. static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
  450. {
  451. struct dice *dice = substream->private_data;
  452. struct snd_pcm_substream *pcm;
  453. switch (cmd) {
  454. case SNDRV_PCM_TRIGGER_START:
  455. pcm = substream;
  456. break;
  457. case SNDRV_PCM_TRIGGER_STOP:
  458. pcm = NULL;
  459. break;
  460. default:
  461. return -EINVAL;
  462. }
  463. amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
  464. return 0;
  465. }
  466. static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
  467. {
  468. struct dice *dice = substream->private_data;
  469. return amdtp_out_stream_pcm_pointer(&dice->stream);
  470. }
  471. static int dice_create_pcm(struct dice *dice)
  472. {
  473. static struct snd_pcm_ops ops = {
  474. .open = dice_open,
  475. .close = dice_close,
  476. .ioctl = snd_pcm_lib_ioctl,
  477. .hw_params = dice_hw_params,
  478. .hw_free = dice_hw_free,
  479. .prepare = dice_prepare,
  480. .trigger = dice_trigger,
  481. .pointer = dice_pointer,
  482. .page = snd_pcm_lib_get_vmalloc_page,
  483. .mmap = snd_pcm_lib_mmap_vmalloc,
  484. };
  485. struct snd_pcm *pcm;
  486. int err;
  487. err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
  488. if (err < 0)
  489. return err;
  490. pcm->private_data = dice;
  491. strcpy(pcm->name, dice->card->shortname);
  492. pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
  493. return 0;
  494. }
  495. static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
  496. long count, loff_t *offset)
  497. {
  498. struct dice *dice = hwdep->private_data;
  499. DEFINE_WAIT(wait);
  500. union snd_firewire_event event;
  501. spin_lock_irq(&dice->lock);
  502. while (!dice->dev_lock_changed && dice->notification_bits == 0) {
  503. prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
  504. spin_unlock_irq(&dice->lock);
  505. schedule();
  506. finish_wait(&dice->hwdep_wait, &wait);
  507. if (signal_pending(current))
  508. return -ERESTARTSYS;
  509. spin_lock_irq(&dice->lock);
  510. }
  511. memset(&event, 0, sizeof(event));
  512. if (dice->dev_lock_changed) {
  513. event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
  514. event.lock_status.status = dice->dev_lock_count > 0;
  515. dice->dev_lock_changed = false;
  516. count = min(count, (long)sizeof(event.lock_status));
  517. } else {
  518. event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
  519. event.dice_notification.notification = dice->notification_bits;
  520. dice->notification_bits = 0;
  521. count = min(count, (long)sizeof(event.dice_notification));
  522. }
  523. spin_unlock_irq(&dice->lock);
  524. if (copy_to_user(buf, &event, count))
  525. return -EFAULT;
  526. return count;
  527. }
  528. static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
  529. poll_table *wait)
  530. {
  531. struct dice *dice = hwdep->private_data;
  532. unsigned int events;
  533. poll_wait(file, &dice->hwdep_wait, wait);
  534. spin_lock_irq(&dice->lock);
  535. if (dice->dev_lock_changed || dice->notification_bits != 0)
  536. events = POLLIN | POLLRDNORM;
  537. else
  538. events = 0;
  539. spin_unlock_irq(&dice->lock);
  540. return events;
  541. }
  542. static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
  543. {
  544. struct fw_device *dev = fw_parent_device(dice->unit);
  545. struct snd_firewire_get_info info;
  546. memset(&info, 0, sizeof(info));
  547. info.type = SNDRV_FIREWIRE_TYPE_DICE;
  548. info.card = dev->card->index;
  549. *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
  550. *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
  551. strlcpy(info.device_name, dev_name(&dev->device),
  552. sizeof(info.device_name));
  553. if (copy_to_user(arg, &info, sizeof(info)))
  554. return -EFAULT;
  555. return 0;
  556. }
  557. static int dice_hwdep_lock(struct dice *dice)
  558. {
  559. int err;
  560. spin_lock_irq(&dice->lock);
  561. if (dice->dev_lock_count == 0) {
  562. dice->dev_lock_count = -1;
  563. err = 0;
  564. } else {
  565. err = -EBUSY;
  566. }
  567. spin_unlock_irq(&dice->lock);
  568. return err;
  569. }
  570. static int dice_hwdep_unlock(struct dice *dice)
  571. {
  572. int err;
  573. spin_lock_irq(&dice->lock);
  574. if (dice->dev_lock_count == -1) {
  575. dice->dev_lock_count = 0;
  576. err = 0;
  577. } else {
  578. err = -EBADFD;
  579. }
  580. spin_unlock_irq(&dice->lock);
  581. return err;
  582. }
  583. static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
  584. {
  585. struct dice *dice = hwdep->private_data;
  586. spin_lock_irq(&dice->lock);
  587. if (dice->dev_lock_count == -1)
  588. dice->dev_lock_count = 0;
  589. spin_unlock_irq(&dice->lock);
  590. return 0;
  591. }
  592. static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
  593. unsigned int cmd, unsigned long arg)
  594. {
  595. struct dice *dice = hwdep->private_data;
  596. switch (cmd) {
  597. case SNDRV_FIREWIRE_IOCTL_GET_INFO:
  598. return dice_hwdep_get_info(dice, (void __user *)arg);
  599. case SNDRV_FIREWIRE_IOCTL_LOCK:
  600. return dice_hwdep_lock(dice);
  601. case SNDRV_FIREWIRE_IOCTL_UNLOCK:
  602. return dice_hwdep_unlock(dice);
  603. default:
  604. return -ENOIOCTLCMD;
  605. }
  606. }
  607. #ifdef CONFIG_COMPAT
  608. static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
  609. unsigned int cmd, unsigned long arg)
  610. {
  611. return dice_hwdep_ioctl(hwdep, file, cmd,
  612. (unsigned long)compat_ptr(arg));
  613. }
  614. #else
  615. #define dice_hwdep_compat_ioctl NULL
  616. #endif
  617. static int dice_create_hwdep(struct dice *dice)
  618. {
  619. static const struct snd_hwdep_ops ops = {
  620. .read = dice_hwdep_read,
  621. .release = dice_hwdep_release,
  622. .poll = dice_hwdep_poll,
  623. .ioctl = dice_hwdep_ioctl,
  624. .ioctl_compat = dice_hwdep_compat_ioctl,
  625. };
  626. struct snd_hwdep *hwdep;
  627. int err;
  628. err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
  629. if (err < 0)
  630. return err;
  631. strcpy(hwdep->name, "DICE");
  632. hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
  633. hwdep->ops = ops;
  634. hwdep->private_data = dice;
  635. hwdep->exclusive = true;
  636. return 0;
  637. }
  638. static void dice_card_free(struct snd_card *card)
  639. {
  640. struct dice *dice = card->private_data;
  641. amdtp_out_stream_destroy(&dice->stream);
  642. fw_core_remove_address_handler(&dice->notification_handler);
  643. mutex_destroy(&dice->mutex);
  644. }
  645. #define DICE_CATEGORY_ID 0x04
  646. static int dice_interface_check(struct fw_unit *unit)
  647. {
  648. static const int min_values[10] = {
  649. 10, 0x64 / 4,
  650. 10, 0x18 / 4,
  651. 10, 0x18 / 4,
  652. 0, 0,
  653. 0, 0,
  654. };
  655. struct fw_device *device = fw_parent_device(unit);
  656. struct fw_csr_iterator it;
  657. int key, value, vendor = -1, model = -1, err;
  658. unsigned int i;
  659. __be32 pointers[ARRAY_SIZE(min_values)];
  660. __be32 version;
  661. /*
  662. * Check that GUID and unit directory are constructed according to DICE
  663. * rules, i.e., that the specifier ID is the GUID's OUI, and that the
  664. * GUID chip ID consists of the 8-bit DICE category ID, the 10-bit
  665. * product ID, and a 22-bit serial number.
  666. */
  667. fw_csr_iterator_init(&it, unit->directory);
  668. while (fw_csr_iterator_next(&it, &key, &value)) {
  669. switch (key) {
  670. case CSR_SPECIFIER_ID:
  671. vendor = value;
  672. break;
  673. case CSR_MODEL:
  674. model = value;
  675. break;
  676. }
  677. }
  678. if (device->config_rom[3] != ((vendor << 8) | DICE_CATEGORY_ID) ||
  679. device->config_rom[4] >> 22 != model)
  680. return -ENODEV;
  681. /*
  682. * Check that the sub address spaces exist and are located inside the
  683. * private address space. The minimum values are chosen so that all
  684. * minimally required registers are included.
  685. */
  686. err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
  687. DICE_PRIVATE_SPACE,
  688. pointers, sizeof(pointers), 0);
  689. if (err < 0)
  690. return -ENODEV;
  691. for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
  692. value = be32_to_cpu(pointers[i]);
  693. if (value < min_values[i] || value >= 0x40000)
  694. return -ENODEV;
  695. }
  696. /*
  697. * Check that the implemented DICE driver specification major version
  698. * number matches.
  699. */
  700. err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
  701. DICE_PRIVATE_SPACE +
  702. be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
  703. &version, 4, 0);
  704. if (err < 0)
  705. return -ENODEV;
  706. if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
  707. dev_err(&unit->device,
  708. "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
  709. return -ENODEV;
  710. }
  711. return 0;
  712. }
  713. static int highest_supported_mode_rate(struct dice *dice, unsigned int mode)
  714. {
  715. int i;
  716. for (i = ARRAY_SIZE(dice_rates) - 1; i >= 0; --i)
  717. if ((dice->clock_caps & (1 << i)) &&
  718. rate_index_to_mode(i) == mode)
  719. return i;
  720. return -1;
  721. }
  722. static int dice_read_mode_params(struct dice *dice, unsigned int mode)
  723. {
  724. __be32 values[2];
  725. int rate_index, err;
  726. rate_index = highest_supported_mode_rate(dice, mode);
  727. if (rate_index < 0) {
  728. dice->rx_channels[mode] = 0;
  729. dice->rx_midi_ports[mode] = 0;
  730. return 0;
  731. }
  732. err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
  733. if (err < 0)
  734. return err;
  735. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  736. rx_address(dice, RX_NUMBER_AUDIO),
  737. values, 2 * 4, 0);
  738. if (err < 0)
  739. return err;
  740. dice->rx_channels[mode] = be32_to_cpu(values[0]);
  741. dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
  742. return 0;
  743. }
  744. static int dice_read_params(struct dice *dice)
  745. {
  746. __be32 pointers[6];
  747. __be32 value;
  748. int mode, err;
  749. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  750. DICE_PRIVATE_SPACE,
  751. pointers, sizeof(pointers), 0);
  752. if (err < 0)
  753. return err;
  754. dice->global_offset = be32_to_cpu(pointers[0]) * 4;
  755. dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
  756. /* some very old firmwares don't tell about their clock support */
  757. if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
  758. err = snd_fw_transaction(
  759. dice->unit, TCODE_READ_QUADLET_REQUEST,
  760. global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
  761. &value, 4, 0);
  762. if (err < 0)
  763. return err;
  764. dice->clock_caps = be32_to_cpu(value);
  765. } else {
  766. /* this should be supported by any device */
  767. dice->clock_caps = CLOCK_CAP_RATE_44100 |
  768. CLOCK_CAP_RATE_48000 |
  769. CLOCK_CAP_SOURCE_ARX1 |
  770. CLOCK_CAP_SOURCE_INTERNAL;
  771. }
  772. for (mode = 2; mode >= 0; --mode) {
  773. err = dice_read_mode_params(dice, mode);
  774. if (err < 0)
  775. return err;
  776. }
  777. return 0;
  778. }
  779. static void dice_card_strings(struct dice *dice)
  780. {
  781. struct snd_card *card = dice->card;
  782. struct fw_device *dev = fw_parent_device(dice->unit);
  783. char vendor[32], model[32];
  784. unsigned int i;
  785. int err;
  786. strcpy(card->driver, "DICE");
  787. strcpy(card->shortname, "DICE");
  788. BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
  789. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  790. global_address(dice, GLOBAL_NICK_NAME),
  791. card->shortname, sizeof(card->shortname), 0);
  792. if (err >= 0) {
  793. /* DICE strings are returned in "always-wrong" endianness */
  794. BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
  795. for (i = 0; i < sizeof(card->shortname); i += 4)
  796. swab32s((u32 *)&card->shortname[i]);
  797. card->shortname[sizeof(card->shortname) - 1] = '\0';
  798. }
  799. strcpy(vendor, "?");
  800. fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
  801. strcpy(model, "?");
  802. fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
  803. snprintf(card->longname, sizeof(card->longname),
  804. "%s %s (serial %u) at %s, S%d",
  805. vendor, model, dev->config_rom[4] & 0x3fffff,
  806. dev_name(&dice->unit->device), 100 << dev->max_speed);
  807. strcpy(card->mixername, "DICE");
  808. }
  809. static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
  810. {
  811. struct snd_card *card;
  812. struct dice *dice;
  813. __be32 clock_sel;
  814. int err;
  815. err = dice_interface_check(unit);
  816. if (err < 0)
  817. return err;
  818. err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
  819. if (err < 0)
  820. return err;
  821. snd_card_set_dev(card, &unit->device);
  822. dice = card->private_data;
  823. dice->card = card;
  824. spin_lock_init(&dice->lock);
  825. mutex_init(&dice->mutex);
  826. dice->unit = unit;
  827. init_completion(&dice->clock_accepted);
  828. init_waitqueue_head(&dice->hwdep_wait);
  829. dice->notification_handler.length = 4;
  830. dice->notification_handler.address_callback = dice_notification;
  831. dice->notification_handler.callback_data = dice;
  832. err = fw_core_add_address_handler(&dice->notification_handler,
  833. &fw_high_memory_region);
  834. if (err < 0)
  835. goto err_mutex;
  836. err = dice_owner_set(dice);
  837. if (err < 0)
  838. goto err_notification_handler;
  839. err = dice_read_params(dice);
  840. if (err < 0)
  841. goto err_owner;
  842. err = fw_iso_resources_init(&dice->resources, unit);
  843. if (err < 0)
  844. goto err_owner;
  845. dice->resources.channels_mask = 0x00000000ffffffffuLL;
  846. err = amdtp_out_stream_init(&dice->stream, unit,
  847. CIP_BLOCKING | CIP_HI_DUALWIRE);
  848. if (err < 0)
  849. goto err_resources;
  850. card->private_free = dice_card_free;
  851. dice_card_strings(dice);
  852. err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
  853. global_address(dice, GLOBAL_CLOCK_SELECT),
  854. &clock_sel, 4, 0);
  855. if (err < 0)
  856. goto error;
  857. clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
  858. clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
  859. err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
  860. global_address(dice, GLOBAL_CLOCK_SELECT),
  861. &clock_sel, 4, 0);
  862. if (err < 0)
  863. goto error;
  864. err = dice_create_pcm(dice);
  865. if (err < 0)
  866. goto error;
  867. err = dice_create_hwdep(dice);
  868. if (err < 0)
  869. goto error;
  870. err = snd_card_register(card);
  871. if (err < 0)
  872. goto error;
  873. dev_set_drvdata(&unit->device, dice);
  874. return 0;
  875. err_resources:
  876. fw_iso_resources_destroy(&dice->resources);
  877. err_owner:
  878. dice_owner_clear(dice);
  879. err_notification_handler:
  880. fw_core_remove_address_handler(&dice->notification_handler);
  881. err_mutex:
  882. mutex_destroy(&dice->mutex);
  883. error:
  884. snd_card_free(card);
  885. return err;
  886. }
  887. static void dice_remove(struct fw_unit *unit)
  888. {
  889. struct dice *dice = dev_get_drvdata(&unit->device);
  890. amdtp_out_stream_pcm_abort(&dice->stream);
  891. snd_card_disconnect(dice->card);
  892. mutex_lock(&dice->mutex);
  893. dice_stream_stop(dice);
  894. dice_owner_clear(dice);
  895. mutex_unlock(&dice->mutex);
  896. snd_card_free_when_closed(dice->card);
  897. }
  898. static void dice_bus_reset(struct fw_unit *unit)
  899. {
  900. struct dice *dice = dev_get_drvdata(&unit->device);
  901. /*
  902. * On a bus reset, the DICE firmware disables streaming and then goes
  903. * off contemplating its own navel for hundreds of milliseconds before
  904. * it can react to any of our attempts to reenable streaming. This
  905. * means that we lose synchronization anyway, so we force our streams
  906. * to stop so that the application can restart them in an orderly
  907. * manner.
  908. */
  909. amdtp_out_stream_pcm_abort(&dice->stream);
  910. mutex_lock(&dice->mutex);
  911. dice->global_enabled = false;
  912. dice_stream_stop_packets(dice);
  913. dice_owner_update(dice);
  914. fw_iso_resources_update(&dice->resources);
  915. mutex_unlock(&dice->mutex);
  916. }
  917. #define DICE_INTERFACE 0x000001
  918. static const struct ieee1394_device_id dice_id_table[] = {
  919. {
  920. .match_flags = IEEE1394_MATCH_VERSION,
  921. .version = DICE_INTERFACE,
  922. },
  923. { }
  924. };
  925. MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
  926. static struct fw_driver dice_driver = {
  927. .driver = {
  928. .owner = THIS_MODULE,
  929. .name = KBUILD_MODNAME,
  930. .bus = &fw_bus_type,
  931. },
  932. .probe = dice_probe,
  933. .update = dice_bus_reset,
  934. .remove = dice_remove,
  935. .id_table = dice_id_table,
  936. };
  937. static int __init alsa_dice_init(void)
  938. {
  939. return driver_register(&dice_driver.driver);
  940. }
  941. static void __exit alsa_dice_exit(void)
  942. {
  943. driver_unregister(&dice_driver.driver);
  944. }
  945. module_init(alsa_dice_init);
  946. module_exit(alsa_dice_exit);