board-ap325rxa.c 14 KB

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  1. /*
  2. * Renesas - AP-325RXA
  3. * (Compatible with Algo System ., LTD. - AP-320A)
  4. *
  5. * Copyright (C) 2008 Renesas Solutions Corp.
  6. * Author : Yusuke Goda <goda.yuske@renesas.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mtd/physmap.h>
  17. #include <linux/mtd/sh_flctl.h>
  18. #include <linux/delay.h>
  19. #include <linux/i2c.h>
  20. #include <linux/smsc911x.h>
  21. #include <linux/gpio.h>
  22. #include <media/ov772x.h>
  23. #include <media/soc_camera.h>
  24. #include <media/soc_camera_platform.h>
  25. #include <media/sh_mobile_ceu.h>
  26. #include <video/sh_mobile_lcdc.h>
  27. #include <asm/io.h>
  28. #include <asm/clock.h>
  29. #include <cpu/sh7723.h>
  30. static struct smsc911x_platform_config smsc911x_config = {
  31. .phy_interface = PHY_INTERFACE_MODE_MII,
  32. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  33. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  34. .flags = SMSC911X_USE_32BIT,
  35. };
  36. static struct resource smsc9118_resources[] = {
  37. [0] = {
  38. .start = 0xb6080000,
  39. .end = 0xb60fffff,
  40. .flags = IORESOURCE_MEM,
  41. },
  42. [1] = {
  43. .start = 35,
  44. .end = 35,
  45. .flags = IORESOURCE_IRQ,
  46. }
  47. };
  48. static struct platform_device smsc9118_device = {
  49. .name = "smsc911x",
  50. .id = -1,
  51. .num_resources = ARRAY_SIZE(smsc9118_resources),
  52. .resource = smsc9118_resources,
  53. .dev = {
  54. .platform_data = &smsc911x_config,
  55. },
  56. };
  57. /*
  58. * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
  59. * If this area erased, this board can not boot.
  60. */
  61. static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
  62. {
  63. .name = "uboot",
  64. .offset = 0,
  65. .size = (1 * 1024 * 1024),
  66. .mask_flags = MTD_WRITEABLE, /* Read-only */
  67. }, {
  68. .name = "kernel",
  69. .offset = MTDPART_OFS_APPEND,
  70. .size = (2 * 1024 * 1024),
  71. }, {
  72. .name = "free-area0",
  73. .offset = MTDPART_OFS_APPEND,
  74. .size = ((7 * 1024 * 1024) + (512 * 1024)),
  75. }, {
  76. .name = "CPLD-Data",
  77. .offset = MTDPART_OFS_APPEND,
  78. .mask_flags = MTD_WRITEABLE, /* Read-only */
  79. .size = (1024 * 128 * 2),
  80. }, {
  81. .name = "free-area1",
  82. .offset = MTDPART_OFS_APPEND,
  83. .size = MTDPART_SIZ_FULL,
  84. },
  85. };
  86. static struct physmap_flash_data ap325rxa_nor_flash_data = {
  87. .width = 2,
  88. .parts = ap325rxa_nor_flash_partitions,
  89. .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
  90. };
  91. static struct resource ap325rxa_nor_flash_resources[] = {
  92. [0] = {
  93. .name = "NOR Flash",
  94. .start = 0x00000000,
  95. .end = 0x00ffffff,
  96. .flags = IORESOURCE_MEM,
  97. }
  98. };
  99. static struct platform_device ap325rxa_nor_flash_device = {
  100. .name = "physmap-flash",
  101. .resource = ap325rxa_nor_flash_resources,
  102. .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
  103. .dev = {
  104. .platform_data = &ap325rxa_nor_flash_data,
  105. },
  106. };
  107. static struct mtd_partition nand_partition_info[] = {
  108. {
  109. .name = "nand_data",
  110. .offset = 0,
  111. .size = MTDPART_SIZ_FULL,
  112. },
  113. };
  114. static struct resource nand_flash_resources[] = {
  115. [0] = {
  116. .start = 0xa4530000,
  117. .end = 0xa45300ff,
  118. .flags = IORESOURCE_MEM,
  119. }
  120. };
  121. static struct sh_flctl_platform_data nand_flash_data = {
  122. .parts = nand_partition_info,
  123. .nr_parts = ARRAY_SIZE(nand_partition_info),
  124. .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
  125. .has_hwecc = 1,
  126. };
  127. static struct platform_device nand_flash_device = {
  128. .name = "sh_flctl",
  129. .resource = nand_flash_resources,
  130. .num_resources = ARRAY_SIZE(nand_flash_resources),
  131. .dev = {
  132. .platform_data = &nand_flash_data,
  133. },
  134. };
  135. #define FPGA_LCDREG 0xB4100180
  136. #define FPGA_BKLREG 0xB4100212
  137. #define FPGA_LCDREG_VAL 0x0018
  138. #define PORT_MSELCRB 0xA4050182
  139. #define PORT_HIZCRC 0xA405015C
  140. #define PORT_DRVCRA 0xA405018A
  141. #define PORT_DRVCRB 0xA405018C
  142. static void ap320_wvga_power_on(void *board_data)
  143. {
  144. msleep(100);
  145. /* ASD AP-320/325 LCD ON */
  146. ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
  147. /* backlight */
  148. gpio_set_value(GPIO_PTS3, 0);
  149. ctrl_outw(0x100, FPGA_BKLREG);
  150. }
  151. static void ap320_wvga_power_off(void *board_data)
  152. {
  153. /* backlight */
  154. ctrl_outw(0, FPGA_BKLREG);
  155. gpio_set_value(GPIO_PTS3, 1);
  156. /* ASD AP-320/325 LCD OFF */
  157. ctrl_outw(0, FPGA_LCDREG);
  158. }
  159. static struct sh_mobile_lcdc_info lcdc_info = {
  160. .clock_source = LCDC_CLK_EXTERNAL,
  161. .ch[0] = {
  162. .chan = LCDC_CHAN_MAINLCD,
  163. .bpp = 16,
  164. .interface_type = RGB18,
  165. .clock_divider = 1,
  166. .lcd_cfg = {
  167. .name = "LB070WV1",
  168. .xres = 800,
  169. .yres = 480,
  170. .left_margin = 32,
  171. .right_margin = 160,
  172. .hsync_len = 8,
  173. .upper_margin = 63,
  174. .lower_margin = 80,
  175. .vsync_len = 1,
  176. .sync = 0, /* hsync and vsync are active low */
  177. },
  178. .lcd_size_cfg = { /* 7.0 inch */
  179. .width = 152,
  180. .height = 91,
  181. },
  182. .board_cfg = {
  183. .display_on = ap320_wvga_power_on,
  184. .display_off = ap320_wvga_power_off,
  185. },
  186. }
  187. };
  188. static struct resource lcdc_resources[] = {
  189. [0] = {
  190. .name = "LCDC",
  191. .start = 0xfe940000, /* P4-only space */
  192. .end = 0xfe942fff,
  193. .flags = IORESOURCE_MEM,
  194. },
  195. [1] = {
  196. .start = 28,
  197. .flags = IORESOURCE_IRQ,
  198. },
  199. };
  200. static struct platform_device lcdc_device = {
  201. .name = "sh_mobile_lcdc_fb",
  202. .num_resources = ARRAY_SIZE(lcdc_resources),
  203. .resource = lcdc_resources,
  204. .dev = {
  205. .platform_data = &lcdc_info,
  206. },
  207. .archdata = {
  208. .hwblk_id = HWBLK_LCDC,
  209. },
  210. };
  211. static void camera_power(int val)
  212. {
  213. gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
  214. mdelay(10);
  215. }
  216. #ifdef CONFIG_I2C
  217. /* support for the old ncm03j camera */
  218. static unsigned char camera_ncm03j_magic[] =
  219. {
  220. 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
  221. 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
  222. 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
  223. 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
  224. 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
  225. 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
  226. 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
  227. 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
  228. 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
  229. 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
  230. 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
  231. 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
  232. 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
  233. 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
  234. 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
  235. 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
  236. };
  237. static int camera_probe(void)
  238. {
  239. struct i2c_adapter *a = i2c_get_adapter(0);
  240. struct i2c_msg msg;
  241. int ret;
  242. if (!a)
  243. return -ENODEV;
  244. camera_power(1);
  245. msg.addr = 0x6e;
  246. msg.buf = camera_ncm03j_magic;
  247. msg.len = 2;
  248. msg.flags = 0;
  249. ret = i2c_transfer(a, &msg, 1);
  250. camera_power(0);
  251. return ret;
  252. }
  253. static int camera_set_capture(struct soc_camera_platform_info *info,
  254. int enable)
  255. {
  256. struct i2c_adapter *a = i2c_get_adapter(0);
  257. struct i2c_msg msg;
  258. int ret = 0;
  259. int i;
  260. camera_power(0);
  261. if (!enable)
  262. return 0; /* no disable for now */
  263. camera_power(1);
  264. for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
  265. u_int8_t buf[8];
  266. msg.addr = 0x6e;
  267. msg.buf = buf;
  268. msg.len = 2;
  269. msg.flags = 0;
  270. buf[0] = camera_ncm03j_magic[i];
  271. buf[1] = camera_ncm03j_magic[i + 1];
  272. ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
  273. }
  274. return ret;
  275. }
  276. static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev);
  277. static void ap325rxa_camera_del(struct soc_camera_link *icl);
  278. static struct soc_camera_platform_info camera_info = {
  279. .format_name = "UYVY",
  280. .format_depth = 16,
  281. .format = {
  282. .pixelformat = V4L2_PIX_FMT_UYVY,
  283. .colorspace = V4L2_COLORSPACE_SMPTE170M,
  284. .width = 640,
  285. .height = 480,
  286. },
  287. .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
  288. SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
  289. .set_capture = camera_set_capture,
  290. .link = {
  291. .bus_id = 0,
  292. .add_device = ap325rxa_camera_add,
  293. .del_device = ap325rxa_camera_del,
  294. .module_name = "soc_camera_platform",
  295. },
  296. };
  297. static void dummy_release(struct device *dev)
  298. {
  299. }
  300. static struct platform_device camera_device = {
  301. .name = "soc_camera_platform",
  302. .dev = {
  303. .platform_data = &camera_info,
  304. .release = dummy_release,
  305. },
  306. };
  307. static int ap325rxa_camera_add(struct soc_camera_link *icl,
  308. struct device *dev)
  309. {
  310. if (icl != &camera_info.link || camera_probe() <= 0)
  311. return -ENODEV;
  312. camera_info.dev = dev;
  313. return platform_device_register(&camera_device);
  314. }
  315. static void ap325rxa_camera_del(struct soc_camera_link *icl)
  316. {
  317. if (icl != &camera_info.link)
  318. return;
  319. platform_device_unregister(&camera_device);
  320. memset(&camera_device.dev.kobj, 0,
  321. sizeof(camera_device.dev.kobj));
  322. }
  323. #endif /* CONFIG_I2C */
  324. static int ov7725_power(struct device *dev, int mode)
  325. {
  326. camera_power(0);
  327. if (mode)
  328. camera_power(1);
  329. return 0;
  330. }
  331. static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
  332. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  333. };
  334. static struct resource ceu_resources[] = {
  335. [0] = {
  336. .name = "CEU",
  337. .start = 0xfe910000,
  338. .end = 0xfe91009f,
  339. .flags = IORESOURCE_MEM,
  340. },
  341. [1] = {
  342. .start = 52,
  343. .flags = IORESOURCE_IRQ,
  344. },
  345. [2] = {
  346. /* place holder for contiguous memory */
  347. },
  348. };
  349. static struct platform_device ceu_device = {
  350. .name = "sh_mobile_ceu",
  351. .id = 0, /* "ceu0" clock */
  352. .num_resources = ARRAY_SIZE(ceu_resources),
  353. .resource = ceu_resources,
  354. .dev = {
  355. .platform_data = &sh_mobile_ceu_info,
  356. },
  357. .archdata = {
  358. .hwblk_id = HWBLK_CEU,
  359. },
  360. };
  361. static struct resource sdhi0_cn3_resources[] = {
  362. [0] = {
  363. .name = "SDHI0",
  364. .start = 0x04ce0000,
  365. .end = 0x04ce01ff,
  366. .flags = IORESOURCE_MEM,
  367. },
  368. [1] = {
  369. .start = 101,
  370. .flags = IORESOURCE_IRQ,
  371. },
  372. };
  373. static struct platform_device sdhi0_cn3_device = {
  374. .name = "sh_mobile_sdhi",
  375. .num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
  376. .resource = sdhi0_cn3_resources,
  377. .archdata = {
  378. .hwblk_id = HWBLK_SDHI0,
  379. },
  380. };
  381. static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
  382. {
  383. I2C_BOARD_INFO("pcf8563", 0x51),
  384. },
  385. };
  386. static struct i2c_board_info ap325rxa_i2c_camera[] = {
  387. {
  388. I2C_BOARD_INFO("ov772x", 0x21),
  389. },
  390. };
  391. static struct ov772x_camera_info ov7725_info = {
  392. .buswidth = SOCAM_DATAWIDTH_8,
  393. .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
  394. .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
  395. .link = {
  396. .bus_id = 0,
  397. .power = ov7725_power,
  398. .board_info = &ap325rxa_i2c_camera[0],
  399. .i2c_adapter_id = 0,
  400. .module_name = "ov772x",
  401. },
  402. };
  403. static struct platform_device ap325rxa_camera[] = {
  404. {
  405. .name = "soc-camera-pdrv",
  406. .id = 0,
  407. .dev = {
  408. .platform_data = &ov7725_info.link,
  409. },
  410. }, {
  411. .name = "soc-camera-pdrv",
  412. .id = 1,
  413. .dev = {
  414. .platform_data = &camera_info.link,
  415. },
  416. },
  417. };
  418. static struct platform_device *ap325rxa_devices[] __initdata = {
  419. &smsc9118_device,
  420. &ap325rxa_nor_flash_device,
  421. &lcdc_device,
  422. &ceu_device,
  423. &nand_flash_device,
  424. &sdhi0_cn3_device,
  425. &ap325rxa_camera[0],
  426. &ap325rxa_camera[1],
  427. };
  428. static int __init ap325rxa_devices_setup(void)
  429. {
  430. /* LD3 and LD4 LEDs */
  431. gpio_request(GPIO_PTX5, NULL); /* RUN */
  432. gpio_direction_output(GPIO_PTX5, 1);
  433. gpio_export(GPIO_PTX5, 0);
  434. gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
  435. gpio_direction_output(GPIO_PTX4, 0);
  436. gpio_export(GPIO_PTX4, 0);
  437. /* SW1 input */
  438. gpio_request(GPIO_PTF7, NULL); /* MODE */
  439. gpio_direction_input(GPIO_PTF7);
  440. gpio_export(GPIO_PTF7, 0);
  441. /* LCDC */
  442. gpio_request(GPIO_FN_LCDD15, NULL);
  443. gpio_request(GPIO_FN_LCDD14, NULL);
  444. gpio_request(GPIO_FN_LCDD13, NULL);
  445. gpio_request(GPIO_FN_LCDD12, NULL);
  446. gpio_request(GPIO_FN_LCDD11, NULL);
  447. gpio_request(GPIO_FN_LCDD10, NULL);
  448. gpio_request(GPIO_FN_LCDD9, NULL);
  449. gpio_request(GPIO_FN_LCDD8, NULL);
  450. gpio_request(GPIO_FN_LCDD7, NULL);
  451. gpio_request(GPIO_FN_LCDD6, NULL);
  452. gpio_request(GPIO_FN_LCDD5, NULL);
  453. gpio_request(GPIO_FN_LCDD4, NULL);
  454. gpio_request(GPIO_FN_LCDD3, NULL);
  455. gpio_request(GPIO_FN_LCDD2, NULL);
  456. gpio_request(GPIO_FN_LCDD1, NULL);
  457. gpio_request(GPIO_FN_LCDD0, NULL);
  458. gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
  459. gpio_request(GPIO_FN_LCDDCK, NULL);
  460. gpio_request(GPIO_FN_LCDVEPWC, NULL);
  461. gpio_request(GPIO_FN_LCDVCPWC, NULL);
  462. gpio_request(GPIO_FN_LCDVSYN, NULL);
  463. gpio_request(GPIO_FN_LCDHSYN, NULL);
  464. gpio_request(GPIO_FN_LCDDISP, NULL);
  465. gpio_request(GPIO_FN_LCDDON, NULL);
  466. /* LCD backlight */
  467. gpio_request(GPIO_PTS3, NULL);
  468. gpio_direction_output(GPIO_PTS3, 1);
  469. /* CEU */
  470. gpio_request(GPIO_FN_VIO_CLK2, NULL);
  471. gpio_request(GPIO_FN_VIO_VD2, NULL);
  472. gpio_request(GPIO_FN_VIO_HD2, NULL);
  473. gpio_request(GPIO_FN_VIO_FLD, NULL);
  474. gpio_request(GPIO_FN_VIO_CKO, NULL);
  475. gpio_request(GPIO_FN_VIO_D15, NULL);
  476. gpio_request(GPIO_FN_VIO_D14, NULL);
  477. gpio_request(GPIO_FN_VIO_D13, NULL);
  478. gpio_request(GPIO_FN_VIO_D12, NULL);
  479. gpio_request(GPIO_FN_VIO_D11, NULL);
  480. gpio_request(GPIO_FN_VIO_D10, NULL);
  481. gpio_request(GPIO_FN_VIO_D9, NULL);
  482. gpio_request(GPIO_FN_VIO_D8, NULL);
  483. gpio_request(GPIO_PTZ7, NULL);
  484. gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
  485. gpio_request(GPIO_PTZ6, NULL);
  486. gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
  487. gpio_request(GPIO_PTZ5, NULL);
  488. gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
  489. gpio_request(GPIO_PTZ4, NULL);
  490. gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
  491. ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
  492. /* FLCTL */
  493. gpio_request(GPIO_FN_FCE, NULL);
  494. gpio_request(GPIO_FN_NAF7, NULL);
  495. gpio_request(GPIO_FN_NAF6, NULL);
  496. gpio_request(GPIO_FN_NAF5, NULL);
  497. gpio_request(GPIO_FN_NAF4, NULL);
  498. gpio_request(GPIO_FN_NAF3, NULL);
  499. gpio_request(GPIO_FN_NAF2, NULL);
  500. gpio_request(GPIO_FN_NAF1, NULL);
  501. gpio_request(GPIO_FN_NAF0, NULL);
  502. gpio_request(GPIO_FN_FCDE, NULL);
  503. gpio_request(GPIO_FN_FOE, NULL);
  504. gpio_request(GPIO_FN_FSC, NULL);
  505. gpio_request(GPIO_FN_FWE, NULL);
  506. gpio_request(GPIO_FN_FRB, NULL);
  507. ctrl_outw(0, PORT_HIZCRC);
  508. ctrl_outw(0xFFFF, PORT_DRVCRA);
  509. ctrl_outw(0xFFFF, PORT_DRVCRB);
  510. platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
  511. /* SDHI0 */
  512. gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
  513. gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
  514. gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
  515. gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
  516. gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
  517. gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
  518. gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
  519. gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
  520. i2c_register_board_info(0, ap325rxa_i2c_devices,
  521. ARRAY_SIZE(ap325rxa_i2c_devices));
  522. return platform_add_devices(ap325rxa_devices,
  523. ARRAY_SIZE(ap325rxa_devices));
  524. }
  525. arch_initcall(ap325rxa_devices_setup);
  526. /* Return the board specific boot mode pin configuration */
  527. static int ap325rxa_mode_pins(void)
  528. {
  529. /* MD0=0, MD1=0, MD2=0: Clock Mode 0
  530. * MD3=0: 16-bit Area0 Bus Width
  531. * MD5=1: Little Endian
  532. * TSTMD=1, MD8=1: Test Mode Disabled
  533. */
  534. return MODE_PIN5 | MODE_PIN8;
  535. }
  536. static struct sh_machine_vector mv_ap325rxa __initmv = {
  537. .mv_name = "AP-325RXA",
  538. .mv_mode_pins = ap325rxa_mode_pins,
  539. };