cx23885-dvb.c 39 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc4000.h"
  38. #include "xc5000.h"
  39. #include "max2165.h"
  40. #include "tda10048.h"
  41. #include "tuner-xc2028.h"
  42. #include "tuner-simple.h"
  43. #include "dib7000p.h"
  44. #include "dibx000_common.h"
  45. #include "zl10353.h"
  46. #include "stv0900.h"
  47. #include "stv0900_reg.h"
  48. #include "stv6110.h"
  49. #include "lnbh24.h"
  50. #include "cx24116.h"
  51. #include "cimax2.h"
  52. #include "lgs8gxx.h"
  53. #include "netup-eeprom.h"
  54. #include "netup-init.h"
  55. #include "lgdt3305.h"
  56. #include "atbm8830.h"
  57. #include "ts2020.h"
  58. #include "ds3000.h"
  59. #include "cx23885-f300.h"
  60. #include "altera-ci.h"
  61. #include "stv0367.h"
  62. #include "drxk.h"
  63. #include "mt2063.h"
  64. #include "stv090x.h"
  65. #include "stb6100.h"
  66. #include "stb6100_cfg.h"
  67. #include "tda10071.h"
  68. #include "a8293.h"
  69. static unsigned int debug;
  70. #define dprintk(level, fmt, arg...)\
  71. do { if (debug >= level)\
  72. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  73. } while (0)
  74. /* ------------------------------------------------------------------ */
  75. static unsigned int alt_tuner;
  76. module_param(alt_tuner, int, 0644);
  77. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  78. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  79. /* ------------------------------------------------------------------ */
  80. static int dvb_buf_setup(struct videobuf_queue *q,
  81. unsigned int *count, unsigned int *size)
  82. {
  83. struct cx23885_tsport *port = q->priv_data;
  84. port->ts_packet_size = 188 * 4;
  85. port->ts_packet_count = 32;
  86. *size = port->ts_packet_size * port->ts_packet_count;
  87. *count = 32;
  88. return 0;
  89. }
  90. static int dvb_buf_prepare(struct videobuf_queue *q,
  91. struct videobuf_buffer *vb, enum v4l2_field field)
  92. {
  93. struct cx23885_tsport *port = q->priv_data;
  94. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  95. }
  96. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  97. {
  98. struct cx23885_tsport *port = q->priv_data;
  99. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  100. }
  101. static void dvb_buf_release(struct videobuf_queue *q,
  102. struct videobuf_buffer *vb)
  103. {
  104. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  105. }
  106. static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
  107. {
  108. struct videobuf_dvb_frontends *f;
  109. struct videobuf_dvb_frontend *fe;
  110. f = &port->frontends;
  111. if (f->gate <= 1) /* undefined or fe0 */
  112. fe = videobuf_dvb_get_frontend(f, 1);
  113. else
  114. fe = videobuf_dvb_get_frontend(f, f->gate);
  115. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  116. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  117. }
  118. static struct videobuf_queue_ops dvb_qops = {
  119. .buf_setup = dvb_buf_setup,
  120. .buf_prepare = dvb_buf_prepare,
  121. .buf_queue = dvb_buf_queue,
  122. .buf_release = dvb_buf_release,
  123. };
  124. static struct s5h1409_config hauppauge_generic_config = {
  125. .demod_address = 0x32 >> 1,
  126. .output_mode = S5H1409_SERIAL_OUTPUT,
  127. .gpio = S5H1409_GPIO_ON,
  128. .qam_if = 44000,
  129. .inversion = S5H1409_INVERSION_OFF,
  130. .status_mode = S5H1409_DEMODLOCKING,
  131. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  132. };
  133. static struct tda10048_config hauppauge_hvr1200_config = {
  134. .demod_address = 0x10 >> 1,
  135. .output_mode = TDA10048_SERIAL_OUTPUT,
  136. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  137. .inversion = TDA10048_INVERSION_ON,
  138. .dtv6_if_freq_khz = TDA10048_IF_3300,
  139. .dtv7_if_freq_khz = TDA10048_IF_3800,
  140. .dtv8_if_freq_khz = TDA10048_IF_4300,
  141. .clk_freq_khz = TDA10048_CLK_16000,
  142. };
  143. static struct tda10048_config hauppauge_hvr1210_config = {
  144. .demod_address = 0x10 >> 1,
  145. .output_mode = TDA10048_SERIAL_OUTPUT,
  146. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  147. .inversion = TDA10048_INVERSION_ON,
  148. .dtv6_if_freq_khz = TDA10048_IF_3300,
  149. .dtv7_if_freq_khz = TDA10048_IF_3500,
  150. .dtv8_if_freq_khz = TDA10048_IF_4000,
  151. .clk_freq_khz = TDA10048_CLK_16000,
  152. };
  153. static struct s5h1409_config hauppauge_ezqam_config = {
  154. .demod_address = 0x32 >> 1,
  155. .output_mode = S5H1409_SERIAL_OUTPUT,
  156. .gpio = S5H1409_GPIO_OFF,
  157. .qam_if = 4000,
  158. .inversion = S5H1409_INVERSION_ON,
  159. .status_mode = S5H1409_DEMODLOCKING,
  160. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  161. };
  162. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  163. .demod_address = 0x32 >> 1,
  164. .output_mode = S5H1409_SERIAL_OUTPUT,
  165. .gpio = S5H1409_GPIO_OFF,
  166. .qam_if = 44000,
  167. .inversion = S5H1409_INVERSION_OFF,
  168. .status_mode = S5H1409_DEMODLOCKING,
  169. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  170. };
  171. static struct s5h1409_config hauppauge_hvr1500_config = {
  172. .demod_address = 0x32 >> 1,
  173. .output_mode = S5H1409_SERIAL_OUTPUT,
  174. .gpio = S5H1409_GPIO_OFF,
  175. .inversion = S5H1409_INVERSION_OFF,
  176. .status_mode = S5H1409_DEMODLOCKING,
  177. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  178. };
  179. static struct mt2131_config hauppauge_generic_tunerconfig = {
  180. 0x61
  181. };
  182. static struct lgdt330x_config fusionhdtv_5_express = {
  183. .demod_address = 0x0e,
  184. .demod_chip = LGDT3303,
  185. .serial_mpeg = 0x40,
  186. };
  187. static struct s5h1409_config hauppauge_hvr1500q_config = {
  188. .demod_address = 0x32 >> 1,
  189. .output_mode = S5H1409_SERIAL_OUTPUT,
  190. .gpio = S5H1409_GPIO_ON,
  191. .qam_if = 44000,
  192. .inversion = S5H1409_INVERSION_OFF,
  193. .status_mode = S5H1409_DEMODLOCKING,
  194. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  195. };
  196. static struct s5h1409_config dvico_s5h1409_config = {
  197. .demod_address = 0x32 >> 1,
  198. .output_mode = S5H1409_SERIAL_OUTPUT,
  199. .gpio = S5H1409_GPIO_ON,
  200. .qam_if = 44000,
  201. .inversion = S5H1409_INVERSION_OFF,
  202. .status_mode = S5H1409_DEMODLOCKING,
  203. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  204. };
  205. static struct s5h1411_config dvico_s5h1411_config = {
  206. .output_mode = S5H1411_SERIAL_OUTPUT,
  207. .gpio = S5H1411_GPIO_ON,
  208. .qam_if = S5H1411_IF_44000,
  209. .vsb_if = S5H1411_IF_44000,
  210. .inversion = S5H1411_INVERSION_OFF,
  211. .status_mode = S5H1411_DEMODLOCKING,
  212. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  213. };
  214. static struct s5h1411_config hcw_s5h1411_config = {
  215. .output_mode = S5H1411_SERIAL_OUTPUT,
  216. .gpio = S5H1411_GPIO_OFF,
  217. .vsb_if = S5H1411_IF_44000,
  218. .qam_if = S5H1411_IF_4000,
  219. .inversion = S5H1411_INVERSION_ON,
  220. .status_mode = S5H1411_DEMODLOCKING,
  221. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  222. };
  223. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  224. .i2c_address = 0x61,
  225. .if_khz = 5380,
  226. };
  227. static struct xc5000_config dvico_xc5000_tunerconfig = {
  228. .i2c_address = 0x64,
  229. .if_khz = 5380,
  230. };
  231. static struct tda829x_config tda829x_no_probe = {
  232. .probe_tuner = TDA829X_DONT_PROBE,
  233. };
  234. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  235. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  236. .if_lvl = 6, .rfagc_top = 0x37 },
  237. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  238. .if_lvl = 6, .rfagc_top = 0x37 },
  239. };
  240. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  241. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  242. .if_lvl = 1, .rfagc_top = 0x37, },
  243. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  244. .if_lvl = 1, .rfagc_top = 0x37, },
  245. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  246. .if_lvl = 1, .rfagc_top = 0x37, },
  247. };
  248. static struct tda18271_config hauppauge_tda18271_config = {
  249. .std_map = &hauppauge_tda18271_std_map,
  250. .gate = TDA18271_GATE_ANALOG,
  251. .output_opt = TDA18271_OUTPUT_LT_OFF,
  252. };
  253. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  254. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  255. .gate = TDA18271_GATE_ANALOG,
  256. .output_opt = TDA18271_OUTPUT_LT_OFF,
  257. };
  258. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  259. .gate = TDA18271_GATE_DIGITAL,
  260. .output_opt = TDA18271_OUTPUT_LT_OFF,
  261. };
  262. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  263. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  264. .if_lvl = 1, .rfagc_top = 0x58 },
  265. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  266. .if_lvl = 1, .rfagc_top = 0x58 },
  267. };
  268. static struct tda18271_config hauppauge_hvr127x_config = {
  269. .std_map = &hauppauge_hvr127x_std_map,
  270. .output_opt = TDA18271_OUTPUT_LT_OFF,
  271. };
  272. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  273. .i2c_addr = 0x0e,
  274. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  275. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  276. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  277. .deny_i2c_rptr = 1,
  278. .spectral_inversion = 1,
  279. .qam_if_khz = 4000,
  280. .vsb_if_khz = 3250,
  281. };
  282. static struct dibx000_agc_config xc3028_agc_config = {
  283. BAND_VHF | BAND_UHF, /* band_caps */
  284. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  285. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  286. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  287. * P_agc_nb_est=2, P_agc_write=0
  288. */
  289. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  290. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  291. 712, /* inv_gain */
  292. 21, /* time_stabiliz */
  293. 0, /* alpha_level */
  294. 118, /* thlock */
  295. 0, /* wbd_inv */
  296. 2867, /* wbd_ref */
  297. 0, /* wbd_sel */
  298. 2, /* wbd_alpha */
  299. 0, /* agc1_max */
  300. 0, /* agc1_min */
  301. 39718, /* agc2_max */
  302. 9930, /* agc2_min */
  303. 0, /* agc1_pt1 */
  304. 0, /* agc1_pt2 */
  305. 0, /* agc1_pt3 */
  306. 0, /* agc1_slope1 */
  307. 0, /* agc1_slope2 */
  308. 0, /* agc2_pt1 */
  309. 128, /* agc2_pt2 */
  310. 29, /* agc2_slope1 */
  311. 29, /* agc2_slope2 */
  312. 17, /* alpha_mant */
  313. 27, /* alpha_exp */
  314. 23, /* beta_mant */
  315. 51, /* beta_exp */
  316. 1, /* perform_agc_softsplit */
  317. };
  318. /* PLL Configuration for COFDM BW_MHz = 8.000000
  319. * With external clock = 30.000000 */
  320. static struct dibx000_bandwidth_config xc3028_bw_config = {
  321. 60000, /* internal */
  322. 30000, /* sampling */
  323. 1, /* pll_cfg: prediv */
  324. 8, /* pll_cfg: ratio */
  325. 3, /* pll_cfg: range */
  326. 1, /* pll_cfg: reset */
  327. 0, /* pll_cfg: bypass */
  328. 0, /* misc: refdiv */
  329. 0, /* misc: bypclk_div */
  330. 1, /* misc: IO_CLK_en_core */
  331. 1, /* misc: ADClkSrc */
  332. 0, /* misc: modulo */
  333. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  334. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  335. 20452225, /* timf */
  336. 30000000 /* xtal_hz */
  337. };
  338. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  339. .output_mpeg2_in_188_bytes = 1,
  340. .hostbus_diversity = 1,
  341. .tuner_is_baseband = 0,
  342. .update_lna = NULL,
  343. .agc_config_count = 1,
  344. .agc = &xc3028_agc_config,
  345. .bw = &xc3028_bw_config,
  346. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  347. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  348. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  349. .pwm_freq_div = 0,
  350. .agc_control = NULL,
  351. .spur_protect = 0,
  352. .output_mode = OUTMODE_MPEG2_SERIAL,
  353. };
  354. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  355. .demod_address = 0x0f,
  356. .if2 = 45600,
  357. .no_tuner = 1,
  358. .disable_i2c_gate_ctrl = 1,
  359. };
  360. static struct stv0900_reg stv0900_ts_regs[] = {
  361. { R0900_TSGENERAL, 0x00 },
  362. { R0900_P1_TSSPEED, 0x40 },
  363. { R0900_P2_TSSPEED, 0x40 },
  364. { R0900_P1_TSCFGM, 0xc0 },
  365. { R0900_P2_TSCFGM, 0xc0 },
  366. { R0900_P1_TSCFGH, 0xe0 },
  367. { R0900_P2_TSCFGH, 0xe0 },
  368. { R0900_P1_TSCFGL, 0x20 },
  369. { R0900_P2_TSCFGL, 0x20 },
  370. { 0xffff, 0xff }, /* terminate */
  371. };
  372. static struct stv0900_config netup_stv0900_config = {
  373. .demod_address = 0x68,
  374. .demod_mode = 1, /* dual */
  375. .xtal = 8000000,
  376. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  377. .diseqc_mode = 2,/* 2/3 PWM */
  378. .ts_config_regs = stv0900_ts_regs,
  379. .tun1_maddress = 0,/* 0x60 */
  380. .tun2_maddress = 3,/* 0x63 */
  381. .tun1_adc = 1,/* 1 Vpp */
  382. .tun2_adc = 1,/* 1 Vpp */
  383. };
  384. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  385. .i2c_address = 0x60,
  386. .mclk = 16000000,
  387. .clk_div = 1,
  388. .gain = 8, /* +16 dB - maximum gain */
  389. };
  390. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  391. .i2c_address = 0x63,
  392. .mclk = 16000000,
  393. .clk_div = 1,
  394. .gain = 8, /* +16 dB - maximum gain */
  395. };
  396. static struct cx24116_config tbs_cx24116_config = {
  397. .demod_address = 0x55,
  398. };
  399. static struct ds3000_config tevii_ds3000_config = {
  400. .demod_address = 0x68,
  401. };
  402. static struct ts2020_config tevii_ts2020_config = {
  403. .tuner_address = 0x60,
  404. .clk_out_div = 1,
  405. };
  406. static struct cx24116_config dvbworld_cx24116_config = {
  407. .demod_address = 0x05,
  408. };
  409. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  410. .prod = LGS8GXX_PROD_LGS8GL5,
  411. .demod_address = 0x19,
  412. .serial_ts = 0,
  413. .ts_clk_pol = 1,
  414. .ts_clk_gated = 1,
  415. .if_clk_freq = 30400, /* 30.4 MHz */
  416. .if_freq = 5380, /* 5.38 MHz */
  417. .if_neg_center = 1,
  418. .ext_adc = 0,
  419. .adc_signed = 0,
  420. .if_neg_edge = 0,
  421. };
  422. static struct xc5000_config mygica_x8506_xc5000_config = {
  423. .i2c_address = 0x61,
  424. .if_khz = 5380,
  425. };
  426. static struct stv090x_config prof_8000_stv090x_config = {
  427. .device = STV0903,
  428. .demod_mode = STV090x_SINGLE,
  429. .clk_mode = STV090x_CLK_EXT,
  430. .xtal = 27000000,
  431. .address = 0x6A,
  432. .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
  433. .repeater_level = STV090x_RPTLEVEL_64,
  434. .adc1_range = STV090x_ADC_2Vpp,
  435. .diseqc_envelope_mode = false,
  436. .tuner_get_frequency = stb6100_get_frequency,
  437. .tuner_set_frequency = stb6100_set_frequency,
  438. .tuner_set_bandwidth = stb6100_set_bandwidth,
  439. .tuner_get_bandwidth = stb6100_get_bandwidth,
  440. };
  441. static struct stb6100_config prof_8000_stb6100_config = {
  442. .tuner_address = 0x60,
  443. .refclock = 27000000,
  444. };
  445. static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  446. {
  447. struct cx23885_tsport *port = fe->dvb->priv;
  448. struct cx23885_dev *dev = port->dev;
  449. if (voltage == SEC_VOLTAGE_18)
  450. cx_write(MC417_RWD, 0x00001e00);
  451. else if (voltage == SEC_VOLTAGE_13)
  452. cx_write(MC417_RWD, 0x00001a00);
  453. else
  454. cx_write(MC417_RWD, 0x00001800);
  455. return 0;
  456. }
  457. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
  458. {
  459. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  460. struct cx23885_tsport *port = fe->dvb->priv;
  461. struct cx23885_dev *dev = port->dev;
  462. switch (dev->board) {
  463. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  464. switch (p->modulation) {
  465. case VSB_8:
  466. cx23885_gpio_clear(dev, GPIO_5);
  467. break;
  468. case QAM_64:
  469. case QAM_256:
  470. default:
  471. cx23885_gpio_set(dev, GPIO_5);
  472. break;
  473. }
  474. break;
  475. case CX23885_BOARD_MYGICA_X8506:
  476. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  477. /* Select Digital TV */
  478. cx23885_gpio_set(dev, GPIO_0);
  479. break;
  480. }
  481. /* Call the real set_frontend */
  482. if (port->set_frontend)
  483. return port->set_frontend(fe);
  484. return 0;
  485. }
  486. static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
  487. struct dvb_frontend *fe)
  488. {
  489. port->set_frontend = fe->ops.set_frontend;
  490. fe->ops.set_frontend = cx23885_dvb_set_frontend;
  491. }
  492. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  493. .prod = LGS8GXX_PROD_LGS8G75,
  494. .demod_address = 0x19,
  495. .serial_ts = 0,
  496. .ts_clk_pol = 1,
  497. .ts_clk_gated = 1,
  498. .if_clk_freq = 30400, /* 30.4 MHz */
  499. .if_freq = 6500, /* 6.50 MHz */
  500. .if_neg_center = 1,
  501. .ext_adc = 0,
  502. .adc_signed = 1,
  503. .adc_vpp = 2, /* 1.6 Vpp */
  504. .if_neg_edge = 1,
  505. };
  506. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  507. .i2c_address = 0x61,
  508. .if_khz = 6500,
  509. };
  510. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  511. .prod = ATBM8830_PROD_8830,
  512. .demod_address = 0x44,
  513. .serial_ts = 0,
  514. .ts_sampling_edge = 1,
  515. .ts_clk_gated = 0,
  516. .osc_clk_freq = 30400, /* in kHz */
  517. .if_freq = 0, /* zero IF */
  518. .zif_swap_iq = 1,
  519. .agc_min = 0x2E,
  520. .agc_max = 0xFF,
  521. .agc_hold_loop = 0,
  522. };
  523. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  524. .i2c_address = 0x60,
  525. .osc_clk = 20
  526. };
  527. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  528. .prod = ATBM8830_PROD_8830,
  529. .demod_address = 0x44,
  530. .serial_ts = 1,
  531. .ts_sampling_edge = 1,
  532. .ts_clk_gated = 0,
  533. .osc_clk_freq = 30400, /* in kHz */
  534. .if_freq = 0, /* zero IF */
  535. .zif_swap_iq = 1,
  536. .agc_min = 0x2E,
  537. .agc_max = 0xFF,
  538. .agc_hold_loop = 0,
  539. };
  540. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  541. .i2c_address = 0x60,
  542. .osc_clk = 20
  543. };
  544. static struct stv0367_config netup_stv0367_config[] = {
  545. {
  546. .demod_address = 0x1c,
  547. .xtal = 27000000,
  548. .if_khz = 4500,
  549. .if_iq_mode = 0,
  550. .ts_mode = 1,
  551. .clk_pol = 0,
  552. }, {
  553. .demod_address = 0x1d,
  554. .xtal = 27000000,
  555. .if_khz = 4500,
  556. .if_iq_mode = 0,
  557. .ts_mode = 1,
  558. .clk_pol = 0,
  559. },
  560. };
  561. static struct xc5000_config netup_xc5000_config[] = {
  562. {
  563. .i2c_address = 0x61,
  564. .if_khz = 4500,
  565. }, {
  566. .i2c_address = 0x64,
  567. .if_khz = 4500,
  568. },
  569. };
  570. static struct drxk_config terratec_drxk_config[] = {
  571. {
  572. .adr = 0x29,
  573. .no_i2c_bridge = 1,
  574. }, {
  575. .adr = 0x2a,
  576. .no_i2c_bridge = 1,
  577. },
  578. };
  579. static struct mt2063_config terratec_mt2063_config[] = {
  580. {
  581. .tuner_address = 0x60,
  582. }, {
  583. .tuner_address = 0x67,
  584. },
  585. };
  586. static const struct tda10071_config hauppauge_tda10071_config = {
  587. .demod_i2c_addr = 0x05,
  588. .tuner_i2c_addr = 0x54,
  589. .i2c_wr_max = 64,
  590. .ts_mode = TDA10071_TS_SERIAL,
  591. .spec_inv = 0,
  592. .xtal = 40444000, /* 40.444 MHz */
  593. .pll_multiplier = 20,
  594. };
  595. static const struct a8293_config hauppauge_a8293_config = {
  596. .i2c_addr = 0x0b,
  597. };
  598. static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
  599. {
  600. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  601. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  602. uint32_t mem = 0;
  603. mem = cx_read(MC417_RWD);
  604. if (read)
  605. cx_set(MC417_OEN, ALT_DATA);
  606. else {
  607. cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
  608. mem &= ~ALT_DATA;
  609. mem |= (data & ALT_DATA);
  610. }
  611. if (flag)
  612. mem |= ALT_AD_RG;
  613. else
  614. mem &= ~ALT_AD_RG;
  615. mem &= ~ALT_CS;
  616. if (read)
  617. mem = (mem & ~ALT_RD) | ALT_WR;
  618. else
  619. mem = (mem & ~ALT_WR) | ALT_RD;
  620. cx_write(MC417_RWD, mem); /* start RW cycle */
  621. for (;;) {
  622. mem = cx_read(MC417_RWD);
  623. if ((mem & ALT_RDY) == 0)
  624. break;
  625. if (time_after(jiffies, timeout))
  626. break;
  627. udelay(1);
  628. }
  629. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  630. if (read)
  631. return mem & ALT_DATA;
  632. return 0;
  633. };
  634. static int dvb_register(struct cx23885_tsport *port)
  635. {
  636. struct cx23885_dev *dev = port->dev;
  637. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  638. struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
  639. int mfe_shared = 0; /* bus not shared by default */
  640. int ret;
  641. /* Get the first frontend */
  642. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  643. if (!fe0)
  644. return -EINVAL;
  645. /* init struct videobuf_dvb */
  646. fe0->dvb.name = dev->name;
  647. /* multi-frontend gate control is undefined or defaults to fe0 */
  648. port->frontends.gate = 0;
  649. /* Sets the gate control callback to be used by i2c command calls */
  650. port->gate_ctrl = cx23885_dvb_gate_ctrl;
  651. /* init frontend */
  652. switch (dev->board) {
  653. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  654. i2c_bus = &dev->i2c_bus[0];
  655. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  656. &hauppauge_generic_config,
  657. &i2c_bus->i2c_adap);
  658. if (fe0->dvb.frontend != NULL) {
  659. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  660. &i2c_bus->i2c_adap,
  661. &hauppauge_generic_tunerconfig, 0);
  662. }
  663. break;
  664. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  665. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  666. i2c_bus = &dev->i2c_bus[0];
  667. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  668. &hauppauge_lgdt3305_config,
  669. &i2c_bus->i2c_adap);
  670. if (fe0->dvb.frontend != NULL) {
  671. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  672. 0x60, &dev->i2c_bus[1].i2c_adap,
  673. &hauppauge_hvr127x_config);
  674. }
  675. if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
  676. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  677. break;
  678. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  679. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  680. i2c_bus = &dev->i2c_bus[0];
  681. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  682. &hcw_s5h1411_config,
  683. &i2c_bus->i2c_adap);
  684. if (fe0->dvb.frontend != NULL) {
  685. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  686. 0x60, &dev->i2c_bus[1].i2c_adap,
  687. &hauppauge_tda18271_config);
  688. }
  689. tda18271_attach(&dev->ts1.analog_fe,
  690. 0x60, &dev->i2c_bus[1].i2c_adap,
  691. &hauppauge_tda18271_config);
  692. break;
  693. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  694. i2c_bus = &dev->i2c_bus[0];
  695. switch (alt_tuner) {
  696. case 1:
  697. fe0->dvb.frontend =
  698. dvb_attach(s5h1409_attach,
  699. &hauppauge_ezqam_config,
  700. &i2c_bus->i2c_adap);
  701. if (fe0->dvb.frontend != NULL) {
  702. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  703. &dev->i2c_bus[1].i2c_adap, 0x42,
  704. &tda829x_no_probe);
  705. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  706. 0x60, &dev->i2c_bus[1].i2c_adap,
  707. &hauppauge_tda18271_config);
  708. }
  709. break;
  710. case 0:
  711. default:
  712. fe0->dvb.frontend =
  713. dvb_attach(s5h1409_attach,
  714. &hauppauge_generic_config,
  715. &i2c_bus->i2c_adap);
  716. if (fe0->dvb.frontend != NULL)
  717. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  718. &i2c_bus->i2c_adap,
  719. &hauppauge_generic_tunerconfig, 0);
  720. break;
  721. }
  722. break;
  723. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  724. i2c_bus = &dev->i2c_bus[0];
  725. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  726. &hauppauge_hvr1800lp_config,
  727. &i2c_bus->i2c_adap);
  728. if (fe0->dvb.frontend != NULL) {
  729. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  730. &i2c_bus->i2c_adap,
  731. &hauppauge_generic_tunerconfig, 0);
  732. }
  733. break;
  734. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  735. i2c_bus = &dev->i2c_bus[0];
  736. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  737. &fusionhdtv_5_express,
  738. &i2c_bus->i2c_adap);
  739. if (fe0->dvb.frontend != NULL) {
  740. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  741. &i2c_bus->i2c_adap, 0x61,
  742. TUNER_LG_TDVS_H06XF);
  743. }
  744. break;
  745. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  746. i2c_bus = &dev->i2c_bus[1];
  747. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  748. &hauppauge_hvr1500q_config,
  749. &dev->i2c_bus[0].i2c_adap);
  750. if (fe0->dvb.frontend != NULL)
  751. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  752. &i2c_bus->i2c_adap,
  753. &hauppauge_hvr1500q_tunerconfig);
  754. break;
  755. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  756. i2c_bus = &dev->i2c_bus[1];
  757. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  758. &hauppauge_hvr1500_config,
  759. &dev->i2c_bus[0].i2c_adap);
  760. if (fe0->dvb.frontend != NULL) {
  761. struct dvb_frontend *fe;
  762. struct xc2028_config cfg = {
  763. .i2c_adap = &i2c_bus->i2c_adap,
  764. .i2c_addr = 0x61,
  765. };
  766. static struct xc2028_ctrl ctl = {
  767. .fname = XC2028_DEFAULT_FIRMWARE,
  768. .max_len = 64,
  769. .demod = XC3028_FE_OREN538,
  770. };
  771. fe = dvb_attach(xc2028_attach,
  772. fe0->dvb.frontend, &cfg);
  773. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  774. fe->ops.tuner_ops.set_config(fe, &ctl);
  775. }
  776. break;
  777. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  778. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  779. i2c_bus = &dev->i2c_bus[0];
  780. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  781. &hauppauge_hvr1200_config,
  782. &i2c_bus->i2c_adap);
  783. if (fe0->dvb.frontend != NULL) {
  784. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  785. &dev->i2c_bus[1].i2c_adap, 0x42,
  786. &tda829x_no_probe);
  787. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  788. 0x60, &dev->i2c_bus[1].i2c_adap,
  789. &hauppauge_hvr1200_tuner_config);
  790. }
  791. break;
  792. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  793. i2c_bus = &dev->i2c_bus[0];
  794. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  795. &hauppauge_hvr1210_config,
  796. &i2c_bus->i2c_adap);
  797. if (fe0->dvb.frontend != NULL) {
  798. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  799. 0x60, &dev->i2c_bus[1].i2c_adap,
  800. &hauppauge_hvr1210_tuner_config);
  801. }
  802. break;
  803. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  804. i2c_bus = &dev->i2c_bus[0];
  805. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  806. &i2c_bus->i2c_adap,
  807. 0x12, &hauppauge_hvr1400_dib7000_config);
  808. if (fe0->dvb.frontend != NULL) {
  809. struct dvb_frontend *fe;
  810. struct xc2028_config cfg = {
  811. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  812. .i2c_addr = 0x64,
  813. };
  814. static struct xc2028_ctrl ctl = {
  815. .fname = XC3028L_DEFAULT_FIRMWARE,
  816. .max_len = 64,
  817. .demod = XC3028_FE_DIBCOM52,
  818. /* This is true for all demods with
  819. v36 firmware? */
  820. .type = XC2028_D2633,
  821. };
  822. fe = dvb_attach(xc2028_attach,
  823. fe0->dvb.frontend, &cfg);
  824. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  825. fe->ops.tuner_ops.set_config(fe, &ctl);
  826. }
  827. break;
  828. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  829. i2c_bus = &dev->i2c_bus[port->nr - 1];
  830. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  831. &dvico_s5h1409_config,
  832. &i2c_bus->i2c_adap);
  833. if (fe0->dvb.frontend == NULL)
  834. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  835. &dvico_s5h1411_config,
  836. &i2c_bus->i2c_adap);
  837. if (fe0->dvb.frontend != NULL)
  838. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  839. &i2c_bus->i2c_adap,
  840. &dvico_xc5000_tunerconfig);
  841. break;
  842. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  843. i2c_bus = &dev->i2c_bus[port->nr - 1];
  844. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  845. &dvico_fusionhdtv_xc3028,
  846. &i2c_bus->i2c_adap);
  847. if (fe0->dvb.frontend != NULL) {
  848. struct dvb_frontend *fe;
  849. struct xc2028_config cfg = {
  850. .i2c_adap = &i2c_bus->i2c_adap,
  851. .i2c_addr = 0x61,
  852. };
  853. static struct xc2028_ctrl ctl = {
  854. .fname = XC2028_DEFAULT_FIRMWARE,
  855. .max_len = 64,
  856. .demod = XC3028_FE_ZARLINK456,
  857. };
  858. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  859. &cfg);
  860. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  861. fe->ops.tuner_ops.set_config(fe, &ctl);
  862. }
  863. break;
  864. }
  865. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  866. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  867. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  868. i2c_bus = &dev->i2c_bus[0];
  869. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  870. &dvico_fusionhdtv_xc3028,
  871. &i2c_bus->i2c_adap);
  872. if (fe0->dvb.frontend != NULL) {
  873. struct dvb_frontend *fe;
  874. struct xc2028_config cfg = {
  875. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  876. .i2c_addr = 0x61,
  877. };
  878. static struct xc2028_ctrl ctl = {
  879. .fname = XC2028_DEFAULT_FIRMWARE,
  880. .max_len = 64,
  881. .demod = XC3028_FE_ZARLINK456,
  882. };
  883. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  884. &cfg);
  885. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  886. fe->ops.tuner_ops.set_config(fe, &ctl);
  887. }
  888. break;
  889. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  890. i2c_bus = &dev->i2c_bus[0];
  891. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  892. &dvico_fusionhdtv_xc3028,
  893. &i2c_bus->i2c_adap);
  894. if (fe0->dvb.frontend != NULL) {
  895. struct dvb_frontend *fe;
  896. struct xc4000_config cfg = {
  897. .i2c_address = 0x61,
  898. .default_pm = 0,
  899. .dvb_amplitude = 134,
  900. .set_smoothedcvbs = 1,
  901. .if_khz = 4560
  902. };
  903. fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
  904. &dev->i2c_bus[1].i2c_adap, &cfg);
  905. if (!fe) {
  906. printk(KERN_ERR "%s/2: xc4000 attach failed\n",
  907. dev->name);
  908. goto frontend_detach;
  909. }
  910. }
  911. break;
  912. case CX23885_BOARD_TBS_6920:
  913. i2c_bus = &dev->i2c_bus[1];
  914. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  915. &tbs_cx24116_config,
  916. &i2c_bus->i2c_adap);
  917. if (fe0->dvb.frontend != NULL)
  918. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  919. break;
  920. case CX23885_BOARD_TEVII_S470:
  921. i2c_bus = &dev->i2c_bus[1];
  922. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  923. &tevii_ds3000_config,
  924. &i2c_bus->i2c_adap);
  925. if (fe0->dvb.frontend != NULL) {
  926. dvb_attach(ts2020_attach, fe0->dvb.frontend,
  927. &tevii_ts2020_config, &i2c_bus->i2c_adap);
  928. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  929. }
  930. break;
  931. case CX23885_BOARD_DVBWORLD_2005:
  932. i2c_bus = &dev->i2c_bus[1];
  933. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  934. &dvbworld_cx24116_config,
  935. &i2c_bus->i2c_adap);
  936. break;
  937. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  938. i2c_bus = &dev->i2c_bus[0];
  939. switch (port->nr) {
  940. /* port B */
  941. case 1:
  942. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  943. &netup_stv0900_config,
  944. &i2c_bus->i2c_adap, 0);
  945. if (fe0->dvb.frontend != NULL) {
  946. if (dvb_attach(stv6110_attach,
  947. fe0->dvb.frontend,
  948. &netup_stv6110_tunerconfig_a,
  949. &i2c_bus->i2c_adap)) {
  950. if (!dvb_attach(lnbh24_attach,
  951. fe0->dvb.frontend,
  952. &i2c_bus->i2c_adap,
  953. LNBH24_PCL | LNBH24_TTX,
  954. LNBH24_TEN, 0x09))
  955. printk(KERN_ERR
  956. "No LNBH24 found!\n");
  957. }
  958. }
  959. break;
  960. /* port C */
  961. case 2:
  962. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  963. &netup_stv0900_config,
  964. &i2c_bus->i2c_adap, 1);
  965. if (fe0->dvb.frontend != NULL) {
  966. if (dvb_attach(stv6110_attach,
  967. fe0->dvb.frontend,
  968. &netup_stv6110_tunerconfig_b,
  969. &i2c_bus->i2c_adap)) {
  970. if (!dvb_attach(lnbh24_attach,
  971. fe0->dvb.frontend,
  972. &i2c_bus->i2c_adap,
  973. LNBH24_PCL | LNBH24_TTX,
  974. LNBH24_TEN, 0x0a))
  975. printk(KERN_ERR
  976. "No LNBH24 found!\n");
  977. }
  978. }
  979. break;
  980. }
  981. break;
  982. case CX23885_BOARD_MYGICA_X8506:
  983. i2c_bus = &dev->i2c_bus[0];
  984. i2c_bus2 = &dev->i2c_bus[1];
  985. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  986. &mygica_x8506_lgs8gl5_config,
  987. &i2c_bus->i2c_adap);
  988. if (fe0->dvb.frontend != NULL) {
  989. dvb_attach(xc5000_attach,
  990. fe0->dvb.frontend,
  991. &i2c_bus2->i2c_adap,
  992. &mygica_x8506_xc5000_config);
  993. }
  994. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  995. break;
  996. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  997. i2c_bus = &dev->i2c_bus[0];
  998. i2c_bus2 = &dev->i2c_bus[1];
  999. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  1000. &magicpro_prohdtve2_lgs8g75_config,
  1001. &i2c_bus->i2c_adap);
  1002. if (fe0->dvb.frontend != NULL) {
  1003. dvb_attach(xc5000_attach,
  1004. fe0->dvb.frontend,
  1005. &i2c_bus2->i2c_adap,
  1006. &magicpro_prohdtve2_xc5000_config);
  1007. }
  1008. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  1009. break;
  1010. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1011. i2c_bus = &dev->i2c_bus[0];
  1012. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1013. &hcw_s5h1411_config,
  1014. &i2c_bus->i2c_adap);
  1015. if (fe0->dvb.frontend != NULL)
  1016. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  1017. 0x60, &dev->i2c_bus[0].i2c_adap,
  1018. &hauppauge_tda18271_config);
  1019. tda18271_attach(&dev->ts1.analog_fe,
  1020. 0x60, &dev->i2c_bus[1].i2c_adap,
  1021. &hauppauge_tda18271_config);
  1022. break;
  1023. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1024. i2c_bus = &dev->i2c_bus[0];
  1025. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1026. &hcw_s5h1411_config,
  1027. &i2c_bus->i2c_adap);
  1028. if (fe0->dvb.frontend != NULL)
  1029. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  1030. 0x60, &dev->i2c_bus[0].i2c_adap,
  1031. &hauppauge_tda18271_config);
  1032. break;
  1033. case CX23885_BOARD_MYGICA_X8558PRO:
  1034. switch (port->nr) {
  1035. /* port B */
  1036. case 1:
  1037. i2c_bus = &dev->i2c_bus[0];
  1038. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1039. &mygica_x8558pro_atbm8830_cfg1,
  1040. &i2c_bus->i2c_adap);
  1041. if (fe0->dvb.frontend != NULL) {
  1042. dvb_attach(max2165_attach,
  1043. fe0->dvb.frontend,
  1044. &i2c_bus->i2c_adap,
  1045. &mygic_x8558pro_max2165_cfg1);
  1046. }
  1047. break;
  1048. /* port C */
  1049. case 2:
  1050. i2c_bus = &dev->i2c_bus[1];
  1051. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1052. &mygica_x8558pro_atbm8830_cfg2,
  1053. &i2c_bus->i2c_adap);
  1054. if (fe0->dvb.frontend != NULL) {
  1055. dvb_attach(max2165_attach,
  1056. fe0->dvb.frontend,
  1057. &i2c_bus->i2c_adap,
  1058. &mygic_x8558pro_max2165_cfg2);
  1059. }
  1060. break;
  1061. }
  1062. break;
  1063. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1064. i2c_bus = &dev->i2c_bus[0];
  1065. mfe_shared = 1;/* MFE */
  1066. port->frontends.gate = 0;/* not clear for me yet */
  1067. /* ports B, C */
  1068. /* MFE frontend 1 DVB-T */
  1069. fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
  1070. &netup_stv0367_config[port->nr - 1],
  1071. &i2c_bus->i2c_adap);
  1072. if (fe0->dvb.frontend != NULL) {
  1073. if (NULL == dvb_attach(xc5000_attach,
  1074. fe0->dvb.frontend,
  1075. &i2c_bus->i2c_adap,
  1076. &netup_xc5000_config[port->nr - 1]))
  1077. goto frontend_detach;
  1078. /* load xc5000 firmware */
  1079. fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
  1080. }
  1081. /* MFE frontend 2 */
  1082. fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
  1083. if (fe1 == NULL)
  1084. goto frontend_detach;
  1085. /* DVB-C init */
  1086. fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
  1087. &netup_stv0367_config[port->nr - 1],
  1088. &i2c_bus->i2c_adap);
  1089. if (fe1->dvb.frontend != NULL) {
  1090. fe1->dvb.frontend->id = 1;
  1091. if (NULL == dvb_attach(xc5000_attach,
  1092. fe1->dvb.frontend,
  1093. &i2c_bus->i2c_adap,
  1094. &netup_xc5000_config[port->nr - 1]))
  1095. goto frontend_detach;
  1096. }
  1097. break;
  1098. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1099. i2c_bus = &dev->i2c_bus[0];
  1100. i2c_bus2 = &dev->i2c_bus[1];
  1101. switch (port->nr) {
  1102. /* port b */
  1103. case 1:
  1104. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1105. &terratec_drxk_config[0],
  1106. &i2c_bus->i2c_adap);
  1107. if (fe0->dvb.frontend != NULL) {
  1108. if (!dvb_attach(mt2063_attach,
  1109. fe0->dvb.frontend,
  1110. &terratec_mt2063_config[0],
  1111. &i2c_bus2->i2c_adap))
  1112. goto frontend_detach;
  1113. }
  1114. break;
  1115. /* port c */
  1116. case 2:
  1117. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1118. &terratec_drxk_config[1],
  1119. &i2c_bus->i2c_adap);
  1120. if (fe0->dvb.frontend != NULL) {
  1121. if (!dvb_attach(mt2063_attach,
  1122. fe0->dvb.frontend,
  1123. &terratec_mt2063_config[1],
  1124. &i2c_bus2->i2c_adap))
  1125. goto frontend_detach;
  1126. }
  1127. break;
  1128. }
  1129. break;
  1130. case CX23885_BOARD_TEVII_S471:
  1131. i2c_bus = &dev->i2c_bus[1];
  1132. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  1133. &tevii_ds3000_config,
  1134. &i2c_bus->i2c_adap);
  1135. if (fe0->dvb.frontend != NULL) {
  1136. dvb_attach(ts2020_attach, fe0->dvb.frontend,
  1137. &tevii_ts2020_config, &i2c_bus->i2c_adap);
  1138. }
  1139. break;
  1140. case CX23885_BOARD_PROF_8000:
  1141. i2c_bus = &dev->i2c_bus[0];
  1142. fe0->dvb.frontend = dvb_attach(stv090x_attach,
  1143. &prof_8000_stv090x_config,
  1144. &i2c_bus->i2c_adap,
  1145. STV090x_DEMODULATOR_0);
  1146. if (fe0->dvb.frontend != NULL) {
  1147. if (!dvb_attach(stb6100_attach,
  1148. fe0->dvb.frontend,
  1149. &prof_8000_stb6100_config,
  1150. &i2c_bus->i2c_adap))
  1151. goto frontend_detach;
  1152. fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
  1153. }
  1154. break;
  1155. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1156. i2c_bus = &dev->i2c_bus[0];
  1157. fe0->dvb.frontend = dvb_attach(tda10071_attach,
  1158. &hauppauge_tda10071_config,
  1159. &i2c_bus->i2c_adap);
  1160. if (fe0->dvb.frontend != NULL) {
  1161. dvb_attach(a8293_attach, fe0->dvb.frontend,
  1162. &i2c_bus->i2c_adap,
  1163. &hauppauge_a8293_config);
  1164. }
  1165. break;
  1166. default:
  1167. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  1168. " isn't supported yet\n",
  1169. dev->name);
  1170. break;
  1171. }
  1172. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  1173. printk(KERN_ERR "%s: frontend initialization failed\n",
  1174. dev->name);
  1175. goto frontend_detach;
  1176. }
  1177. /* define general-purpose callback pointer */
  1178. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  1179. if (fe1)
  1180. fe1->dvb.frontend->callback = cx23885_tuner_callback;
  1181. #if 0
  1182. /* Ensure all frontends negotiate bus access */
  1183. fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1184. if (fe1)
  1185. fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1186. #endif
  1187. /* Put the analog decoder in standby to keep it quiet */
  1188. call_all(dev, core, s_power, 0);
  1189. if (fe0->dvb.frontend->ops.analog_ops.standby)
  1190. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  1191. /* register everything */
  1192. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  1193. &dev->pci->dev, adapter_nr, mfe_shared);
  1194. if (ret)
  1195. goto frontend_detach;
  1196. /* init CI & MAC */
  1197. switch (dev->board) {
  1198. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  1199. static struct netup_card_info cinfo;
  1200. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1201. memcpy(port->frontends.adapter.proposed_mac,
  1202. cinfo.port[port->nr - 1].mac, 6);
  1203. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
  1204. port->nr, port->frontends.adapter.proposed_mac);
  1205. netup_ci_init(port);
  1206. break;
  1207. }
  1208. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1209. struct altera_ci_config netup_ci_cfg = {
  1210. .dev = dev,/* magic number to identify*/
  1211. .adapter = &port->frontends.adapter,/* for CI */
  1212. .demux = &fe0->dvb.demux,/* for hw pid filter */
  1213. .fpga_rw = netup_altera_fpga_rw,
  1214. };
  1215. altera_ci_init(&netup_ci_cfg, port->nr);
  1216. break;
  1217. }
  1218. case CX23885_BOARD_TEVII_S470: {
  1219. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1220. if (port->nr != 1)
  1221. break;
  1222. /* Read entire EEPROM */
  1223. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1224. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
  1225. printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
  1226. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
  1227. break;
  1228. }
  1229. }
  1230. return ret;
  1231. frontend_detach:
  1232. port->gate_ctrl = NULL;
  1233. videobuf_dvb_dealloc_frontends(&port->frontends);
  1234. return -EINVAL;
  1235. }
  1236. int cx23885_dvb_register(struct cx23885_tsport *port)
  1237. {
  1238. struct videobuf_dvb_frontend *fe0;
  1239. struct cx23885_dev *dev = port->dev;
  1240. int err, i;
  1241. /* Here we need to allocate the correct number of frontends,
  1242. * as reflected in the cards struct. The reality is that currently
  1243. * no cx23885 boards support this - yet. But, if we don't modify this
  1244. * code then the second frontend would never be allocated (later)
  1245. * and fail with error before the attach in dvb_register().
  1246. * Without these changes we risk an OOPS later. The changes here
  1247. * are for safety, and should provide a good foundation for the
  1248. * future addition of any multi-frontend cx23885 based boards.
  1249. */
  1250. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  1251. port->num_frontends);
  1252. for (i = 1; i <= port->num_frontends; i++) {
  1253. if (videobuf_dvb_alloc_frontend(
  1254. &port->frontends, i) == NULL) {
  1255. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  1256. return -ENOMEM;
  1257. }
  1258. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  1259. if (!fe0)
  1260. err = -EINVAL;
  1261. dprintk(1, "%s\n", __func__);
  1262. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1263. dev->board,
  1264. dev->name,
  1265. dev->pci_bus,
  1266. dev->pci_slot);
  1267. err = -ENODEV;
  1268. /* dvb stuff */
  1269. /* We have to init the queue for each frontend on a port. */
  1270. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  1271. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  1272. &dev->pci->dev, &port->slock,
  1273. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  1274. sizeof(struct cx23885_buffer), port, NULL);
  1275. }
  1276. err = dvb_register(port);
  1277. if (err != 0)
  1278. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  1279. __func__, err);
  1280. return err;
  1281. }
  1282. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  1283. {
  1284. struct videobuf_dvb_frontend *fe0;
  1285. /* FIXME: in an error condition where the we have
  1286. * an expected number of frontends (attach problem)
  1287. * then this might not clean up correctly, if 1
  1288. * is invalid.
  1289. * This comment only applies to future boards IF they
  1290. * implement MFE support.
  1291. */
  1292. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  1293. if (fe0 && fe0->dvb.frontend)
  1294. videobuf_dvb_unregister_bus(&port->frontends);
  1295. switch (port->dev->board) {
  1296. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1297. netup_ci_exit(port);
  1298. break;
  1299. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1300. altera_ci_release(port->dev, port->nr);
  1301. break;
  1302. }
  1303. port->gate_ctrl = NULL;
  1304. return 0;
  1305. }