main.c 44 KB

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  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* mac80211 and PCI callbacks */
  17. #include <linux/nl80211.h>
  18. #include "core.h"
  19. #define ATH_PCI_VERSION "0.1"
  20. static char *dev_info = "ath9k";
  21. MODULE_AUTHOR("Atheros Communications");
  22. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  23. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  24. MODULE_LICENSE("Dual BSD/GPL");
  25. static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  26. { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
  27. { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  28. { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
  29. { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
  30. { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  31. { 0 }
  32. };
  33. static int ath_get_channel(struct ath_softc *sc,
  34. struct ieee80211_channel *chan)
  35. {
  36. int i;
  37. for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
  38. if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
  39. return i;
  40. }
  41. return -1;
  42. }
  43. static u32 ath_get_extchanmode(struct ath_softc *sc,
  44. struct ieee80211_channel *chan)
  45. {
  46. u32 chanmode = 0;
  47. u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
  48. enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
  49. switch (chan->band) {
  50. case IEEE80211_BAND_2GHZ:
  51. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  52. (tx_chan_width == ATH9K_HT_MACMODE_20))
  53. chanmode = CHANNEL_G_HT20;
  54. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  55. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  56. chanmode = CHANNEL_G_HT40PLUS;
  57. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  58. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  59. chanmode = CHANNEL_G_HT40MINUS;
  60. break;
  61. case IEEE80211_BAND_5GHZ:
  62. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
  63. (tx_chan_width == ATH9K_HT_MACMODE_20))
  64. chanmode = CHANNEL_A_HT20;
  65. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
  66. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  67. chanmode = CHANNEL_A_HT40PLUS;
  68. if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
  69. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  70. chanmode = CHANNEL_A_HT40MINUS;
  71. break;
  72. default:
  73. break;
  74. }
  75. return chanmode;
  76. }
  77. static int ath_setkey_tkip(struct ath_softc *sc,
  78. struct ieee80211_key_conf *key,
  79. struct ath9k_keyval *hk,
  80. const u8 *addr)
  81. {
  82. u8 *key_rxmic = NULL;
  83. u8 *key_txmic = NULL;
  84. key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  85. key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  86. if (addr == NULL) {
  87. /* Group key installation */
  88. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  89. return ath_keyset(sc, key->keyidx, hk, addr);
  90. }
  91. if (!sc->sc_splitmic) {
  92. /*
  93. * data key goes at first index,
  94. * the hal handles the MIC keys at index+64.
  95. */
  96. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  97. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  98. return ath_keyset(sc, key->keyidx, hk, addr);
  99. }
  100. /*
  101. * TX key goes at first index, RX key at +32.
  102. * The hal handles the MIC keys at index+64.
  103. */
  104. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  105. if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
  106. /* Txmic entry failed. No need to proceed further */
  107. DPRINTF(sc, ATH_DBG_KEYCACHE,
  108. "%s Setting TX MIC Key Failed\n", __func__);
  109. return 0;
  110. }
  111. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  112. /* XXX delete tx key on failure? */
  113. return ath_keyset(sc, key->keyidx+32, hk, addr);
  114. }
  115. static int ath_key_config(struct ath_softc *sc,
  116. const u8 *addr,
  117. struct ieee80211_key_conf *key)
  118. {
  119. struct ieee80211_vif *vif;
  120. struct ath9k_keyval hk;
  121. const u8 *mac = NULL;
  122. int ret = 0;
  123. enum nl80211_iftype opmode;
  124. memset(&hk, 0, sizeof(hk));
  125. switch (key->alg) {
  126. case ALG_WEP:
  127. hk.kv_type = ATH9K_CIPHER_WEP;
  128. break;
  129. case ALG_TKIP:
  130. hk.kv_type = ATH9K_CIPHER_TKIP;
  131. break;
  132. case ALG_CCMP:
  133. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  134. break;
  135. default:
  136. return -EINVAL;
  137. }
  138. hk.kv_len = key->keylen;
  139. memcpy(hk.kv_val, key->key, key->keylen);
  140. if (!sc->sc_vaps[0])
  141. return -EIO;
  142. vif = sc->sc_vaps[0];
  143. opmode = vif->type;
  144. /*
  145. * Strategy:
  146. * For _M_STA mc tx, we will not setup a key at all since we never
  147. * tx mc.
  148. * _M_STA mc rx, we will use the keyID.
  149. * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
  150. * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
  151. * peer node. BUT we will plumb a cleartext key so that we can do
  152. * perSta default key table lookup in software.
  153. */
  154. if (is_broadcast_ether_addr(addr)) {
  155. switch (opmode) {
  156. case NL80211_IFTYPE_STATION:
  157. /* default key: could be group WPA key
  158. * or could be static WEP key */
  159. mac = NULL;
  160. break;
  161. case NL80211_IFTYPE_ADHOC:
  162. break;
  163. case NL80211_IFTYPE_AP:
  164. break;
  165. default:
  166. ASSERT(0);
  167. break;
  168. }
  169. } else {
  170. mac = addr;
  171. }
  172. if (key->alg == ALG_TKIP)
  173. ret = ath_setkey_tkip(sc, key, &hk, mac);
  174. else
  175. ret = ath_keyset(sc, key->keyidx, &hk, mac);
  176. if (!ret)
  177. return -EIO;
  178. return 0;
  179. }
  180. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  181. {
  182. int freeslot;
  183. freeslot = (key->keyidx >= 4) ? 1 : 0;
  184. ath_key_reset(sc, key->keyidx, freeslot);
  185. }
  186. static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
  187. {
  188. #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
  189. #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
  190. ht_info->ht_supported = true;
  191. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  192. IEEE80211_HT_CAP_SM_PS |
  193. IEEE80211_HT_CAP_SGI_40 |
  194. IEEE80211_HT_CAP_DSSSCCK40;
  195. ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
  196. ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
  197. /* set up supported mcs set */
  198. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  199. ht_info->mcs.rx_mask[0] = 0xff;
  200. ht_info->mcs.rx_mask[1] = 0xff;
  201. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  202. }
  203. static int ath_rate2idx(struct ath_softc *sc, int rate)
  204. {
  205. int i = 0, cur_band, n_rates;
  206. struct ieee80211_hw *hw = sc->hw;
  207. cur_band = hw->conf.channel->band;
  208. n_rates = sc->sbands[cur_band].n_bitrates;
  209. for (i = 0; i < n_rates; i++) {
  210. if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
  211. break;
  212. }
  213. /*
  214. * NB:mac80211 validates rx rate index against the supported legacy rate
  215. * index only (should be done against ht rates also), return the highest
  216. * legacy rate index for rx rate which does not match any one of the
  217. * supported basic and extended rates to make mac80211 happy.
  218. * The following hack will be cleaned up once the issue with
  219. * the rx rate index validation in mac80211 is fixed.
  220. */
  221. if (i == n_rates)
  222. return n_rates - 1;
  223. return i;
  224. }
  225. static void ath9k_rx_prepare(struct ath_softc *sc,
  226. struct sk_buff *skb,
  227. struct ath_recv_status *status,
  228. struct ieee80211_rx_status *rx_status)
  229. {
  230. struct ieee80211_hw *hw = sc->hw;
  231. struct ieee80211_channel *curchan = hw->conf.channel;
  232. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  233. rx_status->mactime = status->tsf;
  234. rx_status->band = curchan->band;
  235. rx_status->freq = curchan->center_freq;
  236. rx_status->noise = sc->sc_ani.sc_noise_floor;
  237. rx_status->signal = rx_status->noise + status->rssi;
  238. rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
  239. rx_status->antenna = status->antenna;
  240. /* at 45 you will be able to use MCS 15 reliably. A more elaborate
  241. * scheme can be used here but it requires tables of SNR/throughput for
  242. * each possible mode used. */
  243. rx_status->qual = status->rssi * 100 / 45;
  244. /* rssi can be more than 45 though, anything above that
  245. * should be considered at 100% */
  246. if (rx_status->qual > 100)
  247. rx_status->qual = 100;
  248. if (status->flags & ATH_RX_MIC_ERROR)
  249. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  250. if (status->flags & ATH_RX_FCS_ERROR)
  251. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  252. rx_status->flag |= RX_FLAG_TSFT;
  253. }
  254. static void ath9k_ht_conf(struct ath_softc *sc,
  255. struct ieee80211_bss_conf *bss_conf)
  256. {
  257. struct ath_ht_info *ht_info = &sc->sc_ht_info;
  258. if (sc->hw->conf.ht.enabled) {
  259. ht_info->ext_chan_offset = bss_conf->ht.secondary_channel_offset;
  260. if (bss_conf->ht.width_40_ok)
  261. ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
  262. else
  263. ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
  264. ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
  265. }
  266. }
  267. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  268. struct ieee80211_vif *vif,
  269. struct ieee80211_bss_conf *bss_conf)
  270. {
  271. struct ieee80211_hw *hw = sc->hw;
  272. struct ieee80211_channel *curchan = hw->conf.channel;
  273. struct ath_vap *avp = (void *)vif->drv_priv;
  274. int pos;
  275. if (bss_conf->assoc) {
  276. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
  277. __func__,
  278. bss_conf->aid);
  279. /* New association, store aid */
  280. if (avp->av_opmode == ATH9K_M_STA) {
  281. sc->sc_curaid = bss_conf->aid;
  282. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  283. sc->sc_curaid);
  284. }
  285. /* Configure the beacon */
  286. ath_beacon_config(sc, 0);
  287. sc->sc_flags |= SC_OP_BEACONS;
  288. /* Reset rssi stats */
  289. sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  290. sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  291. sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  292. sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  293. /* Update chainmask */
  294. ath_update_chainmask(sc, hw->conf.ht.enabled);
  295. DPRINTF(sc, ATH_DBG_CONFIG,
  296. "%s: bssid %pM aid 0x%x\n",
  297. __func__,
  298. sc->sc_curbssid, sc->sc_curaid);
  299. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  300. __func__,
  301. curchan->center_freq);
  302. pos = ath_get_channel(sc, curchan);
  303. if (pos == -1) {
  304. DPRINTF(sc, ATH_DBG_FATAL,
  305. "%s: Invalid channel\n", __func__);
  306. return;
  307. }
  308. if (hw->conf.ht.enabled)
  309. sc->sc_ah->ah_channels[pos].chanmode =
  310. ath_get_extchanmode(sc, curchan);
  311. else
  312. sc->sc_ah->ah_channels[pos].chanmode =
  313. (curchan->band == IEEE80211_BAND_2GHZ) ?
  314. CHANNEL_G : CHANNEL_A;
  315. /* set h/w channel */
  316. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  317. DPRINTF(sc, ATH_DBG_FATAL,
  318. "%s: Unable to set channel\n",
  319. __func__);
  320. ath_rate_newstate(sc, avp);
  321. /* Update ratectrl about the new state */
  322. ath_rc_node_update(hw, avp->rc_node);
  323. /* Start ANI */
  324. mod_timer(&sc->sc_ani.timer,
  325. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  326. } else {
  327. DPRINTF(sc, ATH_DBG_CONFIG,
  328. "%s: Bss Info DISSOC\n", __func__);
  329. sc->sc_curaid = 0;
  330. }
  331. }
  332. void ath_get_beaconconfig(struct ath_softc *sc,
  333. int if_id,
  334. struct ath_beacon_config *conf)
  335. {
  336. struct ieee80211_hw *hw = sc->hw;
  337. /* fill in beacon config data */
  338. conf->beacon_interval = hw->conf.beacon_int;
  339. conf->listen_interval = 100;
  340. conf->dtim_count = 1;
  341. conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
  342. }
  343. void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  344. struct ath_xmit_status *tx_status)
  345. {
  346. struct ieee80211_hw *hw = sc->hw;
  347. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  348. DPRINTF(sc, ATH_DBG_XMIT,
  349. "%s: TX complete: skb: %p\n", __func__, skb);
  350. ieee80211_tx_info_clear_status(tx_info);
  351. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
  352. tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
  353. /* free driver's private data area of tx_info, XXX: HACK! */
  354. if (tx_info->control.vif != NULL)
  355. kfree(tx_info->control.vif);
  356. tx_info->control.vif = NULL;
  357. }
  358. if (tx_status->flags & ATH_TX_BAR) {
  359. tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  360. tx_status->flags &= ~ATH_TX_BAR;
  361. }
  362. if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
  363. /* Frame was ACKed */
  364. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  365. }
  366. tx_info->status.rates[0].count = tx_status->retries + 1;
  367. ieee80211_tx_status(hw, skb);
  368. }
  369. int _ath_rx_indicate(struct ath_softc *sc,
  370. struct sk_buff *skb,
  371. struct ath_recv_status *status,
  372. u16 keyix)
  373. {
  374. struct ieee80211_hw *hw = sc->hw;
  375. struct ath_node *an = NULL;
  376. struct ieee80211_rx_status rx_status;
  377. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  378. int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  379. int padsize;
  380. enum ATH_RX_TYPE st;
  381. /* see if any padding is done by the hw and remove it */
  382. if (hdrlen & 3) {
  383. padsize = hdrlen % 4;
  384. memmove(skb->data + padsize, skb->data, hdrlen);
  385. skb_pull(skb, padsize);
  386. }
  387. /* Prepare rx status */
  388. ath9k_rx_prepare(sc, skb, status, &rx_status);
  389. if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
  390. !(status->flags & ATH_RX_DECRYPT_ERROR)) {
  391. rx_status.flag |= RX_FLAG_DECRYPTED;
  392. } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
  393. && !(status->flags & ATH_RX_DECRYPT_ERROR)
  394. && skb->len >= hdrlen + 4) {
  395. keyix = skb->data[hdrlen + 3] >> 6;
  396. if (test_bit(keyix, sc->sc_keymap))
  397. rx_status.flag |= RX_FLAG_DECRYPTED;
  398. }
  399. if (an) {
  400. ath_rx_input(sc, an,
  401. skb, status, &st);
  402. }
  403. if (!an || (st != ATH_RX_CONSUMED))
  404. __ieee80211_rx(hw, skb, &rx_status);
  405. return 0;
  406. }
  407. int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
  408. struct ath_recv_status *status)
  409. {
  410. struct ath_softc *sc = an->an_sc;
  411. struct ieee80211_hw *hw = sc->hw;
  412. struct ieee80211_rx_status rx_status;
  413. /* Prepare rx status */
  414. ath9k_rx_prepare(sc, skb, status, &rx_status);
  415. if (!(status->flags & ATH_RX_DECRYPT_ERROR))
  416. rx_status.flag |= RX_FLAG_DECRYPTED;
  417. __ieee80211_rx(hw, skb, &rx_status);
  418. return 0;
  419. }
  420. /********************************/
  421. /* LED functions */
  422. /********************************/
  423. static void ath_led_brightness(struct led_classdev *led_cdev,
  424. enum led_brightness brightness)
  425. {
  426. struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
  427. struct ath_softc *sc = led->sc;
  428. switch (brightness) {
  429. case LED_OFF:
  430. if (led->led_type == ATH_LED_ASSOC ||
  431. led->led_type == ATH_LED_RADIO)
  432. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  433. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
  434. (led->led_type == ATH_LED_RADIO) ? 1 :
  435. !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
  436. break;
  437. case LED_FULL:
  438. if (led->led_type == ATH_LED_ASSOC)
  439. sc->sc_flags |= SC_OP_LED_ASSOCIATED;
  440. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
  441. break;
  442. default:
  443. break;
  444. }
  445. }
  446. static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
  447. char *trigger)
  448. {
  449. int ret;
  450. led->sc = sc;
  451. led->led_cdev.name = led->name;
  452. led->led_cdev.default_trigger = trigger;
  453. led->led_cdev.brightness_set = ath_led_brightness;
  454. ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
  455. if (ret)
  456. DPRINTF(sc, ATH_DBG_FATAL,
  457. "Failed to register led:%s", led->name);
  458. else
  459. led->registered = 1;
  460. return ret;
  461. }
  462. static void ath_unregister_led(struct ath_led *led)
  463. {
  464. if (led->registered) {
  465. led_classdev_unregister(&led->led_cdev);
  466. led->registered = 0;
  467. }
  468. }
  469. static void ath_deinit_leds(struct ath_softc *sc)
  470. {
  471. ath_unregister_led(&sc->assoc_led);
  472. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  473. ath_unregister_led(&sc->tx_led);
  474. ath_unregister_led(&sc->rx_led);
  475. ath_unregister_led(&sc->radio_led);
  476. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  477. }
  478. static void ath_init_leds(struct ath_softc *sc)
  479. {
  480. char *trigger;
  481. int ret;
  482. /* Configure gpio 1 for output */
  483. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  484. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  485. /* LED off, active low */
  486. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  487. trigger = ieee80211_get_radio_led_name(sc->hw);
  488. snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
  489. "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
  490. ret = ath_register_led(sc, &sc->radio_led, trigger);
  491. sc->radio_led.led_type = ATH_LED_RADIO;
  492. if (ret)
  493. goto fail;
  494. trigger = ieee80211_get_assoc_led_name(sc->hw);
  495. snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
  496. "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
  497. ret = ath_register_led(sc, &sc->assoc_led, trigger);
  498. sc->assoc_led.led_type = ATH_LED_ASSOC;
  499. if (ret)
  500. goto fail;
  501. trigger = ieee80211_get_tx_led_name(sc->hw);
  502. snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
  503. "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
  504. ret = ath_register_led(sc, &sc->tx_led, trigger);
  505. sc->tx_led.led_type = ATH_LED_TX;
  506. if (ret)
  507. goto fail;
  508. trigger = ieee80211_get_rx_led_name(sc->hw);
  509. snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
  510. "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
  511. ret = ath_register_led(sc, &sc->rx_led, trigger);
  512. sc->rx_led.led_type = ATH_LED_RX;
  513. if (ret)
  514. goto fail;
  515. return;
  516. fail:
  517. ath_deinit_leds(sc);
  518. }
  519. #ifdef CONFIG_RFKILL
  520. /*******************/
  521. /* Rfkill */
  522. /*******************/
  523. static void ath_radio_enable(struct ath_softc *sc)
  524. {
  525. struct ath_hal *ah = sc->sc_ah;
  526. int status;
  527. spin_lock_bh(&sc->sc_resetlock);
  528. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  529. sc->sc_ht_info.tx_chan_width,
  530. sc->sc_tx_chainmask,
  531. sc->sc_rx_chainmask,
  532. sc->sc_ht_extprotspacing,
  533. false, &status)) {
  534. DPRINTF(sc, ATH_DBG_FATAL,
  535. "%s: unable to reset channel %u (%uMhz) "
  536. "flags 0x%x hal status %u\n", __func__,
  537. ath9k_hw_mhz2ieee(ah,
  538. ah->ah_curchan->channel,
  539. ah->ah_curchan->channelFlags),
  540. ah->ah_curchan->channel,
  541. ah->ah_curchan->channelFlags, status);
  542. }
  543. spin_unlock_bh(&sc->sc_resetlock);
  544. ath_update_txpow(sc);
  545. if (ath_startrecv(sc) != 0) {
  546. DPRINTF(sc, ATH_DBG_FATAL,
  547. "%s: unable to restart recv logic\n", __func__);
  548. return;
  549. }
  550. if (sc->sc_flags & SC_OP_BEACONS)
  551. ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
  552. /* Re-Enable interrupts */
  553. ath9k_hw_set_interrupts(ah, sc->sc_imask);
  554. /* Enable LED */
  555. ath9k_hw_cfg_output(ah, ATH_LED_PIN,
  556. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  557. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
  558. ieee80211_wake_queues(sc->hw);
  559. }
  560. static void ath_radio_disable(struct ath_softc *sc)
  561. {
  562. struct ath_hal *ah = sc->sc_ah;
  563. int status;
  564. ieee80211_stop_queues(sc->hw);
  565. /* Disable LED */
  566. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
  567. ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
  568. /* Disable interrupts */
  569. ath9k_hw_set_interrupts(ah, 0);
  570. ath_draintxq(sc, false); /* clear pending tx frames */
  571. ath_stoprecv(sc); /* turn off frame recv */
  572. ath_flushrecv(sc); /* flush recv queue */
  573. spin_lock_bh(&sc->sc_resetlock);
  574. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  575. sc->sc_ht_info.tx_chan_width,
  576. sc->sc_tx_chainmask,
  577. sc->sc_rx_chainmask,
  578. sc->sc_ht_extprotspacing,
  579. false, &status)) {
  580. DPRINTF(sc, ATH_DBG_FATAL,
  581. "%s: unable to reset channel %u (%uMhz) "
  582. "flags 0x%x hal status %u\n", __func__,
  583. ath9k_hw_mhz2ieee(ah,
  584. ah->ah_curchan->channel,
  585. ah->ah_curchan->channelFlags),
  586. ah->ah_curchan->channel,
  587. ah->ah_curchan->channelFlags, status);
  588. }
  589. spin_unlock_bh(&sc->sc_resetlock);
  590. ath9k_hw_phy_disable(ah);
  591. ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
  592. }
  593. static bool ath_is_rfkill_set(struct ath_softc *sc)
  594. {
  595. struct ath_hal *ah = sc->sc_ah;
  596. return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
  597. ah->ah_rfkill_polarity;
  598. }
  599. /* h/w rfkill poll function */
  600. static void ath_rfkill_poll(struct work_struct *work)
  601. {
  602. struct ath_softc *sc = container_of(work, struct ath_softc,
  603. rf_kill.rfkill_poll.work);
  604. bool radio_on;
  605. if (sc->sc_flags & SC_OP_INVALID)
  606. return;
  607. radio_on = !ath_is_rfkill_set(sc);
  608. /*
  609. * enable/disable radio only when there is a
  610. * state change in RF switch
  611. */
  612. if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
  613. enum rfkill_state state;
  614. if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
  615. state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
  616. : RFKILL_STATE_HARD_BLOCKED;
  617. } else if (radio_on) {
  618. ath_radio_enable(sc);
  619. state = RFKILL_STATE_UNBLOCKED;
  620. } else {
  621. ath_radio_disable(sc);
  622. state = RFKILL_STATE_HARD_BLOCKED;
  623. }
  624. if (state == RFKILL_STATE_HARD_BLOCKED)
  625. sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
  626. else
  627. sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
  628. rfkill_force_state(sc->rf_kill.rfkill, state);
  629. }
  630. queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
  631. msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
  632. }
  633. /* s/w rfkill handler */
  634. static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
  635. {
  636. struct ath_softc *sc = data;
  637. switch (state) {
  638. case RFKILL_STATE_SOFT_BLOCKED:
  639. if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
  640. SC_OP_RFKILL_SW_BLOCKED)))
  641. ath_radio_disable(sc);
  642. sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
  643. return 0;
  644. case RFKILL_STATE_UNBLOCKED:
  645. if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
  646. sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
  647. if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
  648. DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
  649. "radio as it is disabled by h/w \n");
  650. return -EPERM;
  651. }
  652. ath_radio_enable(sc);
  653. }
  654. return 0;
  655. default:
  656. return -EINVAL;
  657. }
  658. }
  659. /* Init s/w rfkill */
  660. static int ath_init_sw_rfkill(struct ath_softc *sc)
  661. {
  662. sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
  663. RFKILL_TYPE_WLAN);
  664. if (!sc->rf_kill.rfkill) {
  665. DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
  666. return -ENOMEM;
  667. }
  668. snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
  669. "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
  670. sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
  671. sc->rf_kill.rfkill->data = sc;
  672. sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
  673. sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
  674. sc->rf_kill.rfkill->user_claim_unsupported = 1;
  675. return 0;
  676. }
  677. /* Deinitialize rfkill */
  678. static void ath_deinit_rfkill(struct ath_softc *sc)
  679. {
  680. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  681. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  682. if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
  683. rfkill_unregister(sc->rf_kill.rfkill);
  684. sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
  685. sc->rf_kill.rfkill = NULL;
  686. }
  687. }
  688. static int ath_start_rfkill_poll(struct ath_softc *sc)
  689. {
  690. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  691. queue_delayed_work(sc->hw->workqueue,
  692. &sc->rf_kill.rfkill_poll, 0);
  693. if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
  694. if (rfkill_register(sc->rf_kill.rfkill)) {
  695. DPRINTF(sc, ATH_DBG_FATAL,
  696. "Unable to register rfkill\n");
  697. rfkill_free(sc->rf_kill.rfkill);
  698. /* Deinitialize the device */
  699. if (sc->pdev->irq)
  700. free_irq(sc->pdev->irq, sc);
  701. ath_detach(sc);
  702. pci_iounmap(sc->pdev, sc->mem);
  703. pci_release_region(sc->pdev, 0);
  704. pci_disable_device(sc->pdev);
  705. ieee80211_free_hw(hw);
  706. return -EIO;
  707. } else {
  708. sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
  709. }
  710. }
  711. return 0;
  712. }
  713. #endif /* CONFIG_RFKILL */
  714. static void ath_detach(struct ath_softc *sc)
  715. {
  716. struct ieee80211_hw *hw = sc->hw;
  717. int i = 0;
  718. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
  719. ieee80211_unregister_hw(hw);
  720. ath_deinit_leds(sc);
  721. #ifdef CONFIG_RFKILL
  722. ath_deinit_rfkill(sc);
  723. #endif
  724. ath_rate_control_unregister();
  725. ath_rate_detach(sc->sc_rc);
  726. ath_rx_cleanup(sc);
  727. ath_tx_cleanup(sc);
  728. tasklet_kill(&sc->intr_tq);
  729. tasklet_kill(&sc->bcon_tasklet);
  730. if (!(sc->sc_flags & SC_OP_INVALID))
  731. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  732. /* cleanup tx queues */
  733. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  734. if (ATH_TXQ_SETUP(sc, i))
  735. ath_tx_cleanupq(sc, &sc->sc_txq[i]);
  736. ath9k_hw_detach(sc->sc_ah);
  737. }
  738. static int ath_attach(u16 devid, struct ath_softc *sc)
  739. {
  740. struct ieee80211_hw *hw = sc->hw;
  741. int error = 0;
  742. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
  743. error = ath_init(devid, sc);
  744. if (error != 0)
  745. return error;
  746. /* get mac address from hardware and set in mac80211 */
  747. SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
  748. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  749. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  750. IEEE80211_HW_SIGNAL_DBM |
  751. IEEE80211_HW_AMPDU_AGGREGATION;
  752. hw->wiphy->interface_modes =
  753. BIT(NL80211_IFTYPE_AP) |
  754. BIT(NL80211_IFTYPE_STATION) |
  755. BIT(NL80211_IFTYPE_ADHOC);
  756. hw->queues = 4;
  757. hw->sta_data_size = sizeof(struct ath_node);
  758. hw->vif_data_size = sizeof(struct ath_vap);
  759. /* Register rate control */
  760. hw->rate_control_algorithm = "ath9k_rate_control";
  761. error = ath_rate_control_register();
  762. if (error != 0) {
  763. DPRINTF(sc, ATH_DBG_FATAL,
  764. "%s: Unable to register rate control "
  765. "algorithm:%d\n", __func__, error);
  766. ath_rate_control_unregister();
  767. goto bad;
  768. }
  769. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
  770. setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  771. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
  772. setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  773. }
  774. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
  775. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
  776. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  777. &sc->sbands[IEEE80211_BAND_5GHZ];
  778. error = ieee80211_register_hw(hw);
  779. if (error != 0) {
  780. ath_rate_control_unregister();
  781. goto bad;
  782. }
  783. /* Initialize LED control */
  784. ath_init_leds(sc);
  785. #ifdef CONFIG_RFKILL
  786. /* Initialze h/w Rfkill */
  787. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  788. INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
  789. /* Initialize s/w rfkill */
  790. if (ath_init_sw_rfkill(sc))
  791. goto detach;
  792. #endif
  793. /* initialize tx/rx engine */
  794. error = ath_tx_init(sc, ATH_TXBUF);
  795. if (error != 0)
  796. goto detach;
  797. error = ath_rx_init(sc, ATH_RXBUF);
  798. if (error != 0)
  799. goto detach;
  800. return 0;
  801. detach:
  802. ath_detach(sc);
  803. bad:
  804. return error;
  805. }
  806. static int ath9k_start(struct ieee80211_hw *hw)
  807. {
  808. struct ath_softc *sc = hw->priv;
  809. struct ieee80211_channel *curchan = hw->conf.channel;
  810. int error = 0, pos;
  811. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
  812. "initial channel: %d MHz\n", __func__, curchan->center_freq);
  813. /* setup initial channel */
  814. pos = ath_get_channel(sc, curchan);
  815. if (pos == -1) {
  816. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  817. error = -EINVAL;
  818. goto exit;
  819. }
  820. sc->sc_ah->ah_channels[pos].chanmode =
  821. (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
  822. error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
  823. if (error) {
  824. DPRINTF(sc, ATH_DBG_FATAL,
  825. "%s: Unable to complete ath_open\n", __func__);
  826. goto exit;
  827. }
  828. #ifdef CONFIG_RFKILL
  829. error = ath_start_rfkill_poll(sc);
  830. #endif
  831. exit:
  832. return error;
  833. }
  834. static int ath9k_tx(struct ieee80211_hw *hw,
  835. struct sk_buff *skb)
  836. {
  837. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  838. struct ath_softc *sc = hw->priv;
  839. struct ath_tx_control txctl;
  840. int hdrlen, padsize;
  841. memset(&txctl, 0, sizeof(struct ath_tx_control));
  842. /*
  843. * As a temporary workaround, assign seq# here; this will likely need
  844. * to be cleaned up to work better with Beacon transmission and virtual
  845. * BSSes.
  846. */
  847. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  848. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  849. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  850. sc->seq_no += 0x10;
  851. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  852. hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
  853. }
  854. /* Add the padding after the header if this is not already done */
  855. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  856. if (hdrlen & 3) {
  857. padsize = hdrlen % 4;
  858. if (skb_headroom(skb) < padsize)
  859. return -1;
  860. skb_push(skb, padsize);
  861. memmove(skb->data, skb->data + padsize, hdrlen);
  862. }
  863. /* Check if a tx queue is available */
  864. txctl.txq = ath_test_get_txq(sc, skb);
  865. if (!txctl.txq)
  866. goto exit;
  867. DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
  868. __func__,
  869. skb);
  870. if (ath_tx_start(sc, skb, &txctl) != 0) {
  871. DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
  872. goto exit;
  873. }
  874. return 0;
  875. exit:
  876. dev_kfree_skb_any(skb);
  877. return 0;
  878. }
  879. static void ath9k_stop(struct ieee80211_hw *hw)
  880. {
  881. struct ath_softc *sc = hw->priv;
  882. if (sc->sc_flags & SC_OP_INVALID) {
  883. DPRINTF(sc, ATH_DBG_ANY, "%s: Device not present\n", __func__);
  884. return;
  885. }
  886. ath_stop(sc);
  887. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
  888. }
  889. static int ath9k_add_interface(struct ieee80211_hw *hw,
  890. struct ieee80211_if_init_conf *conf)
  891. {
  892. struct ath_softc *sc = hw->priv;
  893. struct ath_vap *avp = (void *)conf->vif->drv_priv;
  894. int ic_opmode = 0;
  895. /* Support only vap for now */
  896. if (sc->sc_nvaps)
  897. return -ENOBUFS;
  898. switch (conf->type) {
  899. case NL80211_IFTYPE_STATION:
  900. ic_opmode = ATH9K_M_STA;
  901. break;
  902. case NL80211_IFTYPE_ADHOC:
  903. ic_opmode = ATH9K_M_IBSS;
  904. break;
  905. case NL80211_IFTYPE_AP:
  906. ic_opmode = ATH9K_M_HOSTAP;
  907. break;
  908. default:
  909. DPRINTF(sc, ATH_DBG_FATAL,
  910. "%s: Interface type %d not yet supported\n",
  911. __func__, conf->type);
  912. return -EOPNOTSUPP;
  913. }
  914. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
  915. __func__,
  916. ic_opmode);
  917. /* Set the VAP opmode */
  918. avp->av_opmode = ic_opmode;
  919. avp->av_bslot = -1;
  920. if (ic_opmode == ATH9K_M_HOSTAP)
  921. ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
  922. sc->sc_vaps[0] = conf->vif;
  923. sc->sc_nvaps++;
  924. /* Set the device opmode */
  925. sc->sc_ah->ah_opmode = ic_opmode;
  926. /* default VAP configuration */
  927. avp->av_config.av_fixed_rateset = IEEE80211_FIXED_RATE_NONE;
  928. avp->av_config.av_fixed_retryset = 0x03030303;
  929. if (conf->type == NL80211_IFTYPE_AP) {
  930. /* TODO: is this a suitable place to start ANI for AP mode? */
  931. /* Start ANI */
  932. mod_timer(&sc->sc_ani.timer,
  933. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  934. }
  935. return 0;
  936. }
  937. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  938. struct ieee80211_if_init_conf *conf)
  939. {
  940. struct ath_softc *sc = hw->priv;
  941. struct ath_vap *avp = (void *)conf->vif->drv_priv;
  942. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
  943. #ifdef CONFIG_SLOW_ANT_DIV
  944. ath_slow_ant_div_stop(&sc->sc_antdiv);
  945. #endif
  946. /* Stop ANI */
  947. del_timer_sync(&sc->sc_ani.timer);
  948. /* Reclaim beacon resources */
  949. if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
  950. sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
  951. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  952. ath_beacon_return(sc, avp);
  953. }
  954. sc->sc_flags &= ~SC_OP_BEACONS;
  955. sc->sc_vaps[0] = NULL;
  956. sc->sc_nvaps--;
  957. }
  958. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  959. {
  960. struct ath_softc *sc = hw->priv;
  961. struct ieee80211_channel *curchan = hw->conf.channel;
  962. struct ieee80211_conf *conf = &hw->conf;
  963. int pos;
  964. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  965. __func__,
  966. curchan->center_freq);
  967. /* Update chainmask */
  968. ath_update_chainmask(sc, conf->ht.enabled);
  969. pos = ath_get_channel(sc, curchan);
  970. if (pos == -1) {
  971. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  972. return -EINVAL;
  973. }
  974. sc->sc_ah->ah_channels[pos].chanmode =
  975. (curchan->band == IEEE80211_BAND_2GHZ) ?
  976. CHANNEL_G : CHANNEL_A;
  977. if (sc->sc_curaid && hw->conf.ht.enabled)
  978. sc->sc_ah->ah_channels[pos].chanmode =
  979. ath_get_extchanmode(sc, curchan);
  980. if (changed & IEEE80211_CONF_CHANGE_POWER)
  981. sc->sc_config.txpowlimit = 2 * conf->power_level;
  982. /* set h/w channel */
  983. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  984. DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
  985. __func__);
  986. return 0;
  987. }
  988. static int ath9k_config_interface(struct ieee80211_hw *hw,
  989. struct ieee80211_vif *vif,
  990. struct ieee80211_if_conf *conf)
  991. {
  992. struct ath_softc *sc = hw->priv;
  993. struct ath_hal *ah = sc->sc_ah;
  994. struct ath_vap *avp = (void *)vif->drv_priv;
  995. u32 rfilt = 0;
  996. int error, i;
  997. /* TODO: Need to decide which hw opmode to use for multi-interface
  998. * cases */
  999. if (vif->type == NL80211_IFTYPE_AP &&
  1000. ah->ah_opmode != ATH9K_M_HOSTAP) {
  1001. ah->ah_opmode = ATH9K_M_HOSTAP;
  1002. ath9k_hw_setopmode(ah);
  1003. ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
  1004. /* Request full reset to get hw opmode changed properly */
  1005. sc->sc_flags |= SC_OP_FULL_RESET;
  1006. }
  1007. if ((conf->changed & IEEE80211_IFCC_BSSID) &&
  1008. !is_zero_ether_addr(conf->bssid)) {
  1009. switch (vif->type) {
  1010. case NL80211_IFTYPE_STATION:
  1011. case NL80211_IFTYPE_ADHOC:
  1012. /* Update ratectrl about the new state */
  1013. ath_rate_newstate(sc, avp);
  1014. /* Set BSSID */
  1015. memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
  1016. sc->sc_curaid = 0;
  1017. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  1018. sc->sc_curaid);
  1019. /* Set aggregation protection mode parameters */
  1020. sc->sc_config.ath_aggr_prot = 0;
  1021. /* Disable BMISS interrupt when we're not associated */
  1022. ath9k_hw_set_interrupts(sc->sc_ah,
  1023. sc->sc_imask &
  1024. ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
  1025. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1026. DPRINTF(sc, ATH_DBG_CONFIG,
  1027. "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
  1028. __func__, rfilt,
  1029. sc->sc_curbssid, sc->sc_curaid);
  1030. /* need to reconfigure the beacon */
  1031. sc->sc_flags &= ~SC_OP_BEACONS ;
  1032. break;
  1033. default:
  1034. break;
  1035. }
  1036. }
  1037. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  1038. ((vif->type == NL80211_IFTYPE_ADHOC) ||
  1039. (vif->type == NL80211_IFTYPE_AP))) {
  1040. /*
  1041. * Allocate and setup the beacon frame.
  1042. *
  1043. * Stop any previous beacon DMA. This may be
  1044. * necessary, for example, when an ibss merge
  1045. * causes reconfiguration; we may be called
  1046. * with beacon transmission active.
  1047. */
  1048. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  1049. error = ath_beacon_alloc(sc, 0);
  1050. if (error != 0)
  1051. return error;
  1052. ath_beacon_sync(sc, 0);
  1053. }
  1054. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  1055. if ((avp->av_opmode != ATH9K_M_STA)) {
  1056. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  1057. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  1058. ath9k_hw_keysetmac(sc->sc_ah,
  1059. (u16)i,
  1060. sc->sc_curbssid);
  1061. }
  1062. /* Only legacy IBSS for now */
  1063. if (vif->type == NL80211_IFTYPE_ADHOC)
  1064. ath_update_chainmask(sc, 0);
  1065. return 0;
  1066. }
  1067. #define SUPPORTED_FILTERS \
  1068. (FIF_PROMISC_IN_BSS | \
  1069. FIF_ALLMULTI | \
  1070. FIF_CONTROL | \
  1071. FIF_OTHER_BSS | \
  1072. FIF_BCN_PRBRESP_PROMISC | \
  1073. FIF_FCSFAIL)
  1074. /* FIXME: sc->sc_full_reset ? */
  1075. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1076. unsigned int changed_flags,
  1077. unsigned int *total_flags,
  1078. int mc_count,
  1079. struct dev_mc_list *mclist)
  1080. {
  1081. struct ath_softc *sc = hw->priv;
  1082. u32 rfilt;
  1083. changed_flags &= SUPPORTED_FILTERS;
  1084. *total_flags &= SUPPORTED_FILTERS;
  1085. sc->rx_filter = *total_flags;
  1086. rfilt = ath_calcrxfilter(sc);
  1087. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1088. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1089. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1090. ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
  1091. }
  1092. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
  1093. __func__, sc->rx_filter);
  1094. }
  1095. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1096. struct ieee80211_vif *vif,
  1097. enum sta_notify_cmd cmd,
  1098. struct ieee80211_sta *sta)
  1099. {
  1100. struct ath_softc *sc = hw->priv;
  1101. switch (cmd) {
  1102. case STA_NOTIFY_ADD:
  1103. ath_node_attach(sc, sta);
  1104. break;
  1105. case STA_NOTIFY_REMOVE:
  1106. ath_node_detach(sc, sta);
  1107. break;
  1108. default:
  1109. break;
  1110. }
  1111. }
  1112. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1113. u16 queue,
  1114. const struct ieee80211_tx_queue_params *params)
  1115. {
  1116. struct ath_softc *sc = hw->priv;
  1117. struct ath9k_tx_queue_info qi;
  1118. int ret = 0, qnum;
  1119. if (queue >= WME_NUM_AC)
  1120. return 0;
  1121. qi.tqi_aifs = params->aifs;
  1122. qi.tqi_cwmin = params->cw_min;
  1123. qi.tqi_cwmax = params->cw_max;
  1124. qi.tqi_burstTime = params->txop;
  1125. qnum = ath_get_hal_qnum(queue, sc);
  1126. DPRINTF(sc, ATH_DBG_CONFIG,
  1127. "%s: Configure tx [queue/halq] [%d/%d], "
  1128. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1129. __func__,
  1130. queue,
  1131. qnum,
  1132. params->aifs,
  1133. params->cw_min,
  1134. params->cw_max,
  1135. params->txop);
  1136. ret = ath_txq_update(sc, qnum, &qi);
  1137. if (ret)
  1138. DPRINTF(sc, ATH_DBG_FATAL,
  1139. "%s: TXQ Update failed\n", __func__);
  1140. return ret;
  1141. }
  1142. static int ath9k_set_key(struct ieee80211_hw *hw,
  1143. enum set_key_cmd cmd,
  1144. const u8 *local_addr,
  1145. const u8 *addr,
  1146. struct ieee80211_key_conf *key)
  1147. {
  1148. struct ath_softc *sc = hw->priv;
  1149. int ret = 0;
  1150. DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
  1151. switch (cmd) {
  1152. case SET_KEY:
  1153. ret = ath_key_config(sc, addr, key);
  1154. if (!ret) {
  1155. set_bit(key->keyidx, sc->sc_keymap);
  1156. key->hw_key_idx = key->keyidx;
  1157. /* push IV and Michael MIC generation to stack */
  1158. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1159. if (key->alg == ALG_TKIP)
  1160. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1161. }
  1162. break;
  1163. case DISABLE_KEY:
  1164. ath_key_delete(sc, key);
  1165. clear_bit(key->keyidx, sc->sc_keymap);
  1166. break;
  1167. default:
  1168. ret = -EINVAL;
  1169. }
  1170. return ret;
  1171. }
  1172. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1173. struct ieee80211_vif *vif,
  1174. struct ieee80211_bss_conf *bss_conf,
  1175. u32 changed)
  1176. {
  1177. struct ath_softc *sc = hw->priv;
  1178. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1179. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
  1180. __func__,
  1181. bss_conf->use_short_preamble);
  1182. if (bss_conf->use_short_preamble)
  1183. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1184. else
  1185. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1186. }
  1187. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1188. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
  1189. __func__,
  1190. bss_conf->use_cts_prot);
  1191. if (bss_conf->use_cts_prot &&
  1192. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1193. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1194. else
  1195. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1196. }
  1197. if (changed & BSS_CHANGED_HT) {
  1198. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT\n",
  1199. __func__);
  1200. ath9k_ht_conf(sc, bss_conf);
  1201. }
  1202. if (changed & BSS_CHANGED_ASSOC) {
  1203. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
  1204. __func__,
  1205. bss_conf->assoc);
  1206. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1207. }
  1208. }
  1209. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1210. {
  1211. u64 tsf;
  1212. struct ath_softc *sc = hw->priv;
  1213. struct ath_hal *ah = sc->sc_ah;
  1214. tsf = ath9k_hw_gettsf64(ah);
  1215. return tsf;
  1216. }
  1217. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1218. {
  1219. struct ath_softc *sc = hw->priv;
  1220. struct ath_hal *ah = sc->sc_ah;
  1221. ath9k_hw_reset_tsf(ah);
  1222. }
  1223. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1224. enum ieee80211_ampdu_mlme_action action,
  1225. struct ieee80211_sta *sta,
  1226. u16 tid, u16 *ssn)
  1227. {
  1228. struct ath_softc *sc = hw->priv;
  1229. int ret = 0;
  1230. switch (action) {
  1231. case IEEE80211_AMPDU_RX_START:
  1232. ret = ath_rx_aggr_start(sc, sta, tid, ssn);
  1233. if (ret < 0)
  1234. DPRINTF(sc, ATH_DBG_FATAL,
  1235. "%s: Unable to start RX aggregation\n",
  1236. __func__);
  1237. break;
  1238. case IEEE80211_AMPDU_RX_STOP:
  1239. ret = ath_rx_aggr_stop(sc, sta, tid);
  1240. if (ret < 0)
  1241. DPRINTF(sc, ATH_DBG_FATAL,
  1242. "%s: Unable to stop RX aggregation\n",
  1243. __func__);
  1244. break;
  1245. case IEEE80211_AMPDU_TX_START:
  1246. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1247. if (ret < 0)
  1248. DPRINTF(sc, ATH_DBG_FATAL,
  1249. "%s: Unable to start TX aggregation\n",
  1250. __func__);
  1251. else
  1252. ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1253. break;
  1254. case IEEE80211_AMPDU_TX_STOP:
  1255. ret = ath_tx_aggr_stop(sc, sta, tid);
  1256. if (ret < 0)
  1257. DPRINTF(sc, ATH_DBG_FATAL,
  1258. "%s: Unable to stop TX aggregation\n",
  1259. __func__);
  1260. ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1261. break;
  1262. default:
  1263. DPRINTF(sc, ATH_DBG_FATAL,
  1264. "%s: Unknown AMPDU action\n", __func__);
  1265. }
  1266. return ret;
  1267. }
  1268. static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
  1269. {
  1270. return -EOPNOTSUPP;
  1271. }
  1272. static struct ieee80211_ops ath9k_ops = {
  1273. .tx = ath9k_tx,
  1274. .start = ath9k_start,
  1275. .stop = ath9k_stop,
  1276. .add_interface = ath9k_add_interface,
  1277. .remove_interface = ath9k_remove_interface,
  1278. .config = ath9k_config,
  1279. .config_interface = ath9k_config_interface,
  1280. .configure_filter = ath9k_configure_filter,
  1281. .sta_notify = ath9k_sta_notify,
  1282. .conf_tx = ath9k_conf_tx,
  1283. .bss_info_changed = ath9k_bss_info_changed,
  1284. .set_key = ath9k_set_key,
  1285. .get_tsf = ath9k_get_tsf,
  1286. .reset_tsf = ath9k_reset_tsf,
  1287. .ampdu_action = ath9k_ampdu_action,
  1288. .set_frag_threshold = ath9k_no_fragmentation,
  1289. };
  1290. static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1291. {
  1292. void __iomem *mem;
  1293. struct ath_softc *sc;
  1294. struct ieee80211_hw *hw;
  1295. const char *athname;
  1296. u8 csz;
  1297. u32 val;
  1298. int ret = 0;
  1299. if (pci_enable_device(pdev))
  1300. return -EIO;
  1301. /* XXX 32-bit addressing only */
  1302. if (pci_set_dma_mask(pdev, 0xffffffff)) {
  1303. printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
  1304. ret = -ENODEV;
  1305. goto bad;
  1306. }
  1307. /*
  1308. * Cache line size is used to size and align various
  1309. * structures used to communicate with the hardware.
  1310. */
  1311. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  1312. if (csz == 0) {
  1313. /*
  1314. * Linux 2.4.18 (at least) writes the cache line size
  1315. * register as a 16-bit wide register which is wrong.
  1316. * We must have this setup properly for rx buffer
  1317. * DMA to work so force a reasonable value here if it
  1318. * comes up zero.
  1319. */
  1320. csz = L1_CACHE_BYTES / sizeof(u32);
  1321. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  1322. }
  1323. /*
  1324. * The default setting of latency timer yields poor results,
  1325. * set it to the value used by other systems. It may be worth
  1326. * tweaking this setting more.
  1327. */
  1328. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  1329. pci_set_master(pdev);
  1330. /*
  1331. * Disable the RETRY_TIMEOUT register (0x41) to keep
  1332. * PCI Tx retries from interfering with C3 CPU state.
  1333. */
  1334. pci_read_config_dword(pdev, 0x40, &val);
  1335. if ((val & 0x0000ff00) != 0)
  1336. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1337. ret = pci_request_region(pdev, 0, "ath9k");
  1338. if (ret) {
  1339. dev_err(&pdev->dev, "PCI memory region reserve error\n");
  1340. ret = -ENODEV;
  1341. goto bad;
  1342. }
  1343. mem = pci_iomap(pdev, 0, 0);
  1344. if (!mem) {
  1345. printk(KERN_ERR "PCI memory map error\n") ;
  1346. ret = -EIO;
  1347. goto bad1;
  1348. }
  1349. hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
  1350. if (hw == NULL) {
  1351. printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
  1352. goto bad2;
  1353. }
  1354. SET_IEEE80211_DEV(hw, &pdev->dev);
  1355. pci_set_drvdata(pdev, hw);
  1356. sc = hw->priv;
  1357. sc->hw = hw;
  1358. sc->pdev = pdev;
  1359. sc->mem = mem;
  1360. if (ath_attach(id->device, sc) != 0) {
  1361. ret = -ENODEV;
  1362. goto bad3;
  1363. }
  1364. /* setup interrupt service routine */
  1365. if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
  1366. printk(KERN_ERR "%s: request_irq failed\n",
  1367. wiphy_name(hw->wiphy));
  1368. ret = -EIO;
  1369. goto bad4;
  1370. }
  1371. athname = ath9k_hw_probe(id->vendor, id->device);
  1372. printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n",
  1373. wiphy_name(hw->wiphy),
  1374. athname ? athname : "Atheros ???",
  1375. (unsigned long)mem, pdev->irq);
  1376. return 0;
  1377. bad4:
  1378. ath_detach(sc);
  1379. bad3:
  1380. ieee80211_free_hw(hw);
  1381. bad2:
  1382. pci_iounmap(pdev, mem);
  1383. bad1:
  1384. pci_release_region(pdev, 0);
  1385. bad:
  1386. pci_disable_device(pdev);
  1387. return ret;
  1388. }
  1389. static void ath_pci_remove(struct pci_dev *pdev)
  1390. {
  1391. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1392. struct ath_softc *sc = hw->priv;
  1393. ath_detach(sc);
  1394. if (pdev->irq)
  1395. free_irq(pdev->irq, sc);
  1396. pci_iounmap(pdev, sc->mem);
  1397. pci_release_region(pdev, 0);
  1398. pci_disable_device(pdev);
  1399. ieee80211_free_hw(hw);
  1400. }
  1401. #ifdef CONFIG_PM
  1402. static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1403. {
  1404. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1405. struct ath_softc *sc = hw->priv;
  1406. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1407. #ifdef CONFIG_RFKILL
  1408. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1409. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  1410. #endif
  1411. pci_save_state(pdev);
  1412. pci_disable_device(pdev);
  1413. pci_set_power_state(pdev, 3);
  1414. return 0;
  1415. }
  1416. static int ath_pci_resume(struct pci_dev *pdev)
  1417. {
  1418. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1419. struct ath_softc *sc = hw->priv;
  1420. u32 val;
  1421. int err;
  1422. err = pci_enable_device(pdev);
  1423. if (err)
  1424. return err;
  1425. pci_restore_state(pdev);
  1426. /*
  1427. * Suspend/Resume resets the PCI configuration space, so we have to
  1428. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  1429. * PCI Tx retries from interfering with C3 CPU state
  1430. */
  1431. pci_read_config_dword(pdev, 0x40, &val);
  1432. if ((val & 0x0000ff00) != 0)
  1433. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1434. /* Enable LED */
  1435. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  1436. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  1437. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1438. #ifdef CONFIG_RFKILL
  1439. /*
  1440. * check the h/w rfkill state on resume
  1441. * and start the rfkill poll timer
  1442. */
  1443. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1444. queue_delayed_work(sc->hw->workqueue,
  1445. &sc->rf_kill.rfkill_poll, 0);
  1446. #endif
  1447. return 0;
  1448. }
  1449. #endif /* CONFIG_PM */
  1450. MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
  1451. static struct pci_driver ath_pci_driver = {
  1452. .name = "ath9k",
  1453. .id_table = ath_pci_id_table,
  1454. .probe = ath_pci_probe,
  1455. .remove = ath_pci_remove,
  1456. #ifdef CONFIG_PM
  1457. .suspend = ath_pci_suspend,
  1458. .resume = ath_pci_resume,
  1459. #endif /* CONFIG_PM */
  1460. };
  1461. static int __init init_ath_pci(void)
  1462. {
  1463. printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
  1464. if (pci_register_driver(&ath_pci_driver) < 0) {
  1465. printk(KERN_ERR
  1466. "ath_pci: No devices found, driver not installed.\n");
  1467. pci_unregister_driver(&ath_pci_driver);
  1468. return -ENODEV;
  1469. }
  1470. return 0;
  1471. }
  1472. module_init(init_ath_pci);
  1473. static void __exit exit_ath_pci(void)
  1474. {
  1475. pci_unregister_driver(&ath_pci_driver);
  1476. printk(KERN_INFO "%s: driver unloaded\n", dev_info);
  1477. }
  1478. module_exit(exit_ath_pci);