qlcnic_ctx.c 38 KB

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  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include "qlcnic.h"
  8. static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
  9. {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
  10. {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  11. {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
  12. {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  13. {QLCNIC_CMD_INTRPT_TEST, 4, 1},
  14. {QLCNIC_CMD_SET_MTU, 4, 1},
  15. {QLCNIC_CMD_READ_PHY, 4, 2},
  16. {QLCNIC_CMD_WRITE_PHY, 5, 1},
  17. {QLCNIC_CMD_READ_HW_REG, 4, 1},
  18. {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  19. {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  20. {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  21. {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  22. {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  23. {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
  24. {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
  25. {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
  26. {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  27. {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  28. {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  29. {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  30. {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  31. {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
  32. {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  33. {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  34. {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  35. {QLCNIC_CMD_TEMP_SIZE, 4, 4},
  36. {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
  37. {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
  38. {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
  39. {QLCNIC_CMD_MQ_TX_CONFIG_INTR, 2, 3},
  40. {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  41. };
  42. static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
  43. {
  44. return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
  45. (0xcafe << 16);
  46. }
  47. /* Allocate mailbox registers */
  48. int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
  49. struct qlcnic_adapter *adapter, u32 type)
  50. {
  51. int i, size;
  52. const struct qlcnic_mailbox_metadata *mbx_tbl;
  53. mbx_tbl = qlcnic_mbx_tbl;
  54. size = ARRAY_SIZE(qlcnic_mbx_tbl);
  55. for (i = 0; i < size; i++) {
  56. if (type == mbx_tbl[i].cmd) {
  57. mbx->req.num = mbx_tbl[i].in_args;
  58. mbx->rsp.num = mbx_tbl[i].out_args;
  59. mbx->req.arg = kcalloc(mbx->req.num,
  60. sizeof(u32), GFP_ATOMIC);
  61. if (!mbx->req.arg)
  62. return -ENOMEM;
  63. mbx->rsp.arg = kcalloc(mbx->rsp.num,
  64. sizeof(u32), GFP_ATOMIC);
  65. if (!mbx->rsp.arg) {
  66. kfree(mbx->req.arg);
  67. mbx->req.arg = NULL;
  68. return -ENOMEM;
  69. }
  70. memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
  71. memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
  72. mbx->req.arg[0] = type;
  73. break;
  74. }
  75. }
  76. return 0;
  77. }
  78. /* Free up mailbox registers */
  79. void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
  80. {
  81. kfree(cmd->req.arg);
  82. cmd->req.arg = NULL;
  83. kfree(cmd->rsp.arg);
  84. cmd->rsp.arg = NULL;
  85. }
  86. static int qlcnic_is_valid_nic_func(struct qlcnic_adapter *adapter, u8 pci_func)
  87. {
  88. int i;
  89. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  90. if (adapter->npars[i].pci_func == pci_func)
  91. return i;
  92. }
  93. return -1;
  94. }
  95. static u32
  96. qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
  97. {
  98. u32 rsp;
  99. int timeout = 0, err = 0;
  100. do {
  101. /* give atleast 1ms for firmware to respond */
  102. mdelay(1);
  103. if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
  104. return QLCNIC_CDRP_RSP_TIMEOUT;
  105. rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET, &err);
  106. } while (!QLCNIC_CDRP_IS_RSP(rsp));
  107. return rsp;
  108. }
  109. int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
  110. struct qlcnic_cmd_args *cmd)
  111. {
  112. int i, err = 0;
  113. u32 rsp;
  114. u32 signature;
  115. struct pci_dev *pdev = adapter->pdev;
  116. struct qlcnic_hardware_context *ahw = adapter->ahw;
  117. const char *fmt;
  118. signature = qlcnic_get_cmd_signature(ahw);
  119. /* Acquire semaphore before accessing CRB */
  120. if (qlcnic_api_lock(adapter)) {
  121. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  122. return cmd->rsp.arg[0];
  123. }
  124. QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
  125. for (i = 1; i < QLCNIC_CDRP_MAX_ARGS; i++)
  126. QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
  127. QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
  128. QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
  129. rsp = qlcnic_poll_rsp(adapter);
  130. if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
  131. dev_err(&pdev->dev, "card response timeout.\n");
  132. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  133. } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
  134. cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1), &err);
  135. switch (cmd->rsp.arg[0]) {
  136. case QLCNIC_RCODE_INVALID_ARGS:
  137. fmt = "CDRP invalid args: [%d]\n";
  138. break;
  139. case QLCNIC_RCODE_NOT_SUPPORTED:
  140. case QLCNIC_RCODE_NOT_IMPL:
  141. fmt = "CDRP command not supported: [%d]\n";
  142. break;
  143. case QLCNIC_RCODE_NOT_PERMITTED:
  144. fmt = "CDRP requested action not permitted: [%d]\n";
  145. break;
  146. case QLCNIC_RCODE_INVALID:
  147. fmt = "CDRP invalid or unknown cmd received: [%d]\n";
  148. break;
  149. case QLCNIC_RCODE_TIMEOUT:
  150. fmt = "CDRP command timeout: [%d]\n";
  151. break;
  152. default:
  153. fmt = "CDRP command failed: [%d]\n";
  154. break;
  155. }
  156. dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
  157. qlcnic_dump_mbx(adapter, cmd);
  158. } else if (rsp == QLCNIC_CDRP_RSP_OK)
  159. cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
  160. for (i = 1; i < cmd->rsp.num; i++)
  161. cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i), &err);
  162. /* Release semaphore */
  163. qlcnic_api_unlock(adapter);
  164. return cmd->rsp.arg[0];
  165. }
  166. int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
  167. {
  168. struct qlcnic_cmd_args cmd;
  169. u32 arg1, arg2, arg3;
  170. char drv_string[12];
  171. int err = 0;
  172. memset(drv_string, 0, sizeof(drv_string));
  173. snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
  174. _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
  175. _QLCNIC_LINUX_SUBVERSION);
  176. err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
  177. if (err)
  178. return err;
  179. memcpy(&arg1, drv_string, sizeof(u32));
  180. memcpy(&arg2, drv_string + 4, sizeof(u32));
  181. memcpy(&arg3, drv_string + 8, sizeof(u32));
  182. cmd.req.arg[1] = arg1;
  183. cmd.req.arg[2] = arg2;
  184. cmd.req.arg[3] = arg3;
  185. err = qlcnic_issue_cmd(adapter, &cmd);
  186. if (err) {
  187. dev_info(&adapter->pdev->dev,
  188. "Failed to set driver version in firmware\n");
  189. err = -EIO;
  190. }
  191. qlcnic_free_mbx_args(&cmd);
  192. return err;
  193. }
  194. int
  195. qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
  196. {
  197. int err = 0;
  198. struct qlcnic_cmd_args cmd;
  199. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  200. if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
  201. return err;
  202. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
  203. if (err)
  204. return err;
  205. cmd.req.arg[1] = recv_ctx->context_id;
  206. cmd.req.arg[2] = mtu;
  207. err = qlcnic_issue_cmd(adapter, &cmd);
  208. if (err) {
  209. dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
  210. err = -EIO;
  211. }
  212. qlcnic_free_mbx_args(&cmd);
  213. return err;
  214. }
  215. int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
  216. {
  217. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  218. struct qlcnic_hardware_context *ahw = adapter->ahw;
  219. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  220. struct net_device *netdev = adapter->netdev;
  221. u32 temp_intr_crb_mode, temp_rds_crb_mode;
  222. struct qlcnic_cardrsp_rds_ring *prsp_rds;
  223. struct qlcnic_cardrsp_sds_ring *prsp_sds;
  224. struct qlcnic_hostrq_rds_ring *prq_rds;
  225. struct qlcnic_hostrq_sds_ring *prq_sds;
  226. struct qlcnic_host_rds_ring *rds_ring;
  227. struct qlcnic_host_sds_ring *sds_ring;
  228. struct qlcnic_cardrsp_rx_ctx *prsp;
  229. struct qlcnic_hostrq_rx_ctx *prq;
  230. u8 i, nrds_rings, nsds_rings;
  231. struct qlcnic_cmd_args cmd;
  232. size_t rq_size, rsp_size;
  233. u32 cap, reg, val, reg2;
  234. u64 phys_addr;
  235. u16 temp_u16;
  236. void *addr;
  237. int err;
  238. nrds_rings = adapter->max_rds_rings;
  239. nsds_rings = adapter->max_sds_rings;
  240. rq_size = SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
  241. nsds_rings);
  242. rsp_size = SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
  243. nsds_rings);
  244. addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  245. &hostrq_phys_addr, GFP_KERNEL);
  246. if (addr == NULL)
  247. return -ENOMEM;
  248. prq = addr;
  249. addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  250. &cardrsp_phys_addr, GFP_KERNEL);
  251. if (addr == NULL) {
  252. err = -ENOMEM;
  253. goto out_free_rq;
  254. }
  255. prsp = addr;
  256. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  257. cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
  258. | QLCNIC_CAP0_VALIDOFF);
  259. cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
  260. if (qlcnic_check_multi_tx(adapter) &&
  261. !adapter->ahw->diag_test) {
  262. cap |= QLCNIC_CAP0_TX_MULTI;
  263. } else {
  264. temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
  265. prq->valid_field_offset = cpu_to_le16(temp_u16);
  266. prq->txrx_sds_binding = nsds_rings - 1;
  267. temp_intr_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  268. prq->host_int_crb_mode = cpu_to_le32(temp_intr_crb_mode);
  269. temp_rds_crb_mode = QLCNIC_HOST_RDS_CRB_MODE_UNIQUE;
  270. prq->host_rds_crb_mode = cpu_to_le32(temp_rds_crb_mode);
  271. }
  272. prq->capabilities[0] = cpu_to_le32(cap);
  273. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  274. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  275. prq->rds_ring_offset = 0;
  276. val = le32_to_cpu(prq->rds_ring_offset) +
  277. (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
  278. prq->sds_ring_offset = cpu_to_le32(val);
  279. prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
  280. le32_to_cpu(prq->rds_ring_offset));
  281. for (i = 0; i < nrds_rings; i++) {
  282. rds_ring = &recv_ctx->rds_rings[i];
  283. rds_ring->producer = 0;
  284. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  285. prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
  286. prq_rds[i].ring_kind = cpu_to_le32(i);
  287. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  288. }
  289. prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
  290. le32_to_cpu(prq->sds_ring_offset));
  291. for (i = 0; i < nsds_rings; i++) {
  292. sds_ring = &recv_ctx->sds_rings[i];
  293. sds_ring->consumer = 0;
  294. memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
  295. prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
  296. prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
  297. if (qlcnic_check_multi_tx(adapter) &&
  298. !adapter->ahw->diag_test)
  299. prq_sds[i].msi_index = cpu_to_le16(ahw->intr_tbl[i].id);
  300. else
  301. prq_sds[i].msi_index = cpu_to_le16(i);
  302. }
  303. phys_addr = hostrq_phys_addr;
  304. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
  305. if (err)
  306. goto out_free_rsp;
  307. cmd.req.arg[1] = MSD(phys_addr);
  308. cmd.req.arg[2] = LSD(phys_addr);
  309. cmd.req.arg[3] = rq_size;
  310. err = qlcnic_issue_cmd(adapter, &cmd);
  311. if (err) {
  312. dev_err(&adapter->pdev->dev,
  313. "Failed to create rx ctx in firmware%d\n", err);
  314. goto out_free_rsp;
  315. }
  316. prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
  317. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  318. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  319. rds_ring = &recv_ctx->rds_rings[i];
  320. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  321. rds_ring->crb_rcv_producer = ahw->pci_base0 + reg;
  322. }
  323. prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
  324. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  325. for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
  326. sds_ring = &recv_ctx->sds_rings[i];
  327. reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
  328. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  329. reg2 = ahw->intr_tbl[i].src;
  330. else
  331. reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
  332. sds_ring->crb_intr_mask = ahw->pci_base0 + reg2;
  333. sds_ring->crb_sts_consumer = ahw->pci_base0 + reg;
  334. }
  335. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  336. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  337. recv_ctx->virt_port = prsp->virt_port;
  338. netdev_info(netdev, "Rx Context[%d] Created, state 0x%x\n",
  339. recv_ctx->context_id, recv_ctx->state);
  340. qlcnic_free_mbx_args(&cmd);
  341. out_free_rsp:
  342. dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
  343. cardrsp_phys_addr);
  344. out_free_rq:
  345. dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
  346. return err;
  347. }
  348. void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
  349. {
  350. int err;
  351. struct qlcnic_cmd_args cmd;
  352. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  353. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
  354. if (err)
  355. return;
  356. cmd.req.arg[1] = recv_ctx->context_id;
  357. err = qlcnic_issue_cmd(adapter, &cmd);
  358. if (err)
  359. dev_err(&adapter->pdev->dev,
  360. "Failed to destroy rx ctx in firmware\n");
  361. recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
  362. qlcnic_free_mbx_args(&cmd);
  363. }
  364. int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
  365. struct qlcnic_host_tx_ring *tx_ring,
  366. int ring)
  367. {
  368. struct qlcnic_hardware_context *ahw = adapter->ahw;
  369. struct net_device *netdev = adapter->netdev;
  370. struct qlcnic_hostrq_tx_ctx *prq;
  371. struct qlcnic_hostrq_cds_ring *prq_cds;
  372. struct qlcnic_cardrsp_tx_ctx *prsp;
  373. struct qlcnic_cmd_args cmd;
  374. u32 temp, intr_mask, temp_int_crb_mode;
  375. dma_addr_t rq_phys_addr, rsp_phys_addr;
  376. int temp_nsds_rings, index, err;
  377. void *rq_addr, *rsp_addr;
  378. size_t rq_size, rsp_size;
  379. u64 phys_addr;
  380. u16 msix_id;
  381. /* reset host resources */
  382. tx_ring->producer = 0;
  383. tx_ring->sw_consumer = 0;
  384. *(tx_ring->hw_consumer) = 0;
  385. rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
  386. rq_addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  387. &rq_phys_addr, GFP_KERNEL | __GFP_ZERO);
  388. if (!rq_addr)
  389. return -ENOMEM;
  390. rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
  391. rsp_addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  392. &rsp_phys_addr, GFP_KERNEL | __GFP_ZERO);
  393. if (!rsp_addr) {
  394. err = -ENOMEM;
  395. goto out_free_rq;
  396. }
  397. prq = rq_addr;
  398. prsp = rsp_addr;
  399. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  400. temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
  401. QLCNIC_CAP0_LSO);
  402. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  403. temp |= QLCNIC_CAP0_TX_MULTI;
  404. prq->capabilities[0] = cpu_to_le32(temp);
  405. if (qlcnic_check_multi_tx(adapter) &&
  406. !adapter->ahw->diag_test) {
  407. temp_nsds_rings = adapter->max_sds_rings;
  408. index = temp_nsds_rings + ring;
  409. msix_id = ahw->intr_tbl[index].id;
  410. prq->msi_index = cpu_to_le16(msix_id);
  411. } else {
  412. temp_int_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  413. prq->host_int_crb_mode = cpu_to_le32(temp_int_crb_mode);
  414. prq->msi_index = 0;
  415. }
  416. prq->interrupt_ctl = 0;
  417. prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
  418. prq_cds = &prq->cds_ring;
  419. prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
  420. prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
  421. phys_addr = rq_phys_addr;
  422. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
  423. if (err)
  424. goto out_free_rsp;
  425. cmd.req.arg[1] = MSD(phys_addr);
  426. cmd.req.arg[2] = LSD(phys_addr);
  427. cmd.req.arg[3] = rq_size;
  428. err = qlcnic_issue_cmd(adapter, &cmd);
  429. if (err == QLCNIC_RCODE_SUCCESS) {
  430. tx_ring->state = le32_to_cpu(prsp->host_ctx_state);
  431. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  432. tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
  433. tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
  434. if (qlcnic_check_multi_tx(adapter) &&
  435. !adapter->ahw->diag_test &&
  436. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  437. index = adapter->max_sds_rings + ring;
  438. intr_mask = ahw->intr_tbl[index].src;
  439. tx_ring->crb_intr_mask = ahw->pci_base0 + intr_mask;
  440. }
  441. netdev_info(netdev, "Tx Context[0x%x] Created, state 0x%x\n",
  442. tx_ring->ctx_id, tx_ring->state);
  443. } else {
  444. netdev_err(netdev, "Failed to create tx ctx in firmware%d\n",
  445. err);
  446. err = -EIO;
  447. }
  448. qlcnic_free_mbx_args(&cmd);
  449. out_free_rsp:
  450. dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
  451. rsp_phys_addr);
  452. out_free_rq:
  453. dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
  454. return err;
  455. }
  456. void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
  457. struct qlcnic_host_tx_ring *tx_ring)
  458. {
  459. struct qlcnic_cmd_args cmd;
  460. int ret;
  461. ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
  462. if (ret)
  463. return;
  464. cmd.req.arg[1] = tx_ring->ctx_id;
  465. if (qlcnic_issue_cmd(adapter, &cmd))
  466. dev_err(&adapter->pdev->dev,
  467. "Failed to destroy tx ctx in firmware\n");
  468. qlcnic_free_mbx_args(&cmd);
  469. }
  470. int
  471. qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
  472. {
  473. int err;
  474. struct qlcnic_cmd_args cmd;
  475. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
  476. if (err)
  477. return err;
  478. cmd.req.arg[1] = config;
  479. err = qlcnic_issue_cmd(adapter, &cmd);
  480. qlcnic_free_mbx_args(&cmd);
  481. return err;
  482. }
  483. int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
  484. {
  485. void *addr;
  486. int err, ring;
  487. struct qlcnic_recv_context *recv_ctx;
  488. struct qlcnic_host_rds_ring *rds_ring;
  489. struct qlcnic_host_sds_ring *sds_ring;
  490. struct qlcnic_host_tx_ring *tx_ring;
  491. __le32 *ptr;
  492. struct pci_dev *pdev = adapter->pdev;
  493. recv_ctx = adapter->recv_ctx;
  494. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  495. tx_ring = &adapter->tx_ring[ring];
  496. ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
  497. &tx_ring->hw_cons_phys_addr,
  498. GFP_KERNEL);
  499. if (ptr == NULL)
  500. return -ENOMEM;
  501. tx_ring->hw_consumer = ptr;
  502. /* cmd desc ring */
  503. addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
  504. &tx_ring->phys_addr,
  505. GFP_KERNEL);
  506. if (addr == NULL) {
  507. err = -ENOMEM;
  508. goto err_out_free;
  509. }
  510. tx_ring->desc_head = addr;
  511. }
  512. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  513. rds_ring = &recv_ctx->rds_rings[ring];
  514. addr = dma_alloc_coherent(&adapter->pdev->dev,
  515. RCV_DESC_RINGSIZE(rds_ring),
  516. &rds_ring->phys_addr, GFP_KERNEL);
  517. if (addr == NULL) {
  518. err = -ENOMEM;
  519. goto err_out_free;
  520. }
  521. rds_ring->desc_head = addr;
  522. }
  523. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  524. sds_ring = &recv_ctx->sds_rings[ring];
  525. addr = dma_alloc_coherent(&adapter->pdev->dev,
  526. STATUS_DESC_RINGSIZE(sds_ring),
  527. &sds_ring->phys_addr, GFP_KERNEL);
  528. if (addr == NULL) {
  529. err = -ENOMEM;
  530. goto err_out_free;
  531. }
  532. sds_ring->desc_head = addr;
  533. }
  534. return 0;
  535. err_out_free:
  536. qlcnic_free_hw_resources(adapter);
  537. return err;
  538. }
  539. int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
  540. {
  541. int i, err, ring;
  542. if (dev->flags & QLCNIC_NEED_FLR) {
  543. pci_reset_function(dev->pdev);
  544. dev->flags &= ~QLCNIC_NEED_FLR;
  545. }
  546. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  547. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
  548. err = qlcnic_83xx_config_intrpt(dev, 1);
  549. if (err)
  550. return err;
  551. }
  552. }
  553. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  554. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test) {
  555. err = qlcnic_82xx_mq_intrpt(dev, 1);
  556. if (err)
  557. return err;
  558. }
  559. err = qlcnic_fw_cmd_create_rx_ctx(dev);
  560. if (err)
  561. goto err_out;
  562. for (ring = 0; ring < dev->max_drv_tx_rings; ring++) {
  563. err = qlcnic_fw_cmd_create_tx_ctx(dev,
  564. &dev->tx_ring[ring],
  565. ring);
  566. if (err) {
  567. qlcnic_fw_cmd_del_rx_ctx(dev);
  568. if (ring == 0)
  569. goto err_out;
  570. for (i = 0; i < ring; i++)
  571. qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
  572. goto err_out;
  573. }
  574. }
  575. set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
  576. return 0;
  577. err_out:
  578. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  579. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test)
  580. qlcnic_82xx_config_intrpt(dev, 0);
  581. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  582. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  583. qlcnic_83xx_config_intrpt(dev, 0);
  584. }
  585. return err;
  586. }
  587. void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
  588. {
  589. int ring;
  590. if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
  591. qlcnic_fw_cmd_del_rx_ctx(adapter);
  592. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++)
  593. qlcnic_fw_cmd_del_tx_ctx(adapter,
  594. &adapter->tx_ring[ring]);
  595. if (qlcnic_82xx_check(adapter) &&
  596. (adapter->flags & QLCNIC_MSIX_ENABLED) &&
  597. qlcnic_check_multi_tx(adapter) &&
  598. !adapter->ahw->diag_test)
  599. qlcnic_82xx_config_intrpt(adapter, 0);
  600. if (qlcnic_83xx_check(adapter) &&
  601. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  602. if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  603. qlcnic_83xx_config_intrpt(adapter, 0);
  604. }
  605. /* Allow dma queues to drain after context reset */
  606. mdelay(20);
  607. }
  608. }
  609. void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
  610. {
  611. struct qlcnic_recv_context *recv_ctx;
  612. struct qlcnic_host_rds_ring *rds_ring;
  613. struct qlcnic_host_sds_ring *sds_ring;
  614. struct qlcnic_host_tx_ring *tx_ring;
  615. int ring;
  616. recv_ctx = adapter->recv_ctx;
  617. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  618. tx_ring = &adapter->tx_ring[ring];
  619. if (tx_ring->hw_consumer != NULL) {
  620. dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
  621. tx_ring->hw_consumer,
  622. tx_ring->hw_cons_phys_addr);
  623. tx_ring->hw_consumer = NULL;
  624. }
  625. if (tx_ring->desc_head != NULL) {
  626. dma_free_coherent(&adapter->pdev->dev,
  627. TX_DESC_RINGSIZE(tx_ring),
  628. tx_ring->desc_head,
  629. tx_ring->phys_addr);
  630. tx_ring->desc_head = NULL;
  631. }
  632. }
  633. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  634. rds_ring = &recv_ctx->rds_rings[ring];
  635. if (rds_ring->desc_head != NULL) {
  636. dma_free_coherent(&adapter->pdev->dev,
  637. RCV_DESC_RINGSIZE(rds_ring),
  638. rds_ring->desc_head,
  639. rds_ring->phys_addr);
  640. rds_ring->desc_head = NULL;
  641. }
  642. }
  643. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  644. sds_ring = &recv_ctx->sds_rings[ring];
  645. if (sds_ring->desc_head != NULL) {
  646. dma_free_coherent(&adapter->pdev->dev,
  647. STATUS_DESC_RINGSIZE(sds_ring),
  648. sds_ring->desc_head,
  649. sds_ring->phys_addr);
  650. sds_ring->desc_head = NULL;
  651. }
  652. }
  653. }
  654. int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *adapter, u8 op_type)
  655. {
  656. struct qlcnic_hardware_context *ahw = adapter->ahw;
  657. struct net_device *netdev = adapter->netdev;
  658. struct qlcnic_cmd_args cmd;
  659. u32 type, val;
  660. int i, err = 0;
  661. for (i = 0; i < ahw->num_msix; i++) {
  662. qlcnic_alloc_mbx_args(&cmd, adapter,
  663. QLCNIC_CMD_MQ_TX_CONFIG_INTR);
  664. type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
  665. val = type | (ahw->intr_tbl[i].type << 4);
  666. if (ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
  667. val |= (ahw->intr_tbl[i].id << 16);
  668. cmd.req.arg[1] = val;
  669. err = qlcnic_issue_cmd(adapter, &cmd);
  670. if (err) {
  671. netdev_err(netdev, "Failed to %s interrupts %d\n",
  672. op_type == QLCNIC_INTRPT_ADD ? "Add" :
  673. "Delete", err);
  674. qlcnic_free_mbx_args(&cmd);
  675. return err;
  676. }
  677. val = cmd.rsp.arg[1];
  678. if (LSB(val)) {
  679. netdev_info(netdev,
  680. "failed to configure interrupt for %d\n",
  681. ahw->intr_tbl[i].id);
  682. continue;
  683. }
  684. if (op_type) {
  685. ahw->intr_tbl[i].id = MSW(val);
  686. ahw->intr_tbl[i].enabled = 1;
  687. ahw->intr_tbl[i].src = cmd.rsp.arg[2];
  688. } else {
  689. ahw->intr_tbl[i].id = i;
  690. ahw->intr_tbl[i].enabled = 0;
  691. ahw->intr_tbl[i].src = 0;
  692. }
  693. qlcnic_free_mbx_args(&cmd);
  694. }
  695. return err;
  696. }
  697. int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
  698. u8 function)
  699. {
  700. int err, i;
  701. struct qlcnic_cmd_args cmd;
  702. u32 mac_low, mac_high;
  703. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
  704. if (err)
  705. return err;
  706. cmd.req.arg[1] = function | BIT_8;
  707. err = qlcnic_issue_cmd(adapter, &cmd);
  708. if (err == QLCNIC_RCODE_SUCCESS) {
  709. mac_low = cmd.rsp.arg[1];
  710. mac_high = cmd.rsp.arg[2];
  711. for (i = 0; i < 2; i++)
  712. mac[i] = (u8) (mac_high >> ((1 - i) * 8));
  713. for (i = 2; i < 6; i++)
  714. mac[i] = (u8) (mac_low >> ((5 - i) * 8));
  715. } else {
  716. dev_err(&adapter->pdev->dev,
  717. "Failed to get mac address%d\n", err);
  718. err = -EIO;
  719. }
  720. qlcnic_free_mbx_args(&cmd);
  721. return err;
  722. }
  723. /* Get info of a NIC partition */
  724. int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
  725. struct qlcnic_info *npar_info, u8 func_id)
  726. {
  727. int err;
  728. dma_addr_t nic_dma_t;
  729. const struct qlcnic_info_le *nic_info;
  730. void *nic_info_addr;
  731. struct qlcnic_cmd_args cmd;
  732. size_t nic_size = sizeof(struct qlcnic_info_le);
  733. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  734. &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
  735. if (!nic_info_addr)
  736. return -ENOMEM;
  737. nic_info = nic_info_addr;
  738. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
  739. if (err)
  740. goto out_free_dma;
  741. cmd.req.arg[1] = MSD(nic_dma_t);
  742. cmd.req.arg[2] = LSD(nic_dma_t);
  743. cmd.req.arg[3] = (func_id << 16 | nic_size);
  744. err = qlcnic_issue_cmd(adapter, &cmd);
  745. if (err != QLCNIC_RCODE_SUCCESS) {
  746. dev_err(&adapter->pdev->dev,
  747. "Failed to get nic info%d\n", err);
  748. err = -EIO;
  749. } else {
  750. npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
  751. npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
  752. npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
  753. npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
  754. npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
  755. npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
  756. npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
  757. npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
  758. npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
  759. npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
  760. }
  761. qlcnic_free_mbx_args(&cmd);
  762. out_free_dma:
  763. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  764. nic_dma_t);
  765. return err;
  766. }
  767. /* Configure a NIC partition */
  768. int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
  769. struct qlcnic_info *nic)
  770. {
  771. int err = -EIO;
  772. dma_addr_t nic_dma_t;
  773. void *nic_info_addr;
  774. struct qlcnic_cmd_args cmd;
  775. struct qlcnic_info_le *nic_info;
  776. size_t nic_size = sizeof(struct qlcnic_info_le);
  777. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  778. return err;
  779. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  780. &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
  781. if (!nic_info_addr)
  782. return -ENOMEM;
  783. nic_info = nic_info_addr;
  784. nic_info->pci_func = cpu_to_le16(nic->pci_func);
  785. nic_info->op_mode = cpu_to_le16(nic->op_mode);
  786. nic_info->phys_port = cpu_to_le16(nic->phys_port);
  787. nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
  788. nic_info->capabilities = cpu_to_le32(nic->capabilities);
  789. nic_info->max_mac_filters = nic->max_mac_filters;
  790. nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
  791. nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
  792. nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
  793. nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
  794. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
  795. if (err)
  796. goto out_free_dma;
  797. cmd.req.arg[1] = MSD(nic_dma_t);
  798. cmd.req.arg[2] = LSD(nic_dma_t);
  799. cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
  800. err = qlcnic_issue_cmd(adapter, &cmd);
  801. if (err != QLCNIC_RCODE_SUCCESS) {
  802. dev_err(&adapter->pdev->dev,
  803. "Failed to set nic info%d\n", err);
  804. err = -EIO;
  805. }
  806. qlcnic_free_mbx_args(&cmd);
  807. out_free_dma:
  808. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  809. nic_dma_t);
  810. return err;
  811. }
  812. /* Get PCI Info of a partition */
  813. int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
  814. struct qlcnic_pci_info *pci_info)
  815. {
  816. int err = 0, i;
  817. struct qlcnic_cmd_args cmd;
  818. dma_addr_t pci_info_dma_t;
  819. struct qlcnic_pci_info_le *npar;
  820. void *pci_info_addr;
  821. size_t npar_size = sizeof(struct qlcnic_pci_info_le);
  822. size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
  823. pci_info_addr = dma_alloc_coherent(&adapter->pdev->dev, pci_size,
  824. &pci_info_dma_t,
  825. GFP_KERNEL | __GFP_ZERO);
  826. if (!pci_info_addr)
  827. return -ENOMEM;
  828. npar = pci_info_addr;
  829. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
  830. if (err)
  831. goto out_free_dma;
  832. cmd.req.arg[1] = MSD(pci_info_dma_t);
  833. cmd.req.arg[2] = LSD(pci_info_dma_t);
  834. cmd.req.arg[3] = pci_size;
  835. err = qlcnic_issue_cmd(adapter, &cmd);
  836. adapter->ahw->act_pci_func = 0;
  837. if (err == QLCNIC_RCODE_SUCCESS) {
  838. for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++, pci_info++) {
  839. pci_info->id = le16_to_cpu(npar->id);
  840. pci_info->active = le16_to_cpu(npar->active);
  841. pci_info->type = le16_to_cpu(npar->type);
  842. if (pci_info->type == QLCNIC_TYPE_NIC)
  843. adapter->ahw->act_pci_func++;
  844. pci_info->default_port =
  845. le16_to_cpu(npar->default_port);
  846. pci_info->tx_min_bw =
  847. le16_to_cpu(npar->tx_min_bw);
  848. pci_info->tx_max_bw =
  849. le16_to_cpu(npar->tx_max_bw);
  850. memcpy(pci_info->mac, npar->mac, ETH_ALEN);
  851. }
  852. } else {
  853. dev_err(&adapter->pdev->dev,
  854. "Failed to get PCI Info%d\n", err);
  855. err = -EIO;
  856. }
  857. qlcnic_free_mbx_args(&cmd);
  858. out_free_dma:
  859. dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
  860. pci_info_dma_t);
  861. return err;
  862. }
  863. /* Configure eSwitch for port mirroring */
  864. int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
  865. u8 enable_mirroring, u8 pci_func)
  866. {
  867. struct device *dev = &adapter->pdev->dev;
  868. struct qlcnic_cmd_args cmd;
  869. int err = -EIO;
  870. u32 arg1;
  871. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
  872. !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
  873. return err;
  874. arg1 = id | (enable_mirroring ? BIT_4 : 0);
  875. arg1 |= pci_func << 8;
  876. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  877. QLCNIC_CMD_SET_PORTMIRRORING);
  878. if (err)
  879. return err;
  880. cmd.req.arg[1] = arg1;
  881. err = qlcnic_issue_cmd(adapter, &cmd);
  882. if (err != QLCNIC_RCODE_SUCCESS)
  883. dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
  884. pci_func, id);
  885. else
  886. dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
  887. pci_func, id);
  888. qlcnic_free_mbx_args(&cmd);
  889. return err;
  890. }
  891. int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
  892. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  893. size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
  894. struct qlcnic_esw_stats_le *stats;
  895. dma_addr_t stats_dma_t;
  896. void *stats_addr;
  897. u32 arg1;
  898. struct qlcnic_cmd_args cmd;
  899. int err;
  900. if (esw_stats == NULL)
  901. return -ENOMEM;
  902. if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
  903. (func != adapter->ahw->pci_func)) {
  904. dev_err(&adapter->pdev->dev,
  905. "Not privilege to query stats for func=%d", func);
  906. return -EIO;
  907. }
  908. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  909. &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
  910. if (!stats_addr)
  911. return -ENOMEM;
  912. arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
  913. arg1 |= rx_tx << 15 | stats_size << 16;
  914. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  915. QLCNIC_CMD_GET_ESWITCH_STATS);
  916. if (err)
  917. goto out_free_dma;
  918. cmd.req.arg[1] = arg1;
  919. cmd.req.arg[2] = MSD(stats_dma_t);
  920. cmd.req.arg[3] = LSD(stats_dma_t);
  921. err = qlcnic_issue_cmd(adapter, &cmd);
  922. if (!err) {
  923. stats = stats_addr;
  924. esw_stats->context_id = le16_to_cpu(stats->context_id);
  925. esw_stats->version = le16_to_cpu(stats->version);
  926. esw_stats->size = le16_to_cpu(stats->size);
  927. esw_stats->multicast_frames =
  928. le64_to_cpu(stats->multicast_frames);
  929. esw_stats->broadcast_frames =
  930. le64_to_cpu(stats->broadcast_frames);
  931. esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
  932. esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
  933. esw_stats->local_frames = le64_to_cpu(stats->local_frames);
  934. esw_stats->errors = le64_to_cpu(stats->errors);
  935. esw_stats->numbytes = le64_to_cpu(stats->numbytes);
  936. }
  937. qlcnic_free_mbx_args(&cmd);
  938. out_free_dma:
  939. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  940. stats_dma_t);
  941. return err;
  942. }
  943. /* This routine will retrieve the MAC statistics from firmware */
  944. int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
  945. struct qlcnic_mac_statistics *mac_stats)
  946. {
  947. struct qlcnic_mac_statistics_le *stats;
  948. struct qlcnic_cmd_args cmd;
  949. size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
  950. dma_addr_t stats_dma_t;
  951. void *stats_addr;
  952. int err;
  953. if (mac_stats == NULL)
  954. return -ENOMEM;
  955. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  956. &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
  957. if (!stats_addr)
  958. return -ENOMEM;
  959. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
  960. if (err)
  961. goto out_free_dma;
  962. cmd.req.arg[1] = stats_size << 16;
  963. cmd.req.arg[2] = MSD(stats_dma_t);
  964. cmd.req.arg[3] = LSD(stats_dma_t);
  965. err = qlcnic_issue_cmd(adapter, &cmd);
  966. if (!err) {
  967. stats = stats_addr;
  968. mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
  969. mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
  970. mac_stats->mac_tx_mcast_pkts =
  971. le64_to_cpu(stats->mac_tx_mcast_pkts);
  972. mac_stats->mac_tx_bcast_pkts =
  973. le64_to_cpu(stats->mac_tx_bcast_pkts);
  974. mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
  975. mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
  976. mac_stats->mac_rx_mcast_pkts =
  977. le64_to_cpu(stats->mac_rx_mcast_pkts);
  978. mac_stats->mac_rx_length_error =
  979. le64_to_cpu(stats->mac_rx_length_error);
  980. mac_stats->mac_rx_length_small =
  981. le64_to_cpu(stats->mac_rx_length_small);
  982. mac_stats->mac_rx_length_large =
  983. le64_to_cpu(stats->mac_rx_length_large);
  984. mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
  985. mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
  986. mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
  987. } else {
  988. dev_err(&adapter->pdev->dev,
  989. "%s: Get mac stats failed, err=%d.\n", __func__, err);
  990. }
  991. qlcnic_free_mbx_args(&cmd);
  992. out_free_dma:
  993. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  994. stats_dma_t);
  995. return err;
  996. }
  997. int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
  998. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  999. struct __qlcnic_esw_statistics port_stats;
  1000. u8 i;
  1001. int ret = -EIO;
  1002. if (esw_stats == NULL)
  1003. return -ENOMEM;
  1004. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1005. return -EIO;
  1006. if (adapter->npars == NULL)
  1007. return -EIO;
  1008. memset(esw_stats, 0, sizeof(u64));
  1009. esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1010. esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1011. esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
  1012. esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
  1013. esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
  1014. esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
  1015. esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
  1016. esw_stats->context_id = eswitch;
  1017. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  1018. if (adapter->npars[i].phy_port != eswitch)
  1019. continue;
  1020. memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
  1021. if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
  1022. rx_tx, &port_stats))
  1023. continue;
  1024. esw_stats->size = port_stats.size;
  1025. esw_stats->version = port_stats.version;
  1026. QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
  1027. port_stats.unicast_frames);
  1028. QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
  1029. port_stats.multicast_frames);
  1030. QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
  1031. port_stats.broadcast_frames);
  1032. QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
  1033. port_stats.dropped_frames);
  1034. QLCNIC_ADD_ESW_STATS(esw_stats->errors,
  1035. port_stats.errors);
  1036. QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
  1037. port_stats.local_frames);
  1038. QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
  1039. port_stats.numbytes);
  1040. ret = 0;
  1041. }
  1042. return ret;
  1043. }
  1044. int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
  1045. const u8 port, const u8 rx_tx)
  1046. {
  1047. int err;
  1048. u32 arg1;
  1049. struct qlcnic_cmd_args cmd;
  1050. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1051. return -EIO;
  1052. if (func_esw == QLCNIC_STATS_PORT) {
  1053. if (port >= QLCNIC_MAX_PCI_FUNC)
  1054. goto err_ret;
  1055. } else if (func_esw == QLCNIC_STATS_ESWITCH) {
  1056. if (port >= QLCNIC_NIU_MAX_XG_PORTS)
  1057. goto err_ret;
  1058. } else {
  1059. goto err_ret;
  1060. }
  1061. if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
  1062. goto err_ret;
  1063. arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
  1064. arg1 |= BIT_14 | rx_tx << 15;
  1065. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1066. QLCNIC_CMD_GET_ESWITCH_STATS);
  1067. if (err)
  1068. return err;
  1069. cmd.req.arg[1] = arg1;
  1070. err = qlcnic_issue_cmd(adapter, &cmd);
  1071. qlcnic_free_mbx_args(&cmd);
  1072. return err;
  1073. err_ret:
  1074. dev_err(&adapter->pdev->dev,
  1075. "Invalid args func_esw %d port %d rx_ctx %d\n",
  1076. func_esw, port, rx_tx);
  1077. return -EIO;
  1078. }
  1079. static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1080. u32 *arg1, u32 *arg2)
  1081. {
  1082. struct device *dev = &adapter->pdev->dev;
  1083. struct qlcnic_cmd_args cmd;
  1084. u8 pci_func = *arg1 >> 8;
  1085. int err;
  1086. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1087. QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
  1088. if (err)
  1089. return err;
  1090. cmd.req.arg[1] = *arg1;
  1091. err = qlcnic_issue_cmd(adapter, &cmd);
  1092. *arg1 = cmd.rsp.arg[1];
  1093. *arg2 = cmd.rsp.arg[2];
  1094. qlcnic_free_mbx_args(&cmd);
  1095. if (err == QLCNIC_RCODE_SUCCESS)
  1096. dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
  1097. pci_func);
  1098. else
  1099. dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
  1100. pci_func);
  1101. return err;
  1102. }
  1103. /* Configure eSwitch port
  1104. op_mode = 0 for setting default port behavior
  1105. op_mode = 1 for setting vlan id
  1106. op_mode = 2 for deleting vlan id
  1107. op_type = 0 for vlan_id
  1108. op_type = 1 for port vlan_id
  1109. */
  1110. int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
  1111. struct qlcnic_esw_func_cfg *esw_cfg)
  1112. {
  1113. struct device *dev = &adapter->pdev->dev;
  1114. struct qlcnic_cmd_args cmd;
  1115. int err = -EIO, index;
  1116. u32 arg1, arg2 = 0;
  1117. u8 pci_func;
  1118. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1119. return err;
  1120. pci_func = esw_cfg->pci_func;
  1121. index = qlcnic_is_valid_nic_func(adapter, pci_func);
  1122. if (index < 0)
  1123. return err;
  1124. arg1 = (adapter->npars[index].phy_port & BIT_0);
  1125. arg1 |= (pci_func << 8);
  1126. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1127. return err;
  1128. arg1 &= ~(0x0ff << 8);
  1129. arg1 |= (pci_func << 8);
  1130. arg1 &= ~(BIT_2 | BIT_3);
  1131. switch (esw_cfg->op_mode) {
  1132. case QLCNIC_PORT_DEFAULTS:
  1133. arg1 |= (BIT_4 | BIT_6 | BIT_7);
  1134. arg2 |= (BIT_0 | BIT_1);
  1135. if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
  1136. arg2 |= (BIT_2 | BIT_3);
  1137. if (!(esw_cfg->discard_tagged))
  1138. arg1 &= ~BIT_4;
  1139. if (!(esw_cfg->promisc_mode))
  1140. arg1 &= ~BIT_6;
  1141. if (!(esw_cfg->mac_override))
  1142. arg1 &= ~BIT_7;
  1143. if (!(esw_cfg->mac_anti_spoof))
  1144. arg2 &= ~BIT_0;
  1145. if (!(esw_cfg->offload_flags & BIT_0))
  1146. arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
  1147. if (!(esw_cfg->offload_flags & BIT_1))
  1148. arg2 &= ~BIT_2;
  1149. if (!(esw_cfg->offload_flags & BIT_2))
  1150. arg2 &= ~BIT_3;
  1151. break;
  1152. case QLCNIC_ADD_VLAN:
  1153. arg1 |= (BIT_2 | BIT_5);
  1154. arg1 |= (esw_cfg->vlan_id << 16);
  1155. break;
  1156. case QLCNIC_DEL_VLAN:
  1157. arg1 |= (BIT_3 | BIT_5);
  1158. arg1 &= ~(0x0ffff << 16);
  1159. break;
  1160. default:
  1161. return err;
  1162. }
  1163. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1164. QLCNIC_CMD_CONFIGURE_ESWITCH);
  1165. if (err)
  1166. return err;
  1167. cmd.req.arg[1] = arg1;
  1168. cmd.req.arg[2] = arg2;
  1169. err = qlcnic_issue_cmd(adapter, &cmd);
  1170. qlcnic_free_mbx_args(&cmd);
  1171. if (err != QLCNIC_RCODE_SUCCESS)
  1172. dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
  1173. pci_func);
  1174. else
  1175. dev_info(dev, "Configured eSwitch for vNIC function %d\n",
  1176. pci_func);
  1177. return err;
  1178. }
  1179. int
  1180. qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1181. struct qlcnic_esw_func_cfg *esw_cfg)
  1182. {
  1183. u32 arg1, arg2;
  1184. int index;
  1185. u8 phy_port;
  1186. if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
  1187. index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
  1188. if (index < 0)
  1189. return -EIO;
  1190. phy_port = adapter->npars[index].phy_port;
  1191. } else {
  1192. phy_port = adapter->ahw->physical_port;
  1193. }
  1194. arg1 = phy_port;
  1195. arg1 |= (esw_cfg->pci_func << 8);
  1196. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1197. return -EIO;
  1198. esw_cfg->discard_tagged = !!(arg1 & BIT_4);
  1199. esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
  1200. esw_cfg->promisc_mode = !!(arg1 & BIT_6);
  1201. esw_cfg->mac_override = !!(arg1 & BIT_7);
  1202. esw_cfg->vlan_id = LSW(arg1 >> 16);
  1203. esw_cfg->mac_anti_spoof = (arg2 & 0x1);
  1204. esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
  1205. return 0;
  1206. }