cm_bf537.c 13 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf537/boards/cm_bf537.c
  3. * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
  4. * Author: Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Created: 2005
  7. * Description: Board description file
  8. *
  9. * Modified:
  10. * Copyright 2005 National ICT Australia (NICTA)
  11. * Copyright 2004-2006 Analog Devices Inc.
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <linux/device.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/mtd/mtd.h>
  34. #include <linux/mtd/partitions.h>
  35. #include <linux/spi/spi.h>
  36. #include <linux/spi/flash.h>
  37. #include <linux/usb/isp1362.h>
  38. #include <linux/ata_platform.h>
  39. #include <linux/irq.h>
  40. #include <asm/dma.h>
  41. #include <asm/bfin5xx_spi.h>
  42. #include <asm/portmux.h>
  43. #include <asm/dpmc.h>
  44. /*
  45. * Name the Board for the /proc/cpuinfo
  46. */
  47. const char bfin_board_name[] = "Bluetechnix CM BF537";
  48. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  49. /* all SPI peripherals info goes here */
  50. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  51. static struct mtd_partition bfin_spi_flash_partitions[] = {
  52. {
  53. .name = "bootloader",
  54. .size = 0x00020000,
  55. .offset = 0,
  56. .mask_flags = MTD_CAP_ROM
  57. }, {
  58. .name = "kernel",
  59. .size = 0xe0000,
  60. .offset = 0x20000
  61. }, {
  62. .name = "file system",
  63. .size = 0x700000,
  64. .offset = 0x00100000,
  65. }
  66. };
  67. static struct flash_platform_data bfin_spi_flash_data = {
  68. .name = "m25p80",
  69. .parts = bfin_spi_flash_partitions,
  70. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  71. .type = "m25p64",
  72. };
  73. /* SPI flash chip (m25p64) */
  74. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  75. .enable_dma = 0, /* use dma transfer with this chip*/
  76. .bits_per_word = 8,
  77. };
  78. #endif
  79. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  80. /* SPI ADC chip */
  81. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  82. .enable_dma = 1, /* use dma transfer with this chip*/
  83. .bits_per_word = 16,
  84. };
  85. #endif
  86. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  87. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  88. .enable_dma = 0,
  89. .bits_per_word = 16,
  90. };
  91. #endif
  92. #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
  93. static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
  94. .enable_dma = 0,
  95. .bits_per_word = 16,
  96. };
  97. #endif
  98. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  99. static struct bfin5xx_spi_chip spi_mmc_chip_info = {
  100. .enable_dma = 1,
  101. .bits_per_word = 8,
  102. };
  103. #endif
  104. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  105. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  106. {
  107. /* the modalias must be the same as spi device driver name */
  108. .modalias = "m25p80", /* Name of spi_driver for this device */
  109. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  110. .bus_num = 0, /* Framework bus number */
  111. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  112. .platform_data = &bfin_spi_flash_data,
  113. .controller_data = &spi_flash_chip_info,
  114. .mode = SPI_MODE_3,
  115. },
  116. #endif
  117. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  118. {
  119. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  120. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  121. .bus_num = 0, /* Framework bus number */
  122. .chip_select = 1, /* Framework chip select. */
  123. .platform_data = NULL, /* No spi_driver specific config */
  124. .controller_data = &spi_adc_chip_info,
  125. },
  126. #endif
  127. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  128. {
  129. .modalias = "ad1836-spi",
  130. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  131. .bus_num = 0,
  132. .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
  133. .controller_data = &ad1836_spi_chip_info,
  134. },
  135. #endif
  136. #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
  137. {
  138. .modalias = "ad9960-spi",
  139. .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
  140. .bus_num = 0,
  141. .chip_select = 1,
  142. .controller_data = &ad9960_spi_chip_info,
  143. },
  144. #endif
  145. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  146. {
  147. .modalias = "spi_mmc_dummy",
  148. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  149. .bus_num = 0,
  150. .chip_select = 7,
  151. .platform_data = NULL,
  152. .controller_data = &spi_mmc_chip_info,
  153. .mode = SPI_MODE_3,
  154. },
  155. {
  156. .modalias = "spi_mmc",
  157. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  158. .bus_num = 0,
  159. .chip_select = CONFIG_SPI_MMC_CS_CHAN,
  160. .platform_data = NULL,
  161. .controller_data = &spi_mmc_chip_info,
  162. .mode = SPI_MODE_3,
  163. },
  164. #endif
  165. };
  166. /* SPI (0) */
  167. static struct resource bfin_spi0_resource[] = {
  168. [0] = {
  169. .start = SPI0_REGBASE,
  170. .end = SPI0_REGBASE + 0xFF,
  171. .flags = IORESOURCE_MEM,
  172. },
  173. [1] = {
  174. .start = CH_SPI,
  175. .end = CH_SPI,
  176. .flags = IORESOURCE_IRQ,
  177. }
  178. };
  179. /* SPI controller data */
  180. static struct bfin5xx_spi_master bfin_spi0_info = {
  181. .num_chipselect = 8,
  182. .enable_dma = 1, /* master has the ability to do dma transfer */
  183. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  184. };
  185. static struct platform_device bfin_spi0_device = {
  186. .name = "bfin-spi",
  187. .id = 0, /* Bus number */
  188. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  189. .resource = bfin_spi0_resource,
  190. .dev = {
  191. .platform_data = &bfin_spi0_info, /* Passed to driver */
  192. },
  193. };
  194. #endif /* spi master and devices */
  195. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  196. static struct platform_device rtc_device = {
  197. .name = "rtc-bfin",
  198. .id = -1,
  199. };
  200. #endif
  201. #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
  202. static struct platform_device hitachi_fb_device = {
  203. .name = "hitachi-tx09",
  204. };
  205. #endif
  206. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  207. static struct resource smc91x_resources[] = {
  208. {
  209. .start = 0x20200300,
  210. .end = 0x20200300 + 16,
  211. .flags = IORESOURCE_MEM,
  212. }, {
  213. .start = IRQ_PF14,
  214. .end = IRQ_PF14,
  215. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  216. },
  217. };
  218. static struct platform_device smc91x_device = {
  219. .name = "smc91x",
  220. .id = 0,
  221. .num_resources = ARRAY_SIZE(smc91x_resources),
  222. .resource = smc91x_resources,
  223. };
  224. #endif
  225. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  226. static struct resource isp1362_hcd_resources[] = {
  227. {
  228. .start = 0x20308000,
  229. .end = 0x20308000,
  230. .flags = IORESOURCE_MEM,
  231. }, {
  232. .start = 0x20308004,
  233. .end = 0x20308004,
  234. .flags = IORESOURCE_MEM,
  235. }, {
  236. .start = IRQ_PG15,
  237. .end = IRQ_PG15,
  238. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  239. },
  240. };
  241. static struct isp1362_platform_data isp1362_priv = {
  242. .sel15Kres = 1,
  243. .clknotstop = 0,
  244. .oc_enable = 0,
  245. .int_act_high = 0,
  246. .int_edge_triggered = 0,
  247. .remote_wakeup_connected = 0,
  248. .no_power_switching = 1,
  249. .power_switching_mode = 0,
  250. };
  251. static struct platform_device isp1362_hcd_device = {
  252. .name = "isp1362-hcd",
  253. .id = 0,
  254. .dev = {
  255. .platform_data = &isp1362_priv,
  256. },
  257. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  258. .resource = isp1362_hcd_resources,
  259. };
  260. #endif
  261. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  262. static struct resource net2272_bfin_resources[] = {
  263. {
  264. .start = 0x20200000,
  265. .end = 0x20200000 + 0x100,
  266. .flags = IORESOURCE_MEM,
  267. }, {
  268. .start = IRQ_PH14,
  269. .end = IRQ_PH14,
  270. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  271. },
  272. };
  273. static struct platform_device net2272_bfin_device = {
  274. .name = "net2272",
  275. .id = -1,
  276. .num_resources = ARRAY_SIZE(net2272_bfin_resources),
  277. .resource = net2272_bfin_resources,
  278. };
  279. #endif
  280. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  281. static struct resource bfin_uart_resources[] = {
  282. {
  283. .start = 0xFFC00400,
  284. .end = 0xFFC004FF,
  285. .flags = IORESOURCE_MEM,
  286. }, {
  287. .start = 0xFFC02000,
  288. .end = 0xFFC020FF,
  289. .flags = IORESOURCE_MEM,
  290. },
  291. };
  292. static struct platform_device bfin_uart_device = {
  293. .name = "bfin-uart",
  294. .id = 1,
  295. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  296. .resource = bfin_uart_resources,
  297. };
  298. #endif
  299. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  300. static struct resource bfin_sir_resources[] = {
  301. #ifdef CONFIG_BFIN_SIR0
  302. {
  303. .start = 0xFFC00400,
  304. .end = 0xFFC004FF,
  305. .flags = IORESOURCE_MEM,
  306. },
  307. #endif
  308. #ifdef CONFIG_BFIN_SIR1
  309. {
  310. .start = 0xFFC02000,
  311. .end = 0xFFC020FF,
  312. .flags = IORESOURCE_MEM,
  313. },
  314. #endif
  315. };
  316. static struct platform_device bfin_sir_device = {
  317. .name = "bfin_sir",
  318. .id = 0,
  319. .num_resources = ARRAY_SIZE(bfin_sir_resources),
  320. .resource = bfin_sir_resources,
  321. };
  322. #endif
  323. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  324. static struct resource bfin_twi0_resource[] = {
  325. [0] = {
  326. .start = TWI0_REGBASE,
  327. .end = TWI0_REGBASE,
  328. .flags = IORESOURCE_MEM,
  329. },
  330. [1] = {
  331. .start = IRQ_TWI,
  332. .end = IRQ_TWI,
  333. .flags = IORESOURCE_IRQ,
  334. },
  335. };
  336. static struct platform_device i2c_bfin_twi_device = {
  337. .name = "i2c-bfin-twi",
  338. .id = 0,
  339. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  340. .resource = bfin_twi0_resource,
  341. };
  342. #endif
  343. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  344. static struct platform_device bfin_sport0_uart_device = {
  345. .name = "bfin-sport-uart",
  346. .id = 0,
  347. };
  348. static struct platform_device bfin_sport1_uart_device = {
  349. .name = "bfin-sport-uart",
  350. .id = 1,
  351. };
  352. #endif
  353. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  354. static struct platform_device bfin_mac_device = {
  355. .name = "bfin_mac",
  356. };
  357. #endif
  358. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  359. #define PATA_INT 64
  360. static struct pata_platform_info bfin_pata_platform_data = {
  361. .ioport_shift = 2,
  362. .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
  363. };
  364. static struct resource bfin_pata_resources[] = {
  365. {
  366. .start = 0x2030C000,
  367. .end = 0x2030C01F,
  368. .flags = IORESOURCE_MEM,
  369. },
  370. {
  371. .start = 0x2030D018,
  372. .end = 0x2030D01B,
  373. .flags = IORESOURCE_MEM,
  374. },
  375. {
  376. .start = PATA_INT,
  377. .end = PATA_INT,
  378. .flags = IORESOURCE_IRQ,
  379. },
  380. };
  381. static struct platform_device bfin_pata_device = {
  382. .name = "pata_platform",
  383. .id = -1,
  384. .num_resources = ARRAY_SIZE(bfin_pata_resources),
  385. .resource = bfin_pata_resources,
  386. .dev = {
  387. .platform_data = &bfin_pata_platform_data,
  388. }
  389. };
  390. #endif
  391. static const unsigned int cclk_vlev_datasheet[] =
  392. {
  393. VRPAIR(VLEV_085, 250000000),
  394. VRPAIR(VLEV_090, 376000000),
  395. VRPAIR(VLEV_095, 426000000),
  396. VRPAIR(VLEV_100, 426000000),
  397. VRPAIR(VLEV_105, 476000000),
  398. VRPAIR(VLEV_110, 476000000),
  399. VRPAIR(VLEV_115, 476000000),
  400. VRPAIR(VLEV_120, 500000000),
  401. VRPAIR(VLEV_125, 533000000),
  402. VRPAIR(VLEV_130, 600000000),
  403. };
  404. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  405. .tuple_tab = cclk_vlev_datasheet,
  406. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  407. .vr_settling_time = 25 /* us */,
  408. };
  409. static struct platform_device bfin_dpmc = {
  410. .name = "bfin dpmc",
  411. .dev = {
  412. .platform_data = &bfin_dmpc_vreg_data,
  413. },
  414. };
  415. static struct platform_device *cm_bf537_devices[] __initdata = {
  416. &bfin_dpmc,
  417. #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
  418. &hitachi_fb_device,
  419. #endif
  420. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  421. &rtc_device,
  422. #endif
  423. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  424. &bfin_uart_device,
  425. #endif
  426. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  427. &bfin_sir_device,
  428. #endif
  429. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  430. &i2c_bfin_twi_device,
  431. #endif
  432. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  433. &bfin_sport0_uart_device,
  434. &bfin_sport1_uart_device,
  435. #endif
  436. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  437. &isp1362_hcd_device,
  438. #endif
  439. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  440. &smc91x_device,
  441. #endif
  442. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  443. &bfin_mac_device,
  444. #endif
  445. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  446. &net2272_bfin_device,
  447. #endif
  448. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  449. &bfin_spi0_device,
  450. #endif
  451. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  452. &bfin_pata_device,
  453. #endif
  454. };
  455. static int __init cm_bf537_init(void)
  456. {
  457. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  458. platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
  459. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  460. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  461. #endif
  462. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  463. irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
  464. #endif
  465. return 0;
  466. }
  467. arch_initcall(cm_bf537_init);
  468. void bfin_get_ether_addr(char *addr)
  469. {
  470. random_ether_addr(addr);
  471. printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
  472. }
  473. EXPORT_SYMBOL(bfin_get_ether_addr);