cm_bf533.c 11 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf533/boards/cm_bf533.c
  3. * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
  4. * Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005
  5. *
  6. * Created: 2005
  7. * Description: Board description file
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/device.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/mtd/mtd.h>
  32. #include <linux/mtd/partitions.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/spi/flash.h>
  35. #include <linux/usb/isp1362.h>
  36. #include <linux/ata_platform.h>
  37. #include <linux/irq.h>
  38. #include <asm/dma.h>
  39. #include <asm/bfin5xx_spi.h>
  40. #include <asm/portmux.h>
  41. #include <asm/dpmc.h>
  42. /*
  43. * Name the Board for the /proc/cpuinfo
  44. */
  45. const char bfin_board_name[] = "Bluetechnix CM BF533";
  46. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  47. /* all SPI peripherals info goes here */
  48. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  49. static struct mtd_partition bfin_spi_flash_partitions[] = {
  50. {
  51. .name = "bootloader",
  52. .size = 0x00020000,
  53. .offset = 0,
  54. .mask_flags = MTD_CAP_ROM
  55. }, {
  56. .name = "kernel",
  57. .size = 0xe0000,
  58. .offset = 0x20000
  59. }, {
  60. .name = "file system",
  61. .size = 0x700000,
  62. .offset = 0x00100000,
  63. }
  64. };
  65. static struct flash_platform_data bfin_spi_flash_data = {
  66. .name = "m25p80",
  67. .parts = bfin_spi_flash_partitions,
  68. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  69. .type = "m25p64",
  70. };
  71. /* SPI flash chip (m25p64) */
  72. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  73. .enable_dma = 0, /* use dma transfer with this chip*/
  74. .bits_per_word = 8,
  75. };
  76. #endif
  77. /* SPI ADC chip */
  78. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  79. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  80. .enable_dma = 1, /* use dma transfer with this chip*/
  81. .bits_per_word = 16,
  82. };
  83. #endif
  84. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  85. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  86. .enable_dma = 0,
  87. .bits_per_word = 16,
  88. };
  89. #endif
  90. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  91. static struct bfin5xx_spi_chip spi_mmc_chip_info = {
  92. .enable_dma = 1,
  93. .bits_per_word = 8,
  94. };
  95. #endif
  96. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  97. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  98. {
  99. /* the modalias must be the same as spi device driver name */
  100. .modalias = "m25p80", /* Name of spi_driver for this device */
  101. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  102. .bus_num = 0, /* Framework bus number */
  103. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  104. .platform_data = &bfin_spi_flash_data,
  105. .controller_data = &spi_flash_chip_info,
  106. .mode = SPI_MODE_3,
  107. },
  108. #endif
  109. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  110. {
  111. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  112. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  113. .bus_num = 0, /* Framework bus number */
  114. .chip_select = 2, /* Framework chip select. */
  115. .platform_data = NULL, /* No spi_driver specific config */
  116. .controller_data = &spi_adc_chip_info,
  117. },
  118. #endif
  119. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  120. {
  121. .modalias = "ad1836-spi",
  122. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  123. .bus_num = 0,
  124. .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
  125. .controller_data = &ad1836_spi_chip_info,
  126. },
  127. #endif
  128. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  129. {
  130. .modalias = "spi_mmc_dummy",
  131. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  132. .bus_num = 0,
  133. .chip_select = 0,
  134. .platform_data = NULL,
  135. .controller_data = &spi_mmc_chip_info,
  136. .mode = SPI_MODE_3,
  137. },
  138. {
  139. .modalias = "spi_mmc",
  140. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  141. .bus_num = 0,
  142. .chip_select = CONFIG_SPI_MMC_CS_CHAN,
  143. .platform_data = NULL,
  144. .controller_data = &spi_mmc_chip_info,
  145. .mode = SPI_MODE_3,
  146. },
  147. #endif
  148. };
  149. /* SPI (0) */
  150. static struct resource bfin_spi0_resource[] = {
  151. [0] = {
  152. .start = SPI0_REGBASE,
  153. .end = SPI0_REGBASE + 0xFF,
  154. .flags = IORESOURCE_MEM,
  155. },
  156. [1] = {
  157. .start = CH_SPI,
  158. .end = CH_SPI,
  159. .flags = IORESOURCE_IRQ,
  160. }
  161. };
  162. /* SPI controller data */
  163. static struct bfin5xx_spi_master bfin_spi0_info = {
  164. .num_chipselect = 8,
  165. .enable_dma = 1, /* master has the ability to do dma transfer */
  166. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  167. };
  168. static struct platform_device bfin_spi0_device = {
  169. .name = "bfin-spi",
  170. .id = 0, /* Bus number */
  171. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  172. .resource = bfin_spi0_resource,
  173. .dev = {
  174. .platform_data = &bfin_spi0_info, /* Passed to driver */
  175. },
  176. };
  177. #endif /* spi master and devices */
  178. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  179. static struct platform_device rtc_device = {
  180. .name = "rtc-bfin",
  181. .id = -1,
  182. };
  183. #endif
  184. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  185. static struct resource smc91x_resources[] = {
  186. {
  187. .start = 0x20200300,
  188. .end = 0x20200300 + 16,
  189. .flags = IORESOURCE_MEM,
  190. }, {
  191. .start = IRQ_PF0,
  192. .end = IRQ_PF0,
  193. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  194. },
  195. };
  196. static struct platform_device smc91x_device = {
  197. .name = "smc91x",
  198. .id = 0,
  199. .num_resources = ARRAY_SIZE(smc91x_resources),
  200. .resource = smc91x_resources,
  201. };
  202. #endif
  203. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  204. static struct resource bfin_uart_resources[] = {
  205. {
  206. .start = 0xFFC00400,
  207. .end = 0xFFC004FF,
  208. .flags = IORESOURCE_MEM,
  209. },
  210. };
  211. static struct platform_device bfin_uart_device = {
  212. .name = "bfin-uart",
  213. .id = 1,
  214. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  215. .resource = bfin_uart_resources,
  216. };
  217. #endif
  218. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  219. static struct resource bfin_sir_resources[] = {
  220. #ifdef CONFIG_BFIN_SIR0
  221. {
  222. .start = 0xFFC00400,
  223. .end = 0xFFC004FF,
  224. .flags = IORESOURCE_MEM,
  225. },
  226. #endif
  227. };
  228. static struct platform_device bfin_sir_device = {
  229. .name = "bfin_sir",
  230. .id = 0,
  231. .num_resources = ARRAY_SIZE(bfin_sir_resources),
  232. .resource = bfin_sir_resources,
  233. };
  234. #endif
  235. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  236. static struct platform_device bfin_sport0_uart_device = {
  237. .name = "bfin-sport-uart",
  238. .id = 0,
  239. };
  240. static struct platform_device bfin_sport1_uart_device = {
  241. .name = "bfin-sport-uart",
  242. .id = 1,
  243. };
  244. #endif
  245. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  246. static struct resource isp1362_hcd_resources[] = {
  247. {
  248. .start = 0x20308000,
  249. .end = 0x20308000,
  250. .flags = IORESOURCE_MEM,
  251. }, {
  252. .start = 0x20308004,
  253. .end = 0x20308004,
  254. .flags = IORESOURCE_MEM,
  255. }, {
  256. .start = IRQ_PF4,
  257. .end = IRQ_PF4,
  258. .flags = IORESOURCE_IRQ,
  259. },
  260. };
  261. static struct isp1362_platform_data isp1362_priv = {
  262. .sel15Kres = 1,
  263. .clknotstop = 0,
  264. .oc_enable = 0,
  265. .int_act_high = 0,
  266. .int_edge_triggered = 0,
  267. .remote_wakeup_connected = 0,
  268. .no_power_switching = 1,
  269. .power_switching_mode = 0,
  270. };
  271. static struct platform_device isp1362_hcd_device = {
  272. .name = "isp1362-hcd",
  273. .id = 0,
  274. .dev = {
  275. .platform_data = &isp1362_priv,
  276. },
  277. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  278. .resource = isp1362_hcd_resources,
  279. };
  280. #endif
  281. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  282. #define PATA_INT 38
  283. static struct pata_platform_info bfin_pata_platform_data = {
  284. .ioport_shift = 2,
  285. .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
  286. };
  287. static struct resource bfin_pata_resources[] = {
  288. {
  289. .start = 0x2030C000,
  290. .end = 0x2030C01F,
  291. .flags = IORESOURCE_MEM,
  292. },
  293. {
  294. .start = 0x2030D018,
  295. .end = 0x2030D01B,
  296. .flags = IORESOURCE_MEM,
  297. },
  298. {
  299. .start = PATA_INT,
  300. .end = PATA_INT,
  301. .flags = IORESOURCE_IRQ,
  302. },
  303. };
  304. static struct platform_device bfin_pata_device = {
  305. .name = "pata_platform",
  306. .id = -1,
  307. .num_resources = ARRAY_SIZE(bfin_pata_resources),
  308. .resource = bfin_pata_resources,
  309. .dev = {
  310. .platform_data = &bfin_pata_platform_data,
  311. }
  312. };
  313. #endif
  314. static const unsigned int cclk_vlev_datasheet[] =
  315. {
  316. VRPAIR(VLEV_085, 250000000),
  317. VRPAIR(VLEV_090, 376000000),
  318. VRPAIR(VLEV_095, 426000000),
  319. VRPAIR(VLEV_100, 426000000),
  320. VRPAIR(VLEV_105, 476000000),
  321. VRPAIR(VLEV_110, 476000000),
  322. VRPAIR(VLEV_115, 476000000),
  323. VRPAIR(VLEV_120, 600000000),
  324. VRPAIR(VLEV_125, 600000000),
  325. VRPAIR(VLEV_130, 600000000),
  326. };
  327. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  328. .tuple_tab = cclk_vlev_datasheet,
  329. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  330. .vr_settling_time = 25 /* us */,
  331. };
  332. static struct platform_device bfin_dpmc = {
  333. .name = "bfin dpmc",
  334. .dev = {
  335. .platform_data = &bfin_dmpc_vreg_data,
  336. },
  337. };
  338. static struct platform_device *cm_bf533_devices[] __initdata = {
  339. &bfin_dpmc,
  340. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  341. &bfin_uart_device,
  342. #endif
  343. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  344. &bfin_sir_device,
  345. #endif
  346. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  347. &bfin_sport0_uart_device,
  348. &bfin_sport1_uart_device,
  349. #endif
  350. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  351. &rtc_device,
  352. #endif
  353. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  354. &isp1362_hcd_device,
  355. #endif
  356. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  357. &smc91x_device,
  358. #endif
  359. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  360. &bfin_spi0_device,
  361. #endif
  362. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  363. &bfin_pata_device,
  364. #endif
  365. };
  366. static int __init cm_bf533_init(void)
  367. {
  368. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  369. platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
  370. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  371. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  372. #endif
  373. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  374. irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
  375. #endif
  376. return 0;
  377. }
  378. arch_initcall(cm_bf533_init);