mcdi.c 32 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "farch_regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. #define MCDI_RPC_TIMEOUT (10 * HZ)
  23. /* A reboot/assertion causes the MCDI status word to be set after the
  24. * command word is set or a REBOOT event is sent. If we notice a reboot
  25. * via these mechanisms then wait 10ms for the status word to be set. */
  26. #define MCDI_STATUS_DELAY_US 100
  27. #define MCDI_STATUS_DELAY_COUNT 100
  28. #define MCDI_STATUS_SLEEP_MS \
  29. (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000)
  30. #define SEQ_MASK \
  31. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  32. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  33. {
  34. EFX_BUG_ON_PARANOID(!efx->mcdi);
  35. return &efx->mcdi->iface;
  36. }
  37. int efx_mcdi_init(struct efx_nic *efx)
  38. {
  39. struct efx_mcdi_iface *mcdi;
  40. efx->mcdi = kzalloc(sizeof(*efx->mcdi), GFP_KERNEL);
  41. if (!efx->mcdi)
  42. return -ENOMEM;
  43. mcdi = efx_mcdi(efx);
  44. init_waitqueue_head(&mcdi->wq);
  45. spin_lock_init(&mcdi->iface_lock);
  46. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  47. mcdi->mode = MCDI_MODE_POLL;
  48. (void) efx_mcdi_poll_reboot(efx);
  49. /* Recover from a failed assertion before probing */
  50. return efx_mcdi_handle_assertion(efx);
  51. }
  52. void efx_mcdi_fini(struct efx_nic *efx)
  53. {
  54. BUG_ON(efx->mcdi &&
  55. atomic_read(&efx->mcdi->iface.state) != MCDI_STATE_QUIESCENT);
  56. kfree(efx->mcdi);
  57. }
  58. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  59. const efx_dword_t *inbuf, size_t inlen)
  60. {
  61. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  62. efx_dword_t hdr[2];
  63. size_t hdr_len;
  64. u32 xflags, seqno;
  65. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  66. seqno = mcdi->seqno & SEQ_MASK;
  67. xflags = 0;
  68. if (mcdi->mode == MCDI_MODE_EVENTS)
  69. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  70. if (efx->type->mcdi_max_ver == 1) {
  71. /* MCDI v1 */
  72. EFX_POPULATE_DWORD_6(hdr[0],
  73. MCDI_HEADER_RESPONSE, 0,
  74. MCDI_HEADER_RESYNC, 1,
  75. MCDI_HEADER_CODE, cmd,
  76. MCDI_HEADER_DATALEN, inlen,
  77. MCDI_HEADER_SEQ, seqno,
  78. MCDI_HEADER_XFLAGS, xflags);
  79. hdr_len = 4;
  80. } else {
  81. /* MCDI v2 */
  82. BUG_ON(inlen > MCDI_CTL_SDU_LEN_MAX_V2);
  83. EFX_POPULATE_DWORD_6(hdr[0],
  84. MCDI_HEADER_RESPONSE, 0,
  85. MCDI_HEADER_RESYNC, 1,
  86. MCDI_HEADER_CODE, MC_CMD_V2_EXTN,
  87. MCDI_HEADER_DATALEN, 0,
  88. MCDI_HEADER_SEQ, seqno,
  89. MCDI_HEADER_XFLAGS, xflags);
  90. EFX_POPULATE_DWORD_2(hdr[1],
  91. MC_CMD_V2_EXTN_IN_EXTENDED_CMD, cmd,
  92. MC_CMD_V2_EXTN_IN_ACTUAL_LEN, inlen);
  93. hdr_len = 8;
  94. }
  95. efx->type->mcdi_request(efx, hdr, hdr_len, inbuf, inlen);
  96. }
  97. static int efx_mcdi_errno(unsigned int mcdi_err)
  98. {
  99. switch (mcdi_err) {
  100. case 0:
  101. return 0;
  102. #define TRANSLATE_ERROR(name) \
  103. case MC_CMD_ERR_ ## name: \
  104. return -name;
  105. TRANSLATE_ERROR(EPERM);
  106. TRANSLATE_ERROR(ENOENT);
  107. TRANSLATE_ERROR(EINTR);
  108. TRANSLATE_ERROR(EAGAIN);
  109. TRANSLATE_ERROR(EACCES);
  110. TRANSLATE_ERROR(EBUSY);
  111. TRANSLATE_ERROR(EINVAL);
  112. TRANSLATE_ERROR(EDEADLK);
  113. TRANSLATE_ERROR(ENOSYS);
  114. TRANSLATE_ERROR(ETIME);
  115. TRANSLATE_ERROR(EALREADY);
  116. TRANSLATE_ERROR(ENOSPC);
  117. #undef TRANSLATE_ERROR
  118. case MC_CMD_ERR_ALLOC_FAIL:
  119. return -ENOBUFS;
  120. case MC_CMD_ERR_MAC_EXIST:
  121. return -EADDRINUSE;
  122. default:
  123. return -EPROTO;
  124. }
  125. }
  126. static void efx_mcdi_read_response_header(struct efx_nic *efx)
  127. {
  128. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  129. unsigned int respseq, respcmd, error;
  130. efx_dword_t hdr;
  131. efx->type->mcdi_read_response(efx, &hdr, 0, 4);
  132. respseq = EFX_DWORD_FIELD(hdr, MCDI_HEADER_SEQ);
  133. respcmd = EFX_DWORD_FIELD(hdr, MCDI_HEADER_CODE);
  134. error = EFX_DWORD_FIELD(hdr, MCDI_HEADER_ERROR);
  135. if (respcmd != MC_CMD_V2_EXTN) {
  136. mcdi->resp_hdr_len = 4;
  137. mcdi->resp_data_len = EFX_DWORD_FIELD(hdr, MCDI_HEADER_DATALEN);
  138. } else {
  139. efx->type->mcdi_read_response(efx, &hdr, 4, 4);
  140. mcdi->resp_hdr_len = 8;
  141. mcdi->resp_data_len =
  142. EFX_DWORD_FIELD(hdr, MC_CMD_V2_EXTN_IN_ACTUAL_LEN);
  143. }
  144. if (error && mcdi->resp_data_len == 0) {
  145. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  146. mcdi->resprc = -EIO;
  147. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  148. netif_err(efx, hw, efx->net_dev,
  149. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  150. respseq, mcdi->seqno);
  151. mcdi->resprc = -EIO;
  152. } else if (error) {
  153. efx->type->mcdi_read_response(efx, &hdr, mcdi->resp_hdr_len, 4);
  154. mcdi->resprc =
  155. efx_mcdi_errno(EFX_DWORD_FIELD(hdr, EFX_DWORD_0));
  156. } else {
  157. mcdi->resprc = 0;
  158. }
  159. }
  160. static int efx_mcdi_poll(struct efx_nic *efx)
  161. {
  162. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  163. unsigned long time, finish;
  164. unsigned int spins;
  165. int rc;
  166. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  167. rc = efx_mcdi_poll_reboot(efx);
  168. if (rc) {
  169. spin_lock_bh(&mcdi->iface_lock);
  170. mcdi->resprc = rc;
  171. mcdi->resp_hdr_len = 0;
  172. mcdi->resp_data_len = 0;
  173. spin_unlock_bh(&mcdi->iface_lock);
  174. return 0;
  175. }
  176. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  177. * because generally mcdi responses are fast. After that, back off
  178. * and poll once a jiffy (approximately)
  179. */
  180. spins = TICK_USEC;
  181. finish = jiffies + MCDI_RPC_TIMEOUT;
  182. while (1) {
  183. if (spins != 0) {
  184. --spins;
  185. udelay(1);
  186. } else {
  187. schedule_timeout_uninterruptible(1);
  188. }
  189. time = jiffies;
  190. rmb();
  191. if (efx->type->mcdi_poll_response(efx))
  192. break;
  193. if (time_after(time, finish))
  194. return -ETIMEDOUT;
  195. }
  196. spin_lock_bh(&mcdi->iface_lock);
  197. efx_mcdi_read_response_header(efx);
  198. spin_unlock_bh(&mcdi->iface_lock);
  199. /* Return rc=0 like wait_event_timeout() */
  200. return 0;
  201. }
  202. /* Test and clear MC-rebooted flag for this port/function; reset
  203. * software state as necessary.
  204. */
  205. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  206. {
  207. int rc;
  208. if (!efx->mcdi)
  209. return 0;
  210. rc = efx->type->mcdi_poll_reboot(efx);
  211. if (!rc)
  212. return 0;
  213. /* MAC statistics have been cleared on the NIC; clear our copy
  214. * so that efx_update_diff_stat() can continue to work.
  215. */
  216. memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
  217. return rc;
  218. }
  219. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  220. {
  221. /* Wait until the interface becomes QUIESCENT and we win the race
  222. * to mark it RUNNING. */
  223. wait_event(mcdi->wq,
  224. atomic_cmpxchg(&mcdi->state,
  225. MCDI_STATE_QUIESCENT,
  226. MCDI_STATE_RUNNING)
  227. == MCDI_STATE_QUIESCENT);
  228. }
  229. static int efx_mcdi_await_completion(struct efx_nic *efx)
  230. {
  231. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  232. if (wait_event_timeout(
  233. mcdi->wq,
  234. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  235. MCDI_RPC_TIMEOUT) == 0)
  236. return -ETIMEDOUT;
  237. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  238. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  239. * completed the request first, then we'll just end up completing the
  240. * request again, which is safe.
  241. *
  242. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  243. * wait_event_timeout() implicitly provides.
  244. */
  245. if (mcdi->mode == MCDI_MODE_POLL)
  246. return efx_mcdi_poll(efx);
  247. return 0;
  248. }
  249. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  250. {
  251. /* If the interface is RUNNING, then move to COMPLETED and wake any
  252. * waiters. If the interface isn't in RUNNING then we've received a
  253. * duplicate completion after we've already transitioned back to
  254. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  255. * have failed the seqno check].
  256. */
  257. if (atomic_cmpxchg(&mcdi->state,
  258. MCDI_STATE_RUNNING,
  259. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  260. wake_up(&mcdi->wq);
  261. return true;
  262. }
  263. return false;
  264. }
  265. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  266. {
  267. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  268. wake_up(&mcdi->wq);
  269. }
  270. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  271. unsigned int datalen, unsigned int mcdi_err)
  272. {
  273. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  274. bool wake = false;
  275. spin_lock(&mcdi->iface_lock);
  276. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  277. if (mcdi->credits)
  278. /* The request has been cancelled */
  279. --mcdi->credits;
  280. else
  281. netif_err(efx, hw, efx->net_dev,
  282. "MC response mismatch tx seq 0x%x rx "
  283. "seq 0x%x\n", seqno, mcdi->seqno);
  284. } else {
  285. if (efx->type->mcdi_max_ver >= 2) {
  286. /* MCDI v2 responses don't fit in an event */
  287. efx_mcdi_read_response_header(efx);
  288. } else {
  289. mcdi->resprc = efx_mcdi_errno(mcdi_err);
  290. mcdi->resp_hdr_len = 4;
  291. mcdi->resp_data_len = datalen;
  292. }
  293. wake = true;
  294. }
  295. spin_unlock(&mcdi->iface_lock);
  296. if (wake)
  297. efx_mcdi_complete(mcdi);
  298. }
  299. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  300. const efx_dword_t *inbuf, size_t inlen,
  301. efx_dword_t *outbuf, size_t outlen,
  302. size_t *outlen_actual)
  303. {
  304. int rc;
  305. rc = efx_mcdi_rpc_start(efx, cmd, inbuf, inlen);
  306. if (rc)
  307. return rc;
  308. return efx_mcdi_rpc_finish(efx, cmd, inlen,
  309. outbuf, outlen, outlen_actual);
  310. }
  311. int efx_mcdi_rpc_start(struct efx_nic *efx, unsigned cmd,
  312. const efx_dword_t *inbuf, size_t inlen)
  313. {
  314. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  315. if (efx->type->mcdi_max_ver < 0 ||
  316. (efx->type->mcdi_max_ver < 2 &&
  317. cmd > MC_CMD_CMD_SPACE_ESCAPE_7))
  318. return -EINVAL;
  319. if (inlen > MCDI_CTL_SDU_LEN_MAX_V2 ||
  320. (efx->type->mcdi_max_ver < 2 &&
  321. inlen > MCDI_CTL_SDU_LEN_MAX_V1))
  322. return -EMSGSIZE;
  323. efx_mcdi_acquire(mcdi);
  324. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  325. spin_lock_bh(&mcdi->iface_lock);
  326. ++mcdi->seqno;
  327. spin_unlock_bh(&mcdi->iface_lock);
  328. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  329. return 0;
  330. }
  331. int efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen,
  332. efx_dword_t *outbuf, size_t outlen,
  333. size_t *outlen_actual)
  334. {
  335. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  336. int rc;
  337. if (mcdi->mode == MCDI_MODE_POLL)
  338. rc = efx_mcdi_poll(efx);
  339. else
  340. rc = efx_mcdi_await_completion(efx);
  341. if (rc != 0) {
  342. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  343. * and completing a request we've just cancelled, by ensuring
  344. * that the seqno check therein fails.
  345. */
  346. spin_lock_bh(&mcdi->iface_lock);
  347. ++mcdi->seqno;
  348. ++mcdi->credits;
  349. spin_unlock_bh(&mcdi->iface_lock);
  350. netif_err(efx, hw, efx->net_dev,
  351. "MC command 0x%x inlen %d mode %d timed out\n",
  352. cmd, (int)inlen, mcdi->mode);
  353. } else {
  354. size_t hdr_len, data_len;
  355. /* At the very least we need a memory barrier here to ensure
  356. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  357. * a spurious efx_mcdi_ev_cpl() running concurrently by
  358. * acquiring the iface_lock. */
  359. spin_lock_bh(&mcdi->iface_lock);
  360. rc = mcdi->resprc;
  361. hdr_len = mcdi->resp_hdr_len;
  362. data_len = mcdi->resp_data_len;
  363. spin_unlock_bh(&mcdi->iface_lock);
  364. BUG_ON(rc > 0);
  365. if (rc == 0) {
  366. efx->type->mcdi_read_response(efx, outbuf, hdr_len,
  367. min(outlen, data_len));
  368. if (outlen_actual != NULL)
  369. *outlen_actual = data_len;
  370. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  371. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  372. else if (rc == -EIO || rc == -EINTR) {
  373. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  374. -rc);
  375. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  376. } else
  377. netif_dbg(efx, hw, efx->net_dev,
  378. "MC command 0x%x inlen %d failed rc=%d\n",
  379. cmd, (int)inlen, -rc);
  380. if (rc == -EIO || rc == -EINTR) {
  381. msleep(MCDI_STATUS_SLEEP_MS);
  382. efx_mcdi_poll_reboot(efx);
  383. }
  384. }
  385. efx_mcdi_release(mcdi);
  386. return rc;
  387. }
  388. void efx_mcdi_mode_poll(struct efx_nic *efx)
  389. {
  390. struct efx_mcdi_iface *mcdi;
  391. if (!efx->mcdi)
  392. return;
  393. mcdi = efx_mcdi(efx);
  394. if (mcdi->mode == MCDI_MODE_POLL)
  395. return;
  396. /* We can switch from event completion to polled completion, because
  397. * mcdi requests are always completed in shared memory. We do this by
  398. * switching the mode to POLL'd then completing the request.
  399. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  400. *
  401. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  402. * which efx_mcdi_complete() provides for us.
  403. */
  404. mcdi->mode = MCDI_MODE_POLL;
  405. efx_mcdi_complete(mcdi);
  406. }
  407. void efx_mcdi_mode_event(struct efx_nic *efx)
  408. {
  409. struct efx_mcdi_iface *mcdi;
  410. if (!efx->mcdi)
  411. return;
  412. mcdi = efx_mcdi(efx);
  413. if (mcdi->mode == MCDI_MODE_EVENTS)
  414. return;
  415. /* We can't switch from polled to event completion in the middle of a
  416. * request, because the completion method is specified in the request.
  417. * So acquire the interface to serialise the requestors. We don't need
  418. * to acquire the iface_lock to change the mode here, but we do need a
  419. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  420. * efx_mcdi_acquire() provides.
  421. */
  422. efx_mcdi_acquire(mcdi);
  423. mcdi->mode = MCDI_MODE_EVENTS;
  424. efx_mcdi_release(mcdi);
  425. }
  426. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  427. {
  428. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  429. /* If there is an outstanding MCDI request, it has been terminated
  430. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  431. * in polled mode, then do nothing because the MC reboot handler will
  432. * set the header correctly. However, if the mcdi interface is waiting
  433. * for a CMDDONE event it won't receive it [and since all MCDI events
  434. * are sent to the same queue, we can't be racing with
  435. * efx_mcdi_ev_cpl()]
  436. *
  437. * There's a race here with efx_mcdi_rpc(), because we might receive
  438. * a REBOOT event *before* the request has been copied out. In polled
  439. * mode (during startup) this is irrelevant, because efx_mcdi_complete()
  440. * is ignored. In event mode, this condition is just an edge-case of
  441. * receiving a REBOOT event after posting the MCDI request. Did the mc
  442. * reboot before or after the copyout? The best we can do always is
  443. * just return failure.
  444. */
  445. spin_lock(&mcdi->iface_lock);
  446. if (efx_mcdi_complete(mcdi)) {
  447. if (mcdi->mode == MCDI_MODE_EVENTS) {
  448. mcdi->resprc = rc;
  449. mcdi->resp_hdr_len = 0;
  450. mcdi->resp_data_len = 0;
  451. ++mcdi->credits;
  452. }
  453. } else {
  454. int count;
  455. /* Nobody was waiting for an MCDI request, so trigger a reset */
  456. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  457. /* Consume the status word since efx_mcdi_rpc_finish() won't */
  458. for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) {
  459. if (efx_mcdi_poll_reboot(efx))
  460. break;
  461. udelay(MCDI_STATUS_DELAY_US);
  462. }
  463. }
  464. spin_unlock(&mcdi->iface_lock);
  465. }
  466. /* Called from falcon_process_eventq for MCDI events */
  467. void efx_mcdi_process_event(struct efx_channel *channel,
  468. efx_qword_t *event)
  469. {
  470. struct efx_nic *efx = channel->efx;
  471. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  472. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  473. switch (code) {
  474. case MCDI_EVENT_CODE_BADSSERT:
  475. netif_err(efx, hw, efx->net_dev,
  476. "MC watchdog or assertion failure at 0x%x\n", data);
  477. efx_mcdi_ev_death(efx, -EINTR);
  478. break;
  479. case MCDI_EVENT_CODE_PMNOTICE:
  480. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  481. break;
  482. case MCDI_EVENT_CODE_CMDDONE:
  483. efx_mcdi_ev_cpl(efx,
  484. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  485. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  486. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  487. break;
  488. case MCDI_EVENT_CODE_LINKCHANGE:
  489. efx_mcdi_process_link_change(efx, event);
  490. break;
  491. case MCDI_EVENT_CODE_SENSOREVT:
  492. efx_mcdi_sensor_event(efx, event);
  493. break;
  494. case MCDI_EVENT_CODE_SCHEDERR:
  495. netif_info(efx, hw, efx->net_dev,
  496. "MC Scheduler error address=0x%x\n", data);
  497. break;
  498. case MCDI_EVENT_CODE_REBOOT:
  499. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  500. efx_mcdi_ev_death(efx, -EIO);
  501. break;
  502. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  503. /* MAC stats are gather lazily. We can ignore this. */
  504. break;
  505. case MCDI_EVENT_CODE_FLR:
  506. efx_sriov_flr(efx, MCDI_EVENT_FIELD(*event, FLR_VF));
  507. break;
  508. case MCDI_EVENT_CODE_PTP_RX:
  509. case MCDI_EVENT_CODE_PTP_FAULT:
  510. case MCDI_EVENT_CODE_PTP_PPS:
  511. efx_ptp_event(efx, event);
  512. break;
  513. default:
  514. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  515. code);
  516. }
  517. }
  518. /**************************************************************************
  519. *
  520. * Specific request functions
  521. *
  522. **************************************************************************
  523. */
  524. void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
  525. {
  526. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_VERSION_OUT_LEN);
  527. size_t outlength;
  528. const __le16 *ver_words;
  529. int rc;
  530. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  531. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  532. outbuf, sizeof(outbuf), &outlength);
  533. if (rc)
  534. goto fail;
  535. if (outlength < MC_CMD_GET_VERSION_OUT_LEN) {
  536. rc = -EIO;
  537. goto fail;
  538. }
  539. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  540. snprintf(buf, len, "%u.%u.%u.%u",
  541. le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
  542. le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
  543. return;
  544. fail:
  545. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  546. buf[0] = 0;
  547. }
  548. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  549. bool *was_attached)
  550. {
  551. MCDI_DECLARE_BUF(inbuf, MC_CMD_DRV_ATTACH_IN_LEN);
  552. MCDI_DECLARE_BUF(outbuf, MC_CMD_DRV_ATTACH_OUT_LEN);
  553. size_t outlen;
  554. int rc;
  555. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  556. driver_operating ? 1 : 0);
  557. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  558. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_FIRMWARE_ID, MC_CMD_FW_LOW_LATENCY);
  559. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  560. outbuf, sizeof(outbuf), &outlen);
  561. if (rc)
  562. goto fail;
  563. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  564. rc = -EIO;
  565. goto fail;
  566. }
  567. if (was_attached != NULL)
  568. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  569. return 0;
  570. fail:
  571. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  572. return rc;
  573. }
  574. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  575. u16 *fw_subtype_list, u32 *capabilities)
  576. {
  577. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_BOARD_CFG_OUT_LENMAX);
  578. size_t outlen, i;
  579. int port_num = efx_port_num(efx);
  580. int rc;
  581. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  582. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  583. outbuf, sizeof(outbuf), &outlen);
  584. if (rc)
  585. goto fail;
  586. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
  587. rc = -EIO;
  588. goto fail;
  589. }
  590. if (mac_address)
  591. memcpy(mac_address,
  592. port_num ?
  593. MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1) :
  594. MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0),
  595. ETH_ALEN);
  596. if (fw_subtype_list) {
  597. for (i = 0;
  598. i < MCDI_VAR_ARRAY_LEN(outlen,
  599. GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST);
  600. i++)
  601. fw_subtype_list[i] = MCDI_ARRAY_WORD(
  602. outbuf, GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST, i);
  603. for (; i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM; i++)
  604. fw_subtype_list[i] = 0;
  605. }
  606. if (capabilities) {
  607. if (port_num)
  608. *capabilities = MCDI_DWORD(outbuf,
  609. GET_BOARD_CFG_OUT_CAPABILITIES_PORT1);
  610. else
  611. *capabilities = MCDI_DWORD(outbuf,
  612. GET_BOARD_CFG_OUT_CAPABILITIES_PORT0);
  613. }
  614. return 0;
  615. fail:
  616. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  617. __func__, rc, (int)outlen);
  618. return rc;
  619. }
  620. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  621. {
  622. MCDI_DECLARE_BUF(inbuf, MC_CMD_LOG_CTRL_IN_LEN);
  623. u32 dest = 0;
  624. int rc;
  625. if (uart)
  626. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  627. if (evq)
  628. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  629. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  630. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  631. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  632. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  633. NULL, 0, NULL);
  634. if (rc)
  635. goto fail;
  636. return 0;
  637. fail:
  638. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  639. return rc;
  640. }
  641. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  642. {
  643. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TYPES_OUT_LEN);
  644. size_t outlen;
  645. int rc;
  646. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  647. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  648. outbuf, sizeof(outbuf), &outlen);
  649. if (rc)
  650. goto fail;
  651. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  652. rc = -EIO;
  653. goto fail;
  654. }
  655. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  656. return 0;
  657. fail:
  658. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  659. __func__, rc);
  660. return rc;
  661. }
  662. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  663. size_t *size_out, size_t *erase_size_out,
  664. bool *protected_out)
  665. {
  666. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_INFO_IN_LEN);
  667. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_INFO_OUT_LEN);
  668. size_t outlen;
  669. int rc;
  670. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  671. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  672. outbuf, sizeof(outbuf), &outlen);
  673. if (rc)
  674. goto fail;
  675. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  676. rc = -EIO;
  677. goto fail;
  678. }
  679. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  680. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  681. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  682. (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN));
  683. return 0;
  684. fail:
  685. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  686. return rc;
  687. }
  688. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  689. {
  690. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_START_IN_LEN);
  691. int rc;
  692. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  693. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  694. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  695. NULL, 0, NULL);
  696. if (rc)
  697. goto fail;
  698. return 0;
  699. fail:
  700. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  701. return rc;
  702. }
  703. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  704. loff_t offset, u8 *buffer, size_t length)
  705. {
  706. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_READ_IN_LEN);
  707. MCDI_DECLARE_BUF(outbuf,
  708. MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX));
  709. size_t outlen;
  710. int rc;
  711. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  712. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  713. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  714. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  715. outbuf, sizeof(outbuf), &outlen);
  716. if (rc)
  717. goto fail;
  718. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  719. return 0;
  720. fail:
  721. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  722. return rc;
  723. }
  724. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  725. loff_t offset, const u8 *buffer, size_t length)
  726. {
  727. MCDI_DECLARE_BUF(inbuf,
  728. MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX));
  729. int rc;
  730. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  731. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  732. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  733. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  734. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  735. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  736. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  737. NULL, 0, NULL);
  738. if (rc)
  739. goto fail;
  740. return 0;
  741. fail:
  742. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  743. return rc;
  744. }
  745. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  746. loff_t offset, size_t length)
  747. {
  748. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_ERASE_IN_LEN);
  749. int rc;
  750. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  751. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  752. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  753. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  754. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  755. NULL, 0, NULL);
  756. if (rc)
  757. goto fail;
  758. return 0;
  759. fail:
  760. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  761. return rc;
  762. }
  763. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  764. {
  765. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN);
  766. int rc;
  767. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  768. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  769. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  770. NULL, 0, NULL);
  771. if (rc)
  772. goto fail;
  773. return 0;
  774. fail:
  775. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  776. return rc;
  777. }
  778. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  779. {
  780. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_TEST_IN_LEN);
  781. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TEST_OUT_LEN);
  782. int rc;
  783. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  784. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  785. outbuf, sizeof(outbuf), NULL);
  786. if (rc)
  787. return rc;
  788. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  789. case MC_CMD_NVRAM_TEST_PASS:
  790. case MC_CMD_NVRAM_TEST_NOTSUPP:
  791. return 0;
  792. default:
  793. return -EIO;
  794. }
  795. }
  796. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  797. {
  798. u32 nvram_types;
  799. unsigned int type;
  800. int rc;
  801. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  802. if (rc)
  803. goto fail1;
  804. type = 0;
  805. while (nvram_types != 0) {
  806. if (nvram_types & 1) {
  807. rc = efx_mcdi_nvram_test(efx, type);
  808. if (rc)
  809. goto fail2;
  810. }
  811. type++;
  812. nvram_types >>= 1;
  813. }
  814. return 0;
  815. fail2:
  816. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  817. __func__, type);
  818. fail1:
  819. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  820. return rc;
  821. }
  822. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  823. {
  824. MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_ASSERTS_IN_LEN);
  825. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_ASSERTS_OUT_LEN);
  826. unsigned int flags, index;
  827. const char *reason;
  828. size_t outlen;
  829. int retry;
  830. int rc;
  831. /* Attempt to read any stored assertion state before we reboot
  832. * the mcfw out of the assertion handler. Retry twice, once
  833. * because a boot-time assertion might cause this command to fail
  834. * with EINTR. And once again because GET_ASSERTS can race with
  835. * MC_CMD_REBOOT running on the other port. */
  836. retry = 2;
  837. do {
  838. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  839. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  840. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  841. outbuf, sizeof(outbuf), &outlen);
  842. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  843. if (rc)
  844. return rc;
  845. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  846. return -EIO;
  847. /* Print out any recorded assertion state */
  848. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  849. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  850. return 0;
  851. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  852. ? "system-level assertion"
  853. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  854. ? "thread-level assertion"
  855. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  856. ? "watchdog reset"
  857. : "unknown assertion";
  858. netif_err(efx, hw, efx->net_dev,
  859. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  860. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  861. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  862. /* Print out the registers */
  863. for (index = 0;
  864. index < MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM;
  865. index++)
  866. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n",
  867. 1 + index,
  868. MCDI_ARRAY_DWORD(outbuf, GET_ASSERTS_OUT_GP_REGS_OFFS,
  869. index));
  870. return 0;
  871. }
  872. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  873. {
  874. MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN);
  875. /* If the MC is running debug firmware, it might now be
  876. * waiting for a debugger to attach, but we just want it to
  877. * reboot. We set a flag that makes the command a no-op if it
  878. * has already done so. We don't know what return code to
  879. * expect (0 or -EIO), so ignore it.
  880. */
  881. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  882. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  883. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  884. (void) efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  885. NULL, 0, NULL);
  886. }
  887. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  888. {
  889. int rc;
  890. rc = efx_mcdi_read_assertion(efx);
  891. if (rc)
  892. return rc;
  893. efx_mcdi_exit_assertion(efx);
  894. return 0;
  895. }
  896. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  897. {
  898. MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_ID_LED_IN_LEN);
  899. int rc;
  900. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  901. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  902. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  903. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  904. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  905. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  906. NULL, 0, NULL);
  907. if (rc)
  908. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  909. __func__, rc);
  910. }
  911. static int efx_mcdi_reset_port(struct efx_nic *efx)
  912. {
  913. int rc = efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, NULL, 0, NULL, 0, NULL);
  914. if (rc)
  915. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  916. __func__, rc);
  917. return rc;
  918. }
  919. static int efx_mcdi_reset_mc(struct efx_nic *efx)
  920. {
  921. MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN);
  922. int rc;
  923. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  924. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  925. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  926. NULL, 0, NULL);
  927. /* White is black, and up is down */
  928. if (rc == -EIO)
  929. return 0;
  930. if (rc == 0)
  931. rc = -EIO;
  932. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  933. return rc;
  934. }
  935. enum reset_type efx_mcdi_map_reset_reason(enum reset_type reason)
  936. {
  937. return RESET_TYPE_RECOVER_OR_ALL;
  938. }
  939. int efx_mcdi_reset(struct efx_nic *efx, enum reset_type method)
  940. {
  941. int rc;
  942. /* Recover from a failed assertion pre-reset */
  943. rc = efx_mcdi_handle_assertion(efx);
  944. if (rc)
  945. return rc;
  946. if (method == RESET_TYPE_WORLD)
  947. return efx_mcdi_reset_mc(efx);
  948. else
  949. return efx_mcdi_reset_port(efx);
  950. }
  951. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  952. const u8 *mac, int *id_out)
  953. {
  954. MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_SET_IN_LEN);
  955. MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_SET_OUT_LEN);
  956. size_t outlen;
  957. int rc;
  958. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  959. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  960. MC_CMD_FILTER_MODE_SIMPLE);
  961. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  962. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  963. outbuf, sizeof(outbuf), &outlen);
  964. if (rc)
  965. goto fail;
  966. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  967. rc = -EIO;
  968. goto fail;
  969. }
  970. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  971. return 0;
  972. fail:
  973. *id_out = -1;
  974. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  975. return rc;
  976. }
  977. int
  978. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  979. {
  980. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  981. }
  982. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  983. {
  984. MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_GET_OUT_LEN);
  985. size_t outlen;
  986. int rc;
  987. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  988. outbuf, sizeof(outbuf), &outlen);
  989. if (rc)
  990. goto fail;
  991. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  992. rc = -EIO;
  993. goto fail;
  994. }
  995. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  996. return 0;
  997. fail:
  998. *id_out = -1;
  999. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1000. return rc;
  1001. }
  1002. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  1003. {
  1004. MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_REMOVE_IN_LEN);
  1005. int rc;
  1006. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  1007. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  1008. NULL, 0, NULL);
  1009. if (rc)
  1010. goto fail;
  1011. return 0;
  1012. fail:
  1013. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1014. return rc;
  1015. }
  1016. int efx_mcdi_flush_rxqs(struct efx_nic *efx)
  1017. {
  1018. struct efx_channel *channel;
  1019. struct efx_rx_queue *rx_queue;
  1020. MCDI_DECLARE_BUF(inbuf,
  1021. MC_CMD_FLUSH_RX_QUEUES_IN_LEN(EFX_MAX_CHANNELS));
  1022. int rc, count;
  1023. BUILD_BUG_ON(EFX_MAX_CHANNELS >
  1024. MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
  1025. count = 0;
  1026. efx_for_each_channel(channel, efx) {
  1027. efx_for_each_channel_rx_queue(rx_queue, channel) {
  1028. if (rx_queue->flush_pending) {
  1029. rx_queue->flush_pending = false;
  1030. atomic_dec(&efx->rxq_flush_pending);
  1031. MCDI_SET_ARRAY_DWORD(
  1032. inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
  1033. count, efx_rx_queue_index(rx_queue));
  1034. count++;
  1035. }
  1036. }
  1037. }
  1038. rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf,
  1039. MC_CMD_FLUSH_RX_QUEUES_IN_LEN(count), NULL, 0, NULL);
  1040. WARN_ON(rc < 0);
  1041. return rc;
  1042. }
  1043. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  1044. {
  1045. int rc;
  1046. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  1047. if (rc)
  1048. goto fail;
  1049. return 0;
  1050. fail:
  1051. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1052. return rc;
  1053. }