qlcnic_ctx.c 35 KB

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  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include "qlcnic.h"
  8. static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
  9. {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
  10. {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  11. {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
  12. {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  13. {QLCNIC_CMD_INTRPT_TEST, 4, 1},
  14. {QLCNIC_CMD_SET_MTU, 4, 1},
  15. {QLCNIC_CMD_READ_PHY, 4, 2},
  16. {QLCNIC_CMD_WRITE_PHY, 5, 1},
  17. {QLCNIC_CMD_READ_HW_REG, 4, 1},
  18. {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  19. {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  20. {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  21. {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  22. {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  23. {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
  24. {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
  25. {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
  26. {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  27. {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  28. {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  29. {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  30. {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  31. {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
  32. {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  33. {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  34. {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  35. {QLCNIC_CMD_TEMP_SIZE, 4, 4},
  36. {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
  37. {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
  38. {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
  39. };
  40. static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
  41. {
  42. return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
  43. (0xcafe << 16);
  44. }
  45. /* Allocate mailbox registers */
  46. int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
  47. struct qlcnic_adapter *adapter, u32 type)
  48. {
  49. int i, size;
  50. const struct qlcnic_mailbox_metadata *mbx_tbl;
  51. mbx_tbl = qlcnic_mbx_tbl;
  52. size = ARRAY_SIZE(qlcnic_mbx_tbl);
  53. for (i = 0; i < size; i++) {
  54. if (type == mbx_tbl[i].cmd) {
  55. mbx->req.num = mbx_tbl[i].in_args;
  56. mbx->rsp.num = mbx_tbl[i].out_args;
  57. mbx->req.arg = kcalloc(mbx->req.num,
  58. sizeof(u32), GFP_ATOMIC);
  59. if (!mbx->req.arg)
  60. return -ENOMEM;
  61. mbx->rsp.arg = kcalloc(mbx->rsp.num,
  62. sizeof(u32), GFP_ATOMIC);
  63. if (!mbx->rsp.arg) {
  64. kfree(mbx->req.arg);
  65. mbx->req.arg = NULL;
  66. return -ENOMEM;
  67. }
  68. memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
  69. memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
  70. mbx->req.arg[0] = type;
  71. break;
  72. }
  73. }
  74. return 0;
  75. }
  76. /* Free up mailbox registers */
  77. void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
  78. {
  79. kfree(cmd->req.arg);
  80. cmd->req.arg = NULL;
  81. kfree(cmd->rsp.arg);
  82. cmd->rsp.arg = NULL;
  83. }
  84. static int qlcnic_is_valid_nic_func(struct qlcnic_adapter *adapter, u8 pci_func)
  85. {
  86. int i;
  87. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  88. if (adapter->npars[i].pci_func == pci_func)
  89. return i;
  90. }
  91. return -1;
  92. }
  93. static u32
  94. qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
  95. {
  96. u32 rsp;
  97. int timeout = 0, err = 0;
  98. do {
  99. /* give atleast 1ms for firmware to respond */
  100. mdelay(1);
  101. if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
  102. return QLCNIC_CDRP_RSP_TIMEOUT;
  103. rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET, &err);
  104. } while (!QLCNIC_CDRP_IS_RSP(rsp));
  105. return rsp;
  106. }
  107. int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
  108. struct qlcnic_cmd_args *cmd)
  109. {
  110. int i, err = 0;
  111. u32 rsp;
  112. u32 signature;
  113. struct pci_dev *pdev = adapter->pdev;
  114. struct qlcnic_hardware_context *ahw = adapter->ahw;
  115. const char *fmt;
  116. signature = qlcnic_get_cmd_signature(ahw);
  117. /* Acquire semaphore before accessing CRB */
  118. if (qlcnic_api_lock(adapter)) {
  119. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  120. return cmd->rsp.arg[0];
  121. }
  122. QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
  123. for (i = 1; i < QLCNIC_CDRP_MAX_ARGS; i++)
  124. QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
  125. QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
  126. QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
  127. rsp = qlcnic_poll_rsp(adapter);
  128. if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
  129. dev_err(&pdev->dev, "card response timeout.\n");
  130. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  131. } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
  132. cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1), &err);
  133. switch (cmd->rsp.arg[0]) {
  134. case QLCNIC_RCODE_INVALID_ARGS:
  135. fmt = "CDRP invalid args: [%d]\n";
  136. break;
  137. case QLCNIC_RCODE_NOT_SUPPORTED:
  138. case QLCNIC_RCODE_NOT_IMPL:
  139. fmt = "CDRP command not supported: [%d]\n";
  140. break;
  141. case QLCNIC_RCODE_NOT_PERMITTED:
  142. fmt = "CDRP requested action not permitted: [%d]\n";
  143. break;
  144. case QLCNIC_RCODE_INVALID:
  145. fmt = "CDRP invalid or unknown cmd received: [%d]\n";
  146. break;
  147. case QLCNIC_RCODE_TIMEOUT:
  148. fmt = "CDRP command timeout: [%d]\n";
  149. break;
  150. default:
  151. fmt = "CDRP command failed: [%d]\n";
  152. break;
  153. }
  154. dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
  155. } else if (rsp == QLCNIC_CDRP_RSP_OK)
  156. cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
  157. for (i = 1; i < cmd->rsp.num; i++)
  158. cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i), &err);
  159. /* Release semaphore */
  160. qlcnic_api_unlock(adapter);
  161. return cmd->rsp.arg[0];
  162. }
  163. int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
  164. {
  165. struct qlcnic_cmd_args cmd;
  166. u32 arg1, arg2, arg3;
  167. char drv_string[12];
  168. int err = 0;
  169. memset(drv_string, 0, sizeof(drv_string));
  170. snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
  171. _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
  172. _QLCNIC_LINUX_SUBVERSION);
  173. err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
  174. if (err)
  175. return err;
  176. memcpy(&arg1, drv_string, sizeof(u32));
  177. memcpy(&arg2, drv_string + 4, sizeof(u32));
  178. memcpy(&arg3, drv_string + 8, sizeof(u32));
  179. cmd.req.arg[1] = arg1;
  180. cmd.req.arg[2] = arg2;
  181. cmd.req.arg[3] = arg3;
  182. err = qlcnic_issue_cmd(adapter, &cmd);
  183. if (err) {
  184. dev_info(&adapter->pdev->dev,
  185. "Failed to set driver version in firmware\n");
  186. err = -EIO;
  187. }
  188. qlcnic_free_mbx_args(&cmd);
  189. return err;
  190. }
  191. int
  192. qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
  193. {
  194. int err = 0;
  195. struct qlcnic_cmd_args cmd;
  196. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  197. if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
  198. return err;
  199. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
  200. if (err)
  201. return err;
  202. cmd.req.arg[1] = recv_ctx->context_id;
  203. cmd.req.arg[2] = mtu;
  204. err = qlcnic_issue_cmd(adapter, &cmd);
  205. if (err) {
  206. dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
  207. err = -EIO;
  208. }
  209. qlcnic_free_mbx_args(&cmd);
  210. return err;
  211. }
  212. int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
  213. {
  214. void *addr;
  215. struct qlcnic_hostrq_rx_ctx *prq;
  216. struct qlcnic_cardrsp_rx_ctx *prsp;
  217. struct qlcnic_hostrq_rds_ring *prq_rds;
  218. struct qlcnic_hostrq_sds_ring *prq_sds;
  219. struct qlcnic_cardrsp_rds_ring *prsp_rds;
  220. struct qlcnic_cardrsp_sds_ring *prsp_sds;
  221. struct qlcnic_host_rds_ring *rds_ring;
  222. struct qlcnic_host_sds_ring *sds_ring;
  223. struct qlcnic_cmd_args cmd;
  224. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  225. u64 phys_addr;
  226. u8 i, nrds_rings, nsds_rings;
  227. u16 temp_u16;
  228. size_t rq_size, rsp_size;
  229. u32 cap, reg, val, reg2;
  230. int err;
  231. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  232. nrds_rings = adapter->max_rds_rings;
  233. nsds_rings = adapter->max_sds_rings;
  234. rq_size =
  235. SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
  236. nsds_rings);
  237. rsp_size =
  238. SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
  239. nsds_rings);
  240. addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  241. &hostrq_phys_addr, GFP_KERNEL);
  242. if (addr == NULL)
  243. return -ENOMEM;
  244. prq = addr;
  245. addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  246. &cardrsp_phys_addr, GFP_KERNEL);
  247. if (addr == NULL) {
  248. err = -ENOMEM;
  249. goto out_free_rq;
  250. }
  251. prsp = addr;
  252. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  253. cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
  254. | QLCNIC_CAP0_VALIDOFF);
  255. cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
  256. temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
  257. prq->valid_field_offset = cpu_to_le16(temp_u16);
  258. prq->txrx_sds_binding = nsds_rings - 1;
  259. prq->capabilities[0] = cpu_to_le32(cap);
  260. prq->host_int_crb_mode =
  261. cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
  262. prq->host_rds_crb_mode =
  263. cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE);
  264. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  265. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  266. prq->rds_ring_offset = 0;
  267. val = le32_to_cpu(prq->rds_ring_offset) +
  268. (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
  269. prq->sds_ring_offset = cpu_to_le32(val);
  270. prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
  271. le32_to_cpu(prq->rds_ring_offset));
  272. for (i = 0; i < nrds_rings; i++) {
  273. rds_ring = &recv_ctx->rds_rings[i];
  274. rds_ring->producer = 0;
  275. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  276. prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
  277. prq_rds[i].ring_kind = cpu_to_le32(i);
  278. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  279. }
  280. prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
  281. le32_to_cpu(prq->sds_ring_offset));
  282. for (i = 0; i < nsds_rings; i++) {
  283. sds_ring = &recv_ctx->sds_rings[i];
  284. sds_ring->consumer = 0;
  285. memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
  286. prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
  287. prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
  288. prq_sds[i].msi_index = cpu_to_le16(i);
  289. }
  290. phys_addr = hostrq_phys_addr;
  291. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
  292. if (err)
  293. goto out_free_rsp;
  294. cmd.req.arg[1] = MSD(phys_addr);
  295. cmd.req.arg[2] = LSD(phys_addr);
  296. cmd.req.arg[3] = rq_size;
  297. err = qlcnic_issue_cmd(adapter, &cmd);
  298. if (err) {
  299. dev_err(&adapter->pdev->dev,
  300. "Failed to create rx ctx in firmware%d\n", err);
  301. goto out_free_rsp;
  302. }
  303. prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
  304. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  305. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  306. rds_ring = &recv_ctx->rds_rings[i];
  307. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  308. rds_ring->crb_rcv_producer = adapter->ahw->pci_base0 + reg;
  309. }
  310. prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
  311. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  312. for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
  313. sds_ring = &recv_ctx->sds_rings[i];
  314. reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
  315. reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
  316. sds_ring->crb_sts_consumer = adapter->ahw->pci_base0 + reg;
  317. sds_ring->crb_intr_mask = adapter->ahw->pci_base0 + reg2;
  318. }
  319. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  320. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  321. recv_ctx->virt_port = prsp->virt_port;
  322. qlcnic_free_mbx_args(&cmd);
  323. out_free_rsp:
  324. dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
  325. cardrsp_phys_addr);
  326. out_free_rq:
  327. dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
  328. return err;
  329. }
  330. void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
  331. {
  332. int err;
  333. struct qlcnic_cmd_args cmd;
  334. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  335. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
  336. if (err)
  337. return;
  338. cmd.req.arg[1] = recv_ctx->context_id;
  339. err = qlcnic_issue_cmd(adapter, &cmd);
  340. if (err)
  341. dev_err(&adapter->pdev->dev,
  342. "Failed to destroy rx ctx in firmware\n");
  343. recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
  344. qlcnic_free_mbx_args(&cmd);
  345. }
  346. int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
  347. struct qlcnic_host_tx_ring *tx_ring,
  348. int ring)
  349. {
  350. struct qlcnic_hostrq_tx_ctx *prq;
  351. struct qlcnic_hostrq_cds_ring *prq_cds;
  352. struct qlcnic_cardrsp_tx_ctx *prsp;
  353. void *rq_addr, *rsp_addr;
  354. size_t rq_size, rsp_size;
  355. u32 temp;
  356. struct qlcnic_cmd_args cmd;
  357. int err;
  358. u64 phys_addr;
  359. dma_addr_t rq_phys_addr, rsp_phys_addr;
  360. /* reset host resources */
  361. tx_ring->producer = 0;
  362. tx_ring->sw_consumer = 0;
  363. *(tx_ring->hw_consumer) = 0;
  364. rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
  365. rq_addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  366. &rq_phys_addr, GFP_KERNEL | __GFP_ZERO);
  367. if (!rq_addr)
  368. return -ENOMEM;
  369. rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
  370. rsp_addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  371. &rsp_phys_addr, GFP_KERNEL | __GFP_ZERO);
  372. if (!rsp_addr) {
  373. err = -ENOMEM;
  374. goto out_free_rq;
  375. }
  376. prq = rq_addr;
  377. prsp = rsp_addr;
  378. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  379. temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
  380. QLCNIC_CAP0_LSO);
  381. prq->capabilities[0] = cpu_to_le32(temp);
  382. prq->host_int_crb_mode =
  383. cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
  384. prq->msi_index = 0;
  385. prq->interrupt_ctl = 0;
  386. prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
  387. prq_cds = &prq->cds_ring;
  388. prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
  389. prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
  390. phys_addr = rq_phys_addr;
  391. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
  392. if (err)
  393. goto out_free_rsp;
  394. cmd.req.arg[1] = MSD(phys_addr);
  395. cmd.req.arg[2] = LSD(phys_addr);
  396. cmd.req.arg[3] = rq_size;
  397. err = qlcnic_issue_cmd(adapter, &cmd);
  398. if (err == QLCNIC_RCODE_SUCCESS) {
  399. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  400. tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
  401. tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
  402. } else {
  403. dev_err(&adapter->pdev->dev,
  404. "Failed to create tx ctx in firmware%d\n", err);
  405. err = -EIO;
  406. }
  407. qlcnic_free_mbx_args(&cmd);
  408. out_free_rsp:
  409. dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
  410. rsp_phys_addr);
  411. out_free_rq:
  412. dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
  413. return err;
  414. }
  415. void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
  416. struct qlcnic_host_tx_ring *tx_ring)
  417. {
  418. struct qlcnic_cmd_args cmd;
  419. int ret;
  420. ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
  421. if (ret)
  422. return;
  423. cmd.req.arg[1] = tx_ring->ctx_id;
  424. if (qlcnic_issue_cmd(adapter, &cmd))
  425. dev_err(&adapter->pdev->dev,
  426. "Failed to destroy tx ctx in firmware\n");
  427. qlcnic_free_mbx_args(&cmd);
  428. }
  429. int
  430. qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
  431. {
  432. int err;
  433. struct qlcnic_cmd_args cmd;
  434. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
  435. if (err)
  436. return err;
  437. cmd.req.arg[1] = config;
  438. err = qlcnic_issue_cmd(adapter, &cmd);
  439. qlcnic_free_mbx_args(&cmd);
  440. return err;
  441. }
  442. int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
  443. {
  444. void *addr;
  445. int err, ring;
  446. struct qlcnic_recv_context *recv_ctx;
  447. struct qlcnic_host_rds_ring *rds_ring;
  448. struct qlcnic_host_sds_ring *sds_ring;
  449. struct qlcnic_host_tx_ring *tx_ring;
  450. __le32 *ptr;
  451. struct pci_dev *pdev = adapter->pdev;
  452. recv_ctx = adapter->recv_ctx;
  453. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  454. tx_ring = &adapter->tx_ring[ring];
  455. ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
  456. &tx_ring->hw_cons_phys_addr,
  457. GFP_KERNEL);
  458. if (ptr == NULL)
  459. return -ENOMEM;
  460. tx_ring->hw_consumer = ptr;
  461. /* cmd desc ring */
  462. addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
  463. &tx_ring->phys_addr,
  464. GFP_KERNEL);
  465. if (addr == NULL) {
  466. err = -ENOMEM;
  467. goto err_out_free;
  468. }
  469. tx_ring->desc_head = addr;
  470. }
  471. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  472. rds_ring = &recv_ctx->rds_rings[ring];
  473. addr = dma_alloc_coherent(&adapter->pdev->dev,
  474. RCV_DESC_RINGSIZE(rds_ring),
  475. &rds_ring->phys_addr, GFP_KERNEL);
  476. if (addr == NULL) {
  477. err = -ENOMEM;
  478. goto err_out_free;
  479. }
  480. rds_ring->desc_head = addr;
  481. }
  482. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  483. sds_ring = &recv_ctx->sds_rings[ring];
  484. addr = dma_alloc_coherent(&adapter->pdev->dev,
  485. STATUS_DESC_RINGSIZE(sds_ring),
  486. &sds_ring->phys_addr, GFP_KERNEL);
  487. if (addr == NULL) {
  488. err = -ENOMEM;
  489. goto err_out_free;
  490. }
  491. sds_ring->desc_head = addr;
  492. }
  493. return 0;
  494. err_out_free:
  495. qlcnic_free_hw_resources(adapter);
  496. return err;
  497. }
  498. int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
  499. {
  500. int i, err, ring;
  501. if (dev->flags & QLCNIC_NEED_FLR) {
  502. pci_reset_function(dev->pdev);
  503. dev->flags &= ~QLCNIC_NEED_FLR;
  504. }
  505. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  506. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
  507. err = qlcnic_83xx_config_intrpt(dev, 1);
  508. if (err)
  509. return err;
  510. }
  511. }
  512. err = qlcnic_fw_cmd_create_rx_ctx(dev);
  513. if (err)
  514. goto err_out;
  515. for (ring = 0; ring < dev->max_drv_tx_rings; ring++) {
  516. err = qlcnic_fw_cmd_create_tx_ctx(dev,
  517. &dev->tx_ring[ring],
  518. ring);
  519. if (err) {
  520. qlcnic_fw_cmd_del_rx_ctx(dev);
  521. if (ring == 0)
  522. goto err_out;
  523. for (i = 0; i < ring; i++)
  524. qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
  525. goto err_out;
  526. }
  527. }
  528. set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
  529. return 0;
  530. err_out:
  531. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  532. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  533. qlcnic_83xx_config_intrpt(dev, 0);
  534. }
  535. return err;
  536. }
  537. void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
  538. {
  539. int ring;
  540. if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
  541. qlcnic_fw_cmd_del_rx_ctx(adapter);
  542. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++)
  543. qlcnic_fw_cmd_del_tx_ctx(adapter,
  544. &adapter->tx_ring[ring]);
  545. if (qlcnic_83xx_check(adapter) &&
  546. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  547. if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  548. qlcnic_83xx_config_intrpt(adapter, 0);
  549. }
  550. /* Allow dma queues to drain after context reset */
  551. mdelay(20);
  552. }
  553. }
  554. void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
  555. {
  556. struct qlcnic_recv_context *recv_ctx;
  557. struct qlcnic_host_rds_ring *rds_ring;
  558. struct qlcnic_host_sds_ring *sds_ring;
  559. struct qlcnic_host_tx_ring *tx_ring;
  560. int ring;
  561. recv_ctx = adapter->recv_ctx;
  562. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  563. tx_ring = &adapter->tx_ring[ring];
  564. if (tx_ring->hw_consumer != NULL) {
  565. dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
  566. tx_ring->hw_consumer,
  567. tx_ring->hw_cons_phys_addr);
  568. tx_ring->hw_consumer = NULL;
  569. }
  570. if (tx_ring->desc_head != NULL) {
  571. dma_free_coherent(&adapter->pdev->dev,
  572. TX_DESC_RINGSIZE(tx_ring),
  573. tx_ring->desc_head,
  574. tx_ring->phys_addr);
  575. tx_ring->desc_head = NULL;
  576. }
  577. }
  578. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  579. rds_ring = &recv_ctx->rds_rings[ring];
  580. if (rds_ring->desc_head != NULL) {
  581. dma_free_coherent(&adapter->pdev->dev,
  582. RCV_DESC_RINGSIZE(rds_ring),
  583. rds_ring->desc_head,
  584. rds_ring->phys_addr);
  585. rds_ring->desc_head = NULL;
  586. }
  587. }
  588. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  589. sds_ring = &recv_ctx->sds_rings[ring];
  590. if (sds_ring->desc_head != NULL) {
  591. dma_free_coherent(&adapter->pdev->dev,
  592. STATUS_DESC_RINGSIZE(sds_ring),
  593. sds_ring->desc_head,
  594. sds_ring->phys_addr);
  595. sds_ring->desc_head = NULL;
  596. }
  597. }
  598. }
  599. int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
  600. {
  601. int err, i;
  602. struct qlcnic_cmd_args cmd;
  603. u32 mac_low, mac_high;
  604. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
  605. if (err)
  606. return err;
  607. cmd.req.arg[1] = adapter->ahw->pci_func | BIT_8;
  608. err = qlcnic_issue_cmd(adapter, &cmd);
  609. if (err == QLCNIC_RCODE_SUCCESS) {
  610. mac_low = cmd.rsp.arg[1];
  611. mac_high = cmd.rsp.arg[2];
  612. for (i = 0; i < 2; i++)
  613. mac[i] = (u8) (mac_high >> ((1 - i) * 8));
  614. for (i = 2; i < 6; i++)
  615. mac[i] = (u8) (mac_low >> ((5 - i) * 8));
  616. } else {
  617. dev_err(&adapter->pdev->dev,
  618. "Failed to get mac address%d\n", err);
  619. err = -EIO;
  620. }
  621. qlcnic_free_mbx_args(&cmd);
  622. return err;
  623. }
  624. /* Get info of a NIC partition */
  625. int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
  626. struct qlcnic_info *npar_info, u8 func_id)
  627. {
  628. int err;
  629. dma_addr_t nic_dma_t;
  630. const struct qlcnic_info_le *nic_info;
  631. void *nic_info_addr;
  632. struct qlcnic_cmd_args cmd;
  633. size_t nic_size = sizeof(struct qlcnic_info_le);
  634. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  635. &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
  636. if (!nic_info_addr)
  637. return -ENOMEM;
  638. nic_info = nic_info_addr;
  639. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
  640. if (err)
  641. goto out_free_dma;
  642. cmd.req.arg[1] = MSD(nic_dma_t);
  643. cmd.req.arg[2] = LSD(nic_dma_t);
  644. cmd.req.arg[3] = (func_id << 16 | nic_size);
  645. err = qlcnic_issue_cmd(adapter, &cmd);
  646. if (err != QLCNIC_RCODE_SUCCESS) {
  647. dev_err(&adapter->pdev->dev,
  648. "Failed to get nic info%d\n", err);
  649. err = -EIO;
  650. } else {
  651. npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
  652. npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
  653. npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
  654. npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
  655. npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
  656. npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
  657. npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
  658. npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
  659. npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
  660. npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
  661. }
  662. qlcnic_free_mbx_args(&cmd);
  663. out_free_dma:
  664. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  665. nic_dma_t);
  666. return err;
  667. }
  668. /* Configure a NIC partition */
  669. int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
  670. struct qlcnic_info *nic)
  671. {
  672. int err = -EIO;
  673. dma_addr_t nic_dma_t;
  674. void *nic_info_addr;
  675. struct qlcnic_cmd_args cmd;
  676. struct qlcnic_info_le *nic_info;
  677. size_t nic_size = sizeof(struct qlcnic_info_le);
  678. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  679. return err;
  680. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  681. &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
  682. if (!nic_info_addr)
  683. return -ENOMEM;
  684. nic_info = nic_info_addr;
  685. nic_info->pci_func = cpu_to_le16(nic->pci_func);
  686. nic_info->op_mode = cpu_to_le16(nic->op_mode);
  687. nic_info->phys_port = cpu_to_le16(nic->phys_port);
  688. nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
  689. nic_info->capabilities = cpu_to_le32(nic->capabilities);
  690. nic_info->max_mac_filters = nic->max_mac_filters;
  691. nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
  692. nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
  693. nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
  694. nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
  695. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
  696. if (err)
  697. goto out_free_dma;
  698. cmd.req.arg[1] = MSD(nic_dma_t);
  699. cmd.req.arg[2] = LSD(nic_dma_t);
  700. cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
  701. err = qlcnic_issue_cmd(adapter, &cmd);
  702. if (err != QLCNIC_RCODE_SUCCESS) {
  703. dev_err(&adapter->pdev->dev,
  704. "Failed to set nic info%d\n", err);
  705. err = -EIO;
  706. }
  707. qlcnic_free_mbx_args(&cmd);
  708. out_free_dma:
  709. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  710. nic_dma_t);
  711. return err;
  712. }
  713. /* Get PCI Info of a partition */
  714. int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
  715. struct qlcnic_pci_info *pci_info)
  716. {
  717. int err = 0, i;
  718. struct qlcnic_cmd_args cmd;
  719. dma_addr_t pci_info_dma_t;
  720. struct qlcnic_pci_info_le *npar;
  721. void *pci_info_addr;
  722. size_t npar_size = sizeof(struct qlcnic_pci_info_le);
  723. size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
  724. pci_info_addr = dma_alloc_coherent(&adapter->pdev->dev, pci_size,
  725. &pci_info_dma_t,
  726. GFP_KERNEL | __GFP_ZERO);
  727. if (!pci_info_addr)
  728. return -ENOMEM;
  729. npar = pci_info_addr;
  730. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
  731. if (err)
  732. goto out_free_dma;
  733. cmd.req.arg[1] = MSD(pci_info_dma_t);
  734. cmd.req.arg[2] = LSD(pci_info_dma_t);
  735. cmd.req.arg[3] = pci_size;
  736. err = qlcnic_issue_cmd(adapter, &cmd);
  737. adapter->ahw->act_pci_func = 0;
  738. if (err == QLCNIC_RCODE_SUCCESS) {
  739. for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++, pci_info++) {
  740. pci_info->id = le16_to_cpu(npar->id);
  741. pci_info->active = le16_to_cpu(npar->active);
  742. pci_info->type = le16_to_cpu(npar->type);
  743. if (pci_info->type == QLCNIC_TYPE_NIC)
  744. adapter->ahw->act_pci_func++;
  745. pci_info->default_port =
  746. le16_to_cpu(npar->default_port);
  747. pci_info->tx_min_bw =
  748. le16_to_cpu(npar->tx_min_bw);
  749. pci_info->tx_max_bw =
  750. le16_to_cpu(npar->tx_max_bw);
  751. memcpy(pci_info->mac, npar->mac, ETH_ALEN);
  752. }
  753. } else {
  754. dev_err(&adapter->pdev->dev,
  755. "Failed to get PCI Info%d\n", err);
  756. err = -EIO;
  757. }
  758. qlcnic_free_mbx_args(&cmd);
  759. out_free_dma:
  760. dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
  761. pci_info_dma_t);
  762. return err;
  763. }
  764. /* Configure eSwitch for port mirroring */
  765. int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
  766. u8 enable_mirroring, u8 pci_func)
  767. {
  768. struct device *dev = &adapter->pdev->dev;
  769. struct qlcnic_cmd_args cmd;
  770. int err = -EIO;
  771. u32 arg1;
  772. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
  773. !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
  774. return err;
  775. arg1 = id | (enable_mirroring ? BIT_4 : 0);
  776. arg1 |= pci_func << 8;
  777. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  778. QLCNIC_CMD_SET_PORTMIRRORING);
  779. if (err)
  780. return err;
  781. cmd.req.arg[1] = arg1;
  782. err = qlcnic_issue_cmd(adapter, &cmd);
  783. if (err != QLCNIC_RCODE_SUCCESS)
  784. dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
  785. pci_func, id);
  786. else
  787. dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
  788. pci_func, id);
  789. qlcnic_free_mbx_args(&cmd);
  790. return err;
  791. }
  792. int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
  793. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  794. size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
  795. struct qlcnic_esw_stats_le *stats;
  796. dma_addr_t stats_dma_t;
  797. void *stats_addr;
  798. u32 arg1;
  799. struct qlcnic_cmd_args cmd;
  800. int err;
  801. if (esw_stats == NULL)
  802. return -ENOMEM;
  803. if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
  804. (func != adapter->ahw->pci_func)) {
  805. dev_err(&adapter->pdev->dev,
  806. "Not privilege to query stats for func=%d", func);
  807. return -EIO;
  808. }
  809. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  810. &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
  811. if (!stats_addr)
  812. return -ENOMEM;
  813. arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
  814. arg1 |= rx_tx << 15 | stats_size << 16;
  815. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  816. QLCNIC_CMD_GET_ESWITCH_STATS);
  817. if (err)
  818. goto out_free_dma;
  819. cmd.req.arg[1] = arg1;
  820. cmd.req.arg[2] = MSD(stats_dma_t);
  821. cmd.req.arg[3] = LSD(stats_dma_t);
  822. err = qlcnic_issue_cmd(adapter, &cmd);
  823. if (!err) {
  824. stats = stats_addr;
  825. esw_stats->context_id = le16_to_cpu(stats->context_id);
  826. esw_stats->version = le16_to_cpu(stats->version);
  827. esw_stats->size = le16_to_cpu(stats->size);
  828. esw_stats->multicast_frames =
  829. le64_to_cpu(stats->multicast_frames);
  830. esw_stats->broadcast_frames =
  831. le64_to_cpu(stats->broadcast_frames);
  832. esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
  833. esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
  834. esw_stats->local_frames = le64_to_cpu(stats->local_frames);
  835. esw_stats->errors = le64_to_cpu(stats->errors);
  836. esw_stats->numbytes = le64_to_cpu(stats->numbytes);
  837. }
  838. qlcnic_free_mbx_args(&cmd);
  839. out_free_dma:
  840. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  841. stats_dma_t);
  842. return err;
  843. }
  844. /* This routine will retrieve the MAC statistics from firmware */
  845. int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
  846. struct qlcnic_mac_statistics *mac_stats)
  847. {
  848. struct qlcnic_mac_statistics_le *stats;
  849. struct qlcnic_cmd_args cmd;
  850. size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
  851. dma_addr_t stats_dma_t;
  852. void *stats_addr;
  853. int err;
  854. if (mac_stats == NULL)
  855. return -ENOMEM;
  856. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  857. &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
  858. if (!stats_addr)
  859. return -ENOMEM;
  860. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
  861. if (err)
  862. goto out_free_dma;
  863. cmd.req.arg[1] = stats_size << 16;
  864. cmd.req.arg[2] = MSD(stats_dma_t);
  865. cmd.req.arg[3] = LSD(stats_dma_t);
  866. err = qlcnic_issue_cmd(adapter, &cmd);
  867. if (!err) {
  868. stats = stats_addr;
  869. mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
  870. mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
  871. mac_stats->mac_tx_mcast_pkts =
  872. le64_to_cpu(stats->mac_tx_mcast_pkts);
  873. mac_stats->mac_tx_bcast_pkts =
  874. le64_to_cpu(stats->mac_tx_bcast_pkts);
  875. mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
  876. mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
  877. mac_stats->mac_rx_mcast_pkts =
  878. le64_to_cpu(stats->mac_rx_mcast_pkts);
  879. mac_stats->mac_rx_length_error =
  880. le64_to_cpu(stats->mac_rx_length_error);
  881. mac_stats->mac_rx_length_small =
  882. le64_to_cpu(stats->mac_rx_length_small);
  883. mac_stats->mac_rx_length_large =
  884. le64_to_cpu(stats->mac_rx_length_large);
  885. mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
  886. mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
  887. mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
  888. } else {
  889. dev_err(&adapter->pdev->dev,
  890. "%s: Get mac stats failed, err=%d.\n", __func__, err);
  891. }
  892. qlcnic_free_mbx_args(&cmd);
  893. out_free_dma:
  894. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  895. stats_dma_t);
  896. return err;
  897. }
  898. int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
  899. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  900. struct __qlcnic_esw_statistics port_stats;
  901. u8 i;
  902. int ret = -EIO;
  903. if (esw_stats == NULL)
  904. return -ENOMEM;
  905. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  906. return -EIO;
  907. if (adapter->npars == NULL)
  908. return -EIO;
  909. memset(esw_stats, 0, sizeof(u64));
  910. esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
  911. esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
  912. esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
  913. esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
  914. esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
  915. esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
  916. esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
  917. esw_stats->context_id = eswitch;
  918. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  919. if (adapter->npars[i].phy_port != eswitch)
  920. continue;
  921. memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
  922. if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
  923. rx_tx, &port_stats))
  924. continue;
  925. esw_stats->size = port_stats.size;
  926. esw_stats->version = port_stats.version;
  927. QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
  928. port_stats.unicast_frames);
  929. QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
  930. port_stats.multicast_frames);
  931. QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
  932. port_stats.broadcast_frames);
  933. QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
  934. port_stats.dropped_frames);
  935. QLCNIC_ADD_ESW_STATS(esw_stats->errors,
  936. port_stats.errors);
  937. QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
  938. port_stats.local_frames);
  939. QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
  940. port_stats.numbytes);
  941. ret = 0;
  942. }
  943. return ret;
  944. }
  945. int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
  946. const u8 port, const u8 rx_tx)
  947. {
  948. int err;
  949. u32 arg1;
  950. struct qlcnic_cmd_args cmd;
  951. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  952. return -EIO;
  953. if (func_esw == QLCNIC_STATS_PORT) {
  954. if (port >= QLCNIC_MAX_PCI_FUNC)
  955. goto err_ret;
  956. } else if (func_esw == QLCNIC_STATS_ESWITCH) {
  957. if (port >= QLCNIC_NIU_MAX_XG_PORTS)
  958. goto err_ret;
  959. } else {
  960. goto err_ret;
  961. }
  962. if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
  963. goto err_ret;
  964. arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
  965. arg1 |= BIT_14 | rx_tx << 15;
  966. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  967. QLCNIC_CMD_GET_ESWITCH_STATS);
  968. if (err)
  969. return err;
  970. cmd.req.arg[1] = arg1;
  971. err = qlcnic_issue_cmd(adapter, &cmd);
  972. qlcnic_free_mbx_args(&cmd);
  973. return err;
  974. err_ret:
  975. dev_err(&adapter->pdev->dev,
  976. "Invalid args func_esw %d port %d rx_ctx %d\n",
  977. func_esw, port, rx_tx);
  978. return -EIO;
  979. }
  980. static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  981. u32 *arg1, u32 *arg2)
  982. {
  983. struct device *dev = &adapter->pdev->dev;
  984. struct qlcnic_cmd_args cmd;
  985. u8 pci_func = *arg1 >> 8;
  986. int err;
  987. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  988. QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
  989. if (err)
  990. return err;
  991. cmd.req.arg[1] = *arg1;
  992. err = qlcnic_issue_cmd(adapter, &cmd);
  993. *arg1 = cmd.rsp.arg[1];
  994. *arg2 = cmd.rsp.arg[2];
  995. qlcnic_free_mbx_args(&cmd);
  996. if (err == QLCNIC_RCODE_SUCCESS)
  997. dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
  998. pci_func);
  999. else
  1000. dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
  1001. pci_func);
  1002. return err;
  1003. }
  1004. /* Configure eSwitch port
  1005. op_mode = 0 for setting default port behavior
  1006. op_mode = 1 for setting vlan id
  1007. op_mode = 2 for deleting vlan id
  1008. op_type = 0 for vlan_id
  1009. op_type = 1 for port vlan_id
  1010. */
  1011. int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
  1012. struct qlcnic_esw_func_cfg *esw_cfg)
  1013. {
  1014. struct device *dev = &adapter->pdev->dev;
  1015. struct qlcnic_cmd_args cmd;
  1016. int err = -EIO, index;
  1017. u32 arg1, arg2 = 0;
  1018. u8 pci_func;
  1019. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1020. return err;
  1021. pci_func = esw_cfg->pci_func;
  1022. index = qlcnic_is_valid_nic_func(adapter, pci_func);
  1023. if (index < 0)
  1024. return err;
  1025. arg1 = (adapter->npars[index].phy_port & BIT_0);
  1026. arg1 |= (pci_func << 8);
  1027. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1028. return err;
  1029. arg1 &= ~(0x0ff << 8);
  1030. arg1 |= (pci_func << 8);
  1031. arg1 &= ~(BIT_2 | BIT_3);
  1032. switch (esw_cfg->op_mode) {
  1033. case QLCNIC_PORT_DEFAULTS:
  1034. arg1 |= (BIT_4 | BIT_6 | BIT_7);
  1035. arg2 |= (BIT_0 | BIT_1);
  1036. if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
  1037. arg2 |= (BIT_2 | BIT_3);
  1038. if (!(esw_cfg->discard_tagged))
  1039. arg1 &= ~BIT_4;
  1040. if (!(esw_cfg->promisc_mode))
  1041. arg1 &= ~BIT_6;
  1042. if (!(esw_cfg->mac_override))
  1043. arg1 &= ~BIT_7;
  1044. if (!(esw_cfg->mac_anti_spoof))
  1045. arg2 &= ~BIT_0;
  1046. if (!(esw_cfg->offload_flags & BIT_0))
  1047. arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
  1048. if (!(esw_cfg->offload_flags & BIT_1))
  1049. arg2 &= ~BIT_2;
  1050. if (!(esw_cfg->offload_flags & BIT_2))
  1051. arg2 &= ~BIT_3;
  1052. break;
  1053. case QLCNIC_ADD_VLAN:
  1054. arg1 |= (BIT_2 | BIT_5);
  1055. arg1 |= (esw_cfg->vlan_id << 16);
  1056. break;
  1057. case QLCNIC_DEL_VLAN:
  1058. arg1 |= (BIT_3 | BIT_5);
  1059. arg1 &= ~(0x0ffff << 16);
  1060. break;
  1061. default:
  1062. return err;
  1063. }
  1064. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1065. QLCNIC_CMD_CONFIGURE_ESWITCH);
  1066. if (err)
  1067. return err;
  1068. cmd.req.arg[1] = arg1;
  1069. cmd.req.arg[2] = arg2;
  1070. err = qlcnic_issue_cmd(adapter, &cmd);
  1071. qlcnic_free_mbx_args(&cmd);
  1072. if (err != QLCNIC_RCODE_SUCCESS)
  1073. dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
  1074. pci_func);
  1075. else
  1076. dev_info(dev, "Configured eSwitch for vNIC function %d\n",
  1077. pci_func);
  1078. return err;
  1079. }
  1080. int
  1081. qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1082. struct qlcnic_esw_func_cfg *esw_cfg)
  1083. {
  1084. u32 arg1, arg2;
  1085. int index;
  1086. u8 phy_port;
  1087. if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
  1088. index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
  1089. if (index < 0)
  1090. return -EIO;
  1091. phy_port = adapter->npars[index].phy_port;
  1092. } else {
  1093. phy_port = adapter->ahw->physical_port;
  1094. }
  1095. arg1 = phy_port;
  1096. arg1 |= (esw_cfg->pci_func << 8);
  1097. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1098. return -EIO;
  1099. esw_cfg->discard_tagged = !!(arg1 & BIT_4);
  1100. esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
  1101. esw_cfg->promisc_mode = !!(arg1 & BIT_6);
  1102. esw_cfg->mac_override = !!(arg1 & BIT_7);
  1103. esw_cfg->vlan_id = LSW(arg1 >> 16);
  1104. esw_cfg->mac_anti_spoof = (arg2 & 0x1);
  1105. esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
  1106. return 0;
  1107. }