sdhci.c 32 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. /*
  11. * Note that PIO transfer is rather crappy atm. The buffer full/empty
  12. * interrupts aren't reliable so we currently transfer the entire buffer
  13. * directly. Patches to solve the problem are welcome.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/highmem.h>
  17. #include <linux/pci.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/protocol.h>
  21. #include <asm/scatterlist.h>
  22. #include "sdhci.h"
  23. #define DRIVER_NAME "sdhci"
  24. #define DRIVER_VERSION "0.11"
  25. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  26. #define DBG(f, x...) \
  27. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  28. static const struct pci_device_id pci_ids[] __devinitdata = {
  29. /* handle any SD host controller */
  30. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  31. { /* end: all zeroes */ },
  32. };
  33. MODULE_DEVICE_TABLE(pci, pci_ids);
  34. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  35. static void sdhci_finish_data(struct sdhci_host *);
  36. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  37. static void sdhci_finish_command(struct sdhci_host *);
  38. static void sdhci_dumpregs(struct sdhci_host *host)
  39. {
  40. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  41. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  42. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  43. readw(host->ioaddr + SDHCI_HOST_VERSION));
  44. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  45. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  46. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  47. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  48. readl(host->ioaddr + SDHCI_ARGUMENT),
  49. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  50. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  51. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  52. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  53. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  54. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  55. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  56. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  57. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  58. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  59. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  60. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  61. readl(host->ioaddr + SDHCI_INT_STATUS));
  62. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  63. readl(host->ioaddr + SDHCI_INT_ENABLE),
  64. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  65. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  66. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  67. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  68. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  69. readl(host->ioaddr + SDHCI_CAPABILITIES),
  70. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  71. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  72. }
  73. /*****************************************************************************\
  74. * *
  75. * Low level functions *
  76. * *
  77. \*****************************************************************************/
  78. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  79. {
  80. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  81. if (mask & SDHCI_RESET_ALL) {
  82. host->clock = 0;
  83. mdelay(50);
  84. }
  85. }
  86. static void sdhci_init(struct sdhci_host *host)
  87. {
  88. u32 intmask;
  89. sdhci_reset(host, SDHCI_RESET_ALL);
  90. intmask = ~(SDHCI_INT_CARD_INT | SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  91. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  92. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  93. /* This is unknown magic. */
  94. writeb(0xE, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  95. }
  96. static void sdhci_activate_led(struct sdhci_host *host)
  97. {
  98. u8 ctrl;
  99. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  100. ctrl |= SDHCI_CTRL_LED;
  101. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  102. }
  103. static void sdhci_deactivate_led(struct sdhci_host *host)
  104. {
  105. u8 ctrl;
  106. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  107. ctrl &= ~SDHCI_CTRL_LED;
  108. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  109. }
  110. /*****************************************************************************\
  111. * *
  112. * Core functions *
  113. * *
  114. \*****************************************************************************/
  115. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  116. {
  117. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  118. return host->mapped_sg + host->cur_sg->offset;
  119. }
  120. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  121. {
  122. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  123. }
  124. static inline int sdhci_next_sg(struct sdhci_host* host)
  125. {
  126. /*
  127. * Skip to next SG entry.
  128. */
  129. host->cur_sg++;
  130. host->num_sg--;
  131. /*
  132. * Any entries left?
  133. */
  134. if (host->num_sg > 0) {
  135. host->offset = 0;
  136. host->remain = host->cur_sg->length;
  137. }
  138. return host->num_sg;
  139. }
  140. static void sdhci_transfer_pio(struct sdhci_host *host)
  141. {
  142. char *buffer;
  143. u32 mask;
  144. int bytes, size;
  145. unsigned long max_jiffies;
  146. BUG_ON(!host->data);
  147. if (host->num_sg == 0)
  148. return;
  149. bytes = 0;
  150. if (host->data->flags & MMC_DATA_READ)
  151. mask = SDHCI_DATA_AVAILABLE;
  152. else
  153. mask = SDHCI_SPACE_AVAILABLE;
  154. buffer = sdhci_kmap_sg(host) + host->offset;
  155. /* Transfer shouldn't take more than 5 s */
  156. max_jiffies = jiffies + HZ * 5;
  157. while (host->size > 0) {
  158. if (time_after(jiffies, max_jiffies)) {
  159. printk(KERN_ERR "%s: PIO transfer stalled. "
  160. "Please report this to "
  161. BUGMAIL ".\n", mmc_hostname(host->mmc));
  162. sdhci_dumpregs(host);
  163. sdhci_kunmap_sg(host);
  164. host->data->error = MMC_ERR_FAILED;
  165. sdhci_finish_data(host);
  166. return;
  167. }
  168. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask))
  169. continue;
  170. size = min(host->size, host->remain);
  171. if (size >= 4) {
  172. if (host->data->flags & MMC_DATA_READ)
  173. *(u32*)buffer = readl(host->ioaddr + SDHCI_BUFFER);
  174. else
  175. writel(*(u32*)buffer, host->ioaddr + SDHCI_BUFFER);
  176. size = 4;
  177. } else if (size >= 2) {
  178. if (host->data->flags & MMC_DATA_READ)
  179. *(u16*)buffer = readw(host->ioaddr + SDHCI_BUFFER);
  180. else
  181. writew(*(u16*)buffer, host->ioaddr + SDHCI_BUFFER);
  182. size = 2;
  183. } else {
  184. if (host->data->flags & MMC_DATA_READ)
  185. *(u8*)buffer = readb(host->ioaddr + SDHCI_BUFFER);
  186. else
  187. writeb(*(u8*)buffer, host->ioaddr + SDHCI_BUFFER);
  188. size = 1;
  189. }
  190. buffer += size;
  191. host->offset += size;
  192. host->remain -= size;
  193. bytes += size;
  194. host->size -= size;
  195. if (host->remain == 0) {
  196. sdhci_kunmap_sg(host);
  197. if (sdhci_next_sg(host) == 0) {
  198. DBG("PIO transfer: %d bytes\n", bytes);
  199. return;
  200. }
  201. buffer = sdhci_kmap_sg(host);
  202. }
  203. }
  204. sdhci_kunmap_sg(host);
  205. DBG("PIO transfer: %d bytes\n", bytes);
  206. }
  207. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  208. {
  209. u16 mode;
  210. WARN_ON(host->data);
  211. if (data == NULL) {
  212. writew(0, host->ioaddr + SDHCI_TRANSFER_MODE);
  213. return;
  214. }
  215. DBG("blksz %04x blks %04x flags %08x\n",
  216. data->blksz, data->blocks, data->flags);
  217. DBG("tsac %d ms nsac %d clk\n",
  218. data->timeout_ns / 1000000, data->timeout_clks);
  219. mode = SDHCI_TRNS_BLK_CNT_EN;
  220. if (data->blocks > 1)
  221. mode |= SDHCI_TRNS_MULTI;
  222. if (data->flags & MMC_DATA_READ)
  223. mode |= SDHCI_TRNS_READ;
  224. if (host->flags & SDHCI_USE_DMA)
  225. mode |= SDHCI_TRNS_DMA;
  226. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  227. writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
  228. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  229. if (host->flags & SDHCI_USE_DMA) {
  230. int count;
  231. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  232. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  233. BUG_ON(count != 1);
  234. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  235. } else {
  236. host->size = data->blksz * data->blocks;
  237. host->cur_sg = data->sg;
  238. host->num_sg = data->sg_len;
  239. host->offset = 0;
  240. host->remain = host->cur_sg->length;
  241. }
  242. }
  243. static void sdhci_finish_data(struct sdhci_host *host)
  244. {
  245. struct mmc_data *data;
  246. u32 intmask;
  247. u16 blocks;
  248. BUG_ON(!host->data);
  249. data = host->data;
  250. host->data = NULL;
  251. if (host->flags & SDHCI_USE_DMA) {
  252. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  253. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  254. } else {
  255. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  256. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  257. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  258. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  259. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  260. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  261. }
  262. /*
  263. * Controller doesn't count down when in single block mode.
  264. */
  265. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  266. blocks = 0;
  267. else
  268. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  269. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  270. if ((data->error == MMC_ERR_NONE) && blocks) {
  271. printk(KERN_ERR "%s: Controller signalled completion even "
  272. "though there were blocks left. Please report this "
  273. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  274. data->error = MMC_ERR_FAILED;
  275. }
  276. if (host->size != 0) {
  277. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  278. "Please report this to " BUGMAIL ".\n",
  279. mmc_hostname(host->mmc), host->size);
  280. data->error = MMC_ERR_FAILED;
  281. }
  282. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  283. if (data->stop) {
  284. /*
  285. * The controller needs a reset of internal state machines
  286. * upon error conditions.
  287. */
  288. if (data->error != MMC_ERR_NONE) {
  289. sdhci_reset(host, SDHCI_RESET_CMD);
  290. sdhci_reset(host, SDHCI_RESET_DATA);
  291. }
  292. sdhci_send_command(host, data->stop);
  293. } else
  294. tasklet_schedule(&host->finish_tasklet);
  295. }
  296. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  297. {
  298. int flags;
  299. u32 present;
  300. unsigned long max_jiffies;
  301. WARN_ON(host->cmd);
  302. DBG("Sending cmd (%x)\n", cmd->opcode);
  303. /* Wait max 10 ms */
  304. max_jiffies = jiffies + (HZ + 99)/100;
  305. do {
  306. if (time_after(jiffies, max_jiffies)) {
  307. printk(KERN_ERR "%s: Controller never released "
  308. "inhibit bits. Please report this to "
  309. BUGMAIL ".\n", mmc_hostname(host->mmc));
  310. sdhci_dumpregs(host);
  311. cmd->error = MMC_ERR_FAILED;
  312. tasklet_schedule(&host->finish_tasklet);
  313. return;
  314. }
  315. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  316. } while (present & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT));
  317. mod_timer(&host->timer, jiffies + 10 * HZ);
  318. host->cmd = cmd;
  319. sdhci_prepare_data(host, cmd->data);
  320. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  321. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  322. printk(KERN_ERR "%s: Unsupported response type! "
  323. "Please report this to " BUGMAIL ".\n",
  324. mmc_hostname(host->mmc));
  325. cmd->error = MMC_ERR_INVALID;
  326. tasklet_schedule(&host->finish_tasklet);
  327. return;
  328. }
  329. if (!(cmd->flags & MMC_RSP_PRESENT))
  330. flags = SDHCI_CMD_RESP_NONE;
  331. else if (cmd->flags & MMC_RSP_136)
  332. flags = SDHCI_CMD_RESP_LONG;
  333. else if (cmd->flags & MMC_RSP_BUSY)
  334. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  335. else
  336. flags = SDHCI_CMD_RESP_SHORT;
  337. if (cmd->flags & MMC_RSP_CRC)
  338. flags |= SDHCI_CMD_CRC;
  339. if (cmd->flags & MMC_RSP_OPCODE)
  340. flags |= SDHCI_CMD_INDEX;
  341. if (cmd->data)
  342. flags |= SDHCI_CMD_DATA;
  343. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  344. host->ioaddr + SDHCI_COMMAND);
  345. }
  346. static void sdhci_finish_command(struct sdhci_host *host)
  347. {
  348. int i;
  349. BUG_ON(host->cmd == NULL);
  350. if (host->cmd->flags & MMC_RSP_PRESENT) {
  351. if (host->cmd->flags & MMC_RSP_136) {
  352. /* CRC is stripped so we need to do some shifting. */
  353. for (i = 0;i < 4;i++) {
  354. host->cmd->resp[i] = readl(host->ioaddr +
  355. SDHCI_RESPONSE + (3-i)*4) << 8;
  356. if (i != 3)
  357. host->cmd->resp[i] |=
  358. readb(host->ioaddr +
  359. SDHCI_RESPONSE + (3-i)*4-1);
  360. }
  361. } else {
  362. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  363. }
  364. }
  365. host->cmd->error = MMC_ERR_NONE;
  366. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  367. if (host->cmd->data) {
  368. u32 intmask;
  369. host->data = host->cmd->data;
  370. if (!(host->flags & SDHCI_USE_DMA)) {
  371. /*
  372. * Don't enable the interrupts until now to make sure we
  373. * get stable handling of the FIFO.
  374. */
  375. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  376. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  377. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  378. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  379. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  380. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  381. /*
  382. * The buffer interrupts are to unreliable so we
  383. * start the transfer immediatly.
  384. */
  385. sdhci_transfer_pio(host);
  386. }
  387. } else
  388. tasklet_schedule(&host->finish_tasklet);
  389. host->cmd = NULL;
  390. }
  391. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  392. {
  393. int div;
  394. u16 clk;
  395. unsigned long max_jiffies;
  396. if (clock == host->clock)
  397. return;
  398. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  399. if (clock == 0)
  400. goto out;
  401. for (div = 1;div < 256;div *= 2) {
  402. if ((host->max_clk / div) <= clock)
  403. break;
  404. }
  405. div >>= 1;
  406. clk = div << SDHCI_DIVIDER_SHIFT;
  407. clk |= SDHCI_CLOCK_INT_EN;
  408. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  409. /* Wait max 10 ms */
  410. max_jiffies = jiffies + (HZ + 99)/100;
  411. do {
  412. if (time_after(jiffies, max_jiffies)) {
  413. printk(KERN_ERR "%s: Internal clock never stabilised. "
  414. "Please report this to " BUGMAIL ".\n",
  415. mmc_hostname(host->mmc));
  416. sdhci_dumpregs(host);
  417. return;
  418. }
  419. clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL);
  420. } while (!(clk & SDHCI_CLOCK_INT_STABLE));
  421. clk |= SDHCI_CLOCK_CARD_EN;
  422. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  423. out:
  424. host->clock = clock;
  425. }
  426. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  427. {
  428. u8 pwr;
  429. if (host->power == power)
  430. return;
  431. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  432. if (power == (unsigned short)-1)
  433. goto out;
  434. pwr = SDHCI_POWER_ON;
  435. switch (power) {
  436. case MMC_VDD_170:
  437. case MMC_VDD_180:
  438. case MMC_VDD_190:
  439. pwr |= SDHCI_POWER_180;
  440. break;
  441. case MMC_VDD_290:
  442. case MMC_VDD_300:
  443. case MMC_VDD_310:
  444. pwr |= SDHCI_POWER_300;
  445. break;
  446. case MMC_VDD_320:
  447. case MMC_VDD_330:
  448. case MMC_VDD_340:
  449. pwr |= SDHCI_POWER_330;
  450. break;
  451. default:
  452. BUG();
  453. }
  454. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  455. out:
  456. host->power = power;
  457. }
  458. /*****************************************************************************\
  459. * *
  460. * MMC callbacks *
  461. * *
  462. \*****************************************************************************/
  463. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  464. {
  465. struct sdhci_host *host;
  466. unsigned long flags;
  467. host = mmc_priv(mmc);
  468. spin_lock_irqsave(&host->lock, flags);
  469. WARN_ON(host->mrq != NULL);
  470. sdhci_activate_led(host);
  471. host->mrq = mrq;
  472. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  473. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  474. tasklet_schedule(&host->finish_tasklet);
  475. } else
  476. sdhci_send_command(host, mrq->cmd);
  477. spin_unlock_irqrestore(&host->lock, flags);
  478. }
  479. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  480. {
  481. struct sdhci_host *host;
  482. unsigned long flags;
  483. u8 ctrl;
  484. host = mmc_priv(mmc);
  485. spin_lock_irqsave(&host->lock, flags);
  486. /*
  487. * Reset the chip on each power off.
  488. * Should clear out any weird states.
  489. */
  490. if (ios->power_mode == MMC_POWER_OFF) {
  491. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  492. spin_unlock_irqrestore(&host->lock, flags);
  493. sdhci_init(host);
  494. spin_lock_irqsave(&host->lock, flags);
  495. }
  496. sdhci_set_clock(host, ios->clock);
  497. if (ios->power_mode == MMC_POWER_OFF)
  498. sdhci_set_power(host, -1);
  499. else
  500. sdhci_set_power(host, ios->vdd);
  501. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  502. if (ios->bus_width == MMC_BUS_WIDTH_4)
  503. ctrl |= SDHCI_CTRL_4BITBUS;
  504. else
  505. ctrl &= ~SDHCI_CTRL_4BITBUS;
  506. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  507. spin_unlock_irqrestore(&host->lock, flags);
  508. }
  509. static int sdhci_get_ro(struct mmc_host *mmc)
  510. {
  511. struct sdhci_host *host;
  512. unsigned long flags;
  513. int present;
  514. host = mmc_priv(mmc);
  515. spin_lock_irqsave(&host->lock, flags);
  516. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  517. spin_unlock_irqrestore(&host->lock, flags);
  518. return !(present & SDHCI_WRITE_PROTECT);
  519. }
  520. static struct mmc_host_ops sdhci_ops = {
  521. .request = sdhci_request,
  522. .set_ios = sdhci_set_ios,
  523. .get_ro = sdhci_get_ro,
  524. };
  525. /*****************************************************************************\
  526. * *
  527. * Tasklets *
  528. * *
  529. \*****************************************************************************/
  530. static void sdhci_tasklet_card(unsigned long param)
  531. {
  532. struct sdhci_host *host;
  533. unsigned long flags;
  534. host = (struct sdhci_host*)param;
  535. spin_lock_irqsave(&host->lock, flags);
  536. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  537. if (host->mrq) {
  538. printk(KERN_ERR "%s: Card removed during transfer!\n",
  539. mmc_hostname(host->mmc));
  540. printk(KERN_ERR "%s: Resetting controller.\n",
  541. mmc_hostname(host->mmc));
  542. sdhci_reset(host, SDHCI_RESET_CMD);
  543. sdhci_reset(host, SDHCI_RESET_DATA);
  544. host->mrq->cmd->error = MMC_ERR_FAILED;
  545. tasklet_schedule(&host->finish_tasklet);
  546. }
  547. }
  548. spin_unlock_irqrestore(&host->lock, flags);
  549. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  550. }
  551. static void sdhci_tasklet_finish(unsigned long param)
  552. {
  553. struct sdhci_host *host;
  554. unsigned long flags;
  555. struct mmc_request *mrq;
  556. host = (struct sdhci_host*)param;
  557. spin_lock_irqsave(&host->lock, flags);
  558. del_timer(&host->timer);
  559. mrq = host->mrq;
  560. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  561. /*
  562. * The controller needs a reset of internal state machines
  563. * upon error conditions.
  564. */
  565. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  566. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  567. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  568. sdhci_reset(host, SDHCI_RESET_CMD);
  569. sdhci_reset(host, SDHCI_RESET_DATA);
  570. }
  571. host->mrq = NULL;
  572. host->cmd = NULL;
  573. host->data = NULL;
  574. sdhci_deactivate_led(host);
  575. spin_unlock_irqrestore(&host->lock, flags);
  576. mmc_request_done(host->mmc, mrq);
  577. }
  578. static void sdhci_timeout_timer(unsigned long data)
  579. {
  580. struct sdhci_host *host;
  581. unsigned long flags;
  582. host = (struct sdhci_host*)data;
  583. spin_lock_irqsave(&host->lock, flags);
  584. if (host->mrq) {
  585. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  586. "Please report this to " BUGMAIL ".\n",
  587. mmc_hostname(host->mmc));
  588. sdhci_dumpregs(host);
  589. if (host->data) {
  590. host->data->error = MMC_ERR_TIMEOUT;
  591. sdhci_finish_data(host);
  592. } else {
  593. if (host->cmd)
  594. host->cmd->error = MMC_ERR_TIMEOUT;
  595. else
  596. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  597. tasklet_schedule(&host->finish_tasklet);
  598. }
  599. }
  600. spin_unlock_irqrestore(&host->lock, flags);
  601. }
  602. /*****************************************************************************\
  603. * *
  604. * Interrupt handling *
  605. * *
  606. \*****************************************************************************/
  607. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  608. {
  609. BUG_ON(intmask == 0);
  610. if (!host->cmd) {
  611. printk(KERN_ERR "%s: Got command interrupt even though no "
  612. "command operation was in progress.\n",
  613. mmc_hostname(host->mmc));
  614. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  615. mmc_hostname(host->mmc));
  616. sdhci_dumpregs(host);
  617. return;
  618. }
  619. if (intmask & SDHCI_INT_RESPONSE)
  620. sdhci_finish_command(host);
  621. else {
  622. if (intmask & SDHCI_INT_TIMEOUT)
  623. host->cmd->error = MMC_ERR_TIMEOUT;
  624. else if (intmask & SDHCI_INT_CRC)
  625. host->cmd->error = MMC_ERR_BADCRC;
  626. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  627. host->cmd->error = MMC_ERR_FAILED;
  628. else
  629. host->cmd->error = MMC_ERR_INVALID;
  630. tasklet_schedule(&host->finish_tasklet);
  631. }
  632. }
  633. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  634. {
  635. BUG_ON(intmask == 0);
  636. if (!host->data) {
  637. /*
  638. * A data end interrupt is sent together with the response
  639. * for the stop command.
  640. */
  641. if (intmask & SDHCI_INT_DATA_END)
  642. return;
  643. printk(KERN_ERR "%s: Got data interrupt even though no "
  644. "data operation was in progress.\n",
  645. mmc_hostname(host->mmc));
  646. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  647. mmc_hostname(host->mmc));
  648. sdhci_dumpregs(host);
  649. return;
  650. }
  651. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  652. host->data->error = MMC_ERR_TIMEOUT;
  653. else if (intmask & SDHCI_INT_DATA_CRC)
  654. host->data->error = MMC_ERR_BADCRC;
  655. else if (intmask & SDHCI_INT_DATA_END_BIT)
  656. host->data->error = MMC_ERR_FAILED;
  657. if (host->data->error != MMC_ERR_NONE)
  658. sdhci_finish_data(host);
  659. else {
  660. if (intmask & (SDHCI_INT_BUF_FULL | SDHCI_INT_BUF_EMPTY))
  661. sdhci_transfer_pio(host);
  662. if (intmask & SDHCI_INT_DATA_END)
  663. sdhci_finish_data(host);
  664. }
  665. }
  666. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  667. {
  668. irqreturn_t result;
  669. struct sdhci_host* host = dev_id;
  670. u32 intmask;
  671. spin_lock(&host->lock);
  672. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  673. if (!intmask) {
  674. result = IRQ_NONE;
  675. goto out;
  676. }
  677. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  678. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE))
  679. tasklet_schedule(&host->card_tasklet);
  680. if (intmask & SDHCI_INT_CMD_MASK) {
  681. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  682. writel(intmask & SDHCI_INT_CMD_MASK,
  683. host->ioaddr + SDHCI_INT_STATUS);
  684. }
  685. if (intmask & SDHCI_INT_DATA_MASK) {
  686. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  687. writel(intmask & SDHCI_INT_DATA_MASK,
  688. host->ioaddr + SDHCI_INT_STATUS);
  689. }
  690. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  691. if (intmask & SDHCI_INT_CARD_INT) {
  692. printk(KERN_ERR "%s: Unexpected card interrupt. Please "
  693. "report this to " BUGMAIL ".\n",
  694. mmc_hostname(host->mmc));
  695. sdhci_dumpregs(host);
  696. }
  697. if (intmask & SDHCI_INT_BUS_POWER) {
  698. printk(KERN_ERR "%s: Unexpected bus power interrupt. Please "
  699. "report this to " BUGMAIL ".\n",
  700. mmc_hostname(host->mmc));
  701. sdhci_dumpregs(host);
  702. }
  703. if (intmask & SDHCI_INT_ACMD12ERR) {
  704. printk(KERN_ERR "%s: Unexpected auto CMD12 error. Please "
  705. "report this to " BUGMAIL ".\n",
  706. mmc_hostname(host->mmc));
  707. sdhci_dumpregs(host);
  708. writew(~0, host->ioaddr + SDHCI_ACMD12_ERR);
  709. }
  710. if (intmask)
  711. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  712. result = IRQ_HANDLED;
  713. out:
  714. spin_unlock(&host->lock);
  715. return result;
  716. }
  717. /*****************************************************************************\
  718. * *
  719. * Suspend/resume *
  720. * *
  721. \*****************************************************************************/
  722. #ifdef CONFIG_PM
  723. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  724. {
  725. struct sdhci_chip *chip;
  726. int i, ret;
  727. chip = pci_get_drvdata(pdev);
  728. if (!chip)
  729. return 0;
  730. DBG("Suspending...\n");
  731. for (i = 0;i < chip->num_slots;i++) {
  732. if (!chip->hosts[i])
  733. continue;
  734. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  735. if (ret) {
  736. for (i--;i >= 0;i--)
  737. mmc_resume_host(chip->hosts[i]->mmc);
  738. return ret;
  739. }
  740. }
  741. pci_save_state(pdev);
  742. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  743. pci_disable_device(pdev);
  744. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  745. return 0;
  746. }
  747. static int sdhci_resume (struct pci_dev *pdev)
  748. {
  749. struct sdhci_chip *chip;
  750. int i, ret;
  751. chip = pci_get_drvdata(pdev);
  752. if (!chip)
  753. return 0;
  754. DBG("Resuming...\n");
  755. pci_set_power_state(pdev, PCI_D0);
  756. pci_restore_state(pdev);
  757. pci_enable_device(pdev);
  758. for (i = 0;i < chip->num_slots;i++) {
  759. if (!chip->hosts[i])
  760. continue;
  761. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  762. pci_set_master(pdev);
  763. sdhci_init(chip->hosts[i]);
  764. ret = mmc_resume_host(chip->hosts[i]->mmc);
  765. if (ret)
  766. return ret;
  767. }
  768. return 0;
  769. }
  770. #else /* CONFIG_PM */
  771. #define sdhci_suspend NULL
  772. #define sdhci_resume NULL
  773. #endif /* CONFIG_PM */
  774. /*****************************************************************************\
  775. * *
  776. * Device probing/removal *
  777. * *
  778. \*****************************************************************************/
  779. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  780. {
  781. int ret;
  782. struct sdhci_chip *chip;
  783. struct mmc_host *mmc;
  784. struct sdhci_host *host;
  785. u8 first_bar;
  786. unsigned int caps;
  787. chip = pci_get_drvdata(pdev);
  788. BUG_ON(!chip);
  789. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  790. if (ret)
  791. return ret;
  792. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  793. if (first_bar > 5) {
  794. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  795. return -ENODEV;
  796. }
  797. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  798. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  799. return -ENODEV;
  800. }
  801. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  802. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  803. return -ENODEV;
  804. }
  805. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  806. if (!mmc)
  807. return -ENOMEM;
  808. host = mmc_priv(mmc);
  809. host->mmc = mmc;
  810. host->bar = first_bar + slot;
  811. host->addr = pci_resource_start(pdev, host->bar);
  812. host->irq = pdev->irq;
  813. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  814. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  815. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  816. if (ret)
  817. goto free;
  818. host->ioaddr = ioremap_nocache(host->addr,
  819. pci_resource_len(pdev, host->bar));
  820. if (!host->ioaddr) {
  821. ret = -ENOMEM;
  822. goto release;
  823. }
  824. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  825. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  826. host->flags |= SDHCI_USE_DMA;
  827. if (host->flags & SDHCI_USE_DMA) {
  828. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  829. printk(KERN_WARNING "%s: No suitable DMA available. "
  830. "Falling back to PIO.\n", host->slot_descr);
  831. host->flags &= ~SDHCI_USE_DMA;
  832. }
  833. }
  834. if (host->flags & SDHCI_USE_DMA)
  835. pci_set_master(pdev);
  836. else /* XXX: Hack to get MMC layer to avoid highmem */
  837. pdev->dma_mask = 0;
  838. host->max_clk =
  839. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  840. if (host->max_clk == 0) {
  841. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  842. "frequency.\n", host->slot_descr);
  843. ret = -ENODEV;
  844. goto unmap;
  845. }
  846. host->max_clk *= 1000000;
  847. /*
  848. * Set host parameters.
  849. */
  850. mmc->ops = &sdhci_ops;
  851. mmc->f_min = host->max_clk / 256;
  852. mmc->f_max = host->max_clk;
  853. mmc->caps = MMC_CAP_4_BIT_DATA;
  854. mmc->ocr_avail = 0;
  855. if (caps & SDHCI_CAN_VDD_330)
  856. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  857. else if (caps & SDHCI_CAN_VDD_300)
  858. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  859. else if (caps & SDHCI_CAN_VDD_180)
  860. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  861. if (mmc->ocr_avail == 0) {
  862. printk(KERN_ERR "%s: Hardware doesn't report any "
  863. "support voltages.\n", host->slot_descr);
  864. ret = -ENODEV;
  865. goto unmap;
  866. }
  867. spin_lock_init(&host->lock);
  868. /*
  869. * Maximum number of segments. Hardware cannot do scatter lists.
  870. */
  871. if (host->flags & SDHCI_USE_DMA)
  872. mmc->max_hw_segs = 1;
  873. else
  874. mmc->max_hw_segs = 16;
  875. mmc->max_phys_segs = 16;
  876. /*
  877. * Maximum number of sectors in one transfer. Limited by sector
  878. * count register.
  879. */
  880. mmc->max_sectors = 0x3FFF;
  881. /*
  882. * Maximum segment size. Could be one segment with the maximum number
  883. * of sectors.
  884. */
  885. mmc->max_seg_size = mmc->max_sectors * 512;
  886. /*
  887. * Init tasklets.
  888. */
  889. tasklet_init(&host->card_tasklet,
  890. sdhci_tasklet_card, (unsigned long)host);
  891. tasklet_init(&host->finish_tasklet,
  892. sdhci_tasklet_finish, (unsigned long)host);
  893. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  894. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  895. host->slot_descr, host);
  896. if (ret)
  897. goto untasklet;
  898. sdhci_init(host);
  899. #ifdef CONFIG_MMC_DEBUG
  900. sdhci_dumpregs(host);
  901. #endif
  902. host->chip = chip;
  903. chip->hosts[slot] = host;
  904. mmc_add_host(mmc);
  905. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  906. host->addr, host->irq,
  907. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  908. return 0;
  909. untasklet:
  910. tasklet_kill(&host->card_tasklet);
  911. tasklet_kill(&host->finish_tasklet);
  912. unmap:
  913. iounmap(host->ioaddr);
  914. release:
  915. pci_release_region(pdev, host->bar);
  916. free:
  917. mmc_free_host(mmc);
  918. return ret;
  919. }
  920. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  921. {
  922. struct sdhci_chip *chip;
  923. struct mmc_host *mmc;
  924. struct sdhci_host *host;
  925. chip = pci_get_drvdata(pdev);
  926. host = chip->hosts[slot];
  927. mmc = host->mmc;
  928. chip->hosts[slot] = NULL;
  929. mmc_remove_host(mmc);
  930. sdhci_reset(host, SDHCI_RESET_ALL);
  931. free_irq(host->irq, host);
  932. del_timer_sync(&host->timer);
  933. tasklet_kill(&host->card_tasklet);
  934. tasklet_kill(&host->finish_tasklet);
  935. iounmap(host->ioaddr);
  936. pci_release_region(pdev, host->bar);
  937. mmc_free_host(mmc);
  938. }
  939. static int __devinit sdhci_probe(struct pci_dev *pdev,
  940. const struct pci_device_id *ent)
  941. {
  942. int ret, i;
  943. u8 slots, rev;
  944. struct sdhci_chip *chip;
  945. BUG_ON(pdev == NULL);
  946. BUG_ON(ent == NULL);
  947. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  948. printk(KERN_INFO DRIVER_NAME
  949. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  950. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  951. (int)rev);
  952. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  953. if (ret)
  954. return ret;
  955. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  956. DBG("found %d slot(s)\n", slots);
  957. if (slots == 0)
  958. return -ENODEV;
  959. ret = pci_enable_device(pdev);
  960. if (ret)
  961. return ret;
  962. chip = kzalloc(sizeof(struct sdhci_chip) +
  963. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  964. if (!chip) {
  965. ret = -ENOMEM;
  966. goto err;
  967. }
  968. chip->pdev = pdev;
  969. chip->num_slots = slots;
  970. pci_set_drvdata(pdev, chip);
  971. for (i = 0;i < slots;i++) {
  972. ret = sdhci_probe_slot(pdev, i);
  973. if (ret) {
  974. for (i--;i >= 0;i--)
  975. sdhci_remove_slot(pdev, i);
  976. goto free;
  977. }
  978. }
  979. return 0;
  980. free:
  981. pci_set_drvdata(pdev, NULL);
  982. kfree(chip);
  983. err:
  984. pci_disable_device(pdev);
  985. return ret;
  986. }
  987. static void __devexit sdhci_remove(struct pci_dev *pdev)
  988. {
  989. int i;
  990. struct sdhci_chip *chip;
  991. chip = pci_get_drvdata(pdev);
  992. if (chip) {
  993. for (i = 0;i < chip->num_slots;i++)
  994. sdhci_remove_slot(pdev, i);
  995. pci_set_drvdata(pdev, NULL);
  996. kfree(chip);
  997. }
  998. pci_disable_device(pdev);
  999. }
  1000. static struct pci_driver sdhci_driver = {
  1001. .name = DRIVER_NAME,
  1002. .id_table = pci_ids,
  1003. .probe = sdhci_probe,
  1004. .remove = __devexit_p(sdhci_remove),
  1005. .suspend = sdhci_suspend,
  1006. .resume = sdhci_resume,
  1007. };
  1008. /*****************************************************************************\
  1009. * *
  1010. * Driver init/exit *
  1011. * *
  1012. \*****************************************************************************/
  1013. static int __init sdhci_drv_init(void)
  1014. {
  1015. printk(KERN_INFO DRIVER_NAME
  1016. ": Secure Digital Host Controller Interface driver, "
  1017. DRIVER_VERSION "\n");
  1018. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1019. return pci_register_driver(&sdhci_driver);
  1020. }
  1021. static void __exit sdhci_drv_exit(void)
  1022. {
  1023. DBG("Exiting\n");
  1024. pci_unregister_driver(&sdhci_driver);
  1025. }
  1026. module_init(sdhci_drv_init);
  1027. module_exit(sdhci_drv_exit);
  1028. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1029. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1030. MODULE_VERSION(DRIVER_VERSION);
  1031. MODULE_LICENSE("GPL");