ecx-common.dtsi 5.1 KB

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  1. /*
  2. * Copyright 2011-2012 Calxeda, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. / {
  17. chosen {
  18. bootargs = "console=ttyAMA0";
  19. };
  20. soc {
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. compatible = "simple-bus";
  24. interrupt-parent = <&intc>;
  25. sata@ffe08000 {
  26. compatible = "calxeda,hb-ahci";
  27. reg = <0xffe08000 0x10000>;
  28. interrupts = <0 83 4>;
  29. dma-coherent;
  30. calxeda,port-phys = <&combophy5 0 &combophy0 0
  31. &combophy0 1 &combophy0 2
  32. &combophy0 3>;
  33. calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
  34. calxeda,led-order = <4 0 1 2 3>;
  35. };
  36. sdhci@ffe0e000 {
  37. compatible = "calxeda,hb-sdhci";
  38. reg = <0xffe0e000 0x1000>;
  39. interrupts = <0 90 4>;
  40. clocks = <&eclk>;
  41. status = "disabled";
  42. };
  43. ipc@fff20000 {
  44. compatible = "arm,pl320", "arm,primecell";
  45. reg = <0xfff20000 0x1000>;
  46. interrupts = <0 7 4>;
  47. clocks = <&pclk>;
  48. clock-names = "apb_pclk";
  49. };
  50. gpioe: gpio@fff30000 {
  51. #gpio-cells = <2>;
  52. compatible = "arm,pl061", "arm,primecell";
  53. gpio-controller;
  54. reg = <0xfff30000 0x1000>;
  55. interrupts = <0 14 4>;
  56. clocks = <&pclk>;
  57. clock-names = "apb_pclk";
  58. status = "disabled";
  59. };
  60. gpiof: gpio@fff31000 {
  61. #gpio-cells = <2>;
  62. compatible = "arm,pl061", "arm,primecell";
  63. gpio-controller;
  64. reg = <0xfff31000 0x1000>;
  65. interrupts = <0 15 4>;
  66. clocks = <&pclk>;
  67. clock-names = "apb_pclk";
  68. status = "disabled";
  69. };
  70. gpiog: gpio@fff32000 {
  71. #gpio-cells = <2>;
  72. compatible = "arm,pl061", "arm,primecell";
  73. gpio-controller;
  74. reg = <0xfff32000 0x1000>;
  75. interrupts = <0 16 4>;
  76. clocks = <&pclk>;
  77. clock-names = "apb_pclk";
  78. status = "disabled";
  79. };
  80. gpioh: gpio@fff33000 {
  81. #gpio-cells = <2>;
  82. compatible = "arm,pl061", "arm,primecell";
  83. gpio-controller;
  84. reg = <0xfff33000 0x1000>;
  85. interrupts = <0 17 4>;
  86. clocks = <&pclk>;
  87. clock-names = "apb_pclk";
  88. status = "disabled";
  89. };
  90. timer@fff34000 {
  91. compatible = "arm,sp804", "arm,primecell";
  92. reg = <0xfff34000 0x1000>;
  93. interrupts = <0 18 4>;
  94. clocks = <&pclk>;
  95. clock-names = "apb_pclk";
  96. };
  97. rtc@fff35000 {
  98. compatible = "arm,pl031", "arm,primecell";
  99. reg = <0xfff35000 0x1000>;
  100. interrupts = <0 19 4>;
  101. clocks = <&pclk>;
  102. clock-names = "apb_pclk";
  103. };
  104. serial@fff36000 {
  105. compatible = "arm,pl011", "arm,primecell";
  106. reg = <0xfff36000 0x1000>;
  107. interrupts = <0 20 4>;
  108. clocks = <&pclk>;
  109. clock-names = "apb_pclk";
  110. };
  111. smic@fff3a000 {
  112. compatible = "ipmi-smic";
  113. device_type = "ipmi";
  114. reg = <0xfff3a000 0x1000>;
  115. interrupts = <0 24 4>;
  116. reg-size = <4>;
  117. reg-spacing = <4>;
  118. };
  119. sregs@fff3c000 {
  120. compatible = "calxeda,hb-sregs";
  121. reg = <0xfff3c000 0x1000>;
  122. clocks {
  123. #address-cells = <1>;
  124. #size-cells = <0>;
  125. osc: oscillator {
  126. #clock-cells = <0>;
  127. compatible = "fixed-clock";
  128. clock-frequency = <33333000>;
  129. };
  130. ddrpll: ddrpll {
  131. #clock-cells = <0>;
  132. compatible = "calxeda,hb-pll-clock";
  133. clocks = <&osc>;
  134. reg = <0x108>;
  135. };
  136. a9pll: a9pll {
  137. #clock-cells = <0>;
  138. compatible = "calxeda,hb-pll-clock";
  139. clocks = <&osc>;
  140. reg = <0x100>;
  141. };
  142. a9periphclk: a9periphclk {
  143. #clock-cells = <0>;
  144. compatible = "calxeda,hb-a9periph-clock";
  145. clocks = <&a9pll>;
  146. reg = <0x104>;
  147. };
  148. a9bclk: a9bclk {
  149. #clock-cells = <0>;
  150. compatible = "calxeda,hb-a9bus-clock";
  151. clocks = <&a9pll>;
  152. reg = <0x104>;
  153. };
  154. emmcpll: emmcpll {
  155. #clock-cells = <0>;
  156. compatible = "calxeda,hb-pll-clock";
  157. clocks = <&osc>;
  158. reg = <0x10C>;
  159. };
  160. eclk: eclk {
  161. #clock-cells = <0>;
  162. compatible = "calxeda,hb-emmc-clock";
  163. clocks = <&emmcpll>;
  164. reg = <0x114>;
  165. };
  166. pclk: pclk {
  167. #clock-cells = <0>;
  168. compatible = "fixed-clock";
  169. clock-frequency = <150000000>;
  170. };
  171. };
  172. };
  173. dma@fff3d000 {
  174. compatible = "arm,pl330", "arm,primecell";
  175. reg = <0xfff3d000 0x1000>;
  176. interrupts = <0 92 4>;
  177. clocks = <&pclk>;
  178. clock-names = "apb_pclk";
  179. };
  180. ethernet@fff50000 {
  181. compatible = "calxeda,hb-xgmac";
  182. reg = <0xfff50000 0x1000>;
  183. interrupts = <0 77 4 0 78 4 0 79 4>;
  184. dma-coherent;
  185. };
  186. ethernet@fff51000 {
  187. compatible = "calxeda,hb-xgmac";
  188. reg = <0xfff51000 0x1000>;
  189. interrupts = <0 80 4 0 81 4 0 82 4>;
  190. dma-coherent;
  191. };
  192. combophy0: combo-phy@fff58000 {
  193. compatible = "calxeda,hb-combophy";
  194. #phy-cells = <1>;
  195. reg = <0xfff58000 0x1000>;
  196. phydev = <5>;
  197. };
  198. combophy5: combo-phy@fff5d000 {
  199. compatible = "calxeda,hb-combophy";
  200. #phy-cells = <1>;
  201. reg = <0xfff5d000 0x1000>;
  202. phydev = <31>;
  203. };
  204. };
  205. };