p54pci.c 19 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/firmware.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <net/mac80211.h>
  21. #include "p54.h"
  22. #include "p54pci.h"
  23. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  24. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  25. MODULE_LICENSE("GPL");
  26. MODULE_ALIAS("prism54pci");
  27. static struct pci_device_id p54p_table[] __devinitdata = {
  28. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  29. { PCI_DEVICE(0x1260, 0x3890) },
  30. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  31. { PCI_DEVICE(0x10b7, 0x6001) },
  32. /* Intersil PRISM Indigo Wireless LAN adapter */
  33. { PCI_DEVICE(0x1260, 0x3877) },
  34. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  35. { PCI_DEVICE(0x1260, 0x3886) },
  36. { },
  37. };
  38. MODULE_DEVICE_TABLE(pci, p54p_table);
  39. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  40. {
  41. struct p54p_priv *priv = dev->priv;
  42. const struct firmware *fw_entry = NULL;
  43. __le32 reg;
  44. int err;
  45. __le32 *data;
  46. u32 remains, left, device_addr;
  47. P54P_WRITE(int_enable, cpu_to_le32(0));
  48. P54P_READ(int_enable);
  49. udelay(10);
  50. reg = P54P_READ(ctrl_stat);
  51. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  52. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  53. P54P_WRITE(ctrl_stat, reg);
  54. P54P_READ(ctrl_stat);
  55. udelay(10);
  56. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  57. P54P_WRITE(ctrl_stat, reg);
  58. wmb();
  59. udelay(10);
  60. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  61. P54P_WRITE(ctrl_stat, reg);
  62. wmb();
  63. mdelay(50);
  64. err = request_firmware(&fw_entry, "isl3886", &priv->pdev->dev);
  65. if (err) {
  66. printk(KERN_ERR "%s (p54pci): cannot find firmware "
  67. "(isl3886)\n", pci_name(priv->pdev));
  68. return err;
  69. }
  70. p54_parse_firmware(dev, fw_entry);
  71. data = (__le32 *) fw_entry->data;
  72. remains = fw_entry->size;
  73. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  74. while (remains) {
  75. u32 i = 0;
  76. left = min((u32)0x1000, remains);
  77. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  78. P54P_READ(int_enable);
  79. device_addr += 0x1000;
  80. while (i < left) {
  81. P54P_WRITE(direct_mem_win[i], *data++);
  82. i += sizeof(u32);
  83. }
  84. remains -= left;
  85. P54P_READ(int_enable);
  86. }
  87. release_firmware(fw_entry);
  88. reg = P54P_READ(ctrl_stat);
  89. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  90. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  91. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  92. P54P_WRITE(ctrl_stat, reg);
  93. P54P_READ(ctrl_stat);
  94. udelay(10);
  95. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  96. P54P_WRITE(ctrl_stat, reg);
  97. wmb();
  98. udelay(10);
  99. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  100. P54P_WRITE(ctrl_stat, reg);
  101. wmb();
  102. udelay(10);
  103. return 0;
  104. }
  105. static irqreturn_t p54p_simple_interrupt(int irq, void *dev_id)
  106. {
  107. struct p54p_priv *priv = (struct p54p_priv *) dev_id;
  108. __le32 reg;
  109. reg = P54P_READ(int_ident);
  110. P54P_WRITE(int_ack, reg);
  111. if (reg & P54P_READ(int_enable))
  112. complete(&priv->boot_comp);
  113. return IRQ_HANDLED;
  114. }
  115. static int p54p_read_eeprom(struct ieee80211_hw *dev)
  116. {
  117. struct p54p_priv *priv = dev->priv;
  118. struct p54p_ring_control *ring_control = priv->ring_control;
  119. int err;
  120. struct p54_control_hdr *hdr;
  121. void *eeprom;
  122. dma_addr_t rx_mapping, tx_mapping;
  123. u16 alen;
  124. init_completion(&priv->boot_comp);
  125. err = request_irq(priv->pdev->irq, &p54p_simple_interrupt,
  126. IRQF_SHARED, "p54pci", priv);
  127. if (err) {
  128. printk(KERN_ERR "%s (p54pci): failed to register IRQ handler\n",
  129. pci_name(priv->pdev));
  130. return err;
  131. }
  132. eeprom = kmalloc(0x2010 + EEPROM_READBACK_LEN, GFP_KERNEL);
  133. if (!eeprom) {
  134. printk(KERN_ERR "%s (p54pci): no memory for eeprom!\n",
  135. pci_name(priv->pdev));
  136. err = -ENOMEM;
  137. goto out;
  138. }
  139. memset(ring_control, 0, sizeof(*ring_control));
  140. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  141. P54P_READ(ring_control_base);
  142. udelay(10);
  143. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  144. P54P_READ(int_enable);
  145. udelay(10);
  146. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  147. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  148. printk(KERN_ERR "%s (p54pci): Cannot boot firmware!\n",
  149. pci_name(priv->pdev));
  150. err = -EINVAL;
  151. goto out;
  152. }
  153. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  154. P54P_READ(int_enable);
  155. hdr = eeprom + 0x2010;
  156. p54_fill_eeprom_readback(hdr);
  157. hdr->req_id = cpu_to_le32(priv->common.rx_start);
  158. rx_mapping = pci_map_single(priv->pdev, eeprom,
  159. 0x2010, PCI_DMA_FROMDEVICE);
  160. tx_mapping = pci_map_single(priv->pdev, (void *)hdr,
  161. EEPROM_READBACK_LEN, PCI_DMA_TODEVICE);
  162. ring_control->rx_mgmt[0].host_addr = cpu_to_le32(rx_mapping);
  163. ring_control->rx_mgmt[0].len = cpu_to_le16(0x2010);
  164. ring_control->tx_data[0].host_addr = cpu_to_le32(tx_mapping);
  165. ring_control->tx_data[0].device_addr = hdr->req_id;
  166. ring_control->tx_data[0].len = cpu_to_le16(EEPROM_READBACK_LEN);
  167. ring_control->host_idx[2] = cpu_to_le32(1);
  168. ring_control->host_idx[1] = cpu_to_le32(1);
  169. wmb();
  170. mdelay(100);
  171. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  172. wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ);
  173. wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ);
  174. pci_unmap_single(priv->pdev, tx_mapping,
  175. EEPROM_READBACK_LEN, PCI_DMA_TODEVICE);
  176. pci_unmap_single(priv->pdev, rx_mapping,
  177. 0x2010, PCI_DMA_FROMDEVICE);
  178. alen = le16_to_cpu(ring_control->rx_mgmt[0].len);
  179. if (le32_to_cpu(ring_control->device_idx[2]) != 1 ||
  180. alen < 0x10) {
  181. printk(KERN_ERR "%s (p54pci): Cannot read eeprom!\n",
  182. pci_name(priv->pdev));
  183. err = -EINVAL;
  184. goto out;
  185. }
  186. p54_parse_eeprom(dev, (u8 *)eeprom + 0x10, alen - 0x10);
  187. out:
  188. kfree(eeprom);
  189. P54P_WRITE(int_enable, cpu_to_le32(0));
  190. P54P_READ(int_enable);
  191. udelay(10);
  192. free_irq(priv->pdev->irq, priv);
  193. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  194. return err;
  195. }
  196. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  197. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  198. struct sk_buff **rx_buf)
  199. {
  200. struct p54p_priv *priv = dev->priv;
  201. struct p54p_ring_control *ring_control = priv->ring_control;
  202. u32 limit, idx, i;
  203. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  204. limit = idx;
  205. limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
  206. limit = ring_limit - limit;
  207. i = idx % ring_limit;
  208. while (limit-- > 1) {
  209. struct p54p_desc *desc = &ring[i];
  210. if (!desc->host_addr) {
  211. struct sk_buff *skb;
  212. dma_addr_t mapping;
  213. skb = dev_alloc_skb(MAX_RX_SIZE);
  214. if (!skb)
  215. break;
  216. mapping = pci_map_single(priv->pdev,
  217. skb_tail_pointer(skb),
  218. MAX_RX_SIZE,
  219. PCI_DMA_FROMDEVICE);
  220. desc->host_addr = cpu_to_le32(mapping);
  221. desc->device_addr = 0; // FIXME: necessary?
  222. desc->len = cpu_to_le16(MAX_RX_SIZE);
  223. desc->flags = 0;
  224. rx_buf[i] = skb;
  225. }
  226. i++;
  227. idx++;
  228. i %= ring_limit;
  229. }
  230. wmb();
  231. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  232. }
  233. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  234. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  235. struct sk_buff **rx_buf)
  236. {
  237. struct p54p_priv *priv = dev->priv;
  238. struct p54p_ring_control *ring_control = priv->ring_control;
  239. struct p54p_desc *desc;
  240. u32 idx, i;
  241. i = (*index) % ring_limit;
  242. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  243. idx %= ring_limit;
  244. while (i != idx) {
  245. u16 len;
  246. struct sk_buff *skb;
  247. desc = &ring[i];
  248. len = le16_to_cpu(desc->len);
  249. skb = rx_buf[i];
  250. if (!skb)
  251. continue;
  252. skb_put(skb, len);
  253. if (p54_rx(dev, skb)) {
  254. pci_unmap_single(priv->pdev,
  255. le32_to_cpu(desc->host_addr),
  256. MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
  257. rx_buf[i] = NULL;
  258. desc->host_addr = 0;
  259. } else {
  260. skb_trim(skb, 0);
  261. desc->len = cpu_to_le16(MAX_RX_SIZE);
  262. }
  263. i++;
  264. i %= ring_limit;
  265. }
  266. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
  267. }
  268. /* caller must hold priv->lock */
  269. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  270. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  271. void **tx_buf)
  272. {
  273. struct p54p_priv *priv = dev->priv;
  274. struct p54p_ring_control *ring_control = priv->ring_control;
  275. struct p54p_desc *desc;
  276. u32 idx, i;
  277. i = (*index) % ring_limit;
  278. (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
  279. idx %= ring_limit;
  280. while (i != idx) {
  281. desc = &ring[i];
  282. kfree(tx_buf[i]);
  283. tx_buf[i] = NULL;
  284. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  285. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  286. desc->host_addr = 0;
  287. desc->device_addr = 0;
  288. desc->len = 0;
  289. desc->flags = 0;
  290. i++;
  291. i %= ring_limit;
  292. }
  293. }
  294. static void p54p_rx_tasklet(unsigned long dev_id)
  295. {
  296. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  297. struct p54p_priv *priv = dev->priv;
  298. struct p54p_ring_control *ring_control = priv->ring_control;
  299. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  300. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  301. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  302. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  303. wmb();
  304. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  305. }
  306. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  307. {
  308. struct ieee80211_hw *dev = dev_id;
  309. struct p54p_priv *priv = dev->priv;
  310. struct p54p_ring_control *ring_control = priv->ring_control;
  311. __le32 reg;
  312. spin_lock(&priv->lock);
  313. reg = P54P_READ(int_ident);
  314. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  315. spin_unlock(&priv->lock);
  316. return IRQ_HANDLED;
  317. }
  318. P54P_WRITE(int_ack, reg);
  319. reg &= P54P_READ(int_enable);
  320. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
  321. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
  322. 3, ring_control->tx_mgmt,
  323. ARRAY_SIZE(ring_control->tx_mgmt),
  324. priv->tx_buf_mgmt);
  325. p54p_check_tx_ring(dev, &priv->tx_idx_data,
  326. 1, ring_control->tx_data,
  327. ARRAY_SIZE(ring_control->tx_data),
  328. priv->tx_buf_data);
  329. tasklet_schedule(&priv->rx_tasklet);
  330. } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  331. complete(&priv->boot_comp);
  332. spin_unlock(&priv->lock);
  333. return reg ? IRQ_HANDLED : IRQ_NONE;
  334. }
  335. static void p54p_tx(struct ieee80211_hw *dev, struct p54_control_hdr *data,
  336. size_t len, int free_on_tx)
  337. {
  338. struct p54p_priv *priv = dev->priv;
  339. struct p54p_ring_control *ring_control = priv->ring_control;
  340. unsigned long flags;
  341. struct p54p_desc *desc;
  342. dma_addr_t mapping;
  343. u32 device_idx, idx, i;
  344. spin_lock_irqsave(&priv->lock, flags);
  345. device_idx = le32_to_cpu(ring_control->device_idx[1]);
  346. idx = le32_to_cpu(ring_control->host_idx[1]);
  347. i = idx % ARRAY_SIZE(ring_control->tx_data);
  348. mapping = pci_map_single(priv->pdev, data, len, PCI_DMA_TODEVICE);
  349. desc = &ring_control->tx_data[i];
  350. desc->host_addr = cpu_to_le32(mapping);
  351. desc->device_addr = data->req_id;
  352. desc->len = cpu_to_le16(len);
  353. desc->flags = 0;
  354. wmb();
  355. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  356. if (free_on_tx)
  357. priv->tx_buf_data[i] = data;
  358. spin_unlock_irqrestore(&priv->lock, flags);
  359. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  360. P54P_READ(dev_int);
  361. /* FIXME: unlikely to happen because the device usually runs out of
  362. memory before we fill the ring up, but we can make it impossible */
  363. if (idx - device_idx > ARRAY_SIZE(ring_control->tx_data) - 2)
  364. printk(KERN_INFO "%s: tx overflow.\n", wiphy_name(dev->wiphy));
  365. }
  366. static int p54p_open(struct ieee80211_hw *dev)
  367. {
  368. struct p54p_priv *priv = dev->priv;
  369. int err;
  370. init_completion(&priv->boot_comp);
  371. err = request_irq(priv->pdev->irq, &p54p_interrupt,
  372. IRQF_SHARED, "p54pci", dev);
  373. if (err) {
  374. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  375. wiphy_name(dev->wiphy));
  376. return err;
  377. }
  378. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  379. priv->rx_idx_data = priv->tx_idx_data = 0;
  380. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  381. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  382. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
  383. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  384. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
  385. p54p_upload_firmware(dev);
  386. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  387. P54P_READ(ring_control_base);
  388. wmb();
  389. udelay(10);
  390. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  391. P54P_READ(int_enable);
  392. wmb();
  393. udelay(10);
  394. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  395. P54P_READ(dev_int);
  396. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  397. printk(KERN_ERR "%s: Cannot boot firmware!\n",
  398. wiphy_name(dev->wiphy));
  399. free_irq(priv->pdev->irq, dev);
  400. return -ETIMEDOUT;
  401. }
  402. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  403. P54P_READ(int_enable);
  404. wmb();
  405. udelay(10);
  406. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  407. P54P_READ(dev_int);
  408. wmb();
  409. udelay(10);
  410. return 0;
  411. }
  412. static void p54p_stop(struct ieee80211_hw *dev)
  413. {
  414. struct p54p_priv *priv = dev->priv;
  415. struct p54p_ring_control *ring_control = priv->ring_control;
  416. unsigned int i;
  417. struct p54p_desc *desc;
  418. tasklet_kill(&priv->rx_tasklet);
  419. P54P_WRITE(int_enable, cpu_to_le32(0));
  420. P54P_READ(int_enable);
  421. udelay(10);
  422. free_irq(priv->pdev->irq, dev);
  423. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  424. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  425. desc = &ring_control->rx_data[i];
  426. if (desc->host_addr)
  427. pci_unmap_single(priv->pdev,
  428. le32_to_cpu(desc->host_addr),
  429. MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
  430. kfree_skb(priv->rx_buf_data[i]);
  431. priv->rx_buf_data[i] = NULL;
  432. }
  433. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  434. desc = &ring_control->rx_mgmt[i];
  435. if (desc->host_addr)
  436. pci_unmap_single(priv->pdev,
  437. le32_to_cpu(desc->host_addr),
  438. MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
  439. kfree_skb(priv->rx_buf_mgmt[i]);
  440. priv->rx_buf_mgmt[i] = NULL;
  441. }
  442. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  443. desc = &ring_control->tx_data[i];
  444. if (desc->host_addr)
  445. pci_unmap_single(priv->pdev,
  446. le32_to_cpu(desc->host_addr),
  447. le16_to_cpu(desc->len),
  448. PCI_DMA_TODEVICE);
  449. kfree(priv->tx_buf_data[i]);
  450. priv->tx_buf_data[i] = NULL;
  451. }
  452. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  453. desc = &ring_control->tx_mgmt[i];
  454. if (desc->host_addr)
  455. pci_unmap_single(priv->pdev,
  456. le32_to_cpu(desc->host_addr),
  457. le16_to_cpu(desc->len),
  458. PCI_DMA_TODEVICE);
  459. kfree(priv->tx_buf_mgmt[i]);
  460. priv->tx_buf_mgmt[i] = NULL;
  461. }
  462. memset(ring_control, 0, sizeof(*ring_control));
  463. }
  464. static int __devinit p54p_probe(struct pci_dev *pdev,
  465. const struct pci_device_id *id)
  466. {
  467. struct p54p_priv *priv;
  468. struct ieee80211_hw *dev;
  469. unsigned long mem_addr, mem_len;
  470. int err;
  471. DECLARE_MAC_BUF(mac);
  472. err = pci_enable_device(pdev);
  473. if (err) {
  474. printk(KERN_ERR "%s (p54pci): Cannot enable new PCI device\n",
  475. pci_name(pdev));
  476. return err;
  477. }
  478. mem_addr = pci_resource_start(pdev, 0);
  479. mem_len = pci_resource_len(pdev, 0);
  480. if (mem_len < sizeof(struct p54p_csr)) {
  481. printk(KERN_ERR "%s (p54pci): Too short PCI resources\n",
  482. pci_name(pdev));
  483. pci_disable_device(pdev);
  484. return err;
  485. }
  486. err = pci_request_regions(pdev, "p54pci");
  487. if (err) {
  488. printk(KERN_ERR "%s (p54pci): Cannot obtain PCI resources\n",
  489. pci_name(pdev));
  490. return err;
  491. }
  492. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
  493. pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
  494. printk(KERN_ERR "%s (p54pci): No suitable DMA available\n",
  495. pci_name(pdev));
  496. goto err_free_reg;
  497. }
  498. pci_set_master(pdev);
  499. pci_try_set_mwi(pdev);
  500. pci_write_config_byte(pdev, 0x40, 0);
  501. pci_write_config_byte(pdev, 0x41, 0);
  502. dev = p54_init_common(sizeof(*priv));
  503. if (!dev) {
  504. printk(KERN_ERR "%s (p54pci): ieee80211 alloc failed\n",
  505. pci_name(pdev));
  506. err = -ENOMEM;
  507. goto err_free_reg;
  508. }
  509. priv = dev->priv;
  510. priv->pdev = pdev;
  511. SET_IEEE80211_DEV(dev, &pdev->dev);
  512. pci_set_drvdata(pdev, dev);
  513. priv->map = ioremap(mem_addr, mem_len);
  514. if (!priv->map) {
  515. printk(KERN_ERR "%s (p54pci): Cannot map device memory\n",
  516. pci_name(pdev));
  517. err = -EINVAL; // TODO: use a better error code?
  518. goto err_free_dev;
  519. }
  520. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  521. &priv->ring_control_dma);
  522. if (!priv->ring_control) {
  523. printk(KERN_ERR "%s (p54pci): Cannot allocate rings\n",
  524. pci_name(pdev));
  525. err = -ENOMEM;
  526. goto err_iounmap;
  527. }
  528. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  529. err = p54p_upload_firmware(dev);
  530. if (err)
  531. goto err_free_desc;
  532. err = p54p_read_eeprom(dev);
  533. if (err)
  534. goto err_free_desc;
  535. priv->common.open = p54p_open;
  536. priv->common.stop = p54p_stop;
  537. priv->common.tx = p54p_tx;
  538. spin_lock_init(&priv->lock);
  539. tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
  540. err = ieee80211_register_hw(dev);
  541. if (err) {
  542. printk(KERN_ERR "%s (p54pci): Cannot register netdevice\n",
  543. pci_name(pdev));
  544. goto err_free_common;
  545. }
  546. printk(KERN_INFO "%s: hwaddr %s, isl38%02x\n",
  547. wiphy_name(dev->wiphy),
  548. print_mac(mac, dev->wiphy->perm_addr),
  549. priv->common.version);
  550. return 0;
  551. err_free_common:
  552. p54_free_common(dev);
  553. err_free_desc:
  554. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  555. priv->ring_control, priv->ring_control_dma);
  556. err_iounmap:
  557. iounmap(priv->map);
  558. err_free_dev:
  559. pci_set_drvdata(pdev, NULL);
  560. ieee80211_free_hw(dev);
  561. err_free_reg:
  562. pci_release_regions(pdev);
  563. pci_disable_device(pdev);
  564. return err;
  565. }
  566. static void __devexit p54p_remove(struct pci_dev *pdev)
  567. {
  568. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  569. struct p54p_priv *priv;
  570. if (!dev)
  571. return;
  572. ieee80211_unregister_hw(dev);
  573. priv = dev->priv;
  574. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  575. priv->ring_control, priv->ring_control_dma);
  576. p54_free_common(dev);
  577. iounmap(priv->map);
  578. pci_release_regions(pdev);
  579. pci_disable_device(pdev);
  580. ieee80211_free_hw(dev);
  581. }
  582. #ifdef CONFIG_PM
  583. static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
  584. {
  585. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  586. struct p54p_priv *priv = dev->priv;
  587. if (priv->common.mode != IEEE80211_IF_TYPE_INVALID) {
  588. ieee80211_stop_queues(dev);
  589. p54p_stop(dev);
  590. }
  591. pci_save_state(pdev);
  592. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  593. return 0;
  594. }
  595. static int p54p_resume(struct pci_dev *pdev)
  596. {
  597. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  598. struct p54p_priv *priv = dev->priv;
  599. pci_set_power_state(pdev, PCI_D0);
  600. pci_restore_state(pdev);
  601. if (priv->common.mode != IEEE80211_IF_TYPE_INVALID) {
  602. p54p_open(dev);
  603. ieee80211_wake_queues(dev);
  604. }
  605. return 0;
  606. }
  607. #endif /* CONFIG_PM */
  608. static struct pci_driver p54p_driver = {
  609. .name = "p54pci",
  610. .id_table = p54p_table,
  611. .probe = p54p_probe,
  612. .remove = __devexit_p(p54p_remove),
  613. #ifdef CONFIG_PM
  614. .suspend = p54p_suspend,
  615. .resume = p54p_resume,
  616. #endif /* CONFIG_PM */
  617. };
  618. static int __init p54p_init(void)
  619. {
  620. return pci_register_driver(&p54p_driver);
  621. }
  622. static void __exit p54p_exit(void)
  623. {
  624. pci_unregister_driver(&p54p_driver);
  625. }
  626. module_init(p54p_init);
  627. module_exit(p54p_exit);