pm24xx.c 9.7 KB

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  1. /*
  2. * OMAP2 Power Management Routines
  3. *
  4. * Copyright (C) 2005 Texas Instruments, Inc.
  5. * Copyright (C) 2006-2008 Nokia Corporation
  6. *
  7. * Written by:
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. * Tony Lindgren
  10. * Juha Yrjola
  11. * Amit Kucheria <amit.kucheria@nokia.com>
  12. * Igor Stoppa <igor.stoppa@nokia.com>
  13. *
  14. * Based on pm.c for omap1
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/suspend.h>
  21. #include <linux/sched.h>
  22. #include <linux/proc_fs.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/sysfs.h>
  25. #include <linux/module.h>
  26. #include <linux/delay.h>
  27. #include <linux/clk.h>
  28. #include <linux/irq.h>
  29. #include <linux/time.h>
  30. #include <linux/gpio.h>
  31. #include <asm/mach/time.h>
  32. #include <asm/mach/irq.h>
  33. #include <asm/mach-types.h>
  34. #include <plat/clock.h>
  35. #include <plat/sram.h>
  36. #include <plat/dma.h>
  37. #include <plat/board.h>
  38. #include <mach/irqs.h>
  39. #include "common.h"
  40. #include "prm2xxx_3xxx.h"
  41. #include "prm-regbits-24xx.h"
  42. #include "cm2xxx_3xxx.h"
  43. #include "cm-regbits-24xx.h"
  44. #include "sdrc.h"
  45. #include "pm.h"
  46. #include "control.h"
  47. #include "powerdomain.h"
  48. #include "clockdomain.h"
  49. static void (*omap2_sram_idle)(void);
  50. static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  51. void __iomem *sdrc_power);
  52. static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  53. static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  54. static struct clk *osc_ck, *emul_ck;
  55. static int omap2_fclks_active(void)
  56. {
  57. u32 f1, f2;
  58. f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  59. f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  60. return (f1 | f2) ? 1 : 0;
  61. }
  62. static int omap2_enter_full_retention(void)
  63. {
  64. u32 l;
  65. /* There is 1 reference hold for all children of the oscillator
  66. * clock, the following will remove it. If no one else uses the
  67. * oscillator itself it will be disabled if/when we enter retention
  68. * mode.
  69. */
  70. clk_disable(osc_ck);
  71. /* Clear old wake-up events */
  72. /* REVISIT: These write to reserved bits? */
  73. omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  74. omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  75. omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  76. /*
  77. * Set MPU powerdomain's next power state to RETENTION;
  78. * preserve logic state during retention
  79. */
  80. pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
  81. pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
  82. /* Workaround to kill USB */
  83. l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
  84. omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
  85. omap2_gpio_prepare_for_idle(0);
  86. /* One last check for pending IRQs to avoid extra latency due
  87. * to sleeping unnecessarily. */
  88. if (omap_irq_pending())
  89. goto no_sleep;
  90. /* Jump to SRAM suspend code */
  91. omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
  92. OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
  93. OMAP_SDRC_REGADDR(SDRC_POWER));
  94. no_sleep:
  95. omap2_gpio_resume_after_idle();
  96. clk_enable(osc_ck);
  97. /* clear CORE wake-up events */
  98. omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  99. omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  100. /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
  101. omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
  102. /* MPU domain wake events */
  103. l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
  104. if (l & 0x01)
  105. omap2_prm_write_mod_reg(0x01, OCP_MOD,
  106. OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
  107. if (l & 0x20)
  108. omap2_prm_write_mod_reg(0x20, OCP_MOD,
  109. OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
  110. /* Mask future PRCM-to-MPU interrupts */
  111. omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
  112. return 0;
  113. }
  114. static int omap2_i2c_active(void)
  115. {
  116. u32 l;
  117. l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  118. return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
  119. }
  120. static int sti_console_enabled;
  121. static int omap2_allow_mpu_retention(void)
  122. {
  123. u32 l;
  124. /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
  125. l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  126. if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
  127. OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
  128. OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
  129. return 0;
  130. /* Check for UART3. */
  131. l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  132. if (l & OMAP24XX_EN_UART3_MASK)
  133. return 0;
  134. if (sti_console_enabled)
  135. return 0;
  136. return 1;
  137. }
  138. static void omap2_enter_mpu_retention(void)
  139. {
  140. int only_idle = 0;
  141. /* Putting MPU into the WFI state while a transfer is active
  142. * seems to cause the I2C block to timeout. Why? Good question. */
  143. if (omap2_i2c_active())
  144. return;
  145. /* The peripherals seem not to be able to wake up the MPU when
  146. * it is in retention mode. */
  147. if (omap2_allow_mpu_retention()) {
  148. /* REVISIT: These write to reserved bits? */
  149. omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  150. omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  151. omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  152. /* Try to enter MPU retention */
  153. omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
  154. OMAP_LOGICRETSTATE_MASK,
  155. MPU_MOD, OMAP2_PM_PWSTCTRL);
  156. } else {
  157. /* Block MPU retention */
  158. omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
  159. OMAP2_PM_PWSTCTRL);
  160. only_idle = 1;
  161. }
  162. omap2_sram_idle();
  163. }
  164. static int omap2_can_sleep(void)
  165. {
  166. if (omap2_fclks_active())
  167. return 0;
  168. if (osc_ck->usecount > 1)
  169. return 0;
  170. if (omap_dma_running())
  171. return 0;
  172. return 1;
  173. }
  174. static void omap2_pm_idle(void)
  175. {
  176. local_fiq_disable();
  177. if (!omap2_can_sleep()) {
  178. if (omap_irq_pending())
  179. goto out;
  180. omap2_enter_mpu_retention();
  181. goto out;
  182. }
  183. if (omap_irq_pending())
  184. goto out;
  185. omap2_enter_full_retention();
  186. out:
  187. local_fiq_enable();
  188. }
  189. static void __init prcm_setup_regs(void)
  190. {
  191. int i, num_mem_banks;
  192. struct powerdomain *pwrdm;
  193. /*
  194. * Enable autoidle
  195. * XXX This should be handled by hwmod code or PRCM init code
  196. */
  197. omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
  198. OMAP2_PRCM_SYSCONFIG_OFFSET);
  199. /*
  200. * Set CORE powerdomain memory banks to retain their contents
  201. * during RETENTION
  202. */
  203. num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
  204. for (i = 0; i < num_mem_banks; i++)
  205. pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
  206. /* Set CORE powerdomain's next power state to RETENTION */
  207. pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
  208. /*
  209. * Set MPU powerdomain's next power state to RETENTION;
  210. * preserve logic state during retention
  211. */
  212. pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
  213. pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
  214. /* Force-power down DSP, GFX powerdomains */
  215. pwrdm = clkdm_get_pwrdm(dsp_clkdm);
  216. pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
  217. clkdm_sleep(dsp_clkdm);
  218. pwrdm = clkdm_get_pwrdm(gfx_clkdm);
  219. pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
  220. clkdm_sleep(gfx_clkdm);
  221. /* Enable hardware-supervised idle for all clkdms */
  222. clkdm_for_each(omap_pm_clkdms_setup, NULL);
  223. clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
  224. #ifdef CONFIG_SUSPEND
  225. omap_pm_suspend = omap2_enter_full_retention;
  226. #endif
  227. /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
  228. * stabilisation */
  229. omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
  230. OMAP2_PRCM_CLKSSETUP_OFFSET);
  231. /* Configure automatic voltage transition */
  232. omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
  233. OMAP2_PRCM_VOLTSETUP_OFFSET);
  234. omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
  235. (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
  236. OMAP24XX_MEMRETCTRL_MASK |
  237. (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
  238. (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
  239. OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
  240. /* Enable wake-up events */
  241. omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
  242. WKUP_MOD, PM_WKEN);
  243. }
  244. static int __init omap2_pm_init(void)
  245. {
  246. u32 l;
  247. if (!cpu_is_omap24xx())
  248. return -ENODEV;
  249. printk(KERN_INFO "Power Management for OMAP2 initializing\n");
  250. l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
  251. printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
  252. /* Look up important powerdomains */
  253. mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
  254. if (!mpu_pwrdm)
  255. pr_err("PM: mpu_pwrdm not found\n");
  256. core_pwrdm = pwrdm_lookup("core_pwrdm");
  257. if (!core_pwrdm)
  258. pr_err("PM: core_pwrdm not found\n");
  259. /* Look up important clockdomains */
  260. mpu_clkdm = clkdm_lookup("mpu_clkdm");
  261. if (!mpu_clkdm)
  262. pr_err("PM: mpu_clkdm not found\n");
  263. wkup_clkdm = clkdm_lookup("wkup_clkdm");
  264. if (!wkup_clkdm)
  265. pr_err("PM: wkup_clkdm not found\n");
  266. dsp_clkdm = clkdm_lookup("dsp_clkdm");
  267. if (!dsp_clkdm)
  268. pr_err("PM: dsp_clkdm not found\n");
  269. gfx_clkdm = clkdm_lookup("gfx_clkdm");
  270. if (!gfx_clkdm)
  271. pr_err("PM: gfx_clkdm not found\n");
  272. osc_ck = clk_get(NULL, "osc_ck");
  273. if (IS_ERR(osc_ck)) {
  274. printk(KERN_ERR "could not get osc_ck\n");
  275. return -ENODEV;
  276. }
  277. if (cpu_is_omap242x()) {
  278. emul_ck = clk_get(NULL, "emul_ck");
  279. if (IS_ERR(emul_ck)) {
  280. printk(KERN_ERR "could not get emul_ck\n");
  281. clk_put(osc_ck);
  282. return -ENODEV;
  283. }
  284. }
  285. prcm_setup_regs();
  286. /* Hack to prevent MPU retention when STI console is enabled. */
  287. {
  288. const struct omap_sti_console_config *sti;
  289. sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
  290. struct omap_sti_console_config);
  291. if (sti != NULL && sti->enable)
  292. sti_console_enabled = 1;
  293. }
  294. /*
  295. * We copy the assembler sleep/wakeup routines to SRAM.
  296. * These routines need to be in SRAM as that's the only
  297. * memory the MPU can see when it wakes up.
  298. */
  299. if (cpu_is_omap24xx()) {
  300. omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
  301. omap24xx_idle_loop_suspend_sz);
  302. omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
  303. omap24xx_cpu_suspend_sz);
  304. }
  305. arm_pm_idle = omap2_pm_idle;
  306. return 0;
  307. }
  308. late_initcall(omap2_pm_init);