radeon_test.c 13 KB

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  1. /*
  2. * Copyright 2009 VMware, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Michel Dänzer
  23. */
  24. #include <drm/drmP.h>
  25. #include <drm/radeon_drm.h>
  26. #include "radeon_reg.h"
  27. #include "radeon.h"
  28. /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
  29. void radeon_test_moves(struct radeon_device *rdev)
  30. {
  31. struct radeon_bo *vram_obj = NULL;
  32. struct radeon_bo **gtt_obj = NULL;
  33. struct radeon_fence *fence = NULL;
  34. uint64_t gtt_addr, vram_addr;
  35. unsigned i, n, size;
  36. int r;
  37. size = 1024 * 1024;
  38. /* Number of tests =
  39. * (Total GTT - IB pool - writeback page - ring buffers) / test size
  40. */
  41. n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024;
  42. for (i = 0; i < RADEON_NUM_RINGS; ++i)
  43. n -= rdev->ring[i].ring_size;
  44. if (rdev->wb.wb_obj)
  45. n -= RADEON_GPU_PAGE_SIZE;
  46. if (rdev->ih.ring_obj)
  47. n -= rdev->ih.ring_size;
  48. n /= size;
  49. gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
  50. if (!gtt_obj) {
  51. DRM_ERROR("Failed to allocate %d pointers\n", n);
  52. r = 1;
  53. goto out_cleanup;
  54. }
  55. r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  56. NULL, &vram_obj);
  57. if (r) {
  58. DRM_ERROR("Failed to create VRAM object\n");
  59. goto out_cleanup;
  60. }
  61. r = radeon_bo_reserve(vram_obj, false);
  62. if (unlikely(r != 0))
  63. goto out_cleanup;
  64. r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);
  65. if (r) {
  66. DRM_ERROR("Failed to pin VRAM object\n");
  67. goto out_cleanup;
  68. }
  69. for (i = 0; i < n; i++) {
  70. void *gtt_map, *vram_map;
  71. void **gtt_start, **gtt_end;
  72. void **vram_start, **vram_end;
  73. r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
  74. RADEON_GEM_DOMAIN_GTT, NULL, gtt_obj + i);
  75. if (r) {
  76. DRM_ERROR("Failed to create GTT object %d\n", i);
  77. goto out_cleanup;
  78. }
  79. r = radeon_bo_reserve(gtt_obj[i], false);
  80. if (unlikely(r != 0))
  81. goto out_cleanup;
  82. r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, &gtt_addr);
  83. if (r) {
  84. DRM_ERROR("Failed to pin GTT object %d\n", i);
  85. goto out_cleanup;
  86. }
  87. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  88. if (r) {
  89. DRM_ERROR("Failed to map GTT object %d\n", i);
  90. goto out_cleanup;
  91. }
  92. for (gtt_start = gtt_map, gtt_end = gtt_map + size;
  93. gtt_start < gtt_end;
  94. gtt_start++)
  95. *gtt_start = gtt_start;
  96. radeon_bo_kunmap(gtt_obj[i]);
  97. r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  98. if (r) {
  99. DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
  100. goto out_cleanup;
  101. }
  102. r = radeon_fence_wait(fence, false);
  103. if (r) {
  104. DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
  105. goto out_cleanup;
  106. }
  107. radeon_fence_unref(&fence);
  108. r = radeon_bo_kmap(vram_obj, &vram_map);
  109. if (r) {
  110. DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
  111. goto out_cleanup;
  112. }
  113. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  114. vram_start = vram_map, vram_end = vram_map + size;
  115. vram_start < vram_end;
  116. gtt_start++, vram_start++) {
  117. if (*vram_start != gtt_start) {
  118. DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
  119. "expected 0x%p (GTT/VRAM offset "
  120. "0x%16llx/0x%16llx)\n",
  121. i, *vram_start, gtt_start,
  122. (unsigned long long)
  123. (gtt_addr - rdev->mc.gtt_start +
  124. (void*)gtt_start - gtt_map),
  125. (unsigned long long)
  126. (vram_addr - rdev->mc.vram_start +
  127. (void*)gtt_start - gtt_map));
  128. radeon_bo_kunmap(vram_obj);
  129. goto out_cleanup;
  130. }
  131. *vram_start = vram_start;
  132. }
  133. radeon_bo_kunmap(vram_obj);
  134. r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  135. if (r) {
  136. DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
  137. goto out_cleanup;
  138. }
  139. r = radeon_fence_wait(fence, false);
  140. if (r) {
  141. DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
  142. goto out_cleanup;
  143. }
  144. radeon_fence_unref(&fence);
  145. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  146. if (r) {
  147. DRM_ERROR("Failed to map GTT object after copy %d\n", i);
  148. goto out_cleanup;
  149. }
  150. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  151. vram_start = vram_map, vram_end = vram_map + size;
  152. gtt_start < gtt_end;
  153. gtt_start++, vram_start++) {
  154. if (*gtt_start != vram_start) {
  155. DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
  156. "expected 0x%p (VRAM/GTT offset "
  157. "0x%16llx/0x%16llx)\n",
  158. i, *gtt_start, vram_start,
  159. (unsigned long long)
  160. (vram_addr - rdev->mc.vram_start +
  161. (void*)vram_start - vram_map),
  162. (unsigned long long)
  163. (gtt_addr - rdev->mc.gtt_start +
  164. (void*)vram_start - vram_map));
  165. radeon_bo_kunmap(gtt_obj[i]);
  166. goto out_cleanup;
  167. }
  168. }
  169. radeon_bo_kunmap(gtt_obj[i]);
  170. DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
  171. gtt_addr - rdev->mc.gtt_start);
  172. }
  173. out_cleanup:
  174. if (vram_obj) {
  175. if (radeon_bo_is_reserved(vram_obj)) {
  176. radeon_bo_unpin(vram_obj);
  177. radeon_bo_unreserve(vram_obj);
  178. }
  179. radeon_bo_unref(&vram_obj);
  180. }
  181. if (gtt_obj) {
  182. for (i = 0; i < n; i++) {
  183. if (gtt_obj[i]) {
  184. if (radeon_bo_is_reserved(gtt_obj[i])) {
  185. radeon_bo_unpin(gtt_obj[i]);
  186. radeon_bo_unreserve(gtt_obj[i]);
  187. }
  188. radeon_bo_unref(&gtt_obj[i]);
  189. }
  190. }
  191. kfree(gtt_obj);
  192. }
  193. if (fence) {
  194. radeon_fence_unref(&fence);
  195. }
  196. if (r) {
  197. printk(KERN_WARNING "Error while testing BO move.\n");
  198. }
  199. }
  200. void radeon_test_ring_sync(struct radeon_device *rdev,
  201. struct radeon_ring *ringA,
  202. struct radeon_ring *ringB)
  203. {
  204. struct radeon_fence *fence1 = NULL, *fence2 = NULL;
  205. struct radeon_semaphore *semaphore = NULL;
  206. int r;
  207. r = radeon_semaphore_create(rdev, &semaphore);
  208. if (r) {
  209. DRM_ERROR("Failed to create semaphore\n");
  210. goto out_cleanup;
  211. }
  212. r = radeon_ring_lock(rdev, ringA, 64);
  213. if (r) {
  214. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  215. goto out_cleanup;
  216. }
  217. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  218. r = radeon_fence_emit(rdev, &fence1, ringA->idx);
  219. if (r) {
  220. DRM_ERROR("Failed to emit fence 1\n");
  221. radeon_ring_unlock_undo(rdev, ringA);
  222. goto out_cleanup;
  223. }
  224. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  225. r = radeon_fence_emit(rdev, &fence2, ringA->idx);
  226. if (r) {
  227. DRM_ERROR("Failed to emit fence 2\n");
  228. radeon_ring_unlock_undo(rdev, ringA);
  229. goto out_cleanup;
  230. }
  231. radeon_ring_unlock_commit(rdev, ringA);
  232. mdelay(1000);
  233. if (radeon_fence_signaled(fence1)) {
  234. DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
  235. goto out_cleanup;
  236. }
  237. r = radeon_ring_lock(rdev, ringB, 64);
  238. if (r) {
  239. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  240. goto out_cleanup;
  241. }
  242. radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
  243. radeon_ring_unlock_commit(rdev, ringB);
  244. r = radeon_fence_wait(fence1, false);
  245. if (r) {
  246. DRM_ERROR("Failed to wait for sync fence 1\n");
  247. goto out_cleanup;
  248. }
  249. mdelay(1000);
  250. if (radeon_fence_signaled(fence2)) {
  251. DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
  252. goto out_cleanup;
  253. }
  254. r = radeon_ring_lock(rdev, ringB, 64);
  255. if (r) {
  256. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  257. goto out_cleanup;
  258. }
  259. radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
  260. radeon_ring_unlock_commit(rdev, ringB);
  261. r = radeon_fence_wait(fence2, false);
  262. if (r) {
  263. DRM_ERROR("Failed to wait for sync fence 1\n");
  264. goto out_cleanup;
  265. }
  266. out_cleanup:
  267. radeon_semaphore_free(rdev, &semaphore, NULL);
  268. if (fence1)
  269. radeon_fence_unref(&fence1);
  270. if (fence2)
  271. radeon_fence_unref(&fence2);
  272. if (r)
  273. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  274. }
  275. static void radeon_test_ring_sync2(struct radeon_device *rdev,
  276. struct radeon_ring *ringA,
  277. struct radeon_ring *ringB,
  278. struct radeon_ring *ringC)
  279. {
  280. struct radeon_fence *fenceA = NULL, *fenceB = NULL;
  281. struct radeon_semaphore *semaphore = NULL;
  282. bool sigA, sigB;
  283. int i, r;
  284. r = radeon_semaphore_create(rdev, &semaphore);
  285. if (r) {
  286. DRM_ERROR("Failed to create semaphore\n");
  287. goto out_cleanup;
  288. }
  289. r = radeon_ring_lock(rdev, ringA, 64);
  290. if (r) {
  291. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  292. goto out_cleanup;
  293. }
  294. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  295. r = radeon_fence_emit(rdev, &fenceA, ringA->idx);
  296. if (r) {
  297. DRM_ERROR("Failed to emit sync fence 1\n");
  298. radeon_ring_unlock_undo(rdev, ringA);
  299. goto out_cleanup;
  300. }
  301. radeon_ring_unlock_commit(rdev, ringA);
  302. r = radeon_ring_lock(rdev, ringB, 64);
  303. if (r) {
  304. DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
  305. goto out_cleanup;
  306. }
  307. radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore);
  308. r = radeon_fence_emit(rdev, &fenceB, ringB->idx);
  309. if (r) {
  310. DRM_ERROR("Failed to create sync fence 2\n");
  311. radeon_ring_unlock_undo(rdev, ringB);
  312. goto out_cleanup;
  313. }
  314. radeon_ring_unlock_commit(rdev, ringB);
  315. mdelay(1000);
  316. if (radeon_fence_signaled(fenceA)) {
  317. DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
  318. goto out_cleanup;
  319. }
  320. if (radeon_fence_signaled(fenceB)) {
  321. DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
  322. goto out_cleanup;
  323. }
  324. r = radeon_ring_lock(rdev, ringC, 64);
  325. if (r) {
  326. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  327. goto out_cleanup;
  328. }
  329. radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
  330. radeon_ring_unlock_commit(rdev, ringC);
  331. for (i = 0; i < 30; ++i) {
  332. mdelay(100);
  333. sigA = radeon_fence_signaled(fenceA);
  334. sigB = radeon_fence_signaled(fenceB);
  335. if (sigA || sigB)
  336. break;
  337. }
  338. if (!sigA && !sigB) {
  339. DRM_ERROR("Neither fence A nor B has been signaled\n");
  340. goto out_cleanup;
  341. } else if (sigA && sigB) {
  342. DRM_ERROR("Both fence A and B has been signaled\n");
  343. goto out_cleanup;
  344. }
  345. DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
  346. r = radeon_ring_lock(rdev, ringC, 64);
  347. if (r) {
  348. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  349. goto out_cleanup;
  350. }
  351. radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
  352. radeon_ring_unlock_commit(rdev, ringC);
  353. mdelay(1000);
  354. r = radeon_fence_wait(fenceA, false);
  355. if (r) {
  356. DRM_ERROR("Failed to wait for sync fence A\n");
  357. goto out_cleanup;
  358. }
  359. r = radeon_fence_wait(fenceB, false);
  360. if (r) {
  361. DRM_ERROR("Failed to wait for sync fence B\n");
  362. goto out_cleanup;
  363. }
  364. out_cleanup:
  365. radeon_semaphore_free(rdev, &semaphore, NULL);
  366. if (fenceA)
  367. radeon_fence_unref(&fenceA);
  368. if (fenceB)
  369. radeon_fence_unref(&fenceB);
  370. if (r)
  371. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  372. }
  373. void radeon_test_syncing(struct radeon_device *rdev)
  374. {
  375. int i, j, k;
  376. for (i = 1; i < RADEON_NUM_RINGS; ++i) {
  377. struct radeon_ring *ringA = &rdev->ring[i];
  378. if (!ringA->ready)
  379. continue;
  380. for (j = 0; j < i; ++j) {
  381. struct radeon_ring *ringB = &rdev->ring[j];
  382. if (!ringB->ready)
  383. continue;
  384. DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
  385. radeon_test_ring_sync(rdev, ringA, ringB);
  386. DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
  387. radeon_test_ring_sync(rdev, ringB, ringA);
  388. for (k = 0; k < j; ++k) {
  389. struct radeon_ring *ringC = &rdev->ring[k];
  390. if (!ringC->ready)
  391. continue;
  392. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
  393. radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
  394. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
  395. radeon_test_ring_sync2(rdev, ringA, ringC, ringB);
  396. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
  397. radeon_test_ring_sync2(rdev, ringB, ringA, ringC);
  398. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
  399. radeon_test_ring_sync2(rdev, ringB, ringC, ringA);
  400. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
  401. radeon_test_ring_sync2(rdev, ringC, ringA, ringB);
  402. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
  403. radeon_test_ring_sync2(rdev, ringC, ringB, ringA);
  404. }
  405. }
  406. }
  407. }