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radeon_asic.h

radeon_asic.h 22 KB
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  1. /*
    2. 

  2.  * Copyright 2008 Advanced Micro Devices, Inc.
    3. 

  3.  * Copyright 2008 Red Hat Inc.
    4. 

  4.  * Copyright 2009 Jerome Glisse.
    5. 

  5.  *
    6. 

  6.  * Permission is hereby granted, free of charge, to any person obtaining a
    7. 

  7.  * copy of this software and associated documentation files (the "Software"),
    8. 

  8.  * to deal in the Software without restriction, including without limitation
    9. 

  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    10. 

  10.  * and/or sell copies of the Software, and to permit persons to whom the
    11. 

  11.  * Software is furnished to do so, subject to the following conditions:
    12. 

  12.  *
    13. 

  13.  * The above copyright notice and this permission notice shall be included in
    14. 

  14.  * all copies or substantial portions of the Software.
    15. 

  15.  *
    16. 

  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    17. 

  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    18. 

  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
    19. 

  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
    20. 

  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
    21. 

  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
    22. 

  22.  * OTHER DEALINGS IN THE SOFTWARE.
    23. 

  23.  *
    24. 

  24.  * Authors: Dave Airlie
    25. 

  25.  *          Alex Deucher
    26. 

  26.  *          Jerome Glisse
    27. 

  27.  */
    28. 

  28. #ifndef __RADEON_ASIC_H__
    29. 

  29. #define __RADEON_ASIC_H__
    30. 

  30. 

  31. /*
    32. 

  32.  * common functions
    33. 

  33.  */
    34. 

  34. uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
    35. 

  35. void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
    36. 

  36. uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
    37. 

  37. void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
    38. 

  38. 

  39. uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
    40. 

  40. void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
    41. 

  41. uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
    42. 

  42. void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
    43. 

  43. void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
    44. 

  44. 

  45. void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
    46. 

  46. u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
    47. 

  47. void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
    48. 

  48. u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
    49. 

  49. 

  50. 

  51. /*
    52. 

  52.  * r100,rv100,rs100,rv200,rs200
    53. 

  53.  */
    54. 

  54. struct r100_mc_save {
    55. 

  55. 	u32	GENMO_WT;
    56. 

  56. 	u32	CRTC_EXT_CNTL;
    57. 

  57. 	u32	CRTC_GEN_CNTL;
    58. 

  58. 	u32	CRTC2_GEN_CNTL;
    59. 

  59. 	u32	CUR_OFFSET;
    60. 

  60. 	u32	CUR2_OFFSET;
    61. 

  61. };
    62. 

  62. int r100_init(struct radeon_device *rdev);
    63. 

  63. void r100_fini(struct radeon_device *rdev);
    64. 

  64. int r100_suspend(struct radeon_device *rdev);
    65. 

  65. int r100_resume(struct radeon_device *rdev);
    66. 

  66. void r100_vga_set_state(struct radeon_device *rdev, bool state);
    67. 

  67. bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    68. 

  68. int r100_asic_reset(struct radeon_device *rdev);
    69. 

  69. u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
    70. 

  70. void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
    71. 

  71. int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    72. 

  72. void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
    73. 

  73. int r100_irq_set(struct radeon_device *rdev);
    74. 

  74. int r100_irq_process(struct radeon_device *rdev);
    75. 

  75. void r100_fence_ring_emit(struct radeon_device *rdev,
    76. 

  76. 			  struct radeon_fence *fence);
    77. 

  77. void r100_semaphore_ring_emit(struct radeon_device *rdev,
    78. 

  78. 			      struct radeon_ring *cp,
    79. 

  79. 			      struct radeon_semaphore *semaphore,
    80. 

  80. 			      bool emit_wait);
    81. 

  81. int r100_cs_parse(struct radeon_cs_parser *p);
    82. 

  82. void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    83. 

  83. uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
    84. 

  84. int r100_copy_blit(struct radeon_device *rdev,
    85. 

  85. 		   uint64_t src_offset,
    86. 

  86. 		   uint64_t dst_offset,
    87. 

  87. 		   unsigned num_gpu_pages,
    88. 

  88. 		   struct radeon_fence **fence);
    89. 

  89. int r100_set_surface_reg(struct radeon_device *rdev, int reg,
    90. 

  90. 			 uint32_t tiling_flags, uint32_t pitch,
    91. 

  91. 			 uint32_t offset, uint32_t obj_size);
    92. 

  92. void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
    93. 

  93. void r100_bandwidth_update(struct radeon_device *rdev);
    94. 

  94. void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    95. 

  95. int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
    96. 

  96. void r100_hpd_init(struct radeon_device *rdev);
    97. 

  97. void r100_hpd_fini(struct radeon_device *rdev);
    98. 

  98. bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    99. 

  99. void r100_hpd_set_polarity(struct radeon_device *rdev,
    100. 

  100. 			   enum radeon_hpd_id hpd);
    101. 

  101. int r100_debugfs_rbbm_init(struct radeon_device *rdev);
    102. 

  102. int r100_debugfs_cp_init(struct radeon_device *rdev);
    103. 

  103. void r100_cp_disable(struct radeon_device *rdev);
    104. 

  104. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
    105. 

  105. void r100_cp_fini(struct radeon_device *rdev);
    106. 

  106. int r100_pci_gart_init(struct radeon_device *rdev);
    107. 

  107. void r100_pci_gart_fini(struct radeon_device *rdev);
    108. 

  108. int r100_pci_gart_enable(struct radeon_device *rdev);
    109. 

  109. void r100_pci_gart_disable(struct radeon_device *rdev);
    110. 

  110. int r100_debugfs_mc_info_init(struct radeon_device *rdev);
    111. 

  111. int r100_gui_wait_for_idle(struct radeon_device *rdev);
    112. 

  112. int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
    113. 

  113. void r100_irq_disable(struct radeon_device *rdev);
    114. 

  114. void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
    115. 

  115. void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
    116. 

  116. void r100_vram_init_sizes(struct radeon_device *rdev);
    117. 

  117. int r100_cp_reset(struct radeon_device *rdev);
    118. 

  118. void r100_vga_render_disable(struct radeon_device *rdev);
    119. 

  119. void r100_restore_sanity(struct radeon_device *rdev);
    120. 

  120. int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
    121. 

  121. 					 struct radeon_cs_packet *pkt,
    122. 

  122. 					 struct radeon_bo *robj);
    123. 

  123. int r100_cs_parse_packet0(struct radeon_cs_parser *p,
    124. 

  124. 			  struct radeon_cs_packet *pkt,
    125. 

  125. 			  const unsigned *auth, unsigned n,
    126. 

  126. 			  radeon_packet0_check_t check);
    127. 

  127. int r100_cs_packet_parse(struct radeon_cs_parser *p,
    128. 

  128. 			 struct radeon_cs_packet *pkt,
    129. 

  129. 			 unsigned idx);
    130. 

  130. void r100_enable_bm(struct radeon_device *rdev);
    131. 

  131. void r100_set_common_regs(struct radeon_device *rdev);
    132. 

  132. void r100_bm_disable(struct radeon_device *rdev);
    133. 

  133. extern bool r100_gui_idle(struct radeon_device *rdev);
    134. 

  134. extern void r100_pm_misc(struct radeon_device *rdev);
    135. 

  135. extern void r100_pm_prepare(struct radeon_device *rdev);
    136. 

  136. extern void r100_pm_finish(struct radeon_device *rdev);
    137. 

  137. extern void r100_pm_init_profile(struct radeon_device *rdev);
    138. 

  138. extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
    139. 

  139. extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
    140. 

  140. extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    141. 

  141. extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
    142. 

  142. extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
    143. 

  143. extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
    144. 

  144. 

  145. /*
    146. 

  146.  * r200,rv250,rs300,rv280
    147. 

  147.  */
    148. 

  148. extern int r200_copy_dma(struct radeon_device *rdev,
    149. 

  149. 			 uint64_t src_offset,
    150. 

  150. 			 uint64_t dst_offset,
    151. 

  151. 			 unsigned num_gpu_pages,
    152. 

  152. 			 struct radeon_fence **fence);
    153. 

  153. void r200_set_safe_registers(struct radeon_device *rdev);
    154. 

  154. 

  155. /*
    156. 

  156.  * r300,r350,rv350,rv380
    157. 

  157.  */
    158. 

  158. extern int r300_init(struct radeon_device *rdev);
    159. 

  159. extern void r300_fini(struct radeon_device *rdev);
    160. 

  160. extern int r300_suspend(struct radeon_device *rdev);
    161. 

  161. extern int r300_resume(struct radeon_device *rdev);
    162. 

  162. extern int r300_asic_reset(struct radeon_device *rdev);
    163. 

  163. extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
    164. 

  164. extern void r300_fence_ring_emit(struct radeon_device *rdev,
    165. 

  165. 				struct radeon_fence *fence);
    166. 

  166. extern int r300_cs_parse(struct radeon_cs_parser *p);
    167. 

  167. extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
    168. 

  168. extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    169. 

  169. extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
    170. 

  170. extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
    171. 

  171. extern void r300_set_reg_safe(struct radeon_device *rdev);
    172. 

  172. extern void r300_mc_program(struct radeon_device *rdev);
    173. 

  173. extern void r300_mc_init(struct radeon_device *rdev);
    174. 

  174. extern void r300_clock_startup(struct radeon_device *rdev);
    175. 

  175. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
    176. 

  176. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
    177. 

  177. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
    178. 

  178. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
    179. 

  179. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
    180. 

  180. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
    181. 

  181. 

  182. /*
    183. 

  183.  * r420,r423,rv410
    184. 

  184.  */
    185. 

  185. extern int r420_init(struct radeon_device *rdev);
    186. 

  186. extern void r420_fini(struct radeon_device *rdev);
    187. 

  187. extern int r420_suspend(struct radeon_device *rdev);
    188. 

  188. extern int r420_resume(struct radeon_device *rdev);
    189. 

  189. extern void r420_pm_init_profile(struct radeon_device *rdev);
    190. 

  190. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
    191. 

  191. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
    192. 

  192. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
    193. 

  193. extern void r420_pipes_init(struct radeon_device *rdev);
    194. 

  194. 

  195. /*
    196. 

  196.  * rs400,rs480
    197. 

  197.  */
    198. 

  198. extern int rs400_init(struct radeon_device *rdev);
    199. 

  199. extern void rs400_fini(struct radeon_device *rdev);
    200. 

  200. extern int rs400_suspend(struct radeon_device *rdev);
    201. 

  201. extern int rs400_resume(struct radeon_device *rdev);
    202. 

  202. void rs400_gart_tlb_flush(struct radeon_device *rdev);
    203. 

  203. int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    204. 

  204. uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    205. 

  205. void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    206. 

  206. int rs400_gart_init(struct radeon_device *rdev);
    207. 

  207. int rs400_gart_enable(struct radeon_device *rdev);
    208. 

  208. void rs400_gart_adjust_size(struct radeon_device *rdev);
    209. 

  209. void rs400_gart_disable(struct radeon_device *rdev);
    210. 

  210. void rs400_gart_fini(struct radeon_device *rdev);
    211. 

  211. extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
    212. 

  212. 

  213. /*
    214. 

  214.  * rs600.
    215. 

  215.  */
    216. 

  216. extern int rs600_asic_reset(struct radeon_device *rdev);
    217. 

  217. extern int rs600_init(struct radeon_device *rdev);
    218. 

  218. extern void rs600_fini(struct radeon_device *rdev);
    219. 

  219. extern int rs600_suspend(struct radeon_device *rdev);
    220. 

  220. extern int rs600_resume(struct radeon_device *rdev);
    221. 

  221. int rs600_irq_set(struct radeon_device *rdev);
    222. 

  222. int rs600_irq_process(struct radeon_device *rdev);
    223. 

  223. void rs600_irq_disable(struct radeon_device *rdev);
    224. 

  224. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
    225. 

  225. void rs600_gart_tlb_flush(struct radeon_device *rdev);
    226. 

  226. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
    227. 

  227. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    228. 

  228. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    229. 

  229. void rs600_bandwidth_update(struct radeon_device *rdev);
    230. 

  230. void rs600_hpd_init(struct radeon_device *rdev);
    231. 

  231. void rs600_hpd_fini(struct radeon_device *rdev);
    232. 

  232. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    233. 

  233. void rs600_hpd_set_polarity(struct radeon_device *rdev,
    234. 

  234. 			    enum radeon_hpd_id hpd);
    235. 

  235. extern void rs600_pm_misc(struct radeon_device *rdev);
    236. 

  236. extern void rs600_pm_prepare(struct radeon_device *rdev);
    237. 

  237. extern void rs600_pm_finish(struct radeon_device *rdev);
    238. 

  238. extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
    239. 

  239. extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    240. 

  240. extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
    241. 

  241. void rs600_set_safe_registers(struct radeon_device *rdev);
    242. 

  242. extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
    243. 

  243. extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
    244. 

  244. 

  245. /*
    246. 

  246.  * rs690,rs740
    247. 

  247.  */
    248. 

  248. int rs690_init(struct radeon_device *rdev);
    249. 

  249. void rs690_fini(struct radeon_device *rdev);
    250. 

  250. int rs690_resume(struct radeon_device *rdev);
    251. 

  251. int rs690_suspend(struct radeon_device *rdev);
    252. 

  252. uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    253. 

  253. void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    254. 

  254. void rs690_bandwidth_update(struct radeon_device *rdev);
    255. 

  255. void rs690_line_buffer_adjust(struct radeon_device *rdev,
    256. 

  256. 					struct drm_display_mode *mode1,
    257. 

  257. 					struct drm_display_mode *mode2);
    258. 

  258. extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
    259. 

  259. 

  260. /*
    261. 

  261.  * rv515
    262. 

  262.  */
    263. 

  263. struct rv515_mc_save {
    264. 

  264. 	u32 vga_render_control;
    265. 

  265. 	u32 vga_hdp_control;
    266. 

  266. };
    267. 

  267. 

  268. int rv515_init(struct radeon_device *rdev);
    269. 

  269. void rv515_fini(struct radeon_device *rdev);
    270. 

  270. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
    271. 

  271. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    272. 

  272. void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
    273. 

  273. void rv515_bandwidth_update(struct radeon_device *rdev);
    274. 

  274. int rv515_resume(struct radeon_device *rdev);
    275. 

  275. int rv515_suspend(struct radeon_device *rdev);
    276. 

  276. void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
    277. 

  277. void rv515_vga_render_disable(struct radeon_device *rdev);
    278. 

  278. void rv515_set_safe_registers(struct radeon_device *rdev);
    279. 

  279. void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
    280. 

  280. void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
    281. 

  281. void rv515_clock_startup(struct radeon_device *rdev);
    282. 

  282. void rv515_debugfs(struct radeon_device *rdev);
    283. 

  283. int rv515_mc_wait_for_idle(struct radeon_device *rdev);
    284. 

  284. 

  285. /*
    286. 

  286.  * r520,rv530,rv560,rv570,r580
    287. 

  287.  */
    288. 

  288. int r520_init(struct radeon_device *rdev);
    289. 

  289. int r520_resume(struct radeon_device *rdev);
    290. 

  290. int r520_mc_wait_for_idle(struct radeon_device *rdev);
    291. 

  291. 

  292. /*
    293. 

  293.  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
    294. 

  294.  */
    295. 

  295. int r600_init(struct radeon_device *rdev);
    296. 

  296. void r600_fini(struct radeon_device *rdev);
    297. 

  297. int r600_suspend(struct radeon_device *rdev);
    298. 

  298. int r600_resume(struct radeon_device *rdev);
    299. 

  299. void r600_vga_set_state(struct radeon_device *rdev, bool state);
    300. 

  300. int r600_wb_init(struct radeon_device *rdev);
    301. 

  301. void r600_wb_fini(struct radeon_device *rdev);
    302. 

  302. void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
    303. 

  303. uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
    304. 

  304. void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
    305. 

  305. int r600_cs_parse(struct radeon_cs_parser *p);
    306. 

  306. void r600_fence_ring_emit(struct radeon_device *rdev,
    307. 

  307. 			  struct radeon_fence *fence);
    308. 

  308. void r600_semaphore_ring_emit(struct radeon_device *rdev,
    309. 

  309. 			      struct radeon_ring *cp,
    310. 

  310. 			      struct radeon_semaphore *semaphore,
    311. 

  311. 			      bool emit_wait);
    312. 

  312. bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    313. 

  313. int r600_asic_reset(struct radeon_device *rdev);
    314. 

  314. int r600_set_surface_reg(struct radeon_device *rdev, int reg,
    315. 

  315. 			 uint32_t tiling_flags, uint32_t pitch,
    316. 

  316. 			 uint32_t offset, uint32_t obj_size);
    317. 

  317. void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
    318. 

  318. int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
    319. 

  319. void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    320. 

  320. int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
    321. 

  321. int r600_copy_blit(struct radeon_device *rdev,
    322. 

  322. 		   uint64_t src_offset, uint64_t dst_offset,
    323. 

  323. 		   unsigned num_gpu_pages, struct radeon_fence **fence);
    324. 

  324. void r600_hpd_init(struct radeon_device *rdev);
    325. 

  325. void r600_hpd_fini(struct radeon_device *rdev);
    326. 

  326. bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    327. 

  327. void r600_hpd_set_polarity(struct radeon_device *rdev,
    328. 

  328. 			   enum radeon_hpd_id hpd);
    329. 

  329. extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
    330. 

  330. extern bool r600_gui_idle(struct radeon_device *rdev);
    331. 

  331. extern void r600_pm_misc(struct radeon_device *rdev);
    332. 

  332. extern void r600_pm_init_profile(struct radeon_device *rdev);
    333. 

  333. extern void rs780_pm_init_profile(struct radeon_device *rdev);
    334. 

  334. extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
    335. 

  335. extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
    336. 

  336. extern int r600_get_pcie_lanes(struct radeon_device *rdev);
    337. 

  337. bool r600_card_posted(struct radeon_device *rdev);
    338. 

  338. void r600_cp_stop(struct radeon_device *rdev);
    339. 

  339. int r600_cp_start(struct radeon_device *rdev);
    340. 

  340. void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
    341. 

  341. int r600_cp_resume(struct radeon_device *rdev);
    342. 

  342. void r600_cp_fini(struct radeon_device *rdev);
    343. 

  343. int r600_count_pipe_bits(uint32_t val);
    344. 

  344. int r600_mc_wait_for_idle(struct radeon_device *rdev);
    345. 

  345. int r600_pcie_gart_init(struct radeon_device *rdev);
    346. 

  346. void r600_scratch_init(struct radeon_device *rdev);
    347. 

  347. int r600_blit_init(struct radeon_device *rdev);
    348. 

  348. void r600_blit_fini(struct radeon_device *rdev);
    349. 

  349. int r600_init_microcode(struct radeon_device *rdev);
    350. 

  350. /* r600 irq */
    351. 

  351. int r600_irq_process(struct radeon_device *rdev);
    352. 

  352. int r600_irq_init(struct radeon_device *rdev);
    353. 

  353. void r600_irq_fini(struct radeon_device *rdev);
    354. 

  354. void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
    355. 

  355. int r600_irq_set(struct radeon_device *rdev);
    356. 

  356. void r600_irq_suspend(struct radeon_device *rdev);
    357. 

  357. void r600_disable_interrupts(struct radeon_device *rdev);
    358. 

  358. void r600_rlc_stop(struct radeon_device *rdev);
    359. 

  359. /* r600 audio */
    360. 

  360. int r600_audio_init(struct radeon_device *rdev);
    361. 

  361. void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
    362. 

  362. struct r600_audio r600_audio_status(struct radeon_device *rdev);
    363. 

  363. void r600_audio_fini(struct radeon_device *rdev);
    364. 

  364. int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
    365. 

  365. void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
    366. 

  366. /* r600 blit */
    367. 

  367. int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
    368. 

  368. 			   struct radeon_fence **fence, struct radeon_sa_bo **vb,
    369. 

  369. 			   struct radeon_semaphore **sem);
    370. 

  370. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
    371. 

  371. 			 struct radeon_sa_bo *vb, struct radeon_semaphore *sem);
    372. 

  372. void r600_kms_blit_copy(struct radeon_device *rdev,
    373. 

  373. 			u64 src_gpu_addr, u64 dst_gpu_addr,
    374. 

  374. 			unsigned num_gpu_pages,
    375. 

  375. 			struct radeon_sa_bo *vb);
    376. 

  376. int r600_mc_wait_for_idle(struct radeon_device *rdev);
    377. 

  377. uint64_t r600_get_gpu_clock(struct radeon_device *rdev);
    378. 

  378. 

  379. /*
    380. 

  380.  * rv770,rv730,rv710,rv740
    381. 

  381.  */
    382. 

  382. int rv770_init(struct radeon_device *rdev);
    383. 

  383. void rv770_fini(struct radeon_device *rdev);
    384. 

  384. int rv770_suspend(struct radeon_device *rdev);
    385. 

  385. int rv770_resume(struct radeon_device *rdev);
    386. 

  386. void rv770_pm_misc(struct radeon_device *rdev);
    387. 

  387. u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    388. 

  388. void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
    389. 

  389. void r700_cp_stop(struct radeon_device *rdev);
    390. 

  390. void r700_cp_fini(struct radeon_device *rdev);
    391. 

  391. 

  392. /*
    393. 

  393.  * evergreen
    394. 

  394.  */
    395. 

  395. struct evergreen_mc_save {
    396. 

  396. 	u32 vga_render_control;
    397. 

  397. 	u32 vga_hdp_control;
    398. 

  398. 	bool crtc_enabled[RADEON_MAX_CRTCS];
    399. 

  399. };
    400. 

  400. 

  401. void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
    402. 

  402. int evergreen_init(struct radeon_device *rdev);
    403. 

  403. void evergreen_fini(struct radeon_device *rdev);
    404. 

  404. int evergreen_suspend(struct radeon_device *rdev);
    405. 

  405. int evergreen_resume(struct radeon_device *rdev);
    406. 

  406. bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    407. 

  407. int evergreen_asic_reset(struct radeon_device *rdev);
    408. 

  408. void evergreen_bandwidth_update(struct radeon_device *rdev);
    409. 

  409. void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    410. 

  410. void evergreen_hpd_init(struct radeon_device *rdev);
    411. 

  411. void evergreen_hpd_fini(struct radeon_device *rdev);
    412. 

  412. bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
    413. 

  413. void evergreen_hpd_set_polarity(struct radeon_device *rdev,
    414. 

  414. 				enum radeon_hpd_id hpd);
    415. 

  415. u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
    416. 

  416. int evergreen_irq_set(struct radeon_device *rdev);
    417. 

  417. int evergreen_irq_process(struct radeon_device *rdev);
    418. 

  418. extern int evergreen_cs_parse(struct radeon_cs_parser *p);
    419. 

  419. extern void evergreen_pm_misc(struct radeon_device *rdev);
    420. 

  420. extern void evergreen_pm_prepare(struct radeon_device *rdev);
    421. 

  421. extern void evergreen_pm_finish(struct radeon_device *rdev);
    422. 

  422. extern void sumo_pm_init_profile(struct radeon_device *rdev);
    423. 

  423. extern void btc_pm_init_profile(struct radeon_device *rdev);
    424. 

  424. extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
    425. 

  425. extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
    426. 

  426. extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
    427. 

  427. extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
    428. 

  428. void evergreen_disable_interrupt_state(struct radeon_device *rdev);
    429. 

  429. int evergreen_blit_init(struct radeon_device *rdev);
    430. 

  430. int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
    431. 

  431. 

  432. /*
    433. 

  433.  * cayman
    434. 

  434.  */
    435. 

  435. void cayman_fence_ring_emit(struct radeon_device *rdev,
    436. 

  436. 			    struct radeon_fence *fence);
    437. 

  437. void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
    438. 

  438. int cayman_init(struct radeon_device *rdev);
    439. 

  439. void cayman_fini(struct radeon_device *rdev);
    440. 

  440. int cayman_suspend(struct radeon_device *rdev);
    441. 

  441. int cayman_resume(struct radeon_device *rdev);
    442. 

  442. int cayman_asic_reset(struct radeon_device *rdev);
    443. 

  443. void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    444. 

  444. int cayman_vm_init(struct radeon_device *rdev);
    445. 

  445. void cayman_vm_fini(struct radeon_device *rdev);
    446. 

  446. void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
    447. 

  447. uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
    448. 

  448. void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
    449. 

  449. 			uint64_t addr, unsigned count,
    450. 

  450. 			uint32_t incr, uint32_t flags);
    451. 

  451. int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
    452. 

  452. 

  453. /* DCE6 - SI */
    454. 

  454. void dce6_bandwidth_update(struct radeon_device *rdev);
    455. 

  455. 

  456. /*
    457. 

  457.  * si
    458. 

  458.  */
    459. 

  459. void si_fence_ring_emit(struct radeon_device *rdev,
    460. 

  460. 			struct radeon_fence *fence);
    461. 

  461. void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
    462. 

  462. int si_init(struct radeon_device *rdev);
    463. 

  463. void si_fini(struct radeon_device *rdev);
    464. 

  464. int si_suspend(struct radeon_device *rdev);
    465. 

  465. int si_resume(struct radeon_device *rdev);
    466. 

  466. bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
    467. 

  467. int si_asic_reset(struct radeon_device *rdev);
    468. 

  468. void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
    469. 

  469. int si_irq_set(struct radeon_device *rdev);
    470. 

  470. int si_irq_process(struct radeon_device *rdev);
    471. 

  471. int si_vm_init(struct radeon_device *rdev);
    472. 

  472. void si_vm_fini(struct radeon_device *rdev);
    473. 

  473. void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
    474. 

  474. 		    uint64_t addr, unsigned count,
    475. 

  475. 		    uint32_t incr, uint32_t flags);
    476. 

  476. void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
    477. 

  477. int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
    478. 

  478. uint64_t si_get_gpu_clock(struct radeon_device *rdev);
    479. 

  479. 

  480. #endif
    481.