nouveau_dp.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450
  1. /*
  2. * Copyright 2009 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <drm/drmP.h>
  25. #include <drm/drm_dp_helper.h>
  26. #include "nouveau_drm.h"
  27. #include "nouveau_connector.h"
  28. #include "nouveau_encoder.h"
  29. #include "nouveau_crtc.h"
  30. #include <subdev/gpio.h>
  31. #include <subdev/i2c.h>
  32. u8 *
  33. nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry)
  34. {
  35. struct nouveau_drm *drm = nouveau_drm(dev);
  36. struct bit_entry d;
  37. u8 *table;
  38. int i;
  39. if (bit_table(dev, 'd', &d)) {
  40. NV_ERROR(drm, "BIT 'd' table not found\n");
  41. return NULL;
  42. }
  43. if (d.version != 1) {
  44. NV_ERROR(drm, "BIT 'd' table version %d unknown\n", d.version);
  45. return NULL;
  46. }
  47. table = ROMPTR(dev, d.data[0]);
  48. if (!table) {
  49. NV_ERROR(drm, "displayport table pointer invalid\n");
  50. return NULL;
  51. }
  52. switch (table[0]) {
  53. case 0x20:
  54. case 0x21:
  55. case 0x30:
  56. case 0x40:
  57. break;
  58. default:
  59. NV_ERROR(drm, "displayport table 0x%02x unknown\n", table[0]);
  60. return NULL;
  61. }
  62. for (i = 0; i < table[3]; i++) {
  63. *entry = ROMPTR(dev, table[table[1] + (i * table[2])]);
  64. if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
  65. return table;
  66. }
  67. NV_ERROR(drm, "displayport encoder table not found\n");
  68. return NULL;
  69. }
  70. /******************************************************************************
  71. * link training
  72. *****************************************************************************/
  73. struct dp_state {
  74. struct nouveau_i2c_port *auxch;
  75. struct dp_train_func *func;
  76. struct dcb_output *dcb;
  77. int crtc;
  78. u8 *dpcd;
  79. int link_nr;
  80. u32 link_bw;
  81. u8 stat[6];
  82. u8 conf[4];
  83. };
  84. static void
  85. dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
  86. {
  87. struct nouveau_drm *drm = nouveau_drm(dev);
  88. u8 sink[2];
  89. NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
  90. /* set desired link configuration on the source */
  91. dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
  92. dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);
  93. /* inform the sink of the new configuration */
  94. sink[0] = dp->link_bw / 27000;
  95. sink[1] = dp->link_nr;
  96. if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
  97. sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  98. nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2);
  99. }
  100. static void
  101. dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
  102. {
  103. struct nouveau_drm *drm = nouveau_drm(dev);
  104. u8 sink_tp;
  105. NV_DEBUG(drm, "training pattern %d\n", pattern);
  106. dp->func->train_set(dev, dp->dcb, pattern);
  107. nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
  108. sink_tp &= ~DP_TRAINING_PATTERN_MASK;
  109. sink_tp |= pattern;
  110. nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
  111. }
  112. static int
  113. dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
  114. {
  115. struct nouveau_drm *drm = nouveau_drm(dev);
  116. int i;
  117. for (i = 0; i < dp->link_nr; i++) {
  118. u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
  119. u8 lpre = (lane & 0x0c) >> 2;
  120. u8 lvsw = (lane & 0x03) >> 0;
  121. dp->conf[i] = (lpre << 3) | lvsw;
  122. if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
  123. dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
  124. if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
  125. dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  126. NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]);
  127. dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
  128. }
  129. return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
  130. }
  131. static int
  132. dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
  133. {
  134. struct nouveau_drm *drm = nouveau_drm(dev);
  135. int ret;
  136. udelay(delay);
  137. ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
  138. if (ret)
  139. return ret;
  140. NV_DEBUG(drm, "status %*ph\n", 6, dp->stat);
  141. return 0;
  142. }
  143. static int
  144. dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
  145. {
  146. bool cr_done = false, abort = false;
  147. int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  148. int tries = 0, i;
  149. dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
  150. do {
  151. if (dp_link_train_commit(dev, dp) ||
  152. dp_link_train_update(dev, dp, 100))
  153. break;
  154. cr_done = true;
  155. for (i = 0; i < dp->link_nr; i++) {
  156. u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
  157. if (!(lane & DP_LANE_CR_DONE)) {
  158. cr_done = false;
  159. if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
  160. abort = true;
  161. break;
  162. }
  163. }
  164. if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
  165. voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  166. tries = 0;
  167. }
  168. } while (!cr_done && !abort && ++tries < 5);
  169. return cr_done ? 0 : -1;
  170. }
  171. static int
  172. dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
  173. {
  174. bool eq_done, cr_done = true;
  175. int tries = 0, i;
  176. dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
  177. do {
  178. if (dp_link_train_update(dev, dp, 400))
  179. break;
  180. eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
  181. for (i = 0; i < dp->link_nr && eq_done; i++) {
  182. u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
  183. if (!(lane & DP_LANE_CR_DONE))
  184. cr_done = false;
  185. if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
  186. !(lane & DP_LANE_SYMBOL_LOCKED))
  187. eq_done = false;
  188. }
  189. if (dp_link_train_commit(dev, dp))
  190. break;
  191. } while (!eq_done && cr_done && ++tries <= 5);
  192. return eq_done ? 0 : -1;
  193. }
  194. static void
  195. dp_set_downspread(struct drm_device *dev, struct dp_state *dp, bool enable)
  196. {
  197. u16 script = 0x0000;
  198. u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
  199. if (table) {
  200. if (table[0] >= 0x20 && table[0] <= 0x30) {
  201. if (enable) script = ROM16(entry[12]);
  202. else script = ROM16(entry[14]);
  203. } else
  204. if (table[0] == 0x40) {
  205. if (enable) script = ROM16(entry[11]);
  206. else script = ROM16(entry[13]);
  207. }
  208. }
  209. nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
  210. }
  211. static void
  212. dp_link_train_init(struct drm_device *dev, struct dp_state *dp)
  213. {
  214. u16 script = 0x0000;
  215. u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
  216. if (table) {
  217. if (table[0] >= 0x20 && table[0] <= 0x30)
  218. script = ROM16(entry[6]);
  219. else
  220. if (table[0] == 0x40)
  221. script = ROM16(entry[5]);
  222. }
  223. nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
  224. }
  225. static void
  226. dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
  227. {
  228. u16 script = 0x0000;
  229. u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
  230. if (table) {
  231. if (table[0] >= 0x20 && table[0] <= 0x30)
  232. script = ROM16(entry[8]);
  233. else
  234. if (table[0] == 0x40)
  235. script = ROM16(entry[7]);
  236. }
  237. nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
  238. }
  239. static bool
  240. nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
  241. struct dp_train_func *func)
  242. {
  243. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  244. struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
  245. struct nouveau_connector *nv_connector =
  246. nouveau_encoder_connector_get(nv_encoder);
  247. struct drm_device *dev = encoder->dev;
  248. struct nouveau_drm *drm = nouveau_drm(dev);
  249. struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
  250. struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
  251. const u32 bw_list[] = { 270000, 162000, 0 };
  252. const u32 *link_bw = bw_list;
  253. struct dp_state dp;
  254. dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
  255. if (!dp.auxch)
  256. return false;
  257. dp.func = func;
  258. dp.dcb = nv_encoder->dcb;
  259. dp.crtc = nv_crtc->index;
  260. dp.dpcd = nv_encoder->dp.dpcd;
  261. /* adjust required bandwidth for 8B/10B coding overhead */
  262. datarate = (datarate / 8) * 10;
  263. /* some sinks toggle hotplug in response to some of the actions
  264. * we take during link training (DP_SET_POWER is one), we need
  265. * to ignore them for the moment to avoid races.
  266. */
  267. gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false);
  268. /* enable down-spreading, if possible */
  269. dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
  270. /* execute pre-train script from vbios */
  271. dp_link_train_init(dev, &dp);
  272. /* start off at highest link rate supported by encoder and display */
  273. while (*link_bw > nv_encoder->dp.link_bw)
  274. link_bw++;
  275. while (link_bw[0]) {
  276. /* find minimum required lane count at this link rate */
  277. dp.link_nr = nv_encoder->dp.link_nr;
  278. while ((dp.link_nr >> 1) * link_bw[0] > datarate)
  279. dp.link_nr >>= 1;
  280. /* drop link rate to minimum with this lane count */
  281. while ((link_bw[1] * dp.link_nr) > datarate)
  282. link_bw++;
  283. dp.link_bw = link_bw[0];
  284. /* program selected link configuration */
  285. dp_set_link_config(dev, &dp);
  286. /* attempt to train the link at this configuration */
  287. memset(dp.stat, 0x00, sizeof(dp.stat));
  288. if (!dp_link_train_cr(dev, &dp) &&
  289. !dp_link_train_eq(dev, &dp))
  290. break;
  291. /* retry at lower rate */
  292. link_bw++;
  293. }
  294. /* finish link training */
  295. dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
  296. /* execute post-train script from vbios */
  297. dp_link_train_fini(dev, &dp);
  298. /* re-enable hotplug detect */
  299. gpio->irq(gpio, 0, nv_connector->hpd, 0xff, true);
  300. return true;
  301. }
  302. void
  303. nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
  304. struct dp_train_func *func)
  305. {
  306. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  307. struct nouveau_drm *drm = nouveau_drm(encoder->dev);
  308. struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
  309. struct nouveau_i2c_port *auxch;
  310. u8 status;
  311. auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
  312. if (!auxch)
  313. return;
  314. if (mode == DRM_MODE_DPMS_ON)
  315. status = DP_SET_POWER_D0;
  316. else
  317. status = DP_SET_POWER_D3;
  318. nv_wraux(auxch, DP_SET_POWER, &status, 1);
  319. if (mode == DRM_MODE_DPMS_ON)
  320. nouveau_dp_link_train(encoder, datarate, func);
  321. }
  322. static void
  323. nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch,
  324. u8 *dpcd)
  325. {
  326. struct nouveau_drm *drm = nouveau_drm(dev);
  327. u8 buf[3];
  328. if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
  329. return;
  330. if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3))
  331. NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
  332. buf[0], buf[1], buf[2]);
  333. if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3))
  334. NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
  335. buf[0], buf[1], buf[2]);
  336. }
  337. bool
  338. nouveau_dp_detect(struct drm_encoder *encoder)
  339. {
  340. struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
  341. struct drm_device *dev = encoder->dev;
  342. struct nouveau_drm *drm = nouveau_drm(dev);
  343. struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
  344. struct nouveau_i2c_port *auxch;
  345. u8 *dpcd = nv_encoder->dp.dpcd;
  346. int ret;
  347. auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
  348. if (!auxch)
  349. return false;
  350. ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
  351. if (ret)
  352. return false;
  353. nv_encoder->dp.link_bw = 27000 * dpcd[1];
  354. nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
  355. NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
  356. nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
  357. NV_DEBUG(drm, "encoder: %dx%d\n",
  358. nv_encoder->dcb->dpconf.link_nr,
  359. nv_encoder->dcb->dpconf.link_bw);
  360. if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
  361. nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
  362. if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
  363. nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
  364. NV_DEBUG(drm, "maximum: %dx%d\n",
  365. nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
  366. nouveau_dp_probe_oui(dev, auxch, dpcd);
  367. return true;
  368. }