intel_crt.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796
  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36. /* Here's the desired hotplug mode */
  37. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  38. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  39. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  40. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  41. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  42. ADPA_CRT_HOTPLUG_ENABLE)
  43. struct intel_crt {
  44. struct intel_encoder base;
  45. bool force_hotplug_required;
  46. u32 adpa_reg;
  47. };
  48. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  49. {
  50. return container_of(intel_attached_encoder(connector),
  51. struct intel_crt, base);
  52. }
  53. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  54. {
  55. return container_of(encoder, struct intel_crt, base);
  56. }
  57. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  58. enum pipe *pipe)
  59. {
  60. struct drm_device *dev = encoder->base.dev;
  61. struct drm_i915_private *dev_priv = dev->dev_private;
  62. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  63. u32 tmp;
  64. tmp = I915_READ(crt->adpa_reg);
  65. if (!(tmp & ADPA_DAC_ENABLE))
  66. return false;
  67. if (HAS_PCH_CPT(dev))
  68. *pipe = PORT_TO_PIPE_CPT(tmp);
  69. else
  70. *pipe = PORT_TO_PIPE(tmp);
  71. return true;
  72. }
  73. static void intel_disable_crt(struct intel_encoder *encoder)
  74. {
  75. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  76. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  77. u32 temp;
  78. temp = I915_READ(crt->adpa_reg);
  79. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  80. temp &= ~ADPA_DAC_ENABLE;
  81. I915_WRITE(crt->adpa_reg, temp);
  82. }
  83. static void intel_enable_crt(struct intel_encoder *encoder)
  84. {
  85. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  86. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  87. u32 temp;
  88. temp = I915_READ(crt->adpa_reg);
  89. temp |= ADPA_DAC_ENABLE;
  90. I915_WRITE(crt->adpa_reg, temp);
  91. }
  92. /* Note: The caller is required to filter out dpms modes not supported by the
  93. * platform. */
  94. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  95. {
  96. struct drm_device *dev = encoder->base.dev;
  97. struct drm_i915_private *dev_priv = dev->dev_private;
  98. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  99. u32 temp;
  100. temp = I915_READ(crt->adpa_reg);
  101. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  102. temp &= ~ADPA_DAC_ENABLE;
  103. switch (mode) {
  104. case DRM_MODE_DPMS_ON:
  105. temp |= ADPA_DAC_ENABLE;
  106. break;
  107. case DRM_MODE_DPMS_STANDBY:
  108. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  109. break;
  110. case DRM_MODE_DPMS_SUSPEND:
  111. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  112. break;
  113. case DRM_MODE_DPMS_OFF:
  114. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  115. break;
  116. }
  117. I915_WRITE(crt->adpa_reg, temp);
  118. }
  119. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  120. {
  121. struct drm_device *dev = connector->dev;
  122. struct intel_encoder *encoder = intel_attached_encoder(connector);
  123. struct drm_crtc *crtc;
  124. int old_dpms;
  125. /* PCH platforms and VLV only support on/off. */
  126. if (INTEL_INFO(dev)->gen < 5 && mode != DRM_MODE_DPMS_ON)
  127. mode = DRM_MODE_DPMS_OFF;
  128. if (mode == connector->dpms)
  129. return;
  130. old_dpms = connector->dpms;
  131. connector->dpms = mode;
  132. /* Only need to change hw state when actually enabled */
  133. crtc = encoder->base.crtc;
  134. if (!crtc) {
  135. encoder->connectors_active = false;
  136. return;
  137. }
  138. /* We need the pipe to run for anything but OFF. */
  139. if (mode == DRM_MODE_DPMS_OFF)
  140. encoder->connectors_active = false;
  141. else
  142. encoder->connectors_active = true;
  143. if (mode < old_dpms) {
  144. /* From off to on, enable the pipe first. */
  145. intel_crtc_update_dpms(crtc);
  146. intel_crt_set_dpms(encoder, mode);
  147. } else {
  148. intel_crt_set_dpms(encoder, mode);
  149. intel_crtc_update_dpms(crtc);
  150. }
  151. intel_modeset_check_state(connector->dev);
  152. }
  153. static int intel_crt_mode_valid(struct drm_connector *connector,
  154. struct drm_display_mode *mode)
  155. {
  156. struct drm_device *dev = connector->dev;
  157. int max_clock = 0;
  158. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  159. return MODE_NO_DBLESCAN;
  160. if (mode->clock < 25000)
  161. return MODE_CLOCK_LOW;
  162. if (IS_GEN2(dev))
  163. max_clock = 350000;
  164. else
  165. max_clock = 400000;
  166. if (mode->clock > max_clock)
  167. return MODE_CLOCK_HIGH;
  168. return MODE_OK;
  169. }
  170. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  171. const struct drm_display_mode *mode,
  172. struct drm_display_mode *adjusted_mode)
  173. {
  174. return true;
  175. }
  176. static void intel_crt_mode_set(struct drm_encoder *encoder,
  177. struct drm_display_mode *mode,
  178. struct drm_display_mode *adjusted_mode)
  179. {
  180. struct drm_device *dev = encoder->dev;
  181. struct drm_crtc *crtc = encoder->crtc;
  182. struct intel_crt *crt =
  183. intel_encoder_to_crt(to_intel_encoder(encoder));
  184. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  185. struct drm_i915_private *dev_priv = dev->dev_private;
  186. int dpll_md_reg;
  187. u32 adpa, dpll_md;
  188. dpll_md_reg = DPLL_MD(intel_crtc->pipe);
  189. /*
  190. * Disable separate mode multiplier used when cloning SDVO to CRT
  191. * XXX this needs to be adjusted when we really are cloning
  192. */
  193. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  194. dpll_md = I915_READ(dpll_md_reg);
  195. I915_WRITE(dpll_md_reg,
  196. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  197. }
  198. adpa = ADPA_HOTPLUG_BITS;
  199. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  200. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  201. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  202. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  203. /* For CPT allow 3 pipe config, for others just use A or B */
  204. if (HAS_PCH_CPT(dev))
  205. adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  206. else if (intel_crtc->pipe == 0)
  207. adpa |= ADPA_PIPE_A_SELECT;
  208. else
  209. adpa |= ADPA_PIPE_B_SELECT;
  210. if (!HAS_PCH_SPLIT(dev))
  211. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  212. I915_WRITE(crt->adpa_reg, adpa);
  213. }
  214. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  215. {
  216. struct drm_device *dev = connector->dev;
  217. struct intel_crt *crt = intel_attached_crt(connector);
  218. struct drm_i915_private *dev_priv = dev->dev_private;
  219. u32 adpa;
  220. bool ret;
  221. /* The first time through, trigger an explicit detection cycle */
  222. if (crt->force_hotplug_required) {
  223. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  224. u32 save_adpa;
  225. crt->force_hotplug_required = 0;
  226. save_adpa = adpa = I915_READ(PCH_ADPA);
  227. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  228. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  229. if (turn_off_dac)
  230. adpa &= ~ADPA_DAC_ENABLE;
  231. I915_WRITE(PCH_ADPA, adpa);
  232. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  233. 1000))
  234. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  235. if (turn_off_dac) {
  236. I915_WRITE(PCH_ADPA, save_adpa);
  237. POSTING_READ(PCH_ADPA);
  238. }
  239. }
  240. /* Check the status to see if both blue and green are on now */
  241. adpa = I915_READ(PCH_ADPA);
  242. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  243. ret = true;
  244. else
  245. ret = false;
  246. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  247. return ret;
  248. }
  249. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  250. {
  251. struct drm_device *dev = connector->dev;
  252. struct drm_i915_private *dev_priv = dev->dev_private;
  253. u32 adpa;
  254. bool ret;
  255. u32 save_adpa;
  256. save_adpa = adpa = I915_READ(ADPA);
  257. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  258. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  259. I915_WRITE(ADPA, adpa);
  260. if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  261. 1000)) {
  262. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  263. I915_WRITE(ADPA, save_adpa);
  264. }
  265. /* Check the status to see if both blue and green are on now */
  266. adpa = I915_READ(ADPA);
  267. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  268. ret = true;
  269. else
  270. ret = false;
  271. DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  272. /* FIXME: debug force function and remove */
  273. ret = true;
  274. return ret;
  275. }
  276. /**
  277. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  278. *
  279. * Not for i915G/i915GM
  280. *
  281. * \return true if CRT is connected.
  282. * \return false if CRT is disconnected.
  283. */
  284. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  285. {
  286. struct drm_device *dev = connector->dev;
  287. struct drm_i915_private *dev_priv = dev->dev_private;
  288. u32 hotplug_en, orig, stat;
  289. bool ret = false;
  290. int i, tries = 0;
  291. if (HAS_PCH_SPLIT(dev))
  292. return intel_ironlake_crt_detect_hotplug(connector);
  293. if (IS_VALLEYVIEW(dev))
  294. return valleyview_crt_detect_hotplug(connector);
  295. /*
  296. * On 4 series desktop, CRT detect sequence need to be done twice
  297. * to get a reliable result.
  298. */
  299. if (IS_G4X(dev) && !IS_GM45(dev))
  300. tries = 2;
  301. else
  302. tries = 1;
  303. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  304. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  305. for (i = 0; i < tries ; i++) {
  306. /* turn on the FORCE_DETECT */
  307. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  308. /* wait for FORCE_DETECT to go off */
  309. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  310. CRT_HOTPLUG_FORCE_DETECT) == 0,
  311. 1000))
  312. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  313. }
  314. stat = I915_READ(PORT_HOTPLUG_STAT);
  315. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  316. ret = true;
  317. /* clear the interrupt we just generated, if any */
  318. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  319. /* and put the bits back */
  320. I915_WRITE(PORT_HOTPLUG_EN, orig);
  321. return ret;
  322. }
  323. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  324. struct i2c_adapter *i2c)
  325. {
  326. struct edid *edid;
  327. edid = drm_get_edid(connector, i2c);
  328. if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  329. DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  330. intel_gmbus_force_bit(i2c, true);
  331. edid = drm_get_edid(connector, i2c);
  332. intel_gmbus_force_bit(i2c, false);
  333. }
  334. return edid;
  335. }
  336. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  337. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  338. struct i2c_adapter *adapter)
  339. {
  340. struct edid *edid;
  341. edid = intel_crt_get_edid(connector, adapter);
  342. if (!edid)
  343. return 0;
  344. return intel_connector_update_modes(connector, edid);
  345. }
  346. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  347. {
  348. struct intel_crt *crt = intel_attached_crt(connector);
  349. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  350. struct edid *edid;
  351. struct i2c_adapter *i2c;
  352. BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  353. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  354. edid = intel_crt_get_edid(connector, i2c);
  355. if (edid) {
  356. bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  357. /*
  358. * This may be a DVI-I connector with a shared DDC
  359. * link between analog and digital outputs, so we
  360. * have to check the EDID input spec of the attached device.
  361. */
  362. if (!is_digital) {
  363. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  364. return true;
  365. }
  366. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  367. } else {
  368. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  369. }
  370. kfree(edid);
  371. return false;
  372. }
  373. static enum drm_connector_status
  374. intel_crt_load_detect(struct intel_crt *crt)
  375. {
  376. struct drm_device *dev = crt->base.base.dev;
  377. struct drm_i915_private *dev_priv = dev->dev_private;
  378. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  379. uint32_t save_bclrpat;
  380. uint32_t save_vtotal;
  381. uint32_t vtotal, vactive;
  382. uint32_t vsample;
  383. uint32_t vblank, vblank_start, vblank_end;
  384. uint32_t dsl;
  385. uint32_t bclrpat_reg;
  386. uint32_t vtotal_reg;
  387. uint32_t vblank_reg;
  388. uint32_t vsync_reg;
  389. uint32_t pipeconf_reg;
  390. uint32_t pipe_dsl_reg;
  391. uint8_t st00;
  392. enum drm_connector_status status;
  393. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  394. bclrpat_reg = BCLRPAT(pipe);
  395. vtotal_reg = VTOTAL(pipe);
  396. vblank_reg = VBLANK(pipe);
  397. vsync_reg = VSYNC(pipe);
  398. pipeconf_reg = PIPECONF(pipe);
  399. pipe_dsl_reg = PIPEDSL(pipe);
  400. save_bclrpat = I915_READ(bclrpat_reg);
  401. save_vtotal = I915_READ(vtotal_reg);
  402. vblank = I915_READ(vblank_reg);
  403. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  404. vactive = (save_vtotal & 0x7ff) + 1;
  405. vblank_start = (vblank & 0xfff) + 1;
  406. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  407. /* Set the border color to purple. */
  408. I915_WRITE(bclrpat_reg, 0x500050);
  409. if (!IS_GEN2(dev)) {
  410. uint32_t pipeconf = I915_READ(pipeconf_reg);
  411. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  412. POSTING_READ(pipeconf_reg);
  413. /* Wait for next Vblank to substitue
  414. * border color for Color info */
  415. intel_wait_for_vblank(dev, pipe);
  416. st00 = I915_READ8(VGA_MSR_WRITE);
  417. status = ((st00 & (1 << 4)) != 0) ?
  418. connector_status_connected :
  419. connector_status_disconnected;
  420. I915_WRITE(pipeconf_reg, pipeconf);
  421. } else {
  422. bool restore_vblank = false;
  423. int count, detect;
  424. /*
  425. * If there isn't any border, add some.
  426. * Yes, this will flicker
  427. */
  428. if (vblank_start <= vactive && vblank_end >= vtotal) {
  429. uint32_t vsync = I915_READ(vsync_reg);
  430. uint32_t vsync_start = (vsync & 0xffff) + 1;
  431. vblank_start = vsync_start;
  432. I915_WRITE(vblank_reg,
  433. (vblank_start - 1) |
  434. ((vblank_end - 1) << 16));
  435. restore_vblank = true;
  436. }
  437. /* sample in the vertical border, selecting the larger one */
  438. if (vblank_start - vactive >= vtotal - vblank_end)
  439. vsample = (vblank_start + vactive) >> 1;
  440. else
  441. vsample = (vtotal + vblank_end) >> 1;
  442. /*
  443. * Wait for the border to be displayed
  444. */
  445. while (I915_READ(pipe_dsl_reg) >= vactive)
  446. ;
  447. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  448. ;
  449. /*
  450. * Watch ST00 for an entire scanline
  451. */
  452. detect = 0;
  453. count = 0;
  454. do {
  455. count++;
  456. /* Read the ST00 VGA status register */
  457. st00 = I915_READ8(VGA_MSR_WRITE);
  458. if (st00 & (1 << 4))
  459. detect++;
  460. } while ((I915_READ(pipe_dsl_reg) == dsl));
  461. /* restore vblank if necessary */
  462. if (restore_vblank)
  463. I915_WRITE(vblank_reg, vblank);
  464. /*
  465. * If more than 3/4 of the scanline detected a monitor,
  466. * then it is assumed to be present. This works even on i830,
  467. * where there isn't any way to force the border color across
  468. * the screen
  469. */
  470. status = detect * 4 > count * 3 ?
  471. connector_status_connected :
  472. connector_status_disconnected;
  473. }
  474. /* Restore previous settings */
  475. I915_WRITE(bclrpat_reg, save_bclrpat);
  476. return status;
  477. }
  478. static enum drm_connector_status
  479. intel_crt_detect(struct drm_connector *connector, bool force)
  480. {
  481. struct drm_device *dev = connector->dev;
  482. struct intel_crt *crt = intel_attached_crt(connector);
  483. enum drm_connector_status status;
  484. struct intel_load_detect_pipe tmp;
  485. if (I915_HAS_HOTPLUG(dev)) {
  486. /* We can not rely on the HPD pin always being correctly wired
  487. * up, for example many KVM do not pass it through, and so
  488. * only trust an assertion that the monitor is connected.
  489. */
  490. if (intel_crt_detect_hotplug(connector)) {
  491. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  492. return connector_status_connected;
  493. } else
  494. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  495. }
  496. if (intel_crt_detect_ddc(connector))
  497. return connector_status_connected;
  498. /* Load detection is broken on HPD capable machines. Whoever wants a
  499. * broken monitor (without edid) to work behind a broken kvm (that fails
  500. * to have the right resistors for HP detection) needs to fix this up.
  501. * For now just bail out. */
  502. if (I915_HAS_HOTPLUG(dev))
  503. return connector_status_disconnected;
  504. if (!force)
  505. return connector->status;
  506. /* for pre-945g platforms use load detect */
  507. if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  508. if (intel_crt_detect_ddc(connector))
  509. status = connector_status_connected;
  510. else
  511. status = intel_crt_load_detect(crt);
  512. intel_release_load_detect_pipe(connector, &tmp);
  513. } else
  514. status = connector_status_unknown;
  515. return status;
  516. }
  517. static void intel_crt_destroy(struct drm_connector *connector)
  518. {
  519. drm_sysfs_connector_remove(connector);
  520. drm_connector_cleanup(connector);
  521. kfree(connector);
  522. }
  523. static int intel_crt_get_modes(struct drm_connector *connector)
  524. {
  525. struct drm_device *dev = connector->dev;
  526. struct drm_i915_private *dev_priv = dev->dev_private;
  527. int ret;
  528. struct i2c_adapter *i2c;
  529. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  530. ret = intel_crt_ddc_get_modes(connector, i2c);
  531. if (ret || !IS_G4X(dev))
  532. return ret;
  533. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  534. i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  535. return intel_crt_ddc_get_modes(connector, i2c);
  536. }
  537. static int intel_crt_set_property(struct drm_connector *connector,
  538. struct drm_property *property,
  539. uint64_t value)
  540. {
  541. return 0;
  542. }
  543. static void intel_crt_reset(struct drm_connector *connector)
  544. {
  545. struct drm_device *dev = connector->dev;
  546. struct intel_crt *crt = intel_attached_crt(connector);
  547. if (HAS_PCH_SPLIT(dev))
  548. crt->force_hotplug_required = 1;
  549. }
  550. /*
  551. * Routines for controlling stuff on the analog port
  552. */
  553. static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
  554. .mode_fixup = intel_crt_mode_fixup,
  555. .mode_set = intel_crt_mode_set,
  556. .disable = intel_encoder_noop,
  557. };
  558. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  559. .reset = intel_crt_reset,
  560. .dpms = intel_crt_dpms,
  561. .detect = intel_crt_detect,
  562. .fill_modes = drm_helper_probe_single_connector_modes,
  563. .destroy = intel_crt_destroy,
  564. .set_property = intel_crt_set_property,
  565. };
  566. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  567. .mode_valid = intel_crt_mode_valid,
  568. .get_modes = intel_crt_get_modes,
  569. .best_encoder = intel_best_encoder,
  570. };
  571. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  572. .destroy = intel_encoder_destroy,
  573. };
  574. static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  575. {
  576. DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  577. return 1;
  578. }
  579. static const struct dmi_system_id intel_no_crt[] = {
  580. {
  581. .callback = intel_no_crt_dmi_callback,
  582. .ident = "ACER ZGB",
  583. .matches = {
  584. DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  585. DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  586. },
  587. },
  588. { }
  589. };
  590. void intel_crt_init(struct drm_device *dev)
  591. {
  592. struct drm_connector *connector;
  593. struct intel_crt *crt;
  594. struct intel_connector *intel_connector;
  595. struct drm_i915_private *dev_priv = dev->dev_private;
  596. /* Skip machines without VGA that falsely report hotplug events */
  597. if (dmi_check_system(intel_no_crt))
  598. return;
  599. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  600. if (!crt)
  601. return;
  602. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  603. if (!intel_connector) {
  604. kfree(crt);
  605. return;
  606. }
  607. connector = &intel_connector->base;
  608. drm_connector_init(dev, &intel_connector->base,
  609. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  610. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  611. DRM_MODE_ENCODER_DAC);
  612. intel_connector_attach_encoder(intel_connector, &crt->base);
  613. crt->base.type = INTEL_OUTPUT_ANALOG;
  614. crt->base.cloneable = true;
  615. if (IS_HASWELL(dev))
  616. crt->base.crtc_mask = (1 << 0);
  617. else
  618. crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  619. if (IS_GEN2(dev))
  620. connector->interlace_allowed = 0;
  621. else
  622. connector->interlace_allowed = 1;
  623. connector->doublescan_allowed = 0;
  624. if (HAS_PCH_SPLIT(dev))
  625. crt->adpa_reg = PCH_ADPA;
  626. else if (IS_VALLEYVIEW(dev))
  627. crt->adpa_reg = VLV_ADPA;
  628. else
  629. crt->adpa_reg = ADPA;
  630. crt->base.disable = intel_disable_crt;
  631. crt->base.enable = intel_enable_crt;
  632. crt->base.get_hw_state = intel_crt_get_hw_state;
  633. intel_connector->get_hw_state = intel_connector_get_hw_state;
  634. drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
  635. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  636. drm_sysfs_connector_add(connector);
  637. if (I915_HAS_HOTPLUG(dev))
  638. connector->polled = DRM_CONNECTOR_POLL_HPD;
  639. else
  640. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  641. /*
  642. * Configure the automatic hotplug detection stuff
  643. */
  644. crt->force_hotplug_required = 0;
  645. if (HAS_PCH_SPLIT(dev)) {
  646. u32 adpa;
  647. adpa = I915_READ(PCH_ADPA);
  648. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  649. adpa |= ADPA_HOTPLUG_BITS;
  650. I915_WRITE(PCH_ADPA, adpa);
  651. POSTING_READ(PCH_ADPA);
  652. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  653. crt->force_hotplug_required = 1;
  654. }
  655. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  656. }