exynos_drm_g2d.c 22 KB

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  1. /*
  2. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  3. * Authors: Joonyoung Shim <jy0922.shim@samsung.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundationr
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/clk.h>
  12. #include <linux/err.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/slab.h>
  18. #include <linux/workqueue.h>
  19. #include <drm/drmP.h>
  20. #include <drm/exynos_drm.h>
  21. #include "exynos_drm_drv.h"
  22. #include "exynos_drm_gem.h"
  23. #define G2D_HW_MAJOR_VER 4
  24. #define G2D_HW_MINOR_VER 1
  25. /* vaild register range set from user: 0x0104 ~ 0x0880 */
  26. #define G2D_VALID_START 0x0104
  27. #define G2D_VALID_END 0x0880
  28. /* general registers */
  29. #define G2D_SOFT_RESET 0x0000
  30. #define G2D_INTEN 0x0004
  31. #define G2D_INTC_PEND 0x000C
  32. #define G2D_DMA_SFR_BASE_ADDR 0x0080
  33. #define G2D_DMA_COMMAND 0x0084
  34. #define G2D_DMA_STATUS 0x008C
  35. #define G2D_DMA_HOLD_CMD 0x0090
  36. /* command registers */
  37. #define G2D_BITBLT_START 0x0100
  38. /* registers for base address */
  39. #define G2D_SRC_BASE_ADDR 0x0304
  40. #define G2D_SRC_PLANE2_BASE_ADDR 0x0318
  41. #define G2D_DST_BASE_ADDR 0x0404
  42. #define G2D_DST_PLANE2_BASE_ADDR 0x0418
  43. #define G2D_PAT_BASE_ADDR 0x0500
  44. #define G2D_MSK_BASE_ADDR 0x0520
  45. /* G2D_SOFT_RESET */
  46. #define G2D_SFRCLEAR (1 << 1)
  47. #define G2D_R (1 << 0)
  48. /* G2D_INTEN */
  49. #define G2D_INTEN_ACF (1 << 3)
  50. #define G2D_INTEN_UCF (1 << 2)
  51. #define G2D_INTEN_GCF (1 << 1)
  52. #define G2D_INTEN_SCF (1 << 0)
  53. /* G2D_INTC_PEND */
  54. #define G2D_INTP_ACMD_FIN (1 << 3)
  55. #define G2D_INTP_UCMD_FIN (1 << 2)
  56. #define G2D_INTP_GCMD_FIN (1 << 1)
  57. #define G2D_INTP_SCMD_FIN (1 << 0)
  58. /* G2D_DMA_COMMAND */
  59. #define G2D_DMA_HALT (1 << 2)
  60. #define G2D_DMA_CONTINUE (1 << 1)
  61. #define G2D_DMA_START (1 << 0)
  62. /* G2D_DMA_STATUS */
  63. #define G2D_DMA_LIST_DONE_COUNT (0xFF << 17)
  64. #define G2D_DMA_BITBLT_DONE_COUNT (0xFFFF << 1)
  65. #define G2D_DMA_DONE (1 << 0)
  66. #define G2D_DMA_LIST_DONE_COUNT_OFFSET 17
  67. /* G2D_DMA_HOLD_CMD */
  68. #define G2D_USET_HOLD (1 << 2)
  69. #define G2D_LIST_HOLD (1 << 1)
  70. #define G2D_BITBLT_HOLD (1 << 0)
  71. /* G2D_BITBLT_START */
  72. #define G2D_START_CASESEL (1 << 2)
  73. #define G2D_START_NHOLT (1 << 1)
  74. #define G2D_START_BITBLT (1 << 0)
  75. #define G2D_CMDLIST_SIZE (PAGE_SIZE / 4)
  76. #define G2D_CMDLIST_NUM 64
  77. #define G2D_CMDLIST_POOL_SIZE (G2D_CMDLIST_SIZE * G2D_CMDLIST_NUM)
  78. #define G2D_CMDLIST_DATA_NUM (G2D_CMDLIST_SIZE / sizeof(u32) - 2)
  79. /* cmdlist data structure */
  80. struct g2d_cmdlist {
  81. u32 head;
  82. u32 data[G2D_CMDLIST_DATA_NUM];
  83. u32 last; /* last data offset */
  84. };
  85. struct drm_exynos_pending_g2d_event {
  86. struct drm_pending_event base;
  87. struct drm_exynos_g2d_event event;
  88. };
  89. struct g2d_gem_node {
  90. struct list_head list;
  91. unsigned int handle;
  92. };
  93. struct g2d_cmdlist_node {
  94. struct list_head list;
  95. struct g2d_cmdlist *cmdlist;
  96. unsigned int gem_nr;
  97. dma_addr_t dma_addr;
  98. struct drm_exynos_pending_g2d_event *event;
  99. };
  100. struct g2d_runqueue_node {
  101. struct list_head list;
  102. struct list_head run_cmdlist;
  103. struct list_head event_list;
  104. pid_t pid;
  105. struct completion complete;
  106. int async;
  107. };
  108. struct g2d_data {
  109. struct device *dev;
  110. struct clk *gate_clk;
  111. void __iomem *regs;
  112. int irq;
  113. struct workqueue_struct *g2d_workq;
  114. struct work_struct runqueue_work;
  115. struct exynos_drm_subdrv subdrv;
  116. bool suspended;
  117. /* cmdlist */
  118. struct g2d_cmdlist_node *cmdlist_node;
  119. struct list_head free_cmdlist;
  120. struct mutex cmdlist_mutex;
  121. dma_addr_t cmdlist_pool;
  122. void *cmdlist_pool_virt;
  123. /* runqueue*/
  124. struct g2d_runqueue_node *runqueue_node;
  125. struct list_head runqueue;
  126. struct mutex runqueue_mutex;
  127. struct kmem_cache *runqueue_slab;
  128. };
  129. static int g2d_init_cmdlist(struct g2d_data *g2d)
  130. {
  131. struct device *dev = g2d->dev;
  132. struct g2d_cmdlist_node *node = g2d->cmdlist_node;
  133. int nr;
  134. int ret;
  135. g2d->cmdlist_pool_virt = dma_alloc_coherent(dev, G2D_CMDLIST_POOL_SIZE,
  136. &g2d->cmdlist_pool, GFP_KERNEL);
  137. if (!g2d->cmdlist_pool_virt) {
  138. dev_err(dev, "failed to allocate dma memory\n");
  139. return -ENOMEM;
  140. }
  141. node = kcalloc(G2D_CMDLIST_NUM, sizeof(*node), GFP_KERNEL);
  142. if (!node) {
  143. dev_err(dev, "failed to allocate memory\n");
  144. ret = -ENOMEM;
  145. goto err;
  146. }
  147. for (nr = 0; nr < G2D_CMDLIST_NUM; nr++) {
  148. node[nr].cmdlist =
  149. g2d->cmdlist_pool_virt + nr * G2D_CMDLIST_SIZE;
  150. node[nr].dma_addr =
  151. g2d->cmdlist_pool + nr * G2D_CMDLIST_SIZE;
  152. list_add_tail(&node[nr].list, &g2d->free_cmdlist);
  153. }
  154. return 0;
  155. err:
  156. dma_free_coherent(dev, G2D_CMDLIST_POOL_SIZE, g2d->cmdlist_pool_virt,
  157. g2d->cmdlist_pool);
  158. return ret;
  159. }
  160. static void g2d_fini_cmdlist(struct g2d_data *g2d)
  161. {
  162. struct device *dev = g2d->dev;
  163. kfree(g2d->cmdlist_node);
  164. dma_free_coherent(dev, G2D_CMDLIST_POOL_SIZE, g2d->cmdlist_pool_virt,
  165. g2d->cmdlist_pool);
  166. }
  167. static struct g2d_cmdlist_node *g2d_get_cmdlist(struct g2d_data *g2d)
  168. {
  169. struct device *dev = g2d->dev;
  170. struct g2d_cmdlist_node *node;
  171. mutex_lock(&g2d->cmdlist_mutex);
  172. if (list_empty(&g2d->free_cmdlist)) {
  173. dev_err(dev, "there is no free cmdlist\n");
  174. mutex_unlock(&g2d->cmdlist_mutex);
  175. return NULL;
  176. }
  177. node = list_first_entry(&g2d->free_cmdlist, struct g2d_cmdlist_node,
  178. list);
  179. list_del_init(&node->list);
  180. mutex_unlock(&g2d->cmdlist_mutex);
  181. return node;
  182. }
  183. static void g2d_put_cmdlist(struct g2d_data *g2d, struct g2d_cmdlist_node *node)
  184. {
  185. mutex_lock(&g2d->cmdlist_mutex);
  186. list_move_tail(&node->list, &g2d->free_cmdlist);
  187. mutex_unlock(&g2d->cmdlist_mutex);
  188. }
  189. static void g2d_add_cmdlist_to_inuse(struct exynos_drm_g2d_private *g2d_priv,
  190. struct g2d_cmdlist_node *node)
  191. {
  192. struct g2d_cmdlist_node *lnode;
  193. if (list_empty(&g2d_priv->inuse_cmdlist))
  194. goto add_to_list;
  195. /* this links to base address of new cmdlist */
  196. lnode = list_entry(g2d_priv->inuse_cmdlist.prev,
  197. struct g2d_cmdlist_node, list);
  198. lnode->cmdlist->data[lnode->cmdlist->last] = node->dma_addr;
  199. add_to_list:
  200. list_add_tail(&node->list, &g2d_priv->inuse_cmdlist);
  201. if (node->event)
  202. list_add_tail(&node->event->base.link, &g2d_priv->event_list);
  203. }
  204. static int g2d_get_cmdlist_gem(struct drm_device *drm_dev,
  205. struct drm_file *file,
  206. struct g2d_cmdlist_node *node)
  207. {
  208. struct drm_exynos_file_private *file_priv = file->driver_priv;
  209. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  210. struct g2d_cmdlist *cmdlist = node->cmdlist;
  211. dma_addr_t *addr;
  212. int offset;
  213. int i;
  214. for (i = 0; i < node->gem_nr; i++) {
  215. struct g2d_gem_node *gem_node;
  216. gem_node = kzalloc(sizeof(*gem_node), GFP_KERNEL);
  217. if (!gem_node) {
  218. dev_err(g2d_priv->dev, "failed to allocate gem node\n");
  219. return -ENOMEM;
  220. }
  221. offset = cmdlist->last - (i * 2 + 1);
  222. gem_node->handle = cmdlist->data[offset];
  223. addr = exynos_drm_gem_get_dma_addr(drm_dev, gem_node->handle,
  224. file);
  225. if (IS_ERR(addr)) {
  226. node->gem_nr = i;
  227. kfree(gem_node);
  228. return PTR_ERR(addr);
  229. }
  230. cmdlist->data[offset] = *addr;
  231. list_add_tail(&gem_node->list, &g2d_priv->gem_list);
  232. g2d_priv->gem_nr++;
  233. }
  234. return 0;
  235. }
  236. static void g2d_put_cmdlist_gem(struct drm_device *drm_dev,
  237. struct drm_file *file,
  238. unsigned int nr)
  239. {
  240. struct drm_exynos_file_private *file_priv = file->driver_priv;
  241. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  242. struct g2d_gem_node *node, *n;
  243. list_for_each_entry_safe_reverse(node, n, &g2d_priv->gem_list, list) {
  244. if (!nr)
  245. break;
  246. exynos_drm_gem_put_dma_addr(drm_dev, node->handle, file);
  247. list_del_init(&node->list);
  248. kfree(node);
  249. nr--;
  250. }
  251. }
  252. static void g2d_dma_start(struct g2d_data *g2d,
  253. struct g2d_runqueue_node *runqueue_node)
  254. {
  255. struct g2d_cmdlist_node *node =
  256. list_first_entry(&runqueue_node->run_cmdlist,
  257. struct g2d_cmdlist_node, list);
  258. pm_runtime_get_sync(g2d->dev);
  259. clk_enable(g2d->gate_clk);
  260. /* interrupt enable */
  261. writel_relaxed(G2D_INTEN_ACF | G2D_INTEN_UCF | G2D_INTEN_GCF,
  262. g2d->regs + G2D_INTEN);
  263. writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR);
  264. writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND);
  265. }
  266. static struct g2d_runqueue_node *g2d_get_runqueue_node(struct g2d_data *g2d)
  267. {
  268. struct g2d_runqueue_node *runqueue_node;
  269. if (list_empty(&g2d->runqueue))
  270. return NULL;
  271. runqueue_node = list_first_entry(&g2d->runqueue,
  272. struct g2d_runqueue_node, list);
  273. list_del_init(&runqueue_node->list);
  274. return runqueue_node;
  275. }
  276. static void g2d_free_runqueue_node(struct g2d_data *g2d,
  277. struct g2d_runqueue_node *runqueue_node)
  278. {
  279. if (!runqueue_node)
  280. return;
  281. mutex_lock(&g2d->cmdlist_mutex);
  282. list_splice_tail_init(&runqueue_node->run_cmdlist, &g2d->free_cmdlist);
  283. mutex_unlock(&g2d->cmdlist_mutex);
  284. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  285. }
  286. static void g2d_exec_runqueue(struct g2d_data *g2d)
  287. {
  288. g2d->runqueue_node = g2d_get_runqueue_node(g2d);
  289. if (g2d->runqueue_node)
  290. g2d_dma_start(g2d, g2d->runqueue_node);
  291. }
  292. static void g2d_runqueue_worker(struct work_struct *work)
  293. {
  294. struct g2d_data *g2d = container_of(work, struct g2d_data,
  295. runqueue_work);
  296. mutex_lock(&g2d->runqueue_mutex);
  297. clk_disable(g2d->gate_clk);
  298. pm_runtime_put_sync(g2d->dev);
  299. complete(&g2d->runqueue_node->complete);
  300. if (g2d->runqueue_node->async)
  301. g2d_free_runqueue_node(g2d, g2d->runqueue_node);
  302. if (g2d->suspended)
  303. g2d->runqueue_node = NULL;
  304. else
  305. g2d_exec_runqueue(g2d);
  306. mutex_unlock(&g2d->runqueue_mutex);
  307. }
  308. static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no)
  309. {
  310. struct drm_device *drm_dev = g2d->subdrv.drm_dev;
  311. struct g2d_runqueue_node *runqueue_node = g2d->runqueue_node;
  312. struct drm_exynos_pending_g2d_event *e;
  313. struct timeval now;
  314. unsigned long flags;
  315. if (list_empty(&runqueue_node->event_list))
  316. return;
  317. e = list_first_entry(&runqueue_node->event_list,
  318. struct drm_exynos_pending_g2d_event, base.link);
  319. do_gettimeofday(&now);
  320. e->event.tv_sec = now.tv_sec;
  321. e->event.tv_usec = now.tv_usec;
  322. e->event.cmdlist_no = cmdlist_no;
  323. spin_lock_irqsave(&drm_dev->event_lock, flags);
  324. list_move_tail(&e->base.link, &e->base.file_priv->event_list);
  325. wake_up_interruptible(&e->base.file_priv->event_wait);
  326. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  327. }
  328. static irqreturn_t g2d_irq_handler(int irq, void *dev_id)
  329. {
  330. struct g2d_data *g2d = dev_id;
  331. u32 pending;
  332. pending = readl_relaxed(g2d->regs + G2D_INTC_PEND);
  333. if (pending)
  334. writel_relaxed(pending, g2d->regs + G2D_INTC_PEND);
  335. if (pending & G2D_INTP_GCMD_FIN) {
  336. u32 cmdlist_no = readl_relaxed(g2d->regs + G2D_DMA_STATUS);
  337. cmdlist_no = (cmdlist_no & G2D_DMA_LIST_DONE_COUNT) >>
  338. G2D_DMA_LIST_DONE_COUNT_OFFSET;
  339. g2d_finish_event(g2d, cmdlist_no);
  340. writel_relaxed(0, g2d->regs + G2D_DMA_HOLD_CMD);
  341. if (!(pending & G2D_INTP_ACMD_FIN)) {
  342. writel_relaxed(G2D_DMA_CONTINUE,
  343. g2d->regs + G2D_DMA_COMMAND);
  344. }
  345. }
  346. if (pending & G2D_INTP_ACMD_FIN)
  347. queue_work(g2d->g2d_workq, &g2d->runqueue_work);
  348. return IRQ_HANDLED;
  349. }
  350. static int g2d_check_reg_offset(struct device *dev, struct g2d_cmdlist *cmdlist,
  351. int nr, bool for_addr)
  352. {
  353. int reg_offset;
  354. int index;
  355. int i;
  356. for (i = 0; i < nr; i++) {
  357. index = cmdlist->last - 2 * (i + 1);
  358. reg_offset = cmdlist->data[index] & ~0xfffff000;
  359. if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END)
  360. goto err;
  361. if (reg_offset % 4)
  362. goto err;
  363. switch (reg_offset) {
  364. case G2D_SRC_BASE_ADDR:
  365. case G2D_SRC_PLANE2_BASE_ADDR:
  366. case G2D_DST_BASE_ADDR:
  367. case G2D_DST_PLANE2_BASE_ADDR:
  368. case G2D_PAT_BASE_ADDR:
  369. case G2D_MSK_BASE_ADDR:
  370. if (!for_addr)
  371. goto err;
  372. break;
  373. default:
  374. if (for_addr)
  375. goto err;
  376. break;
  377. }
  378. }
  379. return 0;
  380. err:
  381. dev_err(dev, "Bad register offset: 0x%x\n", cmdlist->data[index]);
  382. return -EINVAL;
  383. }
  384. /* ioctl functions */
  385. int exynos_g2d_get_ver_ioctl(struct drm_device *drm_dev, void *data,
  386. struct drm_file *file)
  387. {
  388. struct drm_exynos_g2d_get_ver *ver = data;
  389. ver->major = G2D_HW_MAJOR_VER;
  390. ver->minor = G2D_HW_MINOR_VER;
  391. return 0;
  392. }
  393. EXPORT_SYMBOL_GPL(exynos_g2d_get_ver_ioctl);
  394. int exynos_g2d_set_cmdlist_ioctl(struct drm_device *drm_dev, void *data,
  395. struct drm_file *file)
  396. {
  397. struct drm_exynos_file_private *file_priv = file->driver_priv;
  398. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  399. struct device *dev = g2d_priv->dev;
  400. struct g2d_data *g2d;
  401. struct drm_exynos_g2d_set_cmdlist *req = data;
  402. struct drm_exynos_g2d_cmd *cmd;
  403. struct drm_exynos_pending_g2d_event *e;
  404. struct g2d_cmdlist_node *node;
  405. struct g2d_cmdlist *cmdlist;
  406. unsigned long flags;
  407. int size;
  408. int ret;
  409. if (!dev)
  410. return -ENODEV;
  411. g2d = dev_get_drvdata(dev);
  412. if (!g2d)
  413. return -EFAULT;
  414. node = g2d_get_cmdlist(g2d);
  415. if (!node)
  416. return -ENOMEM;
  417. node->event = NULL;
  418. if (req->event_type != G2D_EVENT_NOT) {
  419. spin_lock_irqsave(&drm_dev->event_lock, flags);
  420. if (file->event_space < sizeof(e->event)) {
  421. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  422. ret = -ENOMEM;
  423. goto err;
  424. }
  425. file->event_space -= sizeof(e->event);
  426. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  427. e = kzalloc(sizeof(*node->event), GFP_KERNEL);
  428. if (!e) {
  429. dev_err(dev, "failed to allocate event\n");
  430. spin_lock_irqsave(&drm_dev->event_lock, flags);
  431. file->event_space += sizeof(e->event);
  432. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  433. ret = -ENOMEM;
  434. goto err;
  435. }
  436. e->event.base.type = DRM_EXYNOS_G2D_EVENT;
  437. e->event.base.length = sizeof(e->event);
  438. e->event.user_data = req->user_data;
  439. e->base.event = &e->event.base;
  440. e->base.file_priv = file;
  441. e->base.destroy = (void (*) (struct drm_pending_event *)) kfree;
  442. node->event = e;
  443. }
  444. cmdlist = node->cmdlist;
  445. cmdlist->last = 0;
  446. /*
  447. * If don't clear SFR registers, the cmdlist is affected by register
  448. * values of previous cmdlist. G2D hw executes SFR clear command and
  449. * a next command at the same time then the next command is ignored and
  450. * is executed rightly from next next command, so needs a dummy command
  451. * to next command of SFR clear command.
  452. */
  453. cmdlist->data[cmdlist->last++] = G2D_SOFT_RESET;
  454. cmdlist->data[cmdlist->last++] = G2D_SFRCLEAR;
  455. cmdlist->data[cmdlist->last++] = G2D_SRC_BASE_ADDR;
  456. cmdlist->data[cmdlist->last++] = 0;
  457. if (node->event) {
  458. cmdlist->data[cmdlist->last++] = G2D_DMA_HOLD_CMD;
  459. cmdlist->data[cmdlist->last++] = G2D_LIST_HOLD;
  460. }
  461. /* Check size of cmdlist: last 2 is about G2D_BITBLT_START */
  462. size = cmdlist->last + req->cmd_nr * 2 + req->cmd_gem_nr * 2 + 2;
  463. if (size > G2D_CMDLIST_DATA_NUM) {
  464. dev_err(dev, "cmdlist size is too big\n");
  465. ret = -EINVAL;
  466. goto err_free_event;
  467. }
  468. cmd = (struct drm_exynos_g2d_cmd *)(uint32_t)req->cmd;
  469. if (copy_from_user(cmdlist->data + cmdlist->last,
  470. (void __user *)cmd,
  471. sizeof(*cmd) * req->cmd_nr)) {
  472. ret = -EFAULT;
  473. goto err_free_event;
  474. }
  475. cmdlist->last += req->cmd_nr * 2;
  476. ret = g2d_check_reg_offset(dev, cmdlist, req->cmd_nr, false);
  477. if (ret < 0)
  478. goto err_free_event;
  479. node->gem_nr = req->cmd_gem_nr;
  480. if (req->cmd_gem_nr) {
  481. struct drm_exynos_g2d_cmd *cmd_gem;
  482. cmd_gem = (struct drm_exynos_g2d_cmd *)(uint32_t)req->cmd_gem;
  483. if (copy_from_user(cmdlist->data + cmdlist->last,
  484. (void __user *)cmd_gem,
  485. sizeof(*cmd_gem) * req->cmd_gem_nr)) {
  486. ret = -EFAULT;
  487. goto err_free_event;
  488. }
  489. cmdlist->last += req->cmd_gem_nr * 2;
  490. ret = g2d_check_reg_offset(dev, cmdlist, req->cmd_gem_nr, true);
  491. if (ret < 0)
  492. goto err_free_event;
  493. ret = g2d_get_cmdlist_gem(drm_dev, file, node);
  494. if (ret < 0)
  495. goto err_unmap;
  496. }
  497. cmdlist->data[cmdlist->last++] = G2D_BITBLT_START;
  498. cmdlist->data[cmdlist->last++] = G2D_START_BITBLT;
  499. /* head */
  500. cmdlist->head = cmdlist->last / 2;
  501. /* tail */
  502. cmdlist->data[cmdlist->last] = 0;
  503. g2d_add_cmdlist_to_inuse(g2d_priv, node);
  504. return 0;
  505. err_unmap:
  506. g2d_put_cmdlist_gem(drm_dev, file, node->gem_nr);
  507. err_free_event:
  508. if (node->event) {
  509. spin_lock_irqsave(&drm_dev->event_lock, flags);
  510. file->event_space += sizeof(e->event);
  511. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  512. kfree(node->event);
  513. }
  514. err:
  515. g2d_put_cmdlist(g2d, node);
  516. return ret;
  517. }
  518. EXPORT_SYMBOL_GPL(exynos_g2d_set_cmdlist_ioctl);
  519. int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data,
  520. struct drm_file *file)
  521. {
  522. struct drm_exynos_file_private *file_priv = file->driver_priv;
  523. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  524. struct device *dev = g2d_priv->dev;
  525. struct g2d_data *g2d;
  526. struct drm_exynos_g2d_exec *req = data;
  527. struct g2d_runqueue_node *runqueue_node;
  528. struct list_head *run_cmdlist;
  529. struct list_head *event_list;
  530. if (!dev)
  531. return -ENODEV;
  532. g2d = dev_get_drvdata(dev);
  533. if (!g2d)
  534. return -EFAULT;
  535. runqueue_node = kmem_cache_alloc(g2d->runqueue_slab, GFP_KERNEL);
  536. if (!runqueue_node) {
  537. dev_err(dev, "failed to allocate memory\n");
  538. return -ENOMEM;
  539. }
  540. run_cmdlist = &runqueue_node->run_cmdlist;
  541. event_list = &runqueue_node->event_list;
  542. INIT_LIST_HEAD(run_cmdlist);
  543. INIT_LIST_HEAD(event_list);
  544. init_completion(&runqueue_node->complete);
  545. runqueue_node->async = req->async;
  546. list_splice_init(&g2d_priv->inuse_cmdlist, run_cmdlist);
  547. list_splice_init(&g2d_priv->event_list, event_list);
  548. if (list_empty(run_cmdlist)) {
  549. dev_err(dev, "there is no inuse cmdlist\n");
  550. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  551. return -EPERM;
  552. }
  553. mutex_lock(&g2d->runqueue_mutex);
  554. runqueue_node->pid = current->pid;
  555. list_add_tail(&runqueue_node->list, &g2d->runqueue);
  556. if (!g2d->runqueue_node)
  557. g2d_exec_runqueue(g2d);
  558. mutex_unlock(&g2d->runqueue_mutex);
  559. if (runqueue_node->async)
  560. goto out;
  561. wait_for_completion(&runqueue_node->complete);
  562. g2d_free_runqueue_node(g2d, runqueue_node);
  563. out:
  564. return 0;
  565. }
  566. EXPORT_SYMBOL_GPL(exynos_g2d_exec_ioctl);
  567. static int g2d_open(struct drm_device *drm_dev, struct device *dev,
  568. struct drm_file *file)
  569. {
  570. struct drm_exynos_file_private *file_priv = file->driver_priv;
  571. struct exynos_drm_g2d_private *g2d_priv;
  572. g2d_priv = kzalloc(sizeof(*g2d_priv), GFP_KERNEL);
  573. if (!g2d_priv) {
  574. dev_err(dev, "failed to allocate g2d private data\n");
  575. return -ENOMEM;
  576. }
  577. g2d_priv->dev = dev;
  578. file_priv->g2d_priv = g2d_priv;
  579. INIT_LIST_HEAD(&g2d_priv->inuse_cmdlist);
  580. INIT_LIST_HEAD(&g2d_priv->event_list);
  581. INIT_LIST_HEAD(&g2d_priv->gem_list);
  582. return 0;
  583. }
  584. static void g2d_close(struct drm_device *drm_dev, struct device *dev,
  585. struct drm_file *file)
  586. {
  587. struct drm_exynos_file_private *file_priv = file->driver_priv;
  588. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  589. struct g2d_data *g2d;
  590. struct g2d_cmdlist_node *node, *n;
  591. if (!dev)
  592. return;
  593. g2d = dev_get_drvdata(dev);
  594. if (!g2d)
  595. return;
  596. mutex_lock(&g2d->cmdlist_mutex);
  597. list_for_each_entry_safe(node, n, &g2d_priv->inuse_cmdlist, list)
  598. list_move_tail(&node->list, &g2d->free_cmdlist);
  599. mutex_unlock(&g2d->cmdlist_mutex);
  600. g2d_put_cmdlist_gem(drm_dev, file, g2d_priv->gem_nr);
  601. kfree(file_priv->g2d_priv);
  602. }
  603. static int __devinit g2d_probe(struct platform_device *pdev)
  604. {
  605. struct device *dev = &pdev->dev;
  606. struct resource *res;
  607. struct g2d_data *g2d;
  608. struct exynos_drm_subdrv *subdrv;
  609. int ret;
  610. g2d = devm_kzalloc(&pdev->dev, sizeof(*g2d), GFP_KERNEL);
  611. if (!g2d) {
  612. dev_err(dev, "failed to allocate driver data\n");
  613. return -ENOMEM;
  614. }
  615. g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab",
  616. sizeof(struct g2d_runqueue_node), 0, 0, NULL);
  617. if (!g2d->runqueue_slab)
  618. return -ENOMEM;
  619. g2d->dev = dev;
  620. g2d->g2d_workq = create_singlethread_workqueue("g2d");
  621. if (!g2d->g2d_workq) {
  622. dev_err(dev, "failed to create workqueue\n");
  623. ret = -EINVAL;
  624. goto err_destroy_slab;
  625. }
  626. INIT_WORK(&g2d->runqueue_work, g2d_runqueue_worker);
  627. INIT_LIST_HEAD(&g2d->free_cmdlist);
  628. INIT_LIST_HEAD(&g2d->runqueue);
  629. mutex_init(&g2d->cmdlist_mutex);
  630. mutex_init(&g2d->runqueue_mutex);
  631. ret = g2d_init_cmdlist(g2d);
  632. if (ret < 0)
  633. goto err_destroy_workqueue;
  634. g2d->gate_clk = clk_get(dev, "fimg2d");
  635. if (IS_ERR(g2d->gate_clk)) {
  636. dev_err(dev, "failed to get gate clock\n");
  637. ret = PTR_ERR(g2d->gate_clk);
  638. goto err_fini_cmdlist;
  639. }
  640. pm_runtime_enable(dev);
  641. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  642. g2d->regs = devm_request_and_ioremap(&pdev->dev, res);
  643. if (!g2d->regs) {
  644. dev_err(dev, "failed to remap I/O memory\n");
  645. ret = -ENXIO;
  646. goto err_put_clk;
  647. }
  648. g2d->irq = platform_get_irq(pdev, 0);
  649. if (g2d->irq < 0) {
  650. dev_err(dev, "failed to get irq\n");
  651. ret = g2d->irq;
  652. goto err_put_clk;
  653. }
  654. ret = devm_request_irq(&pdev->dev, g2d->irq, g2d_irq_handler, 0,
  655. "drm_g2d", g2d);
  656. if (ret < 0) {
  657. dev_err(dev, "irq request failed\n");
  658. goto err_put_clk;
  659. }
  660. platform_set_drvdata(pdev, g2d);
  661. subdrv = &g2d->subdrv;
  662. subdrv->dev = dev;
  663. subdrv->open = g2d_open;
  664. subdrv->close = g2d_close;
  665. ret = exynos_drm_subdrv_register(subdrv);
  666. if (ret < 0) {
  667. dev_err(dev, "failed to register drm g2d device\n");
  668. goto err_put_clk;
  669. }
  670. dev_info(dev, "The exynos g2d(ver %d.%d) successfully probed\n",
  671. G2D_HW_MAJOR_VER, G2D_HW_MINOR_VER);
  672. return 0;
  673. err_put_clk:
  674. pm_runtime_disable(dev);
  675. clk_put(g2d->gate_clk);
  676. err_fini_cmdlist:
  677. g2d_fini_cmdlist(g2d);
  678. err_destroy_workqueue:
  679. destroy_workqueue(g2d->g2d_workq);
  680. err_destroy_slab:
  681. kmem_cache_destroy(g2d->runqueue_slab);
  682. return ret;
  683. }
  684. static int __devexit g2d_remove(struct platform_device *pdev)
  685. {
  686. struct g2d_data *g2d = platform_get_drvdata(pdev);
  687. cancel_work_sync(&g2d->runqueue_work);
  688. exynos_drm_subdrv_unregister(&g2d->subdrv);
  689. while (g2d->runqueue_node) {
  690. g2d_free_runqueue_node(g2d, g2d->runqueue_node);
  691. g2d->runqueue_node = g2d_get_runqueue_node(g2d);
  692. }
  693. pm_runtime_disable(&pdev->dev);
  694. clk_put(g2d->gate_clk);
  695. g2d_fini_cmdlist(g2d);
  696. destroy_workqueue(g2d->g2d_workq);
  697. kmem_cache_destroy(g2d->runqueue_slab);
  698. return 0;
  699. }
  700. #ifdef CONFIG_PM_SLEEP
  701. static int g2d_suspend(struct device *dev)
  702. {
  703. struct g2d_data *g2d = dev_get_drvdata(dev);
  704. mutex_lock(&g2d->runqueue_mutex);
  705. g2d->suspended = true;
  706. mutex_unlock(&g2d->runqueue_mutex);
  707. while (g2d->runqueue_node)
  708. /* FIXME: good range? */
  709. usleep_range(500, 1000);
  710. flush_work(&g2d->runqueue_work);
  711. return 0;
  712. }
  713. static int g2d_resume(struct device *dev)
  714. {
  715. struct g2d_data *g2d = dev_get_drvdata(dev);
  716. g2d->suspended = false;
  717. g2d_exec_runqueue(g2d);
  718. return 0;
  719. }
  720. #endif
  721. static SIMPLE_DEV_PM_OPS(g2d_pm_ops, g2d_suspend, g2d_resume);
  722. struct platform_driver g2d_driver = {
  723. .probe = g2d_probe,
  724. .remove = __devexit_p(g2d_remove),
  725. .driver = {
  726. .name = "s5p-g2d",
  727. .owner = THIS_MODULE,
  728. .pm = &g2d_pm_ops,
  729. },
  730. };