be_main.c 138 KB

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  1. /**
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  48. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  49. MODULE_VERSION(BUILD_STR);
  50. MODULE_AUTHOR("Emulex Corporation");
  51. MODULE_LICENSE("GPL");
  52. module_param(be_iopoll_budget, int, 0);
  53. module_param(enable_msix, int, 0);
  54. module_param(be_max_phys_size, uint, S_IRUGO);
  55. MODULE_PARM_DESC(be_max_phys_size,
  56. "Maximum Size (In Kilobytes) of physically contiguous "
  57. "memory that can be allocated. Range is 16 - 128");
  58. #define beiscsi_disp_param(_name)\
  59. ssize_t \
  60. beiscsi_##_name##_disp(struct device *dev,\
  61. struct device_attribute *attrib, char *buf) \
  62. { \
  63. struct Scsi_Host *shost = class_to_shost(dev);\
  64. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  65. uint32_t param_val = 0; \
  66. param_val = phba->attr_##_name;\
  67. return snprintf(buf, PAGE_SIZE, "%d\n",\
  68. phba->attr_##_name);\
  69. }
  70. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  71. int \
  72. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  73. {\
  74. if (val >= _minval && val <= _maxval) {\
  75. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  76. "BA_%d : beiscsi_"#_name" updated "\
  77. "from 0x%x ==> 0x%x\n",\
  78. phba->attr_##_name, val); \
  79. phba->attr_##_name = val;\
  80. return 0;\
  81. } \
  82. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  83. "BA_%d beiscsi_"#_name" attribute "\
  84. "cannot be updated to 0x%x, "\
  85. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  86. return -EINVAL;\
  87. }
  88. #define beiscsi_store_param(_name) \
  89. ssize_t \
  90. beiscsi_##_name##_store(struct device *dev,\
  91. struct device_attribute *attr, const char *buf,\
  92. size_t count) \
  93. { \
  94. struct Scsi_Host *shost = class_to_shost(dev);\
  95. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  96. uint32_t param_val = 0;\
  97. if (!isdigit(buf[0]))\
  98. return -EINVAL;\
  99. if (sscanf(buf, "%i", &param_val) != 1)\
  100. return -EINVAL;\
  101. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  102. return strlen(buf);\
  103. else \
  104. return -EINVAL;\
  105. }
  106. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  107. int \
  108. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  109. { \
  110. if (val >= _minval && val <= _maxval) {\
  111. phba->attr_##_name = val;\
  112. return 0;\
  113. } \
  114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  115. "BA_%d beiscsi_"#_name" attribute " \
  116. "cannot be updated to 0x%x, "\
  117. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  118. phba->attr_##_name = _defval;\
  119. return -EINVAL;\
  120. }
  121. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  122. static uint beiscsi_##_name = _defval;\
  123. module_param(beiscsi_##_name, uint, S_IRUGO);\
  124. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  125. beiscsi_disp_param(_name)\
  126. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  127. beiscsi_store_param(_name)\
  128. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  129. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  130. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  131. /*
  132. * When new log level added update the
  133. * the MAX allowed value for log_enable
  134. */
  135. BEISCSI_RW_ATTR(log_enable, 0x00,
  136. 0xFF, 0x00, "Enable logging Bit Mask\n"
  137. "\t\t\t\tInitialization Events : 0x01\n"
  138. "\t\t\t\tMailbox Events : 0x02\n"
  139. "\t\t\t\tMiscellaneous Events : 0x04\n"
  140. "\t\t\t\tError Handling : 0x08\n"
  141. "\t\t\t\tIO Path Events : 0x10\n"
  142. "\t\t\t\tConfiguration Path : 0x20\n");
  143. DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
  144. struct device_attribute *beiscsi_attrs[] = {
  145. &dev_attr_beiscsi_log_enable,
  146. &dev_attr_beiscsi_drvr_ver,
  147. NULL,
  148. };
  149. static char const *cqe_desc[] = {
  150. "RESERVED_DESC",
  151. "SOL_CMD_COMPLETE",
  152. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  153. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  154. "CXN_KILLED_BURST_LEN_MISMATCH",
  155. "CXN_KILLED_AHS_RCVD",
  156. "CXN_KILLED_HDR_DIGEST_ERR",
  157. "CXN_KILLED_UNKNOWN_HDR",
  158. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  159. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  160. "CXN_KILLED_RST_RCVD",
  161. "CXN_KILLED_TIMED_OUT",
  162. "CXN_KILLED_RST_SENT",
  163. "CXN_KILLED_FIN_RCVD",
  164. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  165. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  166. "CXN_KILLED_OVER_RUN_RESIDUAL",
  167. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  168. "CMD_KILLED_INVALID_STATSN_RCVD",
  169. "CMD_KILLED_INVALID_R2T_RCVD",
  170. "CMD_CXN_KILLED_LUN_INVALID",
  171. "CMD_CXN_KILLED_ICD_INVALID",
  172. "CMD_CXN_KILLED_ITT_INVALID",
  173. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  174. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  175. "CXN_INVALIDATE_NOTIFY",
  176. "CXN_INVALIDATE_INDEX_NOTIFY",
  177. "CMD_INVALIDATED_NOTIFY",
  178. "UNSOL_HDR_NOTIFY",
  179. "UNSOL_DATA_NOTIFY",
  180. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  181. "DRIVERMSG_NOTIFY",
  182. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  183. "SOL_CMD_KILLED_DIF_ERR",
  184. "CXN_KILLED_SYN_RCVD",
  185. "CXN_KILLED_IMM_DATA_RCVD"
  186. };
  187. static int beiscsi_slave_configure(struct scsi_device *sdev)
  188. {
  189. blk_queue_max_segment_size(sdev->request_queue, 65536);
  190. return 0;
  191. }
  192. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  193. {
  194. struct iscsi_cls_session *cls_session;
  195. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  196. struct beiscsi_io_task *aborted_io_task;
  197. struct iscsi_conn *conn;
  198. struct beiscsi_conn *beiscsi_conn;
  199. struct beiscsi_hba *phba;
  200. struct iscsi_session *session;
  201. struct invalidate_command_table *inv_tbl;
  202. struct be_dma_mem nonemb_cmd;
  203. unsigned int cid, tag, num_invalidate;
  204. cls_session = starget_to_session(scsi_target(sc->device));
  205. session = cls_session->dd_data;
  206. spin_lock_bh(&session->lock);
  207. if (!aborted_task || !aborted_task->sc) {
  208. /* we raced */
  209. spin_unlock_bh(&session->lock);
  210. return SUCCESS;
  211. }
  212. aborted_io_task = aborted_task->dd_data;
  213. if (!aborted_io_task->scsi_cmnd) {
  214. /* raced or invalid command */
  215. spin_unlock_bh(&session->lock);
  216. return SUCCESS;
  217. }
  218. spin_unlock_bh(&session->lock);
  219. conn = aborted_task->conn;
  220. beiscsi_conn = conn->dd_data;
  221. phba = beiscsi_conn->phba;
  222. /* invalidate iocb */
  223. cid = beiscsi_conn->beiscsi_conn_cid;
  224. inv_tbl = phba->inv_tbl;
  225. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  226. inv_tbl->cid = cid;
  227. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  228. num_invalidate = 1;
  229. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  230. sizeof(struct invalidate_commands_params_in),
  231. &nonemb_cmd.dma);
  232. if (nonemb_cmd.va == NULL) {
  233. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  234. "BM_%d : Failed to allocate memory for"
  235. "mgmt_invalidate_icds\n");
  236. return FAILED;
  237. }
  238. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  239. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  240. cid, &nonemb_cmd);
  241. if (!tag) {
  242. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  243. "BM_%d : mgmt_invalidate_icds could not be"
  244. "submitted\n");
  245. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  246. nonemb_cmd.va, nonemb_cmd.dma);
  247. return FAILED;
  248. } else {
  249. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  250. phba->ctrl.mcc_numtag[tag]);
  251. free_mcc_tag(&phba->ctrl, tag);
  252. }
  253. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  254. nonemb_cmd.va, nonemb_cmd.dma);
  255. return iscsi_eh_abort(sc);
  256. }
  257. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  258. {
  259. struct iscsi_task *abrt_task;
  260. struct beiscsi_io_task *abrt_io_task;
  261. struct iscsi_conn *conn;
  262. struct beiscsi_conn *beiscsi_conn;
  263. struct beiscsi_hba *phba;
  264. struct iscsi_session *session;
  265. struct iscsi_cls_session *cls_session;
  266. struct invalidate_command_table *inv_tbl;
  267. struct be_dma_mem nonemb_cmd;
  268. unsigned int cid, tag, i, num_invalidate;
  269. /* invalidate iocbs */
  270. cls_session = starget_to_session(scsi_target(sc->device));
  271. session = cls_session->dd_data;
  272. spin_lock_bh(&session->lock);
  273. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  274. spin_unlock_bh(&session->lock);
  275. return FAILED;
  276. }
  277. conn = session->leadconn;
  278. beiscsi_conn = conn->dd_data;
  279. phba = beiscsi_conn->phba;
  280. cid = beiscsi_conn->beiscsi_conn_cid;
  281. inv_tbl = phba->inv_tbl;
  282. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  283. num_invalidate = 0;
  284. for (i = 0; i < conn->session->cmds_max; i++) {
  285. abrt_task = conn->session->cmds[i];
  286. abrt_io_task = abrt_task->dd_data;
  287. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  288. continue;
  289. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  290. continue;
  291. inv_tbl->cid = cid;
  292. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  293. num_invalidate++;
  294. inv_tbl++;
  295. }
  296. spin_unlock_bh(&session->lock);
  297. inv_tbl = phba->inv_tbl;
  298. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  299. sizeof(struct invalidate_commands_params_in),
  300. &nonemb_cmd.dma);
  301. if (nonemb_cmd.va == NULL) {
  302. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  303. "BM_%d : Failed to allocate memory for"
  304. "mgmt_invalidate_icds\n");
  305. return FAILED;
  306. }
  307. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  308. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  309. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  310. cid, &nonemb_cmd);
  311. if (!tag) {
  312. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  313. "BM_%d : mgmt_invalidate_icds could not be"
  314. " submitted\n");
  315. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  316. nonemb_cmd.va, nonemb_cmd.dma);
  317. return FAILED;
  318. } else {
  319. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  320. phba->ctrl.mcc_numtag[tag]);
  321. free_mcc_tag(&phba->ctrl, tag);
  322. }
  323. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  324. nonemb_cmd.va, nonemb_cmd.dma);
  325. return iscsi_eh_device_reset(sc);
  326. }
  327. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  328. {
  329. struct beiscsi_hba *phba = data;
  330. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  331. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  332. char *str = buf;
  333. int rc;
  334. switch (type) {
  335. case ISCSI_BOOT_TGT_NAME:
  336. rc = sprintf(buf, "%.*s\n",
  337. (int)strlen(boot_sess->target_name),
  338. (char *)&boot_sess->target_name);
  339. break;
  340. case ISCSI_BOOT_TGT_IP_ADDR:
  341. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  342. rc = sprintf(buf, "%pI4\n",
  343. (char *)&boot_conn->dest_ipaddr.addr);
  344. else
  345. rc = sprintf(str, "%pI6\n",
  346. (char *)&boot_conn->dest_ipaddr.addr);
  347. break;
  348. case ISCSI_BOOT_TGT_PORT:
  349. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  350. break;
  351. case ISCSI_BOOT_TGT_CHAP_NAME:
  352. rc = sprintf(str, "%.*s\n",
  353. boot_conn->negotiated_login_options.auth_data.chap.
  354. target_chap_name_length,
  355. (char *)&boot_conn->negotiated_login_options.
  356. auth_data.chap.target_chap_name);
  357. break;
  358. case ISCSI_BOOT_TGT_CHAP_SECRET:
  359. rc = sprintf(str, "%.*s\n",
  360. boot_conn->negotiated_login_options.auth_data.chap.
  361. target_secret_length,
  362. (char *)&boot_conn->negotiated_login_options.
  363. auth_data.chap.target_secret);
  364. break;
  365. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  366. rc = sprintf(str, "%.*s\n",
  367. boot_conn->negotiated_login_options.auth_data.chap.
  368. intr_chap_name_length,
  369. (char *)&boot_conn->negotiated_login_options.
  370. auth_data.chap.intr_chap_name);
  371. break;
  372. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  373. rc = sprintf(str, "%.*s\n",
  374. boot_conn->negotiated_login_options.auth_data.chap.
  375. intr_secret_length,
  376. (char *)&boot_conn->negotiated_login_options.
  377. auth_data.chap.intr_secret);
  378. break;
  379. case ISCSI_BOOT_TGT_FLAGS:
  380. rc = sprintf(str, "2\n");
  381. break;
  382. case ISCSI_BOOT_TGT_NIC_ASSOC:
  383. rc = sprintf(str, "0\n");
  384. break;
  385. default:
  386. rc = -ENOSYS;
  387. break;
  388. }
  389. return rc;
  390. }
  391. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  392. {
  393. struct beiscsi_hba *phba = data;
  394. char *str = buf;
  395. int rc;
  396. switch (type) {
  397. case ISCSI_BOOT_INI_INITIATOR_NAME:
  398. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  399. break;
  400. default:
  401. rc = -ENOSYS;
  402. break;
  403. }
  404. return rc;
  405. }
  406. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  407. {
  408. struct beiscsi_hba *phba = data;
  409. char *str = buf;
  410. int rc;
  411. switch (type) {
  412. case ISCSI_BOOT_ETH_FLAGS:
  413. rc = sprintf(str, "2\n");
  414. break;
  415. case ISCSI_BOOT_ETH_INDEX:
  416. rc = sprintf(str, "0\n");
  417. break;
  418. case ISCSI_BOOT_ETH_MAC:
  419. rc = beiscsi_get_macaddr(str, phba);
  420. break;
  421. default:
  422. rc = -ENOSYS;
  423. break;
  424. }
  425. return rc;
  426. }
  427. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  428. {
  429. umode_t rc;
  430. switch (type) {
  431. case ISCSI_BOOT_TGT_NAME:
  432. case ISCSI_BOOT_TGT_IP_ADDR:
  433. case ISCSI_BOOT_TGT_PORT:
  434. case ISCSI_BOOT_TGT_CHAP_NAME:
  435. case ISCSI_BOOT_TGT_CHAP_SECRET:
  436. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  437. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  438. case ISCSI_BOOT_TGT_NIC_ASSOC:
  439. case ISCSI_BOOT_TGT_FLAGS:
  440. rc = S_IRUGO;
  441. break;
  442. default:
  443. rc = 0;
  444. break;
  445. }
  446. return rc;
  447. }
  448. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  449. {
  450. umode_t rc;
  451. switch (type) {
  452. case ISCSI_BOOT_INI_INITIATOR_NAME:
  453. rc = S_IRUGO;
  454. break;
  455. default:
  456. rc = 0;
  457. break;
  458. }
  459. return rc;
  460. }
  461. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  462. {
  463. umode_t rc;
  464. switch (type) {
  465. case ISCSI_BOOT_ETH_FLAGS:
  466. case ISCSI_BOOT_ETH_MAC:
  467. case ISCSI_BOOT_ETH_INDEX:
  468. rc = S_IRUGO;
  469. break;
  470. default:
  471. rc = 0;
  472. break;
  473. }
  474. return rc;
  475. }
  476. /*------------------- PCI Driver operations and data ----------------- */
  477. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  478. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  479. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  480. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  481. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  482. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  483. { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
  484. { 0 }
  485. };
  486. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  487. static struct scsi_host_template beiscsi_sht = {
  488. .module = THIS_MODULE,
  489. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  490. .proc_name = DRV_NAME,
  491. .queuecommand = iscsi_queuecommand,
  492. .change_queue_depth = iscsi_change_queue_depth,
  493. .slave_configure = beiscsi_slave_configure,
  494. .target_alloc = iscsi_target_alloc,
  495. .eh_abort_handler = beiscsi_eh_abort,
  496. .eh_device_reset_handler = beiscsi_eh_device_reset,
  497. .eh_target_reset_handler = iscsi_eh_session_reset,
  498. .shost_attrs = beiscsi_attrs,
  499. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  500. .can_queue = BE2_IO_DEPTH,
  501. .this_id = -1,
  502. .max_sectors = BEISCSI_MAX_SECTORS,
  503. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  504. .use_clustering = ENABLE_CLUSTERING,
  505. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  506. };
  507. static struct scsi_transport_template *beiscsi_scsi_transport;
  508. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  509. {
  510. struct beiscsi_hba *phba;
  511. struct Scsi_Host *shost;
  512. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  513. if (!shost) {
  514. dev_err(&pcidev->dev,
  515. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  516. return NULL;
  517. }
  518. shost->dma_boundary = pcidev->dma_mask;
  519. shost->max_id = BE2_MAX_SESSIONS;
  520. shost->max_channel = 0;
  521. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  522. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  523. shost->transportt = beiscsi_scsi_transport;
  524. phba = iscsi_host_priv(shost);
  525. memset(phba, 0, sizeof(*phba));
  526. phba->shost = shost;
  527. phba->pcidev = pci_dev_get(pcidev);
  528. pci_set_drvdata(pcidev, phba);
  529. phba->interface_handle = 0xFFFFFFFF;
  530. if (iscsi_host_add(shost, &phba->pcidev->dev))
  531. goto free_devices;
  532. return phba;
  533. free_devices:
  534. pci_dev_put(phba->pcidev);
  535. iscsi_host_free(phba->shost);
  536. return NULL;
  537. }
  538. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  539. {
  540. if (phba->csr_va) {
  541. iounmap(phba->csr_va);
  542. phba->csr_va = NULL;
  543. }
  544. if (phba->db_va) {
  545. iounmap(phba->db_va);
  546. phba->db_va = NULL;
  547. }
  548. if (phba->pci_va) {
  549. iounmap(phba->pci_va);
  550. phba->pci_va = NULL;
  551. }
  552. }
  553. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  554. struct pci_dev *pcidev)
  555. {
  556. u8 __iomem *addr;
  557. int pcicfg_reg;
  558. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  559. pci_resource_len(pcidev, 2));
  560. if (addr == NULL)
  561. return -ENOMEM;
  562. phba->ctrl.csr = addr;
  563. phba->csr_va = addr;
  564. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  565. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  566. if (addr == NULL)
  567. goto pci_map_err;
  568. phba->ctrl.db = addr;
  569. phba->db_va = addr;
  570. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  571. if (phba->generation == BE_GEN2)
  572. pcicfg_reg = 1;
  573. else
  574. pcicfg_reg = 0;
  575. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  576. pci_resource_len(pcidev, pcicfg_reg));
  577. if (addr == NULL)
  578. goto pci_map_err;
  579. phba->ctrl.pcicfg = addr;
  580. phba->pci_va = addr;
  581. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  582. return 0;
  583. pci_map_err:
  584. beiscsi_unmap_pci_function(phba);
  585. return -ENOMEM;
  586. }
  587. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  588. {
  589. int ret;
  590. ret = pci_enable_device(pcidev);
  591. if (ret) {
  592. dev_err(&pcidev->dev,
  593. "beiscsi_enable_pci - enable device failed\n");
  594. return ret;
  595. }
  596. pci_set_master(pcidev);
  597. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  598. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  599. if (ret) {
  600. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  601. pci_disable_device(pcidev);
  602. return ret;
  603. }
  604. }
  605. return 0;
  606. }
  607. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  608. {
  609. struct be_ctrl_info *ctrl = &phba->ctrl;
  610. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  611. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  612. int status = 0;
  613. ctrl->pdev = pdev;
  614. status = beiscsi_map_pci_bars(phba, pdev);
  615. if (status)
  616. return status;
  617. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  618. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  619. mbox_mem_alloc->size,
  620. &mbox_mem_alloc->dma);
  621. if (!mbox_mem_alloc->va) {
  622. beiscsi_unmap_pci_function(phba);
  623. return -ENOMEM;
  624. }
  625. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  626. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  627. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  628. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  629. spin_lock_init(&ctrl->mbox_lock);
  630. spin_lock_init(&phba->ctrl.mcc_lock);
  631. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  632. return status;
  633. }
  634. static void beiscsi_get_params(struct beiscsi_hba *phba)
  635. {
  636. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  637. - (phba->fw_config.iscsi_cid_count
  638. + BE2_TMFS
  639. + BE2_NOPOUT_REQ));
  640. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  641. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  642. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  643. phba->params.num_sge_per_io = BE2_SGE;
  644. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  645. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  646. phba->params.eq_timer = 64;
  647. phba->params.num_eq_entries =
  648. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  649. + BE2_TMFS) / 512) + 1) * 512;
  650. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  651. ? 1024 : phba->params.num_eq_entries;
  652. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  653. "BM_%d : phba->params.num_eq_entries=%d\n",
  654. phba->params.num_eq_entries);
  655. phba->params.num_cq_entries =
  656. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  657. + BE2_TMFS) / 512) + 1) * 512;
  658. phba->params.wrbs_per_cxn = 256;
  659. }
  660. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  661. unsigned int id, unsigned int clr_interrupt,
  662. unsigned int num_processed,
  663. unsigned char rearm, unsigned char event)
  664. {
  665. u32 val = 0;
  666. val |= id & DB_EQ_RING_ID_MASK;
  667. if (rearm)
  668. val |= 1 << DB_EQ_REARM_SHIFT;
  669. if (clr_interrupt)
  670. val |= 1 << DB_EQ_CLR_SHIFT;
  671. if (event)
  672. val |= 1 << DB_EQ_EVNT_SHIFT;
  673. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  674. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  675. }
  676. /**
  677. * be_isr_mcc - The isr routine of the driver.
  678. * @irq: Not used
  679. * @dev_id: Pointer to host adapter structure
  680. */
  681. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  682. {
  683. struct beiscsi_hba *phba;
  684. struct be_eq_entry *eqe = NULL;
  685. struct be_queue_info *eq;
  686. struct be_queue_info *mcc;
  687. unsigned int num_eq_processed;
  688. struct be_eq_obj *pbe_eq;
  689. unsigned long flags;
  690. pbe_eq = dev_id;
  691. eq = &pbe_eq->q;
  692. phba = pbe_eq->phba;
  693. mcc = &phba->ctrl.mcc_obj.cq;
  694. eqe = queue_tail_node(eq);
  695. num_eq_processed = 0;
  696. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  697. & EQE_VALID_MASK) {
  698. if (((eqe->dw[offsetof(struct amap_eq_entry,
  699. resource_id) / 32] &
  700. EQE_RESID_MASK) >> 16) == mcc->id) {
  701. spin_lock_irqsave(&phba->isr_lock, flags);
  702. pbe_eq->todo_mcc_cq = true;
  703. spin_unlock_irqrestore(&phba->isr_lock, flags);
  704. }
  705. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  706. queue_tail_inc(eq);
  707. eqe = queue_tail_node(eq);
  708. num_eq_processed++;
  709. }
  710. if (pbe_eq->todo_mcc_cq)
  711. queue_work(phba->wq, &pbe_eq->work_cqs);
  712. if (num_eq_processed)
  713. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  714. return IRQ_HANDLED;
  715. }
  716. /**
  717. * be_isr_msix - The isr routine of the driver.
  718. * @irq: Not used
  719. * @dev_id: Pointer to host adapter structure
  720. */
  721. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  722. {
  723. struct beiscsi_hba *phba;
  724. struct be_eq_entry *eqe = NULL;
  725. struct be_queue_info *eq;
  726. struct be_queue_info *cq;
  727. unsigned int num_eq_processed;
  728. struct be_eq_obj *pbe_eq;
  729. unsigned long flags;
  730. pbe_eq = dev_id;
  731. eq = &pbe_eq->q;
  732. cq = pbe_eq->cq;
  733. eqe = queue_tail_node(eq);
  734. phba = pbe_eq->phba;
  735. num_eq_processed = 0;
  736. if (blk_iopoll_enabled) {
  737. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  738. & EQE_VALID_MASK) {
  739. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  740. blk_iopoll_sched(&pbe_eq->iopoll);
  741. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  742. queue_tail_inc(eq);
  743. eqe = queue_tail_node(eq);
  744. num_eq_processed++;
  745. }
  746. } else {
  747. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  748. & EQE_VALID_MASK) {
  749. spin_lock_irqsave(&phba->isr_lock, flags);
  750. pbe_eq->todo_cq = true;
  751. spin_unlock_irqrestore(&phba->isr_lock, flags);
  752. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  753. queue_tail_inc(eq);
  754. eqe = queue_tail_node(eq);
  755. num_eq_processed++;
  756. }
  757. if (pbe_eq->todo_cq)
  758. queue_work(phba->wq, &pbe_eq->work_cqs);
  759. }
  760. if (num_eq_processed)
  761. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  762. return IRQ_HANDLED;
  763. }
  764. /**
  765. * be_isr - The isr routine of the driver.
  766. * @irq: Not used
  767. * @dev_id: Pointer to host adapter structure
  768. */
  769. static irqreturn_t be_isr(int irq, void *dev_id)
  770. {
  771. struct beiscsi_hba *phba;
  772. struct hwi_controller *phwi_ctrlr;
  773. struct hwi_context_memory *phwi_context;
  774. struct be_eq_entry *eqe = NULL;
  775. struct be_queue_info *eq;
  776. struct be_queue_info *cq;
  777. struct be_queue_info *mcc;
  778. unsigned long flags, index;
  779. unsigned int num_mcceq_processed, num_ioeq_processed;
  780. struct be_ctrl_info *ctrl;
  781. struct be_eq_obj *pbe_eq;
  782. int isr;
  783. phba = dev_id;
  784. ctrl = &phba->ctrl;
  785. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  786. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  787. if (!isr)
  788. return IRQ_NONE;
  789. phwi_ctrlr = phba->phwi_ctrlr;
  790. phwi_context = phwi_ctrlr->phwi_ctxt;
  791. pbe_eq = &phwi_context->be_eq[0];
  792. eq = &phwi_context->be_eq[0].q;
  793. mcc = &phba->ctrl.mcc_obj.cq;
  794. index = 0;
  795. eqe = queue_tail_node(eq);
  796. num_ioeq_processed = 0;
  797. num_mcceq_processed = 0;
  798. if (blk_iopoll_enabled) {
  799. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  800. & EQE_VALID_MASK) {
  801. if (((eqe->dw[offsetof(struct amap_eq_entry,
  802. resource_id) / 32] &
  803. EQE_RESID_MASK) >> 16) == mcc->id) {
  804. spin_lock_irqsave(&phba->isr_lock, flags);
  805. pbe_eq->todo_mcc_cq = true;
  806. spin_unlock_irqrestore(&phba->isr_lock, flags);
  807. num_mcceq_processed++;
  808. } else {
  809. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  810. blk_iopoll_sched(&pbe_eq->iopoll);
  811. num_ioeq_processed++;
  812. }
  813. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  814. queue_tail_inc(eq);
  815. eqe = queue_tail_node(eq);
  816. }
  817. if (num_ioeq_processed || num_mcceq_processed) {
  818. if (pbe_eq->todo_mcc_cq)
  819. queue_work(phba->wq, &pbe_eq->work_cqs);
  820. if ((num_mcceq_processed) && (!num_ioeq_processed))
  821. hwi_ring_eq_db(phba, eq->id, 0,
  822. (num_ioeq_processed +
  823. num_mcceq_processed) , 1, 1);
  824. else
  825. hwi_ring_eq_db(phba, eq->id, 0,
  826. (num_ioeq_processed +
  827. num_mcceq_processed), 0, 1);
  828. return IRQ_HANDLED;
  829. } else
  830. return IRQ_NONE;
  831. } else {
  832. cq = &phwi_context->be_cq[0];
  833. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  834. & EQE_VALID_MASK) {
  835. if (((eqe->dw[offsetof(struct amap_eq_entry,
  836. resource_id) / 32] &
  837. EQE_RESID_MASK) >> 16) != cq->id) {
  838. spin_lock_irqsave(&phba->isr_lock, flags);
  839. pbe_eq->todo_mcc_cq = true;
  840. spin_unlock_irqrestore(&phba->isr_lock, flags);
  841. } else {
  842. spin_lock_irqsave(&phba->isr_lock, flags);
  843. pbe_eq->todo_cq = true;
  844. spin_unlock_irqrestore(&phba->isr_lock, flags);
  845. }
  846. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  847. queue_tail_inc(eq);
  848. eqe = queue_tail_node(eq);
  849. num_ioeq_processed++;
  850. }
  851. if (pbe_eq->todo_cq || pbe_eq->todo_mcc_cq)
  852. queue_work(phba->wq, &pbe_eq->work_cqs);
  853. if (num_ioeq_processed) {
  854. hwi_ring_eq_db(phba, eq->id, 0,
  855. num_ioeq_processed, 1, 1);
  856. return IRQ_HANDLED;
  857. } else
  858. return IRQ_NONE;
  859. }
  860. }
  861. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  862. {
  863. struct pci_dev *pcidev = phba->pcidev;
  864. struct hwi_controller *phwi_ctrlr;
  865. struct hwi_context_memory *phwi_context;
  866. int ret, msix_vec, i, j;
  867. phwi_ctrlr = phba->phwi_ctrlr;
  868. phwi_context = phwi_ctrlr->phwi_ctxt;
  869. if (phba->msix_enabled) {
  870. for (i = 0; i < phba->num_cpus; i++) {
  871. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  872. GFP_KERNEL);
  873. if (!phba->msi_name[i]) {
  874. ret = -ENOMEM;
  875. goto free_msix_irqs;
  876. }
  877. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  878. phba->shost->host_no, i);
  879. msix_vec = phba->msix_entries[i].vector;
  880. ret = request_irq(msix_vec, be_isr_msix, 0,
  881. phba->msi_name[i],
  882. &phwi_context->be_eq[i]);
  883. if (ret) {
  884. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  885. "BM_%d : beiscsi_init_irqs-Failed to"
  886. "register msix for i = %d\n",
  887. i);
  888. kfree(phba->msi_name[i]);
  889. goto free_msix_irqs;
  890. }
  891. }
  892. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  893. if (!phba->msi_name[i]) {
  894. ret = -ENOMEM;
  895. goto free_msix_irqs;
  896. }
  897. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  898. phba->shost->host_no);
  899. msix_vec = phba->msix_entries[i].vector;
  900. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  901. &phwi_context->be_eq[i]);
  902. if (ret) {
  903. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  904. "BM_%d : beiscsi_init_irqs-"
  905. "Failed to register beiscsi_msix_mcc\n");
  906. kfree(phba->msi_name[i]);
  907. goto free_msix_irqs;
  908. }
  909. } else {
  910. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  911. "beiscsi", phba);
  912. if (ret) {
  913. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  914. "BM_%d : beiscsi_init_irqs-"
  915. "Failed to register irq\\n");
  916. return ret;
  917. }
  918. }
  919. return 0;
  920. free_msix_irqs:
  921. for (j = i - 1; j >= 0; j--) {
  922. kfree(phba->msi_name[j]);
  923. msix_vec = phba->msix_entries[j].vector;
  924. free_irq(msix_vec, &phwi_context->be_eq[j]);
  925. }
  926. return ret;
  927. }
  928. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  929. unsigned int id, unsigned int num_processed,
  930. unsigned char rearm, unsigned char event)
  931. {
  932. u32 val = 0;
  933. val |= id & DB_CQ_RING_ID_MASK;
  934. if (rearm)
  935. val |= 1 << DB_CQ_REARM_SHIFT;
  936. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  937. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  938. }
  939. static unsigned int
  940. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  941. struct beiscsi_hba *phba,
  942. unsigned short cid,
  943. struct pdu_base *ppdu,
  944. unsigned long pdu_len,
  945. void *pbuffer, unsigned long buf_len)
  946. {
  947. struct iscsi_conn *conn = beiscsi_conn->conn;
  948. struct iscsi_session *session = conn->session;
  949. struct iscsi_task *task;
  950. struct beiscsi_io_task *io_task;
  951. struct iscsi_hdr *login_hdr;
  952. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  953. PDUBASE_OPCODE_MASK) {
  954. case ISCSI_OP_NOOP_IN:
  955. pbuffer = NULL;
  956. buf_len = 0;
  957. break;
  958. case ISCSI_OP_ASYNC_EVENT:
  959. break;
  960. case ISCSI_OP_REJECT:
  961. WARN_ON(!pbuffer);
  962. WARN_ON(!(buf_len == 48));
  963. beiscsi_log(phba, KERN_ERR,
  964. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  965. "BM_%d : In ISCSI_OP_REJECT\n");
  966. break;
  967. case ISCSI_OP_LOGIN_RSP:
  968. case ISCSI_OP_TEXT_RSP:
  969. task = conn->login_task;
  970. io_task = task->dd_data;
  971. login_hdr = (struct iscsi_hdr *)ppdu;
  972. login_hdr->itt = io_task->libiscsi_itt;
  973. break;
  974. default:
  975. beiscsi_log(phba, KERN_WARNING,
  976. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  977. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  978. (ppdu->
  979. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  980. & PDUBASE_OPCODE_MASK));
  981. return 1;
  982. }
  983. spin_lock_bh(&session->lock);
  984. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  985. spin_unlock_bh(&session->lock);
  986. return 0;
  987. }
  988. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  989. {
  990. struct sgl_handle *psgl_handle;
  991. if (phba->io_sgl_hndl_avbl) {
  992. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  993. "BM_%d : In alloc_io_sgl_handle,"
  994. " io_sgl_alloc_index=%d\n",
  995. phba->io_sgl_alloc_index);
  996. psgl_handle = phba->io_sgl_hndl_base[phba->
  997. io_sgl_alloc_index];
  998. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  999. phba->io_sgl_hndl_avbl--;
  1000. if (phba->io_sgl_alloc_index == (phba->params.
  1001. ios_per_ctrl - 1))
  1002. phba->io_sgl_alloc_index = 0;
  1003. else
  1004. phba->io_sgl_alloc_index++;
  1005. } else
  1006. psgl_handle = NULL;
  1007. return psgl_handle;
  1008. }
  1009. static void
  1010. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1011. {
  1012. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1013. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1014. phba->io_sgl_free_index);
  1015. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1016. /*
  1017. * this can happen if clean_task is called on a task that
  1018. * failed in xmit_task or alloc_pdu.
  1019. */
  1020. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1021. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1022. "value there=%p\n", phba->io_sgl_free_index,
  1023. phba->io_sgl_hndl_base
  1024. [phba->io_sgl_free_index]);
  1025. return;
  1026. }
  1027. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1028. phba->io_sgl_hndl_avbl++;
  1029. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1030. phba->io_sgl_free_index = 0;
  1031. else
  1032. phba->io_sgl_free_index++;
  1033. }
  1034. /**
  1035. * alloc_wrb_handle - To allocate a wrb handle
  1036. * @phba: The hba pointer
  1037. * @cid: The cid to use for allocation
  1038. *
  1039. * This happens under session_lock until submission to chip
  1040. */
  1041. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1042. {
  1043. struct hwi_wrb_context *pwrb_context;
  1044. struct hwi_controller *phwi_ctrlr;
  1045. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1046. phwi_ctrlr = phba->phwi_ctrlr;
  1047. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  1048. if (pwrb_context->wrb_handles_available >= 2) {
  1049. pwrb_handle = pwrb_context->pwrb_handle_base[
  1050. pwrb_context->alloc_index];
  1051. pwrb_context->wrb_handles_available--;
  1052. if (pwrb_context->alloc_index ==
  1053. (phba->params.wrbs_per_cxn - 1))
  1054. pwrb_context->alloc_index = 0;
  1055. else
  1056. pwrb_context->alloc_index++;
  1057. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1058. pwrb_context->alloc_index];
  1059. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1060. } else
  1061. pwrb_handle = NULL;
  1062. return pwrb_handle;
  1063. }
  1064. /**
  1065. * free_wrb_handle - To free the wrb handle back to pool
  1066. * @phba: The hba pointer
  1067. * @pwrb_context: The context to free from
  1068. * @pwrb_handle: The wrb_handle to free
  1069. *
  1070. * This happens under session_lock until submission to chip
  1071. */
  1072. static void
  1073. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1074. struct wrb_handle *pwrb_handle)
  1075. {
  1076. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1077. pwrb_context->wrb_handles_available++;
  1078. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1079. pwrb_context->free_index = 0;
  1080. else
  1081. pwrb_context->free_index++;
  1082. beiscsi_log(phba, KERN_INFO,
  1083. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1084. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1085. "wrb_handles_available=%d\n",
  1086. pwrb_handle, pwrb_context->free_index,
  1087. pwrb_context->wrb_handles_available);
  1088. }
  1089. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1090. {
  1091. struct sgl_handle *psgl_handle;
  1092. if (phba->eh_sgl_hndl_avbl) {
  1093. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1094. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1095. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1096. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1097. phba->eh_sgl_alloc_index,
  1098. phba->eh_sgl_alloc_index);
  1099. phba->eh_sgl_hndl_avbl--;
  1100. if (phba->eh_sgl_alloc_index ==
  1101. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1102. 1))
  1103. phba->eh_sgl_alloc_index = 0;
  1104. else
  1105. phba->eh_sgl_alloc_index++;
  1106. } else
  1107. psgl_handle = NULL;
  1108. return psgl_handle;
  1109. }
  1110. void
  1111. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1112. {
  1113. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1114. "BM_%d : In free_mgmt_sgl_handle,"
  1115. "eh_sgl_free_index=%d\n",
  1116. phba->eh_sgl_free_index);
  1117. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1118. /*
  1119. * this can happen if clean_task is called on a task that
  1120. * failed in xmit_task or alloc_pdu.
  1121. */
  1122. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1123. "BM_%d : Double Free in eh SGL ,"
  1124. "eh_sgl_free_index=%d\n",
  1125. phba->eh_sgl_free_index);
  1126. return;
  1127. }
  1128. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1129. phba->eh_sgl_hndl_avbl++;
  1130. if (phba->eh_sgl_free_index ==
  1131. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1132. phba->eh_sgl_free_index = 0;
  1133. else
  1134. phba->eh_sgl_free_index++;
  1135. }
  1136. static void
  1137. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1138. struct iscsi_task *task, struct sol_cqe *psol)
  1139. {
  1140. struct beiscsi_io_task *io_task = task->dd_data;
  1141. struct be_status_bhs *sts_bhs =
  1142. (struct be_status_bhs *)io_task->cmd_bhs;
  1143. struct iscsi_conn *conn = beiscsi_conn->conn;
  1144. unsigned char *sense;
  1145. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1146. u8 rsp, status, flags;
  1147. exp_cmdsn = (psol->
  1148. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1149. & SOL_EXP_CMD_SN_MASK);
  1150. max_cmdsn = ((psol->
  1151. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1152. & SOL_EXP_CMD_SN_MASK) +
  1153. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1154. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1155. rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
  1156. & SOL_RESP_MASK) >> 16);
  1157. status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
  1158. & SOL_STS_MASK) >> 8);
  1159. flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1160. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1161. if (!task->sc) {
  1162. if (io_task->scsi_cmnd)
  1163. scsi_dma_unmap(io_task->scsi_cmnd);
  1164. return;
  1165. }
  1166. task->sc->result = (DID_OK << 16) | status;
  1167. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1168. task->sc->result = DID_ERROR << 16;
  1169. goto unmap;
  1170. }
  1171. /* bidi not initially supported */
  1172. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1173. resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
  1174. 32] & SOL_RES_CNT_MASK);
  1175. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1176. task->sc->result = DID_ERROR << 16;
  1177. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1178. scsi_set_resid(task->sc, resid);
  1179. if (!status && (scsi_bufflen(task->sc) - resid <
  1180. task->sc->underflow))
  1181. task->sc->result = DID_ERROR << 16;
  1182. }
  1183. }
  1184. if (status == SAM_STAT_CHECK_CONDITION) {
  1185. u16 sense_len;
  1186. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1187. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1188. sense_len = be16_to_cpu(*slen);
  1189. memcpy(task->sc->sense_buffer, sense,
  1190. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1191. }
  1192. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
  1193. if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1194. & SOL_RES_CNT_MASK)
  1195. conn->rxdata_octets += (psol->
  1196. dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1197. & SOL_RES_CNT_MASK);
  1198. }
  1199. unmap:
  1200. scsi_dma_unmap(io_task->scsi_cmnd);
  1201. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1202. }
  1203. static void
  1204. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1205. struct iscsi_task *task, struct sol_cqe *psol)
  1206. {
  1207. struct iscsi_logout_rsp *hdr;
  1208. struct beiscsi_io_task *io_task = task->dd_data;
  1209. struct iscsi_conn *conn = beiscsi_conn->conn;
  1210. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1211. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1212. hdr->t2wait = 5;
  1213. hdr->t2retain = 0;
  1214. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1215. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1216. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1217. 32] & SOL_RESP_MASK);
  1218. hdr->exp_cmdsn = cpu_to_be32(psol->
  1219. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1220. & SOL_EXP_CMD_SN_MASK);
  1221. hdr->max_cmdsn = be32_to_cpu((psol->
  1222. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1223. & SOL_EXP_CMD_SN_MASK) +
  1224. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1225. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1226. hdr->dlength[0] = 0;
  1227. hdr->dlength[1] = 0;
  1228. hdr->dlength[2] = 0;
  1229. hdr->hlength = 0;
  1230. hdr->itt = io_task->libiscsi_itt;
  1231. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1232. }
  1233. static void
  1234. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1235. struct iscsi_task *task, struct sol_cqe *psol)
  1236. {
  1237. struct iscsi_tm_rsp *hdr;
  1238. struct iscsi_conn *conn = beiscsi_conn->conn;
  1239. struct beiscsi_io_task *io_task = task->dd_data;
  1240. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1241. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1242. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1243. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1244. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1245. 32] & SOL_RESP_MASK);
  1246. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1247. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1248. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1249. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1250. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1251. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1252. hdr->itt = io_task->libiscsi_itt;
  1253. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1254. }
  1255. static void
  1256. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1257. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1258. {
  1259. struct hwi_wrb_context *pwrb_context;
  1260. struct wrb_handle *pwrb_handle = NULL;
  1261. struct hwi_controller *phwi_ctrlr;
  1262. struct iscsi_task *task;
  1263. struct beiscsi_io_task *io_task;
  1264. struct iscsi_conn *conn = beiscsi_conn->conn;
  1265. struct iscsi_session *session = conn->session;
  1266. phwi_ctrlr = phba->phwi_ctrlr;
  1267. pwrb_context = &phwi_ctrlr->wrb_context[((psol->
  1268. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1269. SOL_CID_MASK) >> 6) -
  1270. phba->fw_config.iscsi_cid_start];
  1271. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1272. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1273. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1274. task = pwrb_handle->pio_handle;
  1275. io_task = task->dd_data;
  1276. spin_lock_bh(&phba->mgmt_sgl_lock);
  1277. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1278. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1279. spin_lock_bh(&session->lock);
  1280. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1281. spin_unlock_bh(&session->lock);
  1282. }
  1283. static void
  1284. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1285. struct iscsi_task *task, struct sol_cqe *psol)
  1286. {
  1287. struct iscsi_nopin *hdr;
  1288. struct iscsi_conn *conn = beiscsi_conn->conn;
  1289. struct beiscsi_io_task *io_task = task->dd_data;
  1290. hdr = (struct iscsi_nopin *)task->hdr;
  1291. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1292. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1293. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1294. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1295. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1296. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1297. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1298. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1299. hdr->opcode = ISCSI_OP_NOOP_IN;
  1300. hdr->itt = io_task->libiscsi_itt;
  1301. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1302. }
  1303. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1304. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1305. {
  1306. struct hwi_wrb_context *pwrb_context;
  1307. struct wrb_handle *pwrb_handle;
  1308. struct iscsi_wrb *pwrb = NULL;
  1309. struct hwi_controller *phwi_ctrlr;
  1310. struct iscsi_task *task;
  1311. unsigned int type;
  1312. struct iscsi_conn *conn = beiscsi_conn->conn;
  1313. struct iscsi_session *session = conn->session;
  1314. phwi_ctrlr = phba->phwi_ctrlr;
  1315. pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
  1316. (struct amap_sol_cqe, cid) / 32]
  1317. & SOL_CID_MASK) >> 6) -
  1318. phba->fw_config.iscsi_cid_start];
  1319. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1320. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1321. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1322. task = pwrb_handle->pio_handle;
  1323. pwrb = pwrb_handle->pwrb;
  1324. type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
  1325. WRB_TYPE_MASK) >> 28;
  1326. spin_lock_bh(&session->lock);
  1327. switch (type) {
  1328. case HWH_TYPE_IO:
  1329. case HWH_TYPE_IO_RD:
  1330. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1331. ISCSI_OP_NOOP_OUT)
  1332. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1333. else
  1334. be_complete_io(beiscsi_conn, task, psol);
  1335. break;
  1336. case HWH_TYPE_LOGOUT:
  1337. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1338. be_complete_logout(beiscsi_conn, task, psol);
  1339. else
  1340. be_complete_tmf(beiscsi_conn, task, psol);
  1341. break;
  1342. case HWH_TYPE_LOGIN:
  1343. beiscsi_log(phba, KERN_ERR,
  1344. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1345. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1346. " hwi_complete_cmd- Solicited path\n");
  1347. break;
  1348. case HWH_TYPE_NOP:
  1349. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1350. break;
  1351. default:
  1352. beiscsi_log(phba, KERN_WARNING,
  1353. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1354. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1355. "wrb_index 0x%x CID 0x%x\n", type,
  1356. ((psol->dw[offsetof(struct amap_iscsi_wrb,
  1357. type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
  1358. ((psol->dw[offsetof(struct amap_sol_cqe,
  1359. cid) / 32] & SOL_CID_MASK) >> 6));
  1360. break;
  1361. }
  1362. spin_unlock_bh(&session->lock);
  1363. }
  1364. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1365. *pasync_ctx, unsigned int is_header,
  1366. unsigned int host_write_ptr)
  1367. {
  1368. if (is_header)
  1369. return &pasync_ctx->async_entry[host_write_ptr].
  1370. header_busy_list;
  1371. else
  1372. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1373. }
  1374. static struct async_pdu_handle *
  1375. hwi_get_async_handle(struct beiscsi_hba *phba,
  1376. struct beiscsi_conn *beiscsi_conn,
  1377. struct hwi_async_pdu_context *pasync_ctx,
  1378. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1379. {
  1380. struct be_bus_address phys_addr;
  1381. struct list_head *pbusy_list;
  1382. struct async_pdu_handle *pasync_handle = NULL;
  1383. unsigned char is_header = 0;
  1384. phys_addr.u.a32.address_lo =
  1385. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
  1386. ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1387. & PDUCQE_DPL_MASK) >> 16);
  1388. phys_addr.u.a32.address_hi =
  1389. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
  1390. phys_addr.u.a64.address =
  1391. *((unsigned long long *)(&phys_addr.u.a64.address));
  1392. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1393. & PDUCQE_CODE_MASK) {
  1394. case UNSOL_HDR_NOTIFY:
  1395. is_header = 1;
  1396. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
  1397. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1398. index) / 32] & PDUCQE_INDEX_MASK));
  1399. break;
  1400. case UNSOL_DATA_NOTIFY:
  1401. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
  1402. dw[offsetof(struct amap_i_t_dpdu_cqe,
  1403. index) / 32] & PDUCQE_INDEX_MASK));
  1404. break;
  1405. default:
  1406. pbusy_list = NULL;
  1407. beiscsi_log(phba, KERN_WARNING,
  1408. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1409. "BM_%d : Unexpected code=%d\n",
  1410. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1411. code) / 32] & PDUCQE_CODE_MASK);
  1412. return NULL;
  1413. }
  1414. WARN_ON(list_empty(pbusy_list));
  1415. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1416. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1417. break;
  1418. }
  1419. WARN_ON(!pasync_handle);
  1420. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1421. phba->fw_config.iscsi_cid_start;
  1422. pasync_handle->is_header = is_header;
  1423. pasync_handle->buffer_len = ((pdpdu_cqe->
  1424. dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1425. & PDUCQE_DPL_MASK) >> 16);
  1426. *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1427. index) / 32] & PDUCQE_INDEX_MASK);
  1428. return pasync_handle;
  1429. }
  1430. static unsigned int
  1431. hwi_update_async_writables(struct beiscsi_hba *phba,
  1432. struct hwi_async_pdu_context *pasync_ctx,
  1433. unsigned int is_header, unsigned int cq_index)
  1434. {
  1435. struct list_head *pbusy_list;
  1436. struct async_pdu_handle *pasync_handle;
  1437. unsigned int num_entries, writables = 0;
  1438. unsigned int *pep_read_ptr, *pwritables;
  1439. num_entries = pasync_ctx->num_entries;
  1440. if (is_header) {
  1441. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1442. pwritables = &pasync_ctx->async_header.writables;
  1443. } else {
  1444. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1445. pwritables = &pasync_ctx->async_data.writables;
  1446. }
  1447. while ((*pep_read_ptr) != cq_index) {
  1448. (*pep_read_ptr)++;
  1449. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1450. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1451. *pep_read_ptr);
  1452. if (writables == 0)
  1453. WARN_ON(list_empty(pbusy_list));
  1454. if (!list_empty(pbusy_list)) {
  1455. pasync_handle = list_entry(pbusy_list->next,
  1456. struct async_pdu_handle,
  1457. link);
  1458. WARN_ON(!pasync_handle);
  1459. pasync_handle->consumed = 1;
  1460. }
  1461. writables++;
  1462. }
  1463. if (!writables) {
  1464. beiscsi_log(phba, KERN_ERR,
  1465. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1466. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1467. cq_index);
  1468. WARN_ON(1);
  1469. }
  1470. *pwritables = *pwritables + writables;
  1471. return 0;
  1472. }
  1473. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1474. unsigned int cri)
  1475. {
  1476. struct hwi_controller *phwi_ctrlr;
  1477. struct hwi_async_pdu_context *pasync_ctx;
  1478. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1479. struct list_head *plist;
  1480. phwi_ctrlr = phba->phwi_ctrlr;
  1481. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1482. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1483. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1484. list_del(&pasync_handle->link);
  1485. if (pasync_handle->is_header) {
  1486. list_add_tail(&pasync_handle->link,
  1487. &pasync_ctx->async_header.free_list);
  1488. pasync_ctx->async_header.free_entries++;
  1489. } else {
  1490. list_add_tail(&pasync_handle->link,
  1491. &pasync_ctx->async_data.free_list);
  1492. pasync_ctx->async_data.free_entries++;
  1493. }
  1494. }
  1495. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1496. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1497. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1498. }
  1499. static struct phys_addr *
  1500. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1501. unsigned int is_header, unsigned int host_write_ptr)
  1502. {
  1503. struct phys_addr *pasync_sge = NULL;
  1504. if (is_header)
  1505. pasync_sge = pasync_ctx->async_header.ring_base;
  1506. else
  1507. pasync_sge = pasync_ctx->async_data.ring_base;
  1508. return pasync_sge + host_write_ptr;
  1509. }
  1510. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1511. unsigned int is_header)
  1512. {
  1513. struct hwi_controller *phwi_ctrlr;
  1514. struct hwi_async_pdu_context *pasync_ctx;
  1515. struct async_pdu_handle *pasync_handle;
  1516. struct list_head *pfree_link, *pbusy_list;
  1517. struct phys_addr *pasync_sge;
  1518. unsigned int ring_id, num_entries;
  1519. unsigned int host_write_num;
  1520. unsigned int writables;
  1521. unsigned int i = 0;
  1522. u32 doorbell = 0;
  1523. phwi_ctrlr = phba->phwi_ctrlr;
  1524. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1525. num_entries = pasync_ctx->num_entries;
  1526. if (is_header) {
  1527. writables = min(pasync_ctx->async_header.writables,
  1528. pasync_ctx->async_header.free_entries);
  1529. pfree_link = pasync_ctx->async_header.free_list.next;
  1530. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1531. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1532. } else {
  1533. writables = min(pasync_ctx->async_data.writables,
  1534. pasync_ctx->async_data.free_entries);
  1535. pfree_link = pasync_ctx->async_data.free_list.next;
  1536. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1537. ring_id = phwi_ctrlr->default_pdu_data.id;
  1538. }
  1539. writables = (writables / 8) * 8;
  1540. if (writables) {
  1541. for (i = 0; i < writables; i++) {
  1542. pbusy_list =
  1543. hwi_get_async_busy_list(pasync_ctx, is_header,
  1544. host_write_num);
  1545. pasync_handle =
  1546. list_entry(pfree_link, struct async_pdu_handle,
  1547. link);
  1548. WARN_ON(!pasync_handle);
  1549. pasync_handle->consumed = 0;
  1550. pfree_link = pfree_link->next;
  1551. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1552. is_header, host_write_num);
  1553. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1554. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1555. list_move(&pasync_handle->link, pbusy_list);
  1556. host_write_num++;
  1557. host_write_num = host_write_num % num_entries;
  1558. }
  1559. if (is_header) {
  1560. pasync_ctx->async_header.host_write_ptr =
  1561. host_write_num;
  1562. pasync_ctx->async_header.free_entries -= writables;
  1563. pasync_ctx->async_header.writables -= writables;
  1564. pasync_ctx->async_header.busy_entries += writables;
  1565. } else {
  1566. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1567. pasync_ctx->async_data.free_entries -= writables;
  1568. pasync_ctx->async_data.writables -= writables;
  1569. pasync_ctx->async_data.busy_entries += writables;
  1570. }
  1571. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1572. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1573. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1574. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1575. << DB_DEF_PDU_CQPROC_SHIFT;
  1576. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1577. }
  1578. }
  1579. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1580. struct beiscsi_conn *beiscsi_conn,
  1581. struct i_t_dpdu_cqe *pdpdu_cqe)
  1582. {
  1583. struct hwi_controller *phwi_ctrlr;
  1584. struct hwi_async_pdu_context *pasync_ctx;
  1585. struct async_pdu_handle *pasync_handle = NULL;
  1586. unsigned int cq_index = -1;
  1587. phwi_ctrlr = phba->phwi_ctrlr;
  1588. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1589. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1590. pdpdu_cqe, &cq_index);
  1591. BUG_ON(pasync_handle->is_header != 0);
  1592. if (pasync_handle->consumed == 0)
  1593. hwi_update_async_writables(phba, pasync_ctx,
  1594. pasync_handle->is_header, cq_index);
  1595. hwi_free_async_msg(phba, pasync_handle->cri);
  1596. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1597. }
  1598. static unsigned int
  1599. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1600. struct beiscsi_hba *phba,
  1601. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1602. {
  1603. struct list_head *plist;
  1604. struct async_pdu_handle *pasync_handle;
  1605. void *phdr = NULL;
  1606. unsigned int hdr_len = 0, buf_len = 0;
  1607. unsigned int status, index = 0, offset = 0;
  1608. void *pfirst_buffer = NULL;
  1609. unsigned int num_buf = 0;
  1610. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1611. list_for_each_entry(pasync_handle, plist, link) {
  1612. if (index == 0) {
  1613. phdr = pasync_handle->pbuffer;
  1614. hdr_len = pasync_handle->buffer_len;
  1615. } else {
  1616. buf_len = pasync_handle->buffer_len;
  1617. if (!num_buf) {
  1618. pfirst_buffer = pasync_handle->pbuffer;
  1619. num_buf++;
  1620. }
  1621. memcpy(pfirst_buffer + offset,
  1622. pasync_handle->pbuffer, buf_len);
  1623. offset += buf_len;
  1624. }
  1625. index++;
  1626. }
  1627. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1628. (beiscsi_conn->beiscsi_conn_cid -
  1629. phba->fw_config.iscsi_cid_start),
  1630. phdr, hdr_len, pfirst_buffer,
  1631. offset);
  1632. hwi_free_async_msg(phba, cri);
  1633. return 0;
  1634. }
  1635. static unsigned int
  1636. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1637. struct beiscsi_hba *phba,
  1638. struct async_pdu_handle *pasync_handle)
  1639. {
  1640. struct hwi_async_pdu_context *pasync_ctx;
  1641. struct hwi_controller *phwi_ctrlr;
  1642. unsigned int bytes_needed = 0, status = 0;
  1643. unsigned short cri = pasync_handle->cri;
  1644. struct pdu_base *ppdu;
  1645. phwi_ctrlr = phba->phwi_ctrlr;
  1646. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1647. list_del(&pasync_handle->link);
  1648. if (pasync_handle->is_header) {
  1649. pasync_ctx->async_header.busy_entries--;
  1650. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1651. hwi_free_async_msg(phba, cri);
  1652. BUG();
  1653. }
  1654. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1655. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1656. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1657. (unsigned short)pasync_handle->buffer_len;
  1658. list_add_tail(&pasync_handle->link,
  1659. &pasync_ctx->async_entry[cri].wait_queue.list);
  1660. ppdu = pasync_handle->pbuffer;
  1661. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1662. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1663. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1664. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1665. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1666. if (status == 0) {
  1667. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1668. bytes_needed;
  1669. if (bytes_needed == 0)
  1670. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1671. pasync_ctx, cri);
  1672. }
  1673. } else {
  1674. pasync_ctx->async_data.busy_entries--;
  1675. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1676. list_add_tail(&pasync_handle->link,
  1677. &pasync_ctx->async_entry[cri].wait_queue.
  1678. list);
  1679. pasync_ctx->async_entry[cri].wait_queue.
  1680. bytes_received +=
  1681. (unsigned short)pasync_handle->buffer_len;
  1682. if (pasync_ctx->async_entry[cri].wait_queue.
  1683. bytes_received >=
  1684. pasync_ctx->async_entry[cri].wait_queue.
  1685. bytes_needed)
  1686. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1687. pasync_ctx, cri);
  1688. }
  1689. }
  1690. return status;
  1691. }
  1692. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1693. struct beiscsi_hba *phba,
  1694. struct i_t_dpdu_cqe *pdpdu_cqe)
  1695. {
  1696. struct hwi_controller *phwi_ctrlr;
  1697. struct hwi_async_pdu_context *pasync_ctx;
  1698. struct async_pdu_handle *pasync_handle = NULL;
  1699. unsigned int cq_index = -1;
  1700. phwi_ctrlr = phba->phwi_ctrlr;
  1701. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1702. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1703. pdpdu_cqe, &cq_index);
  1704. if (pasync_handle->consumed == 0)
  1705. hwi_update_async_writables(phba, pasync_ctx,
  1706. pasync_handle->is_header, cq_index);
  1707. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1708. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1709. }
  1710. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1711. {
  1712. struct be_queue_info *mcc_cq;
  1713. struct be_mcc_compl *mcc_compl;
  1714. unsigned int num_processed = 0;
  1715. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1716. mcc_compl = queue_tail_node(mcc_cq);
  1717. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1718. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1719. if (num_processed >= 32) {
  1720. hwi_ring_cq_db(phba, mcc_cq->id,
  1721. num_processed, 0, 0);
  1722. num_processed = 0;
  1723. }
  1724. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1725. /* Interpret flags as an async trailer */
  1726. if (is_link_state_evt(mcc_compl->flags))
  1727. /* Interpret compl as a async link evt */
  1728. beiscsi_async_link_state_process(phba,
  1729. (struct be_async_event_link_state *) mcc_compl);
  1730. else
  1731. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1732. "BM_%d : Unsupported Async Event, flags"
  1733. " = 0x%08x\n",
  1734. mcc_compl->flags);
  1735. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1736. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1737. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1738. }
  1739. mcc_compl->flags = 0;
  1740. queue_tail_inc(mcc_cq);
  1741. mcc_compl = queue_tail_node(mcc_cq);
  1742. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1743. num_processed++;
  1744. }
  1745. if (num_processed > 0)
  1746. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1747. }
  1748. /**
  1749. * beiscsi_process_cq()- Process the Completion Queue
  1750. * @pbe_eq: Event Q on which the Completion has come
  1751. *
  1752. * return
  1753. * Number of Completion Entries processed.
  1754. **/
  1755. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1756. {
  1757. struct be_queue_info *cq;
  1758. struct sol_cqe *sol;
  1759. struct dmsg_cqe *dmsg;
  1760. unsigned int num_processed = 0;
  1761. unsigned int tot_nump = 0;
  1762. unsigned short code = 0, cid = 0;
  1763. struct beiscsi_conn *beiscsi_conn;
  1764. struct beiscsi_endpoint *beiscsi_ep;
  1765. struct iscsi_endpoint *ep;
  1766. struct beiscsi_hba *phba;
  1767. cq = pbe_eq->cq;
  1768. sol = queue_tail_node(cq);
  1769. phba = pbe_eq->phba;
  1770. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1771. CQE_VALID_MASK) {
  1772. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1773. cid = ((sol->dw[offsetof(struct amap_sol_cqe, cid)/32] &
  1774. CQE_CID_MASK) >> 6);
  1775. code = (sol->dw[offsetof(struct amap_sol_cqe, code)/32] &
  1776. CQE_CODE_MASK);
  1777. ep = phba->ep_array[cid - phba->fw_config.iscsi_cid_start];
  1778. beiscsi_ep = ep->dd_data;
  1779. beiscsi_conn = beiscsi_ep->conn;
  1780. if (num_processed >= 32) {
  1781. hwi_ring_cq_db(phba, cq->id,
  1782. num_processed, 0, 0);
  1783. tot_nump += num_processed;
  1784. num_processed = 0;
  1785. }
  1786. switch (code) {
  1787. case SOL_CMD_COMPLETE:
  1788. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1789. break;
  1790. case DRIVERMSG_NOTIFY:
  1791. beiscsi_log(phba, KERN_INFO,
  1792. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1793. "BM_%d : Received %s[%d] on CID : %d\n",
  1794. cqe_desc[code], code, cid);
  1795. dmsg = (struct dmsg_cqe *)sol;
  1796. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1797. break;
  1798. case UNSOL_HDR_NOTIFY:
  1799. beiscsi_log(phba, KERN_INFO,
  1800. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1801. "BM_%d : Received %s[%d] on CID : %d\n",
  1802. cqe_desc[code], code, cid);
  1803. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1804. (struct i_t_dpdu_cqe *)sol);
  1805. break;
  1806. case UNSOL_DATA_NOTIFY:
  1807. beiscsi_log(phba, KERN_INFO,
  1808. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1809. "BM_%d : Received %s[%d] on CID : %d\n",
  1810. cqe_desc[code], code, cid);
  1811. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1812. (struct i_t_dpdu_cqe *)sol);
  1813. break;
  1814. case CXN_INVALIDATE_INDEX_NOTIFY:
  1815. case CMD_INVALIDATED_NOTIFY:
  1816. case CXN_INVALIDATE_NOTIFY:
  1817. beiscsi_log(phba, KERN_ERR,
  1818. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1819. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1820. cqe_desc[code], code, cid);
  1821. break;
  1822. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1823. case CMD_KILLED_INVALID_STATSN_RCVD:
  1824. case CMD_KILLED_INVALID_R2T_RCVD:
  1825. case CMD_CXN_KILLED_LUN_INVALID:
  1826. case CMD_CXN_KILLED_ICD_INVALID:
  1827. case CMD_CXN_KILLED_ITT_INVALID:
  1828. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1829. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1830. beiscsi_log(phba, KERN_ERR,
  1831. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1832. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1833. cqe_desc[code], code, cid);
  1834. break;
  1835. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1836. beiscsi_log(phba, KERN_ERR,
  1837. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1838. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1839. cqe_desc[code], code, cid);
  1840. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1841. (struct i_t_dpdu_cqe *) sol);
  1842. break;
  1843. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1844. case CXN_KILLED_BURST_LEN_MISMATCH:
  1845. case CXN_KILLED_AHS_RCVD:
  1846. case CXN_KILLED_HDR_DIGEST_ERR:
  1847. case CXN_KILLED_UNKNOWN_HDR:
  1848. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1849. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1850. case CXN_KILLED_TIMED_OUT:
  1851. case CXN_KILLED_FIN_RCVD:
  1852. case CXN_KILLED_RST_SENT:
  1853. case CXN_KILLED_RST_RCVD:
  1854. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1855. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1856. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1857. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1858. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1859. beiscsi_log(phba, KERN_ERR,
  1860. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1861. "BM_%d : Event %s[%d] received on CID : %d\n",
  1862. cqe_desc[code], code, cid);
  1863. if (beiscsi_conn)
  1864. iscsi_conn_failure(beiscsi_conn->conn,
  1865. ISCSI_ERR_CONN_FAILED);
  1866. break;
  1867. default:
  1868. beiscsi_log(phba, KERN_ERR,
  1869. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1870. "BM_%d : Invalid CQE Event Received Code : %d"
  1871. "CID 0x%x...\n",
  1872. code, cid);
  1873. break;
  1874. }
  1875. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1876. queue_tail_inc(cq);
  1877. sol = queue_tail_node(cq);
  1878. num_processed++;
  1879. }
  1880. if (num_processed > 0) {
  1881. tot_nump += num_processed;
  1882. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1883. }
  1884. return tot_nump;
  1885. }
  1886. void beiscsi_process_all_cqs(struct work_struct *work)
  1887. {
  1888. unsigned long flags;
  1889. struct hwi_controller *phwi_ctrlr;
  1890. struct hwi_context_memory *phwi_context;
  1891. struct beiscsi_hba *phba;
  1892. struct be_eq_obj *pbe_eq =
  1893. container_of(work, struct be_eq_obj, work_cqs);
  1894. phba = pbe_eq->phba;
  1895. phwi_ctrlr = phba->phwi_ctrlr;
  1896. phwi_context = phwi_ctrlr->phwi_ctxt;
  1897. if (pbe_eq->todo_mcc_cq) {
  1898. spin_lock_irqsave(&phba->isr_lock, flags);
  1899. pbe_eq->todo_mcc_cq = false;
  1900. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1901. beiscsi_process_mcc_isr(phba);
  1902. }
  1903. if (pbe_eq->todo_cq) {
  1904. spin_lock_irqsave(&phba->isr_lock, flags);
  1905. pbe_eq->todo_cq = false;
  1906. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1907. beiscsi_process_cq(pbe_eq);
  1908. }
  1909. /* rearm EQ for further interrupts */
  1910. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1911. }
  1912. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1913. {
  1914. static unsigned int ret;
  1915. struct beiscsi_hba *phba;
  1916. struct be_eq_obj *pbe_eq;
  1917. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1918. ret = beiscsi_process_cq(pbe_eq);
  1919. if (ret < budget) {
  1920. phba = pbe_eq->phba;
  1921. blk_iopoll_complete(iop);
  1922. beiscsi_log(phba, KERN_INFO,
  1923. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1924. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1925. pbe_eq->q.id);
  1926. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1927. }
  1928. return ret;
  1929. }
  1930. static void
  1931. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1932. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1933. {
  1934. struct iscsi_sge *psgl;
  1935. unsigned int sg_len, index;
  1936. unsigned int sge_len = 0;
  1937. unsigned long long addr;
  1938. struct scatterlist *l_sg;
  1939. unsigned int offset;
  1940. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1941. io_task->bhs_pa.u.a32.address_lo);
  1942. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1943. io_task->bhs_pa.u.a32.address_hi);
  1944. l_sg = sg;
  1945. for (index = 0; (index < num_sg) && (index < 2); index++,
  1946. sg = sg_next(sg)) {
  1947. if (index == 0) {
  1948. sg_len = sg_dma_len(sg);
  1949. addr = (u64) sg_dma_address(sg);
  1950. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1951. ((u32)(addr & 0xFFFFFFFF)));
  1952. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1953. ((u32)(addr >> 32)));
  1954. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1955. sg_len);
  1956. sge_len = sg_len;
  1957. } else {
  1958. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  1959. pwrb, sge_len);
  1960. sg_len = sg_dma_len(sg);
  1961. addr = (u64) sg_dma_address(sg);
  1962. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  1963. ((u32)(addr & 0xFFFFFFFF)));
  1964. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  1965. ((u32)(addr >> 32)));
  1966. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  1967. sg_len);
  1968. }
  1969. }
  1970. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1971. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  1972. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  1973. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1974. io_task->bhs_pa.u.a32.address_hi);
  1975. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1976. io_task->bhs_pa.u.a32.address_lo);
  1977. if (num_sg == 1) {
  1978. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1979. 1);
  1980. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1981. 0);
  1982. } else if (num_sg == 2) {
  1983. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1984. 0);
  1985. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1986. 1);
  1987. } else {
  1988. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1989. 0);
  1990. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1991. 0);
  1992. }
  1993. sg = l_sg;
  1994. psgl++;
  1995. psgl++;
  1996. offset = 0;
  1997. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  1998. sg_len = sg_dma_len(sg);
  1999. addr = (u64) sg_dma_address(sg);
  2000. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2001. (addr & 0xFFFFFFFF));
  2002. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2003. (addr >> 32));
  2004. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2005. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2006. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2007. offset += sg_len;
  2008. }
  2009. psgl--;
  2010. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2011. }
  2012. /**
  2013. * hwi_write_buffer()- Populate the WRB with task info
  2014. * @pwrb: ptr to the WRB entry
  2015. * @task: iscsi task which is to be executed
  2016. **/
  2017. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2018. {
  2019. struct iscsi_sge *psgl;
  2020. struct beiscsi_io_task *io_task = task->dd_data;
  2021. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2022. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2023. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2024. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2025. io_task->bhs_pa.u.a32.address_lo);
  2026. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2027. io_task->bhs_pa.u.a32.address_hi);
  2028. if (task->data) {
  2029. if (task->data_count) {
  2030. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  2031. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2032. task->data,
  2033. task->data_count,
  2034. PCI_DMA_TODEVICE);
  2035. io_task->mtask_data_count = task->data_count;
  2036. } else {
  2037. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2038. io_task->mtask_addr = 0;
  2039. }
  2040. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2041. lower_32_bits(io_task->mtask_addr));
  2042. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2043. upper_32_bits(io_task->mtask_addr));
  2044. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2045. task->data_count);
  2046. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2047. } else {
  2048. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2049. io_task->mtask_addr = 0;
  2050. }
  2051. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2052. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2053. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2054. io_task->bhs_pa.u.a32.address_hi);
  2055. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2056. io_task->bhs_pa.u.a32.address_lo);
  2057. if (task->data) {
  2058. psgl++;
  2059. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2060. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2061. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2062. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2063. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2064. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2065. psgl++;
  2066. if (task->data) {
  2067. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2068. lower_32_bits(io_task->mtask_addr));
  2069. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2070. upper_32_bits(io_task->mtask_addr));
  2071. }
  2072. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2073. }
  2074. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2075. }
  2076. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2077. {
  2078. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2079. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2080. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2081. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2082. sizeof(struct sol_cqe));
  2083. num_async_pdu_buf_pages =
  2084. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2085. phba->params.defpdu_hdr_sz);
  2086. num_async_pdu_buf_sgl_pages =
  2087. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2088. sizeof(struct phys_addr));
  2089. num_async_pdu_data_pages =
  2090. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2091. phba->params.defpdu_data_sz);
  2092. num_async_pdu_data_sgl_pages =
  2093. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2094. sizeof(struct phys_addr));
  2095. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2096. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2097. BE_ISCSI_PDU_HEADER_SIZE;
  2098. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2099. sizeof(struct hwi_context_memory);
  2100. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2101. * (phba->params.wrbs_per_cxn)
  2102. * phba->params.cxns_per_ctrl;
  2103. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2104. (phba->params.wrbs_per_cxn);
  2105. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2106. phba->params.cxns_per_ctrl);
  2107. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2108. phba->params.icds_per_ctrl;
  2109. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2110. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2111. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2112. num_async_pdu_buf_pages * PAGE_SIZE;
  2113. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2114. num_async_pdu_data_pages * PAGE_SIZE;
  2115. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2116. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2117. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2118. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2119. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2120. phba->params.asyncpdus_per_ctrl *
  2121. sizeof(struct async_pdu_handle);
  2122. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2123. phba->params.asyncpdus_per_ctrl *
  2124. sizeof(struct async_pdu_handle);
  2125. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2126. sizeof(struct hwi_async_pdu_context) +
  2127. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2128. }
  2129. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2130. {
  2131. struct be_mem_descriptor *mem_descr;
  2132. dma_addr_t bus_add;
  2133. struct mem_array *mem_arr, *mem_arr_orig;
  2134. unsigned int i, j, alloc_size, curr_alloc_size;
  2135. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2136. if (!phba->phwi_ctrlr)
  2137. return -ENOMEM;
  2138. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2139. GFP_KERNEL);
  2140. if (!phba->init_mem) {
  2141. kfree(phba->phwi_ctrlr);
  2142. return -ENOMEM;
  2143. }
  2144. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2145. GFP_KERNEL);
  2146. if (!mem_arr_orig) {
  2147. kfree(phba->init_mem);
  2148. kfree(phba->phwi_ctrlr);
  2149. return -ENOMEM;
  2150. }
  2151. mem_descr = phba->init_mem;
  2152. for (i = 0; i < SE_MEM_MAX; i++) {
  2153. j = 0;
  2154. mem_arr = mem_arr_orig;
  2155. alloc_size = phba->mem_req[i];
  2156. memset(mem_arr, 0, sizeof(struct mem_array) *
  2157. BEISCSI_MAX_FRAGS_INIT);
  2158. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2159. do {
  2160. mem_arr->virtual_address = pci_alloc_consistent(
  2161. phba->pcidev,
  2162. curr_alloc_size,
  2163. &bus_add);
  2164. if (!mem_arr->virtual_address) {
  2165. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2166. goto free_mem;
  2167. if (curr_alloc_size -
  2168. rounddown_pow_of_two(curr_alloc_size))
  2169. curr_alloc_size = rounddown_pow_of_two
  2170. (curr_alloc_size);
  2171. else
  2172. curr_alloc_size = curr_alloc_size / 2;
  2173. } else {
  2174. mem_arr->bus_address.u.
  2175. a64.address = (__u64) bus_add;
  2176. mem_arr->size = curr_alloc_size;
  2177. alloc_size -= curr_alloc_size;
  2178. curr_alloc_size = min(be_max_phys_size *
  2179. 1024, alloc_size);
  2180. j++;
  2181. mem_arr++;
  2182. }
  2183. } while (alloc_size);
  2184. mem_descr->num_elements = j;
  2185. mem_descr->size_in_bytes = phba->mem_req[i];
  2186. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2187. GFP_KERNEL);
  2188. if (!mem_descr->mem_array)
  2189. goto free_mem;
  2190. memcpy(mem_descr->mem_array, mem_arr_orig,
  2191. sizeof(struct mem_array) * j);
  2192. mem_descr++;
  2193. }
  2194. kfree(mem_arr_orig);
  2195. return 0;
  2196. free_mem:
  2197. mem_descr->num_elements = j;
  2198. while ((i) || (j)) {
  2199. for (j = mem_descr->num_elements; j > 0; j--) {
  2200. pci_free_consistent(phba->pcidev,
  2201. mem_descr->mem_array[j - 1].size,
  2202. mem_descr->mem_array[j - 1].
  2203. virtual_address,
  2204. (unsigned long)mem_descr->
  2205. mem_array[j - 1].
  2206. bus_address.u.a64.address);
  2207. }
  2208. if (i) {
  2209. i--;
  2210. kfree(mem_descr->mem_array);
  2211. mem_descr--;
  2212. }
  2213. }
  2214. kfree(mem_arr_orig);
  2215. kfree(phba->init_mem);
  2216. kfree(phba->phwi_ctrlr);
  2217. return -ENOMEM;
  2218. }
  2219. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2220. {
  2221. beiscsi_find_mem_req(phba);
  2222. return beiscsi_alloc_mem(phba);
  2223. }
  2224. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2225. {
  2226. struct pdu_data_out *pdata_out;
  2227. struct pdu_nop_out *pnop_out;
  2228. struct be_mem_descriptor *mem_descr;
  2229. mem_descr = phba->init_mem;
  2230. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2231. pdata_out =
  2232. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2233. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2234. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2235. IIOC_SCSI_DATA);
  2236. pnop_out =
  2237. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2238. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2239. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2240. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2241. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2242. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2243. }
  2244. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2245. {
  2246. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2247. struct wrb_handle *pwrb_handle = NULL;
  2248. struct hwi_controller *phwi_ctrlr;
  2249. struct hwi_wrb_context *pwrb_context;
  2250. struct iscsi_wrb *pwrb = NULL;
  2251. unsigned int num_cxn_wrbh = 0;
  2252. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2253. mem_descr_wrbh = phba->init_mem;
  2254. mem_descr_wrbh += HWI_MEM_WRBH;
  2255. mem_descr_wrb = phba->init_mem;
  2256. mem_descr_wrb += HWI_MEM_WRB;
  2257. phwi_ctrlr = phba->phwi_ctrlr;
  2258. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2259. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2260. pwrb_context->pwrb_handle_base =
  2261. kzalloc(sizeof(struct wrb_handle *) *
  2262. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2263. if (!pwrb_context->pwrb_handle_base) {
  2264. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2265. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2266. goto init_wrb_hndl_failed;
  2267. }
  2268. pwrb_context->pwrb_handle_basestd =
  2269. kzalloc(sizeof(struct wrb_handle *) *
  2270. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2271. if (!pwrb_context->pwrb_handle_basestd) {
  2272. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2273. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2274. goto init_wrb_hndl_failed;
  2275. }
  2276. if (!num_cxn_wrbh) {
  2277. pwrb_handle =
  2278. mem_descr_wrbh->mem_array[idx].virtual_address;
  2279. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2280. ((sizeof(struct wrb_handle)) *
  2281. phba->params.wrbs_per_cxn));
  2282. idx++;
  2283. }
  2284. pwrb_context->alloc_index = 0;
  2285. pwrb_context->wrb_handles_available = 0;
  2286. pwrb_context->free_index = 0;
  2287. if (num_cxn_wrbh) {
  2288. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2289. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2290. pwrb_context->pwrb_handle_basestd[j] =
  2291. pwrb_handle;
  2292. pwrb_context->wrb_handles_available++;
  2293. pwrb_handle->wrb_index = j;
  2294. pwrb_handle++;
  2295. }
  2296. num_cxn_wrbh--;
  2297. }
  2298. }
  2299. idx = 0;
  2300. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2301. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2302. if (!num_cxn_wrb) {
  2303. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2304. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2305. ((sizeof(struct iscsi_wrb) *
  2306. phba->params.wrbs_per_cxn));
  2307. idx++;
  2308. }
  2309. if (num_cxn_wrb) {
  2310. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2311. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2312. pwrb_handle->pwrb = pwrb;
  2313. pwrb++;
  2314. }
  2315. num_cxn_wrb--;
  2316. }
  2317. }
  2318. return 0;
  2319. init_wrb_hndl_failed:
  2320. for (j = index; j > 0; j--) {
  2321. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2322. kfree(pwrb_context->pwrb_handle_base);
  2323. kfree(pwrb_context->pwrb_handle_basestd);
  2324. }
  2325. return -ENOMEM;
  2326. }
  2327. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2328. {
  2329. struct hwi_controller *phwi_ctrlr;
  2330. struct hba_parameters *p = &phba->params;
  2331. struct hwi_async_pdu_context *pasync_ctx;
  2332. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2333. unsigned int index, idx, num_per_mem, num_async_data;
  2334. struct be_mem_descriptor *mem_descr;
  2335. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2336. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2337. phwi_ctrlr = phba->phwi_ctrlr;
  2338. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2339. mem_descr->mem_array[0].virtual_address;
  2340. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2341. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2342. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2343. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2344. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2345. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2346. if (mem_descr->mem_array[0].virtual_address) {
  2347. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2348. "BM_%d : hwi_init_async_pdu_ctx"
  2349. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2350. mem_descr->mem_array[0].virtual_address);
  2351. } else
  2352. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2353. "BM_%d : No Virtual address\n");
  2354. pasync_ctx->async_header.va_base =
  2355. mem_descr->mem_array[0].virtual_address;
  2356. pasync_ctx->async_header.pa_base.u.a64.address =
  2357. mem_descr->mem_array[0].bus_address.u.a64.address;
  2358. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2359. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2360. if (mem_descr->mem_array[0].virtual_address) {
  2361. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2362. "BM_%d : hwi_init_async_pdu_ctx"
  2363. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2364. mem_descr->mem_array[0].virtual_address);
  2365. } else
  2366. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2367. "BM_%d : No Virtual address\n");
  2368. pasync_ctx->async_header.ring_base =
  2369. mem_descr->mem_array[0].virtual_address;
  2370. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2371. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2372. if (mem_descr->mem_array[0].virtual_address) {
  2373. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2374. "BM_%d : hwi_init_async_pdu_ctx"
  2375. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2376. mem_descr->mem_array[0].virtual_address);
  2377. } else
  2378. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2379. "BM_%d : No Virtual address\n");
  2380. pasync_ctx->async_header.handle_base =
  2381. mem_descr->mem_array[0].virtual_address;
  2382. pasync_ctx->async_header.writables = 0;
  2383. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2384. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2385. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2386. if (mem_descr->mem_array[0].virtual_address) {
  2387. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2388. "BM_%d : hwi_init_async_pdu_ctx"
  2389. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2390. mem_descr->mem_array[0].virtual_address);
  2391. } else
  2392. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2393. "BM_%d : No Virtual address\n");
  2394. pasync_ctx->async_data.ring_base =
  2395. mem_descr->mem_array[0].virtual_address;
  2396. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2397. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2398. if (!mem_descr->mem_array[0].virtual_address)
  2399. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2400. "BM_%d : No Virtual address\n");
  2401. pasync_ctx->async_data.handle_base =
  2402. mem_descr->mem_array[0].virtual_address;
  2403. pasync_ctx->async_data.writables = 0;
  2404. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2405. pasync_header_h =
  2406. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2407. pasync_data_h =
  2408. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2409. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2410. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2411. if (mem_descr->mem_array[0].virtual_address) {
  2412. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2413. "BM_%d : hwi_init_async_pdu_ctx"
  2414. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2415. mem_descr->mem_array[0].virtual_address);
  2416. } else
  2417. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2418. "BM_%d : No Virtual address\n");
  2419. idx = 0;
  2420. pasync_ctx->async_data.va_base =
  2421. mem_descr->mem_array[idx].virtual_address;
  2422. pasync_ctx->async_data.pa_base.u.a64.address =
  2423. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2424. num_async_data = ((mem_descr->mem_array[idx].size) /
  2425. phba->params.defpdu_data_sz);
  2426. num_per_mem = 0;
  2427. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2428. pasync_header_h->cri = -1;
  2429. pasync_header_h->index = (char)index;
  2430. INIT_LIST_HEAD(&pasync_header_h->link);
  2431. pasync_header_h->pbuffer =
  2432. (void *)((unsigned long)
  2433. (pasync_ctx->async_header.va_base) +
  2434. (p->defpdu_hdr_sz * index));
  2435. pasync_header_h->pa.u.a64.address =
  2436. pasync_ctx->async_header.pa_base.u.a64.address +
  2437. (p->defpdu_hdr_sz * index);
  2438. list_add_tail(&pasync_header_h->link,
  2439. &pasync_ctx->async_header.free_list);
  2440. pasync_header_h++;
  2441. pasync_ctx->async_header.free_entries++;
  2442. pasync_ctx->async_header.writables++;
  2443. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2444. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2445. header_busy_list);
  2446. pasync_data_h->cri = -1;
  2447. pasync_data_h->index = (char)index;
  2448. INIT_LIST_HEAD(&pasync_data_h->link);
  2449. if (!num_async_data) {
  2450. num_per_mem = 0;
  2451. idx++;
  2452. pasync_ctx->async_data.va_base =
  2453. mem_descr->mem_array[idx].virtual_address;
  2454. pasync_ctx->async_data.pa_base.u.a64.address =
  2455. mem_descr->mem_array[idx].
  2456. bus_address.u.a64.address;
  2457. num_async_data = ((mem_descr->mem_array[idx].size) /
  2458. phba->params.defpdu_data_sz);
  2459. }
  2460. pasync_data_h->pbuffer =
  2461. (void *)((unsigned long)
  2462. (pasync_ctx->async_data.va_base) +
  2463. (p->defpdu_data_sz * num_per_mem));
  2464. pasync_data_h->pa.u.a64.address =
  2465. pasync_ctx->async_data.pa_base.u.a64.address +
  2466. (p->defpdu_data_sz * num_per_mem);
  2467. num_per_mem++;
  2468. num_async_data--;
  2469. list_add_tail(&pasync_data_h->link,
  2470. &pasync_ctx->async_data.free_list);
  2471. pasync_data_h++;
  2472. pasync_ctx->async_data.free_entries++;
  2473. pasync_ctx->async_data.writables++;
  2474. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2475. }
  2476. pasync_ctx->async_header.host_write_ptr = 0;
  2477. pasync_ctx->async_header.ep_read_ptr = -1;
  2478. pasync_ctx->async_data.host_write_ptr = 0;
  2479. pasync_ctx->async_data.ep_read_ptr = -1;
  2480. }
  2481. static int
  2482. be_sgl_create_contiguous(void *virtual_address,
  2483. u64 physical_address, u32 length,
  2484. struct be_dma_mem *sgl)
  2485. {
  2486. WARN_ON(!virtual_address);
  2487. WARN_ON(!physical_address);
  2488. WARN_ON(!length > 0);
  2489. WARN_ON(!sgl);
  2490. sgl->va = virtual_address;
  2491. sgl->dma = (unsigned long)physical_address;
  2492. sgl->size = length;
  2493. return 0;
  2494. }
  2495. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2496. {
  2497. memset(sgl, 0, sizeof(*sgl));
  2498. }
  2499. static void
  2500. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2501. struct mem_array *pmem, struct be_dma_mem *sgl)
  2502. {
  2503. if (sgl->va)
  2504. be_sgl_destroy_contiguous(sgl);
  2505. be_sgl_create_contiguous(pmem->virtual_address,
  2506. pmem->bus_address.u.a64.address,
  2507. pmem->size, sgl);
  2508. }
  2509. static void
  2510. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2511. struct mem_array *pmem, struct be_dma_mem *sgl)
  2512. {
  2513. if (sgl->va)
  2514. be_sgl_destroy_contiguous(sgl);
  2515. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2516. pmem->bus_address.u.a64.address,
  2517. pmem->size, sgl);
  2518. }
  2519. static int be_fill_queue(struct be_queue_info *q,
  2520. u16 len, u16 entry_size, void *vaddress)
  2521. {
  2522. struct be_dma_mem *mem = &q->dma_mem;
  2523. memset(q, 0, sizeof(*q));
  2524. q->len = len;
  2525. q->entry_size = entry_size;
  2526. mem->size = len * entry_size;
  2527. mem->va = vaddress;
  2528. if (!mem->va)
  2529. return -ENOMEM;
  2530. memset(mem->va, 0, mem->size);
  2531. return 0;
  2532. }
  2533. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2534. struct hwi_context_memory *phwi_context)
  2535. {
  2536. unsigned int i, num_eq_pages;
  2537. int ret = 0, eq_for_mcc;
  2538. struct be_queue_info *eq;
  2539. struct be_dma_mem *mem;
  2540. void *eq_vaddress;
  2541. dma_addr_t paddr;
  2542. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2543. sizeof(struct be_eq_entry));
  2544. if (phba->msix_enabled)
  2545. eq_for_mcc = 1;
  2546. else
  2547. eq_for_mcc = 0;
  2548. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2549. eq = &phwi_context->be_eq[i].q;
  2550. mem = &eq->dma_mem;
  2551. phwi_context->be_eq[i].phba = phba;
  2552. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2553. num_eq_pages * PAGE_SIZE,
  2554. &paddr);
  2555. if (!eq_vaddress)
  2556. goto create_eq_error;
  2557. mem->va = eq_vaddress;
  2558. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2559. sizeof(struct be_eq_entry), eq_vaddress);
  2560. if (ret) {
  2561. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2562. "BM_%d : be_fill_queue Failed for EQ\n");
  2563. goto create_eq_error;
  2564. }
  2565. mem->dma = paddr;
  2566. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2567. phwi_context->cur_eqd);
  2568. if (ret) {
  2569. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2570. "BM_%d : beiscsi_cmd_eq_create"
  2571. "Failed for EQ\n");
  2572. goto create_eq_error;
  2573. }
  2574. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2575. "BM_%d : eqid = %d\n",
  2576. phwi_context->be_eq[i].q.id);
  2577. }
  2578. return 0;
  2579. create_eq_error:
  2580. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2581. eq = &phwi_context->be_eq[i].q;
  2582. mem = &eq->dma_mem;
  2583. if (mem->va)
  2584. pci_free_consistent(phba->pcidev, num_eq_pages
  2585. * PAGE_SIZE,
  2586. mem->va, mem->dma);
  2587. }
  2588. return ret;
  2589. }
  2590. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2591. struct hwi_context_memory *phwi_context)
  2592. {
  2593. unsigned int i, num_cq_pages;
  2594. int ret = 0;
  2595. struct be_queue_info *cq, *eq;
  2596. struct be_dma_mem *mem;
  2597. struct be_eq_obj *pbe_eq;
  2598. void *cq_vaddress;
  2599. dma_addr_t paddr;
  2600. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2601. sizeof(struct sol_cqe));
  2602. for (i = 0; i < phba->num_cpus; i++) {
  2603. cq = &phwi_context->be_cq[i];
  2604. eq = &phwi_context->be_eq[i].q;
  2605. pbe_eq = &phwi_context->be_eq[i];
  2606. pbe_eq->cq = cq;
  2607. pbe_eq->phba = phba;
  2608. mem = &cq->dma_mem;
  2609. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2610. num_cq_pages * PAGE_SIZE,
  2611. &paddr);
  2612. if (!cq_vaddress)
  2613. goto create_cq_error;
  2614. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2615. sizeof(struct sol_cqe), cq_vaddress);
  2616. if (ret) {
  2617. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2618. "BM_%d : be_fill_queue Failed "
  2619. "for ISCSI CQ\n");
  2620. goto create_cq_error;
  2621. }
  2622. mem->dma = paddr;
  2623. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2624. false, 0);
  2625. if (ret) {
  2626. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2627. "BM_%d : beiscsi_cmd_eq_create"
  2628. "Failed for ISCSI CQ\n");
  2629. goto create_cq_error;
  2630. }
  2631. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2632. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2633. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2634. }
  2635. return 0;
  2636. create_cq_error:
  2637. for (i = 0; i < phba->num_cpus; i++) {
  2638. cq = &phwi_context->be_cq[i];
  2639. mem = &cq->dma_mem;
  2640. if (mem->va)
  2641. pci_free_consistent(phba->pcidev, num_cq_pages
  2642. * PAGE_SIZE,
  2643. mem->va, mem->dma);
  2644. }
  2645. return ret;
  2646. }
  2647. static int
  2648. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2649. struct hwi_context_memory *phwi_context,
  2650. struct hwi_controller *phwi_ctrlr,
  2651. unsigned int def_pdu_ring_sz)
  2652. {
  2653. unsigned int idx;
  2654. int ret;
  2655. struct be_queue_info *dq, *cq;
  2656. struct be_dma_mem *mem;
  2657. struct be_mem_descriptor *mem_descr;
  2658. void *dq_vaddress;
  2659. idx = 0;
  2660. dq = &phwi_context->be_def_hdrq;
  2661. cq = &phwi_context->be_cq[0];
  2662. mem = &dq->dma_mem;
  2663. mem_descr = phba->init_mem;
  2664. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2665. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2666. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2667. sizeof(struct phys_addr),
  2668. sizeof(struct phys_addr), dq_vaddress);
  2669. if (ret) {
  2670. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2671. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2672. return ret;
  2673. }
  2674. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2675. bus_address.u.a64.address;
  2676. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2677. def_pdu_ring_sz,
  2678. phba->params.defpdu_hdr_sz);
  2679. if (ret) {
  2680. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2681. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2682. return ret;
  2683. }
  2684. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2685. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2686. "BM_%d : iscsi def pdu id is %d\n",
  2687. phwi_context->be_def_hdrq.id);
  2688. hwi_post_async_buffers(phba, 1);
  2689. return 0;
  2690. }
  2691. static int
  2692. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2693. struct hwi_context_memory *phwi_context,
  2694. struct hwi_controller *phwi_ctrlr,
  2695. unsigned int def_pdu_ring_sz)
  2696. {
  2697. unsigned int idx;
  2698. int ret;
  2699. struct be_queue_info *dataq, *cq;
  2700. struct be_dma_mem *mem;
  2701. struct be_mem_descriptor *mem_descr;
  2702. void *dq_vaddress;
  2703. idx = 0;
  2704. dataq = &phwi_context->be_def_dataq;
  2705. cq = &phwi_context->be_cq[0];
  2706. mem = &dataq->dma_mem;
  2707. mem_descr = phba->init_mem;
  2708. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2709. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2710. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2711. sizeof(struct phys_addr),
  2712. sizeof(struct phys_addr), dq_vaddress);
  2713. if (ret) {
  2714. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2715. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2716. return ret;
  2717. }
  2718. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2719. bus_address.u.a64.address;
  2720. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2721. def_pdu_ring_sz,
  2722. phba->params.defpdu_data_sz);
  2723. if (ret) {
  2724. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2725. "BM_%d be_cmd_create_default_pdu_queue"
  2726. " Failed for DEF PDU DATA\n");
  2727. return ret;
  2728. }
  2729. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2730. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2731. "BM_%d : iscsi def data id is %d\n",
  2732. phwi_context->be_def_dataq.id);
  2733. hwi_post_async_buffers(phba, 0);
  2734. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2735. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2736. return 0;
  2737. }
  2738. static int
  2739. beiscsi_post_pages(struct beiscsi_hba *phba)
  2740. {
  2741. struct be_mem_descriptor *mem_descr;
  2742. struct mem_array *pm_arr;
  2743. unsigned int page_offset, i;
  2744. struct be_dma_mem sgl;
  2745. int status;
  2746. mem_descr = phba->init_mem;
  2747. mem_descr += HWI_MEM_SGE;
  2748. pm_arr = mem_descr->mem_array;
  2749. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2750. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2751. for (i = 0; i < mem_descr->num_elements; i++) {
  2752. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2753. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2754. page_offset,
  2755. (pm_arr->size / PAGE_SIZE));
  2756. page_offset += pm_arr->size / PAGE_SIZE;
  2757. if (status != 0) {
  2758. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2759. "BM_%d : post sgl failed.\n");
  2760. return status;
  2761. }
  2762. pm_arr++;
  2763. }
  2764. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2765. "BM_%d : POSTED PAGES\n");
  2766. return 0;
  2767. }
  2768. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2769. {
  2770. struct be_dma_mem *mem = &q->dma_mem;
  2771. if (mem->va) {
  2772. pci_free_consistent(phba->pcidev, mem->size,
  2773. mem->va, mem->dma);
  2774. mem->va = NULL;
  2775. }
  2776. }
  2777. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2778. u16 len, u16 entry_size)
  2779. {
  2780. struct be_dma_mem *mem = &q->dma_mem;
  2781. memset(q, 0, sizeof(*q));
  2782. q->len = len;
  2783. q->entry_size = entry_size;
  2784. mem->size = len * entry_size;
  2785. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2786. if (!mem->va)
  2787. return -ENOMEM;
  2788. memset(mem->va, 0, mem->size);
  2789. return 0;
  2790. }
  2791. static int
  2792. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2793. struct hwi_context_memory *phwi_context,
  2794. struct hwi_controller *phwi_ctrlr)
  2795. {
  2796. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2797. u64 pa_addr_lo;
  2798. unsigned int idx, num, i;
  2799. struct mem_array *pwrb_arr;
  2800. void *wrb_vaddr;
  2801. struct be_dma_mem sgl;
  2802. struct be_mem_descriptor *mem_descr;
  2803. int status;
  2804. idx = 0;
  2805. mem_descr = phba->init_mem;
  2806. mem_descr += HWI_MEM_WRB;
  2807. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2808. GFP_KERNEL);
  2809. if (!pwrb_arr) {
  2810. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2811. "BM_%d : Memory alloc failed in create wrb ring.\n");
  2812. return -ENOMEM;
  2813. }
  2814. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2815. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2816. num_wrb_rings = mem_descr->mem_array[idx].size /
  2817. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2818. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2819. if (num_wrb_rings) {
  2820. pwrb_arr[num].virtual_address = wrb_vaddr;
  2821. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2822. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2823. sizeof(struct iscsi_wrb);
  2824. wrb_vaddr += pwrb_arr[num].size;
  2825. pa_addr_lo += pwrb_arr[num].size;
  2826. num_wrb_rings--;
  2827. } else {
  2828. idx++;
  2829. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2830. pa_addr_lo = mem_descr->mem_array[idx].\
  2831. bus_address.u.a64.address;
  2832. num_wrb_rings = mem_descr->mem_array[idx].size /
  2833. (phba->params.wrbs_per_cxn *
  2834. sizeof(struct iscsi_wrb));
  2835. pwrb_arr[num].virtual_address = wrb_vaddr;
  2836. pwrb_arr[num].bus_address.u.a64.address\
  2837. = pa_addr_lo;
  2838. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2839. sizeof(struct iscsi_wrb);
  2840. wrb_vaddr += pwrb_arr[num].size;
  2841. pa_addr_lo += pwrb_arr[num].size;
  2842. num_wrb_rings--;
  2843. }
  2844. }
  2845. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2846. wrb_mem_index = 0;
  2847. offset = 0;
  2848. size = 0;
  2849. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2850. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2851. &phwi_context->be_wrbq[i]);
  2852. if (status != 0) {
  2853. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2854. "BM_%d : wrbq create failed.");
  2855. kfree(pwrb_arr);
  2856. return status;
  2857. }
  2858. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  2859. id;
  2860. }
  2861. kfree(pwrb_arr);
  2862. return 0;
  2863. }
  2864. static void free_wrb_handles(struct beiscsi_hba *phba)
  2865. {
  2866. unsigned int index;
  2867. struct hwi_controller *phwi_ctrlr;
  2868. struct hwi_wrb_context *pwrb_context;
  2869. phwi_ctrlr = phba->phwi_ctrlr;
  2870. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2871. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2872. kfree(pwrb_context->pwrb_handle_base);
  2873. kfree(pwrb_context->pwrb_handle_basestd);
  2874. }
  2875. }
  2876. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  2877. {
  2878. struct be_queue_info *q;
  2879. struct be_ctrl_info *ctrl = &phba->ctrl;
  2880. q = &phba->ctrl.mcc_obj.q;
  2881. if (q->created)
  2882. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  2883. be_queue_free(phba, q);
  2884. q = &phba->ctrl.mcc_obj.cq;
  2885. if (q->created)
  2886. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2887. be_queue_free(phba, q);
  2888. }
  2889. static void hwi_cleanup(struct beiscsi_hba *phba)
  2890. {
  2891. struct be_queue_info *q;
  2892. struct be_ctrl_info *ctrl = &phba->ctrl;
  2893. struct hwi_controller *phwi_ctrlr;
  2894. struct hwi_context_memory *phwi_context;
  2895. int i, eq_num;
  2896. phwi_ctrlr = phba->phwi_ctrlr;
  2897. phwi_context = phwi_ctrlr->phwi_ctxt;
  2898. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2899. q = &phwi_context->be_wrbq[i];
  2900. if (q->created)
  2901. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  2902. }
  2903. free_wrb_handles(phba);
  2904. q = &phwi_context->be_def_hdrq;
  2905. if (q->created)
  2906. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2907. q = &phwi_context->be_def_dataq;
  2908. if (q->created)
  2909. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2910. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  2911. for (i = 0; i < (phba->num_cpus); i++) {
  2912. q = &phwi_context->be_cq[i];
  2913. if (q->created)
  2914. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2915. }
  2916. if (phba->msix_enabled)
  2917. eq_num = 1;
  2918. else
  2919. eq_num = 0;
  2920. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  2921. q = &phwi_context->be_eq[i].q;
  2922. if (q->created)
  2923. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  2924. }
  2925. be_mcc_queues_destroy(phba);
  2926. }
  2927. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  2928. struct hwi_context_memory *phwi_context)
  2929. {
  2930. struct be_queue_info *q, *cq;
  2931. struct be_ctrl_info *ctrl = &phba->ctrl;
  2932. /* Alloc MCC compl queue */
  2933. cq = &phba->ctrl.mcc_obj.cq;
  2934. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  2935. sizeof(struct be_mcc_compl)))
  2936. goto err;
  2937. /* Ask BE to create MCC compl queue; */
  2938. if (phba->msix_enabled) {
  2939. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  2940. [phba->num_cpus].q, false, true, 0))
  2941. goto mcc_cq_free;
  2942. } else {
  2943. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  2944. false, true, 0))
  2945. goto mcc_cq_free;
  2946. }
  2947. /* Alloc MCC queue */
  2948. q = &phba->ctrl.mcc_obj.q;
  2949. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  2950. goto mcc_cq_destroy;
  2951. /* Ask BE to create MCC queue */
  2952. if (beiscsi_cmd_mccq_create(phba, q, cq))
  2953. goto mcc_q_free;
  2954. return 0;
  2955. mcc_q_free:
  2956. be_queue_free(phba, q);
  2957. mcc_cq_destroy:
  2958. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  2959. mcc_cq_free:
  2960. be_queue_free(phba, cq);
  2961. err:
  2962. return -ENOMEM;
  2963. }
  2964. /**
  2965. * find_num_cpus()- Get the CPU online count
  2966. * @phba: ptr to priv structure
  2967. *
  2968. * CPU count is used for creating EQ.
  2969. **/
  2970. static void find_num_cpus(struct beiscsi_hba *phba)
  2971. {
  2972. int num_cpus = 0;
  2973. num_cpus = num_online_cpus();
  2974. phba->num_cpus = (num_cpus >= BEISCSI_MAX_NUM_CPU) ?
  2975. (BEISCSI_MAX_NUM_CPU - 1) : num_cpus;
  2976. }
  2977. static int hwi_init_port(struct beiscsi_hba *phba)
  2978. {
  2979. struct hwi_controller *phwi_ctrlr;
  2980. struct hwi_context_memory *phwi_context;
  2981. unsigned int def_pdu_ring_sz;
  2982. struct be_ctrl_info *ctrl = &phba->ctrl;
  2983. int status;
  2984. def_pdu_ring_sz =
  2985. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  2986. phwi_ctrlr = phba->phwi_ctrlr;
  2987. phwi_context = phwi_ctrlr->phwi_ctxt;
  2988. phwi_context->max_eqd = 0;
  2989. phwi_context->min_eqd = 0;
  2990. phwi_context->cur_eqd = 64;
  2991. be_cmd_fw_initialize(&phba->ctrl);
  2992. status = beiscsi_create_eqs(phba, phwi_context);
  2993. if (status != 0) {
  2994. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2995. "BM_%d : EQ not created\n");
  2996. goto error;
  2997. }
  2998. status = be_mcc_queues_create(phba, phwi_context);
  2999. if (status != 0)
  3000. goto error;
  3001. status = mgmt_check_supported_fw(ctrl, phba);
  3002. if (status != 0) {
  3003. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3004. "BM_%d : Unsupported fw version\n");
  3005. goto error;
  3006. }
  3007. status = beiscsi_create_cqs(phba, phwi_context);
  3008. if (status != 0) {
  3009. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3010. "BM_%d : CQ not created\n");
  3011. goto error;
  3012. }
  3013. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  3014. def_pdu_ring_sz);
  3015. if (status != 0) {
  3016. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3017. "BM_%d : Default Header not created\n");
  3018. goto error;
  3019. }
  3020. status = beiscsi_create_def_data(phba, phwi_context,
  3021. phwi_ctrlr, def_pdu_ring_sz);
  3022. if (status != 0) {
  3023. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3024. "BM_%d : Default Data not created\n");
  3025. goto error;
  3026. }
  3027. status = beiscsi_post_pages(phba);
  3028. if (status != 0) {
  3029. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3030. "BM_%d : Post SGL Pages Failed\n");
  3031. goto error;
  3032. }
  3033. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3034. if (status != 0) {
  3035. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3036. "BM_%d : WRB Rings not created\n");
  3037. goto error;
  3038. }
  3039. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3040. "BM_%d : hwi_init_port success\n");
  3041. return 0;
  3042. error:
  3043. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3044. "BM_%d : hwi_init_port failed");
  3045. hwi_cleanup(phba);
  3046. return status;
  3047. }
  3048. static int hwi_init_controller(struct beiscsi_hba *phba)
  3049. {
  3050. struct hwi_controller *phwi_ctrlr;
  3051. phwi_ctrlr = phba->phwi_ctrlr;
  3052. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3053. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3054. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3055. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3056. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3057. phwi_ctrlr->phwi_ctxt);
  3058. } else {
  3059. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3060. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3061. "than one element.Failing to load\n");
  3062. return -ENOMEM;
  3063. }
  3064. iscsi_init_global_templates(phba);
  3065. if (beiscsi_init_wrb_handle(phba))
  3066. return -ENOMEM;
  3067. hwi_init_async_pdu_ctx(phba);
  3068. if (hwi_init_port(phba) != 0) {
  3069. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3070. "BM_%d : hwi_init_controller failed\n");
  3071. return -ENOMEM;
  3072. }
  3073. return 0;
  3074. }
  3075. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3076. {
  3077. struct be_mem_descriptor *mem_descr;
  3078. int i, j;
  3079. mem_descr = phba->init_mem;
  3080. i = 0;
  3081. j = 0;
  3082. for (i = 0; i < SE_MEM_MAX; i++) {
  3083. for (j = mem_descr->num_elements; j > 0; j--) {
  3084. pci_free_consistent(phba->pcidev,
  3085. mem_descr->mem_array[j - 1].size,
  3086. mem_descr->mem_array[j - 1].virtual_address,
  3087. (unsigned long)mem_descr->mem_array[j - 1].
  3088. bus_address.u.a64.address);
  3089. }
  3090. kfree(mem_descr->mem_array);
  3091. mem_descr++;
  3092. }
  3093. kfree(phba->init_mem);
  3094. kfree(phba->phwi_ctrlr);
  3095. }
  3096. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3097. {
  3098. int ret = -ENOMEM;
  3099. ret = beiscsi_get_memory(phba);
  3100. if (ret < 0) {
  3101. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3102. "BM_%d : beiscsi_dev_probe -"
  3103. "Failed in beiscsi_alloc_memory\n");
  3104. return ret;
  3105. }
  3106. ret = hwi_init_controller(phba);
  3107. if (ret)
  3108. goto free_init;
  3109. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3110. "BM_%d : Return success from beiscsi_init_controller");
  3111. return 0;
  3112. free_init:
  3113. beiscsi_free_mem(phba);
  3114. return ret;
  3115. }
  3116. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3117. {
  3118. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3119. struct sgl_handle *psgl_handle;
  3120. struct iscsi_sge *pfrag;
  3121. unsigned int arr_index, i, idx;
  3122. phba->io_sgl_hndl_avbl = 0;
  3123. phba->eh_sgl_hndl_avbl = 0;
  3124. mem_descr_sglh = phba->init_mem;
  3125. mem_descr_sglh += HWI_MEM_SGLH;
  3126. if (1 == mem_descr_sglh->num_elements) {
  3127. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3128. phba->params.ios_per_ctrl,
  3129. GFP_KERNEL);
  3130. if (!phba->io_sgl_hndl_base) {
  3131. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3132. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3133. return -ENOMEM;
  3134. }
  3135. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3136. (phba->params.icds_per_ctrl -
  3137. phba->params.ios_per_ctrl),
  3138. GFP_KERNEL);
  3139. if (!phba->eh_sgl_hndl_base) {
  3140. kfree(phba->io_sgl_hndl_base);
  3141. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3142. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3143. return -ENOMEM;
  3144. }
  3145. } else {
  3146. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3147. "BM_%d : HWI_MEM_SGLH is more than one element."
  3148. "Failing to load\n");
  3149. return -ENOMEM;
  3150. }
  3151. arr_index = 0;
  3152. idx = 0;
  3153. while (idx < mem_descr_sglh->num_elements) {
  3154. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3155. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3156. sizeof(struct sgl_handle)); i++) {
  3157. if (arr_index < phba->params.ios_per_ctrl) {
  3158. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3159. phba->io_sgl_hndl_avbl++;
  3160. arr_index++;
  3161. } else {
  3162. phba->eh_sgl_hndl_base[arr_index -
  3163. phba->params.ios_per_ctrl] =
  3164. psgl_handle;
  3165. arr_index++;
  3166. phba->eh_sgl_hndl_avbl++;
  3167. }
  3168. psgl_handle++;
  3169. }
  3170. idx++;
  3171. }
  3172. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3173. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3174. "phba->eh_sgl_hndl_avbl=%d\n",
  3175. phba->io_sgl_hndl_avbl,
  3176. phba->eh_sgl_hndl_avbl);
  3177. mem_descr_sg = phba->init_mem;
  3178. mem_descr_sg += HWI_MEM_SGE;
  3179. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3180. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3181. mem_descr_sg->num_elements);
  3182. arr_index = 0;
  3183. idx = 0;
  3184. while (idx < mem_descr_sg->num_elements) {
  3185. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3186. for (i = 0;
  3187. i < (mem_descr_sg->mem_array[idx].size) /
  3188. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3189. i++) {
  3190. if (arr_index < phba->params.ios_per_ctrl)
  3191. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3192. else
  3193. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3194. phba->params.ios_per_ctrl];
  3195. psgl_handle->pfrag = pfrag;
  3196. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3197. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3198. pfrag += phba->params.num_sge_per_io;
  3199. psgl_handle->sgl_index =
  3200. phba->fw_config.iscsi_icd_start + arr_index++;
  3201. }
  3202. idx++;
  3203. }
  3204. phba->io_sgl_free_index = 0;
  3205. phba->io_sgl_alloc_index = 0;
  3206. phba->eh_sgl_free_index = 0;
  3207. phba->eh_sgl_alloc_index = 0;
  3208. return 0;
  3209. }
  3210. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3211. {
  3212. int i, new_cid;
  3213. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3214. GFP_KERNEL);
  3215. if (!phba->cid_array) {
  3216. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3217. "BM_%d : Failed to allocate memory in "
  3218. "hba_setup_cid_tbls\n");
  3219. return -ENOMEM;
  3220. }
  3221. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3222. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3223. if (!phba->ep_array) {
  3224. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3225. "BM_%d : Failed to allocate memory in "
  3226. "hba_setup_cid_tbls\n");
  3227. kfree(phba->cid_array);
  3228. return -ENOMEM;
  3229. }
  3230. new_cid = phba->fw_config.iscsi_cid_start;
  3231. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3232. phba->cid_array[i] = new_cid;
  3233. new_cid += 2;
  3234. }
  3235. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3236. return 0;
  3237. }
  3238. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3239. {
  3240. struct be_ctrl_info *ctrl = &phba->ctrl;
  3241. struct hwi_controller *phwi_ctrlr;
  3242. struct hwi_context_memory *phwi_context;
  3243. struct be_queue_info *eq;
  3244. u8 __iomem *addr;
  3245. u32 reg, i;
  3246. u32 enabled;
  3247. phwi_ctrlr = phba->phwi_ctrlr;
  3248. phwi_context = phwi_ctrlr->phwi_ctxt;
  3249. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3250. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3251. reg = ioread32(addr);
  3252. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3253. if (!enabled) {
  3254. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3255. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3256. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3257. iowrite32(reg, addr);
  3258. }
  3259. if (!phba->msix_enabled) {
  3260. eq = &phwi_context->be_eq[0].q;
  3261. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3262. "BM_%d : eq->id=%d\n", eq->id);
  3263. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3264. } else {
  3265. for (i = 0; i <= phba->num_cpus; i++) {
  3266. eq = &phwi_context->be_eq[i].q;
  3267. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3268. "BM_%d : eq->id=%d\n", eq->id);
  3269. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3270. }
  3271. }
  3272. }
  3273. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3274. {
  3275. struct be_ctrl_info *ctrl = &phba->ctrl;
  3276. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3277. u32 reg = ioread32(addr);
  3278. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3279. if (enabled) {
  3280. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3281. iowrite32(reg, addr);
  3282. } else
  3283. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3284. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3285. }
  3286. /**
  3287. * beiscsi_get_boot_info()- Get the boot session info
  3288. * @phba: The device priv structure instance
  3289. *
  3290. * Get the boot target info and store in driver priv structure
  3291. *
  3292. * return values
  3293. * Success: 0
  3294. * Failure: Non-Zero Value
  3295. **/
  3296. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3297. {
  3298. struct be_cmd_get_session_resp *session_resp;
  3299. struct be_mcc_wrb *wrb;
  3300. struct be_dma_mem nonemb_cmd;
  3301. unsigned int tag, wrb_num;
  3302. unsigned short status, extd_status;
  3303. unsigned int s_handle;
  3304. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3305. int ret = -ENOMEM;
  3306. /* Get the session handle of the boot target */
  3307. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3308. if (ret) {
  3309. beiscsi_log(phba, KERN_ERR,
  3310. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3311. "BM_%d : No boot session\n");
  3312. return ret;
  3313. }
  3314. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3315. sizeof(*session_resp),
  3316. &nonemb_cmd.dma);
  3317. if (nonemb_cmd.va == NULL) {
  3318. beiscsi_log(phba, KERN_ERR,
  3319. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3320. "BM_%d : Failed to allocate memory for"
  3321. "beiscsi_get_session_info\n");
  3322. return -ENOMEM;
  3323. }
  3324. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3325. tag = mgmt_get_session_info(phba, s_handle,
  3326. &nonemb_cmd);
  3327. if (!tag) {
  3328. beiscsi_log(phba, KERN_ERR,
  3329. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3330. "BM_%d : beiscsi_get_session_info"
  3331. " Failed\n");
  3332. goto boot_freemem;
  3333. } else
  3334. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3335. phba->ctrl.mcc_numtag[tag]);
  3336. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3337. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3338. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3339. if (status || extd_status) {
  3340. beiscsi_log(phba, KERN_ERR,
  3341. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3342. "BM_%d : beiscsi_get_session_info Failed"
  3343. " status = %d extd_status = %d\n",
  3344. status, extd_status);
  3345. free_mcc_tag(&phba->ctrl, tag);
  3346. goto boot_freemem;
  3347. }
  3348. wrb = queue_get_wrb(mccq, wrb_num);
  3349. free_mcc_tag(&phba->ctrl, tag);
  3350. session_resp = nonemb_cmd.va ;
  3351. memcpy(&phba->boot_sess, &session_resp->session_info,
  3352. sizeof(struct mgmt_session_info));
  3353. ret = 0;
  3354. boot_freemem:
  3355. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3356. nonemb_cmd.va, nonemb_cmd.dma);
  3357. return ret;
  3358. }
  3359. static void beiscsi_boot_release(void *data)
  3360. {
  3361. struct beiscsi_hba *phba = data;
  3362. scsi_host_put(phba->shost);
  3363. }
  3364. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3365. {
  3366. struct iscsi_boot_kobj *boot_kobj;
  3367. /* get boot info using mgmt cmd */
  3368. if (beiscsi_get_boot_info(phba))
  3369. /* Try to see if we can carry on without this */
  3370. return 0;
  3371. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3372. if (!phba->boot_kset)
  3373. return -ENOMEM;
  3374. /* get a ref because the show function will ref the phba */
  3375. if (!scsi_host_get(phba->shost))
  3376. goto free_kset;
  3377. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3378. beiscsi_show_boot_tgt_info,
  3379. beiscsi_tgt_get_attr_visibility,
  3380. beiscsi_boot_release);
  3381. if (!boot_kobj)
  3382. goto put_shost;
  3383. if (!scsi_host_get(phba->shost))
  3384. goto free_kset;
  3385. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3386. beiscsi_show_boot_ini_info,
  3387. beiscsi_ini_get_attr_visibility,
  3388. beiscsi_boot_release);
  3389. if (!boot_kobj)
  3390. goto put_shost;
  3391. if (!scsi_host_get(phba->shost))
  3392. goto free_kset;
  3393. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3394. beiscsi_show_boot_eth_info,
  3395. beiscsi_eth_get_attr_visibility,
  3396. beiscsi_boot_release);
  3397. if (!boot_kobj)
  3398. goto put_shost;
  3399. return 0;
  3400. put_shost:
  3401. scsi_host_put(phba->shost);
  3402. free_kset:
  3403. iscsi_boot_destroy_kset(phba->boot_kset);
  3404. return -ENOMEM;
  3405. }
  3406. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3407. {
  3408. int ret;
  3409. ret = beiscsi_init_controller(phba);
  3410. if (ret < 0) {
  3411. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3412. "BM_%d : beiscsi_dev_probe - Failed in"
  3413. "beiscsi_init_controller\n");
  3414. return ret;
  3415. }
  3416. ret = beiscsi_init_sgl_handle(phba);
  3417. if (ret < 0) {
  3418. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3419. "BM_%d : beiscsi_dev_probe - Failed in"
  3420. "beiscsi_init_sgl_handle\n");
  3421. goto do_cleanup_ctrlr;
  3422. }
  3423. if (hba_setup_cid_tbls(phba)) {
  3424. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3425. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3426. kfree(phba->io_sgl_hndl_base);
  3427. kfree(phba->eh_sgl_hndl_base);
  3428. goto do_cleanup_ctrlr;
  3429. }
  3430. return ret;
  3431. do_cleanup_ctrlr:
  3432. hwi_cleanup(phba);
  3433. return ret;
  3434. }
  3435. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3436. {
  3437. struct hwi_controller *phwi_ctrlr;
  3438. struct hwi_context_memory *phwi_context;
  3439. struct be_queue_info *eq;
  3440. struct be_eq_entry *eqe = NULL;
  3441. int i, eq_msix;
  3442. unsigned int num_processed;
  3443. phwi_ctrlr = phba->phwi_ctrlr;
  3444. phwi_context = phwi_ctrlr->phwi_ctxt;
  3445. if (phba->msix_enabled)
  3446. eq_msix = 1;
  3447. else
  3448. eq_msix = 0;
  3449. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3450. eq = &phwi_context->be_eq[i].q;
  3451. eqe = queue_tail_node(eq);
  3452. num_processed = 0;
  3453. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3454. & EQE_VALID_MASK) {
  3455. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3456. queue_tail_inc(eq);
  3457. eqe = queue_tail_node(eq);
  3458. num_processed++;
  3459. }
  3460. if (num_processed)
  3461. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3462. }
  3463. }
  3464. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3465. {
  3466. int mgmt_status;
  3467. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3468. if (mgmt_status)
  3469. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3470. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3471. hwi_purge_eq(phba);
  3472. hwi_cleanup(phba);
  3473. kfree(phba->io_sgl_hndl_base);
  3474. kfree(phba->eh_sgl_hndl_base);
  3475. kfree(phba->cid_array);
  3476. kfree(phba->ep_array);
  3477. }
  3478. /**
  3479. * beiscsi_cleanup_task()- Free driver resources of the task
  3480. * @task: ptr to the iscsi task
  3481. *
  3482. **/
  3483. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3484. {
  3485. struct beiscsi_io_task *io_task = task->dd_data;
  3486. struct iscsi_conn *conn = task->conn;
  3487. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3488. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3489. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3490. struct hwi_wrb_context *pwrb_context;
  3491. struct hwi_controller *phwi_ctrlr;
  3492. phwi_ctrlr = phba->phwi_ctrlr;
  3493. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3494. - phba->fw_config.iscsi_cid_start];
  3495. if (io_task->cmd_bhs) {
  3496. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3497. io_task->bhs_pa.u.a64.address);
  3498. io_task->cmd_bhs = NULL;
  3499. }
  3500. if (task->sc) {
  3501. if (io_task->pwrb_handle) {
  3502. free_wrb_handle(phba, pwrb_context,
  3503. io_task->pwrb_handle);
  3504. io_task->pwrb_handle = NULL;
  3505. }
  3506. if (io_task->psgl_handle) {
  3507. spin_lock(&phba->io_sgl_lock);
  3508. free_io_sgl_handle(phba, io_task->psgl_handle);
  3509. spin_unlock(&phba->io_sgl_lock);
  3510. io_task->psgl_handle = NULL;
  3511. }
  3512. } else {
  3513. if (!beiscsi_conn->login_in_progress) {
  3514. if (io_task->pwrb_handle) {
  3515. free_wrb_handle(phba, pwrb_context,
  3516. io_task->pwrb_handle);
  3517. io_task->pwrb_handle = NULL;
  3518. }
  3519. if (io_task->psgl_handle) {
  3520. spin_lock(&phba->mgmt_sgl_lock);
  3521. free_mgmt_sgl_handle(phba,
  3522. io_task->psgl_handle);
  3523. spin_unlock(&phba->mgmt_sgl_lock);
  3524. io_task->psgl_handle = NULL;
  3525. }
  3526. if (io_task->mtask_addr) {
  3527. pci_unmap_single(phba->pcidev,
  3528. io_task->mtask_addr,
  3529. io_task->mtask_data_count,
  3530. PCI_DMA_TODEVICE);
  3531. io_task->mtask_addr = 0;
  3532. }
  3533. }
  3534. }
  3535. }
  3536. void
  3537. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3538. struct beiscsi_offload_params *params)
  3539. {
  3540. struct wrb_handle *pwrb_handle;
  3541. struct iscsi_target_context_update_wrb *pwrb = NULL;
  3542. struct be_mem_descriptor *mem_descr;
  3543. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3544. struct iscsi_task *task = beiscsi_conn->task;
  3545. struct iscsi_session *session = task->conn->session;
  3546. u32 doorbell = 0;
  3547. /*
  3548. * We can always use 0 here because it is reserved by libiscsi for
  3549. * login/startup related tasks.
  3550. */
  3551. beiscsi_conn->login_in_progress = 0;
  3552. spin_lock_bh(&session->lock);
  3553. beiscsi_cleanup_task(task);
  3554. spin_unlock_bh(&session->lock);
  3555. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3556. phba->fw_config.iscsi_cid_start));
  3557. pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
  3558. memset(pwrb, 0, sizeof(*pwrb));
  3559. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3560. max_burst_length, pwrb, params->dw[offsetof
  3561. (struct amap_beiscsi_offload_params,
  3562. max_burst_length) / 32]);
  3563. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3564. max_send_data_segment_length, pwrb,
  3565. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3566. max_send_data_segment_length) / 32]);
  3567. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3568. first_burst_length,
  3569. pwrb,
  3570. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3571. first_burst_length) / 32]);
  3572. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
  3573. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3574. erl) / 32] & OFFLD_PARAMS_ERL));
  3575. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
  3576. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3577. dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
  3578. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
  3579. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3580. hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
  3581. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
  3582. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3583. ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
  3584. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
  3585. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3586. imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
  3587. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
  3588. pwrb,
  3589. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3590. exp_statsn) / 32] + 1));
  3591. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
  3592. 0x7);
  3593. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
  3594. pwrb, pwrb_handle->wrb_index);
  3595. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
  3596. pwrb, pwrb_handle->nxt_wrb_index);
  3597. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3598. session_state, pwrb, 0);
  3599. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
  3600. pwrb, 1);
  3601. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
  3602. pwrb, 0);
  3603. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
  3604. 0);
  3605. mem_descr = phba->init_mem;
  3606. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  3607. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3608. pad_buffer_addr_hi, pwrb,
  3609. mem_descr->mem_array[0].bus_address.u.a32.address_hi);
  3610. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3611. pad_buffer_addr_lo, pwrb,
  3612. mem_descr->mem_array[0].bus_address.u.a32.address_lo);
  3613. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
  3614. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3615. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3616. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3617. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3618. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3619. }
  3620. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3621. int *index, int *age)
  3622. {
  3623. *index = (int)itt;
  3624. if (age)
  3625. *age = conn->session->age;
  3626. }
  3627. /**
  3628. * beiscsi_alloc_pdu - allocates pdu and related resources
  3629. * @task: libiscsi task
  3630. * @opcode: opcode of pdu for task
  3631. *
  3632. * This is called with the session lock held. It will allocate
  3633. * the wrb and sgl if needed for the command. And it will prep
  3634. * the pdu's itt. beiscsi_parse_pdu will later translate
  3635. * the pdu itt to the libiscsi task itt.
  3636. */
  3637. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3638. {
  3639. struct beiscsi_io_task *io_task = task->dd_data;
  3640. struct iscsi_conn *conn = task->conn;
  3641. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3642. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3643. struct hwi_wrb_context *pwrb_context;
  3644. struct hwi_controller *phwi_ctrlr;
  3645. itt_t itt;
  3646. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3647. dma_addr_t paddr;
  3648. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3649. GFP_ATOMIC, &paddr);
  3650. if (!io_task->cmd_bhs)
  3651. return -ENOMEM;
  3652. io_task->bhs_pa.u.a64.address = paddr;
  3653. io_task->libiscsi_itt = (itt_t)task->itt;
  3654. io_task->conn = beiscsi_conn;
  3655. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3656. task->hdr_max = sizeof(struct be_cmd_bhs);
  3657. io_task->psgl_handle = NULL;
  3658. io_task->pwrb_handle = NULL;
  3659. if (task->sc) {
  3660. spin_lock(&phba->io_sgl_lock);
  3661. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3662. spin_unlock(&phba->io_sgl_lock);
  3663. if (!io_task->psgl_handle) {
  3664. beiscsi_log(phba, KERN_ERR,
  3665. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3666. "BM_%d : Alloc of IO_SGL_ICD Failed"
  3667. "for the CID : %d\n",
  3668. beiscsi_conn->beiscsi_conn_cid);
  3669. goto free_hndls;
  3670. }
  3671. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3672. beiscsi_conn->beiscsi_conn_cid -
  3673. phba->fw_config.iscsi_cid_start);
  3674. if (!io_task->pwrb_handle) {
  3675. beiscsi_log(phba, KERN_ERR,
  3676. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3677. "BM_%d : Alloc of WRB_HANDLE Failed"
  3678. "for the CID : %d\n",
  3679. beiscsi_conn->beiscsi_conn_cid);
  3680. goto free_io_hndls;
  3681. }
  3682. } else {
  3683. io_task->scsi_cmnd = NULL;
  3684. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3685. if (!beiscsi_conn->login_in_progress) {
  3686. spin_lock(&phba->mgmt_sgl_lock);
  3687. io_task->psgl_handle = (struct sgl_handle *)
  3688. alloc_mgmt_sgl_handle(phba);
  3689. spin_unlock(&phba->mgmt_sgl_lock);
  3690. if (!io_task->psgl_handle) {
  3691. beiscsi_log(phba, KERN_ERR,
  3692. BEISCSI_LOG_IO |
  3693. BEISCSI_LOG_CONFIG,
  3694. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3695. "for the CID : %d\n",
  3696. beiscsi_conn->
  3697. beiscsi_conn_cid);
  3698. goto free_hndls;
  3699. }
  3700. beiscsi_conn->login_in_progress = 1;
  3701. beiscsi_conn->plogin_sgl_handle =
  3702. io_task->psgl_handle;
  3703. io_task->pwrb_handle =
  3704. alloc_wrb_handle(phba,
  3705. beiscsi_conn->beiscsi_conn_cid -
  3706. phba->fw_config.iscsi_cid_start);
  3707. if (!io_task->pwrb_handle) {
  3708. beiscsi_log(phba, KERN_ERR,
  3709. BEISCSI_LOG_IO |
  3710. BEISCSI_LOG_CONFIG,
  3711. "BM_%d : Alloc of WRB_HANDLE Failed"
  3712. "for the CID : %d\n",
  3713. beiscsi_conn->
  3714. beiscsi_conn_cid);
  3715. goto free_mgmt_hndls;
  3716. }
  3717. beiscsi_conn->plogin_wrb_handle =
  3718. io_task->pwrb_handle;
  3719. } else {
  3720. io_task->psgl_handle =
  3721. beiscsi_conn->plogin_sgl_handle;
  3722. io_task->pwrb_handle =
  3723. beiscsi_conn->plogin_wrb_handle;
  3724. }
  3725. beiscsi_conn->task = task;
  3726. } else {
  3727. spin_lock(&phba->mgmt_sgl_lock);
  3728. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3729. spin_unlock(&phba->mgmt_sgl_lock);
  3730. if (!io_task->psgl_handle) {
  3731. beiscsi_log(phba, KERN_ERR,
  3732. BEISCSI_LOG_IO |
  3733. BEISCSI_LOG_CONFIG,
  3734. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3735. "for the CID : %d\n",
  3736. beiscsi_conn->
  3737. beiscsi_conn_cid);
  3738. goto free_hndls;
  3739. }
  3740. io_task->pwrb_handle =
  3741. alloc_wrb_handle(phba,
  3742. beiscsi_conn->beiscsi_conn_cid -
  3743. phba->fw_config.iscsi_cid_start);
  3744. if (!io_task->pwrb_handle) {
  3745. beiscsi_log(phba, KERN_ERR,
  3746. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3747. "BM_%d : Alloc of WRB_HANDLE Failed"
  3748. "for the CID : %d\n",
  3749. beiscsi_conn->beiscsi_conn_cid);
  3750. goto free_mgmt_hndls;
  3751. }
  3752. }
  3753. }
  3754. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3755. wrb_index << 16) | (unsigned int)
  3756. (io_task->psgl_handle->sgl_index));
  3757. io_task->pwrb_handle->pio_handle = task;
  3758. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3759. return 0;
  3760. free_io_hndls:
  3761. spin_lock(&phba->io_sgl_lock);
  3762. free_io_sgl_handle(phba, io_task->psgl_handle);
  3763. spin_unlock(&phba->io_sgl_lock);
  3764. goto free_hndls;
  3765. free_mgmt_hndls:
  3766. spin_lock(&phba->mgmt_sgl_lock);
  3767. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3768. spin_unlock(&phba->mgmt_sgl_lock);
  3769. free_hndls:
  3770. phwi_ctrlr = phba->phwi_ctrlr;
  3771. pwrb_context = &phwi_ctrlr->wrb_context[
  3772. beiscsi_conn->beiscsi_conn_cid -
  3773. phba->fw_config.iscsi_cid_start];
  3774. if (io_task->pwrb_handle)
  3775. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3776. io_task->pwrb_handle = NULL;
  3777. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3778. io_task->bhs_pa.u.a64.address);
  3779. io_task->cmd_bhs = NULL;
  3780. return -ENOMEM;
  3781. }
  3782. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3783. unsigned int num_sg, unsigned int xferlen,
  3784. unsigned int writedir)
  3785. {
  3786. struct beiscsi_io_task *io_task = task->dd_data;
  3787. struct iscsi_conn *conn = task->conn;
  3788. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3789. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3790. struct iscsi_wrb *pwrb = NULL;
  3791. unsigned int doorbell = 0;
  3792. pwrb = io_task->pwrb_handle->pwrb;
  3793. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3794. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3795. if (writedir) {
  3796. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3797. INI_WR_CMD);
  3798. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3799. } else {
  3800. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3801. INI_RD_CMD);
  3802. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3803. }
  3804. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3805. cpu_to_be16(*(unsigned short *)
  3806. &io_task->cmd_bhs->iscsi_hdr.lun));
  3807. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3808. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3809. io_task->pwrb_handle->wrb_index);
  3810. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3811. be32_to_cpu(task->cmdsn));
  3812. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3813. io_task->psgl_handle->sgl_index);
  3814. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3815. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3816. io_task->pwrb_handle->nxt_wrb_index);
  3817. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3818. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3819. doorbell |= (io_task->pwrb_handle->wrb_index &
  3820. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3821. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3822. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3823. return 0;
  3824. }
  3825. static int beiscsi_mtask(struct iscsi_task *task)
  3826. {
  3827. struct beiscsi_io_task *io_task = task->dd_data;
  3828. struct iscsi_conn *conn = task->conn;
  3829. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3830. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3831. struct iscsi_wrb *pwrb = NULL;
  3832. unsigned int doorbell = 0;
  3833. unsigned int cid;
  3834. cid = beiscsi_conn->beiscsi_conn_cid;
  3835. pwrb = io_task->pwrb_handle->pwrb;
  3836. memset(pwrb, 0, sizeof(*pwrb));
  3837. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3838. be32_to_cpu(task->cmdsn));
  3839. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3840. io_task->pwrb_handle->wrb_index);
  3841. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3842. io_task->psgl_handle->sgl_index);
  3843. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  3844. case ISCSI_OP_LOGIN:
  3845. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3846. TGT_DM_CMD);
  3847. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3848. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  3849. hwi_write_buffer(pwrb, task);
  3850. break;
  3851. case ISCSI_OP_NOOP_OUT:
  3852. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  3853. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3854. TGT_DM_CMD);
  3855. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
  3856. pwrb, 0);
  3857. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
  3858. } else {
  3859. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3860. INI_RD_CMD);
  3861. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3862. }
  3863. hwi_write_buffer(pwrb, task);
  3864. break;
  3865. case ISCSI_OP_TEXT:
  3866. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3867. TGT_DM_CMD);
  3868. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3869. hwi_write_buffer(pwrb, task);
  3870. break;
  3871. case ISCSI_OP_SCSI_TMFUNC:
  3872. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3873. INI_TMF_CMD);
  3874. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3875. hwi_write_buffer(pwrb, task);
  3876. break;
  3877. case ISCSI_OP_LOGOUT:
  3878. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3879. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3880. HWH_TYPE_LOGOUT);
  3881. hwi_write_buffer(pwrb, task);
  3882. break;
  3883. default:
  3884. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3885. "BM_%d : opcode =%d Not supported\n",
  3886. task->hdr->opcode & ISCSI_OPCODE_MASK);
  3887. return -EINVAL;
  3888. }
  3889. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  3890. task->data_count);
  3891. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3892. io_task->pwrb_handle->nxt_wrb_index);
  3893. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3894. doorbell |= cid & DB_WRB_POST_CID_MASK;
  3895. doorbell |= (io_task->pwrb_handle->wrb_index &
  3896. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3897. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3898. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3899. return 0;
  3900. }
  3901. static int beiscsi_task_xmit(struct iscsi_task *task)
  3902. {
  3903. struct beiscsi_io_task *io_task = task->dd_data;
  3904. struct scsi_cmnd *sc = task->sc;
  3905. struct scatterlist *sg;
  3906. int num_sg;
  3907. unsigned int writedir = 0, xferlen = 0;
  3908. if (!sc)
  3909. return beiscsi_mtask(task);
  3910. io_task->scsi_cmnd = sc;
  3911. num_sg = scsi_dma_map(sc);
  3912. if (num_sg < 0) {
  3913. struct iscsi_conn *conn = task->conn;
  3914. struct beiscsi_hba *phba = NULL;
  3915. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  3916. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  3917. "BM_%d : scsi_dma_map Failed\n");
  3918. return num_sg;
  3919. }
  3920. xferlen = scsi_bufflen(sc);
  3921. sg = scsi_sglist(sc);
  3922. if (sc->sc_data_direction == DMA_TO_DEVICE)
  3923. writedir = 1;
  3924. else
  3925. writedir = 0;
  3926. return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
  3927. }
  3928. /**
  3929. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  3930. * @job: job to handle
  3931. */
  3932. static int beiscsi_bsg_request(struct bsg_job *job)
  3933. {
  3934. struct Scsi_Host *shost;
  3935. struct beiscsi_hba *phba;
  3936. struct iscsi_bsg_request *bsg_req = job->request;
  3937. int rc = -EINVAL;
  3938. unsigned int tag;
  3939. struct be_dma_mem nonemb_cmd;
  3940. struct be_cmd_resp_hdr *resp;
  3941. struct iscsi_bsg_reply *bsg_reply = job->reply;
  3942. unsigned short status, extd_status;
  3943. shost = iscsi_job_to_shost(job);
  3944. phba = iscsi_host_priv(shost);
  3945. switch (bsg_req->msgcode) {
  3946. case ISCSI_BSG_HST_VENDOR:
  3947. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3948. job->request_payload.payload_len,
  3949. &nonemb_cmd.dma);
  3950. if (nonemb_cmd.va == NULL) {
  3951. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3952. "BM_%d : Failed to allocate memory for "
  3953. "beiscsi_bsg_request\n");
  3954. return -ENOMEM;
  3955. }
  3956. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  3957. &nonemb_cmd);
  3958. if (!tag) {
  3959. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3960. "BM_%d : MBX Tag Allocation Failed\n");
  3961. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3962. nonemb_cmd.va, nonemb_cmd.dma);
  3963. return -EAGAIN;
  3964. } else
  3965. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3966. phba->ctrl.mcc_numtag[tag]);
  3967. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3968. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3969. free_mcc_tag(&phba->ctrl, tag);
  3970. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  3971. sg_copy_from_buffer(job->reply_payload.sg_list,
  3972. job->reply_payload.sg_cnt,
  3973. nonemb_cmd.va, (resp->response_length
  3974. + sizeof(*resp)));
  3975. bsg_reply->reply_payload_rcv_len = resp->response_length;
  3976. bsg_reply->result = status;
  3977. bsg_job_done(job, bsg_reply->result,
  3978. bsg_reply->reply_payload_rcv_len);
  3979. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3980. nonemb_cmd.va, nonemb_cmd.dma);
  3981. if (status || extd_status) {
  3982. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3983. "BM_%d : MBX Cmd Failed"
  3984. " status = %d extd_status = %d\n",
  3985. status, extd_status);
  3986. return -EIO;
  3987. } else {
  3988. rc = 0;
  3989. }
  3990. break;
  3991. default:
  3992. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3993. "BM_%d : Unsupported bsg command: 0x%x\n",
  3994. bsg_req->msgcode);
  3995. break;
  3996. }
  3997. return rc;
  3998. }
  3999. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  4000. {
  4001. /* Set the logging parameter */
  4002. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  4003. }
  4004. /*
  4005. * beiscsi_quiesce()- Cleanup Driver resources
  4006. * @phba: Instance Priv structure
  4007. *
  4008. * Free the OS and HW resources held by the driver
  4009. **/
  4010. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  4011. {
  4012. struct hwi_controller *phwi_ctrlr;
  4013. struct hwi_context_memory *phwi_context;
  4014. struct be_eq_obj *pbe_eq;
  4015. unsigned int i, msix_vec;
  4016. phwi_ctrlr = phba->phwi_ctrlr;
  4017. phwi_context = phwi_ctrlr->phwi_ctxt;
  4018. hwi_disable_intr(phba);
  4019. if (phba->msix_enabled) {
  4020. for (i = 0; i <= phba->num_cpus; i++) {
  4021. msix_vec = phba->msix_entries[i].vector;
  4022. free_irq(msix_vec, &phwi_context->be_eq[i]);
  4023. kfree(phba->msi_name[i]);
  4024. }
  4025. } else
  4026. if (phba->pcidev->irq)
  4027. free_irq(phba->pcidev->irq, phba);
  4028. pci_disable_msix(phba->pcidev);
  4029. destroy_workqueue(phba->wq);
  4030. if (blk_iopoll_enabled)
  4031. for (i = 0; i < phba->num_cpus; i++) {
  4032. pbe_eq = &phwi_context->be_eq[i];
  4033. blk_iopoll_disable(&pbe_eq->iopoll);
  4034. }
  4035. beiscsi_clean_port(phba);
  4036. beiscsi_free_mem(phba);
  4037. beiscsi_unmap_pci_function(phba);
  4038. pci_free_consistent(phba->pcidev,
  4039. phba->ctrl.mbox_mem_alloced.size,
  4040. phba->ctrl.mbox_mem_alloced.va,
  4041. phba->ctrl.mbox_mem_alloced.dma);
  4042. }
  4043. static void beiscsi_remove(struct pci_dev *pcidev)
  4044. {
  4045. struct beiscsi_hba *phba = NULL;
  4046. phba = pci_get_drvdata(pcidev);
  4047. if (!phba) {
  4048. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4049. return;
  4050. }
  4051. beiscsi_destroy_def_ifaces(phba);
  4052. beiscsi_quiesce(phba);
  4053. iscsi_boot_destroy_kset(phba->boot_kset);
  4054. iscsi_host_remove(phba->shost);
  4055. pci_dev_put(phba->pcidev);
  4056. iscsi_host_free(phba->shost);
  4057. pci_disable_device(pcidev);
  4058. }
  4059. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4060. {
  4061. struct beiscsi_hba *phba = NULL;
  4062. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4063. if (!phba) {
  4064. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4065. return;
  4066. }
  4067. beiscsi_quiesce(phba);
  4068. pci_disable_device(pcidev);
  4069. }
  4070. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4071. {
  4072. int i, status;
  4073. for (i = 0; i <= phba->num_cpus; i++)
  4074. phba->msix_entries[i].entry = i;
  4075. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4076. (phba->num_cpus + 1));
  4077. if (!status)
  4078. phba->msix_enabled = true;
  4079. return;
  4080. }
  4081. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  4082. const struct pci_device_id *id)
  4083. {
  4084. struct beiscsi_hba *phba = NULL;
  4085. struct hwi_controller *phwi_ctrlr;
  4086. struct hwi_context_memory *phwi_context;
  4087. struct be_eq_obj *pbe_eq;
  4088. int ret, i;
  4089. ret = beiscsi_enable_pci(pcidev);
  4090. if (ret < 0) {
  4091. dev_err(&pcidev->dev,
  4092. "beiscsi_dev_probe - Failed to enable pci device\n");
  4093. return ret;
  4094. }
  4095. phba = beiscsi_hba_alloc(pcidev);
  4096. if (!phba) {
  4097. dev_err(&pcidev->dev,
  4098. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4099. goto disable_pci;
  4100. }
  4101. /* Initialize Driver configuration Paramters */
  4102. beiscsi_hba_attrs_init(phba);
  4103. switch (pcidev->device) {
  4104. case BE_DEVICE_ID1:
  4105. case OC_DEVICE_ID1:
  4106. case OC_DEVICE_ID2:
  4107. phba->generation = BE_GEN2;
  4108. break;
  4109. case BE_DEVICE_ID2:
  4110. case OC_DEVICE_ID3:
  4111. phba->generation = BE_GEN3;
  4112. break;
  4113. case OC_SKH_ID1:
  4114. phba->generation = BE_GEN4;
  4115. default:
  4116. phba->generation = 0;
  4117. }
  4118. if (enable_msix)
  4119. find_num_cpus(phba);
  4120. else
  4121. phba->num_cpus = 1;
  4122. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4123. "BM_%d : num_cpus = %d\n",
  4124. phba->num_cpus);
  4125. if (enable_msix) {
  4126. beiscsi_msix_enable(phba);
  4127. if (!phba->msix_enabled)
  4128. phba->num_cpus = 1;
  4129. }
  4130. ret = be_ctrl_init(phba, pcidev);
  4131. if (ret) {
  4132. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4133. "BM_%d : beiscsi_dev_probe-"
  4134. "Failed in be_ctrl_init\n");
  4135. goto hba_free;
  4136. }
  4137. ret = beiscsi_cmd_reset_function(phba);
  4138. if (ret) {
  4139. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4140. "BM_%d : Reset Failed. Aborting Crashdump\n");
  4141. goto hba_free;
  4142. }
  4143. ret = be_chk_reset_complete(phba);
  4144. if (ret) {
  4145. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4146. "BM_%d : Failed to get out of reset."
  4147. "Aborting Crashdump\n");
  4148. goto hba_free;
  4149. }
  4150. spin_lock_init(&phba->io_sgl_lock);
  4151. spin_lock_init(&phba->mgmt_sgl_lock);
  4152. spin_lock_init(&phba->isr_lock);
  4153. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4154. if (ret != 0) {
  4155. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4156. "BM_%d : Error getting fw config\n");
  4157. goto free_port;
  4158. }
  4159. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  4160. beiscsi_get_params(phba);
  4161. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4162. ret = beiscsi_init_port(phba);
  4163. if (ret < 0) {
  4164. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4165. "BM_%d : beiscsi_dev_probe-"
  4166. "Failed in beiscsi_init_port\n");
  4167. goto free_port;
  4168. }
  4169. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4170. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4171. phba->ctrl.mcc_tag[i] = i + 1;
  4172. phba->ctrl.mcc_numtag[i + 1] = 0;
  4173. phba->ctrl.mcc_tag_available++;
  4174. }
  4175. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4176. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
  4177. phba->shost->host_no);
  4178. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  4179. if (!phba->wq) {
  4180. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4181. "BM_%d : beiscsi_dev_probe-"
  4182. "Failed to allocate work queue\n");
  4183. goto free_twq;
  4184. }
  4185. phwi_ctrlr = phba->phwi_ctrlr;
  4186. phwi_context = phwi_ctrlr->phwi_ctxt;
  4187. if (blk_iopoll_enabled) {
  4188. for (i = 0; i < phba->num_cpus; i++) {
  4189. pbe_eq = &phwi_context->be_eq[i];
  4190. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4191. be_iopoll);
  4192. blk_iopoll_enable(&pbe_eq->iopoll);
  4193. }
  4194. i = (phba->msix_enabled) ? i : 0;
  4195. /* Work item for MCC handling */
  4196. pbe_eq = &phwi_context->be_eq[i];
  4197. INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
  4198. } else {
  4199. if (phba->msix_enabled) {
  4200. for (i = 0; i <= phba->num_cpus; i++) {
  4201. pbe_eq = &phwi_context->be_eq[i];
  4202. INIT_WORK(&pbe_eq->work_cqs,
  4203. beiscsi_process_all_cqs);
  4204. }
  4205. } else {
  4206. pbe_eq = &phwi_context->be_eq[0];
  4207. INIT_WORK(&pbe_eq->work_cqs,
  4208. beiscsi_process_all_cqs);
  4209. }
  4210. }
  4211. ret = beiscsi_init_irqs(phba);
  4212. if (ret < 0) {
  4213. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4214. "BM_%d : beiscsi_dev_probe-"
  4215. "Failed to beiscsi_init_irqs\n");
  4216. goto free_blkenbld;
  4217. }
  4218. hwi_enable_intr(phba);
  4219. if (beiscsi_setup_boot_info(phba))
  4220. /*
  4221. * log error but continue, because we may not be using
  4222. * iscsi boot.
  4223. */
  4224. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4225. "BM_%d : Could not set up "
  4226. "iSCSI boot info.\n");
  4227. beiscsi_create_def_ifaces(phba);
  4228. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4229. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4230. return 0;
  4231. free_blkenbld:
  4232. destroy_workqueue(phba->wq);
  4233. if (blk_iopoll_enabled)
  4234. for (i = 0; i < phba->num_cpus; i++) {
  4235. pbe_eq = &phwi_context->be_eq[i];
  4236. blk_iopoll_disable(&pbe_eq->iopoll);
  4237. }
  4238. free_twq:
  4239. beiscsi_clean_port(phba);
  4240. beiscsi_free_mem(phba);
  4241. free_port:
  4242. pci_free_consistent(phba->pcidev,
  4243. phba->ctrl.mbox_mem_alloced.size,
  4244. phba->ctrl.mbox_mem_alloced.va,
  4245. phba->ctrl.mbox_mem_alloced.dma);
  4246. beiscsi_unmap_pci_function(phba);
  4247. hba_free:
  4248. if (phba->msix_enabled)
  4249. pci_disable_msix(phba->pcidev);
  4250. iscsi_host_remove(phba->shost);
  4251. pci_dev_put(phba->pcidev);
  4252. iscsi_host_free(phba->shost);
  4253. disable_pci:
  4254. pci_disable_device(pcidev);
  4255. return ret;
  4256. }
  4257. struct iscsi_transport beiscsi_iscsi_transport = {
  4258. .owner = THIS_MODULE,
  4259. .name = DRV_NAME,
  4260. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4261. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4262. .create_session = beiscsi_session_create,
  4263. .destroy_session = beiscsi_session_destroy,
  4264. .create_conn = beiscsi_conn_create,
  4265. .bind_conn = beiscsi_conn_bind,
  4266. .destroy_conn = iscsi_conn_teardown,
  4267. .attr_is_visible = be2iscsi_attr_is_visible,
  4268. .set_iface_param = be2iscsi_iface_set_param,
  4269. .get_iface_param = be2iscsi_iface_get_param,
  4270. .set_param = beiscsi_set_param,
  4271. .get_conn_param = iscsi_conn_get_param,
  4272. .get_session_param = iscsi_session_get_param,
  4273. .get_host_param = beiscsi_get_host_param,
  4274. .start_conn = beiscsi_conn_start,
  4275. .stop_conn = iscsi_conn_stop,
  4276. .send_pdu = iscsi_conn_send_pdu,
  4277. .xmit_task = beiscsi_task_xmit,
  4278. .cleanup_task = beiscsi_cleanup_task,
  4279. .alloc_pdu = beiscsi_alloc_pdu,
  4280. .parse_pdu_itt = beiscsi_parse_pdu,
  4281. .get_stats = beiscsi_conn_get_stats,
  4282. .get_ep_param = beiscsi_ep_get_param,
  4283. .ep_connect = beiscsi_ep_connect,
  4284. .ep_poll = beiscsi_ep_poll,
  4285. .ep_disconnect = beiscsi_ep_disconnect,
  4286. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4287. .bsg_request = beiscsi_bsg_request,
  4288. };
  4289. static struct pci_driver beiscsi_pci_driver = {
  4290. .name = DRV_NAME,
  4291. .probe = beiscsi_dev_probe,
  4292. .remove = beiscsi_remove,
  4293. .shutdown = beiscsi_shutdown,
  4294. .id_table = beiscsi_pci_id_table
  4295. };
  4296. static int __init beiscsi_module_init(void)
  4297. {
  4298. int ret;
  4299. beiscsi_scsi_transport =
  4300. iscsi_register_transport(&beiscsi_iscsi_transport);
  4301. if (!beiscsi_scsi_transport) {
  4302. printk(KERN_ERR
  4303. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4304. return -ENOMEM;
  4305. }
  4306. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4307. &beiscsi_iscsi_transport);
  4308. ret = pci_register_driver(&beiscsi_pci_driver);
  4309. if (ret) {
  4310. printk(KERN_ERR
  4311. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4312. goto unregister_iscsi_transport;
  4313. }
  4314. return 0;
  4315. unregister_iscsi_transport:
  4316. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4317. return ret;
  4318. }
  4319. static void __exit beiscsi_module_exit(void)
  4320. {
  4321. pci_unregister_driver(&beiscsi_pci_driver);
  4322. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4323. }
  4324. module_init(beiscsi_module_init);
  4325. module_exit(beiscsi_module_exit);