uhci-q.c 36 KB

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  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2005 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. static void uhci_free_pending_tds(struct uhci_hcd *uhci);
  19. /*
  20. * Technically, updating td->status here is a race, but it's not really a
  21. * problem. The worst that can happen is that we set the IOC bit again
  22. * generating a spurious interrupt. We could fix this by creating another
  23. * QH and leaving the IOC bit always set, but then we would have to play
  24. * games with the FSBR code to make sure we get the correct order in all
  25. * the cases. I don't think it's worth the effort
  26. */
  27. static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  28. {
  29. if (uhci->is_stopped)
  30. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  31. uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
  32. }
  33. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  34. {
  35. uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
  36. }
  37. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  38. {
  39. dma_addr_t dma_handle;
  40. struct uhci_td *td;
  41. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  42. if (!td)
  43. return NULL;
  44. td->dma_handle = dma_handle;
  45. td->frame = -1;
  46. INIT_LIST_HEAD(&td->list);
  47. INIT_LIST_HEAD(&td->remove_list);
  48. INIT_LIST_HEAD(&td->fl_list);
  49. return td;
  50. }
  51. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  52. {
  53. if (!list_empty(&td->list))
  54. dev_warn(uhci_dev(uhci), "td %p still in list!\n", td);
  55. if (!list_empty(&td->remove_list))
  56. dev_warn(uhci_dev(uhci), "td %p still in remove_list!\n", td);
  57. if (!list_empty(&td->fl_list))
  58. dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  59. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  60. }
  61. static inline void uhci_fill_td(struct uhci_td *td, u32 status,
  62. u32 token, u32 buffer)
  63. {
  64. td->status = cpu_to_le32(status);
  65. td->token = cpu_to_le32(token);
  66. td->buffer = cpu_to_le32(buffer);
  67. }
  68. /*
  69. * We insert Isochronous URBs directly into the frame list at the beginning
  70. */
  71. static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
  72. struct uhci_td *td, unsigned framenum)
  73. {
  74. framenum &= (UHCI_NUMFRAMES - 1);
  75. td->frame = framenum;
  76. /* Is there a TD already mapped there? */
  77. if (uhci->frame_cpu[framenum]) {
  78. struct uhci_td *ftd, *ltd;
  79. ftd = uhci->frame_cpu[framenum];
  80. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  81. list_add_tail(&td->fl_list, &ftd->fl_list);
  82. td->link = ltd->link;
  83. wmb();
  84. ltd->link = cpu_to_le32(td->dma_handle);
  85. } else {
  86. td->link = uhci->frame[framenum];
  87. wmb();
  88. uhci->frame[framenum] = cpu_to_le32(td->dma_handle);
  89. uhci->frame_cpu[framenum] = td;
  90. }
  91. }
  92. static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
  93. struct uhci_td *td)
  94. {
  95. /* If it's not inserted, don't remove it */
  96. if (td->frame == -1) {
  97. WARN_ON(!list_empty(&td->fl_list));
  98. return;
  99. }
  100. if (uhci->frame_cpu[td->frame] == td) {
  101. if (list_empty(&td->fl_list)) {
  102. uhci->frame[td->frame] = td->link;
  103. uhci->frame_cpu[td->frame] = NULL;
  104. } else {
  105. struct uhci_td *ntd;
  106. ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
  107. uhci->frame[td->frame] = cpu_to_le32(ntd->dma_handle);
  108. uhci->frame_cpu[td->frame] = ntd;
  109. }
  110. } else {
  111. struct uhci_td *ptd;
  112. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  113. ptd->link = td->link;
  114. }
  115. list_del_init(&td->fl_list);
  116. td->frame = -1;
  117. }
  118. /*
  119. * Remove all the TDs for an Isochronous URB from the frame list
  120. */
  121. static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
  122. {
  123. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  124. struct uhci_td *td;
  125. list_for_each_entry(td, &urbp->td_list, list)
  126. uhci_remove_td_from_frame_list(uhci, td);
  127. wmb();
  128. }
  129. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
  130. struct usb_device *udev, struct usb_host_endpoint *hep)
  131. {
  132. dma_addr_t dma_handle;
  133. struct uhci_qh *qh;
  134. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  135. if (!qh)
  136. return NULL;
  137. qh->dma_handle = dma_handle;
  138. qh->element = UHCI_PTR_TERM;
  139. qh->link = UHCI_PTR_TERM;
  140. INIT_LIST_HEAD(&qh->queue);
  141. INIT_LIST_HEAD(&qh->node);
  142. if (udev) { /* Normal QH */
  143. qh->dummy_td = uhci_alloc_td(uhci);
  144. if (!qh->dummy_td) {
  145. dma_pool_free(uhci->qh_pool, qh, dma_handle);
  146. return NULL;
  147. }
  148. qh->state = QH_STATE_IDLE;
  149. qh->hep = hep;
  150. qh->udev = udev;
  151. hep->hcpriv = qh;
  152. usb_get_dev(udev);
  153. } else { /* Skeleton QH */
  154. qh->state = QH_STATE_ACTIVE;
  155. qh->udev = NULL;
  156. }
  157. return qh;
  158. }
  159. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  160. {
  161. WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
  162. if (!list_empty(&qh->queue))
  163. dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  164. list_del(&qh->node);
  165. if (qh->udev) {
  166. qh->hep->hcpriv = NULL;
  167. usb_put_dev(qh->udev);
  168. uhci_free_td(uhci, qh->dummy_td);
  169. }
  170. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  171. }
  172. /*
  173. * When the currently executing URB is dequeued, save its current toggle value
  174. */
  175. static void uhci_save_toggle(struct uhci_qh *qh, struct urb *urb)
  176. {
  177. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  178. struct uhci_td *td;
  179. /* If the QH element pointer is UHCI_PTR_TERM then then currently
  180. * executing URB has already been unlinked, so this one isn't it. */
  181. if (qh_element(qh) == UHCI_PTR_TERM ||
  182. qh->queue.next != &urbp->node)
  183. return;
  184. qh->element = UHCI_PTR_TERM;
  185. /* Only bulk and interrupt pipes have to worry about toggles */
  186. if (!(usb_pipetype(urb->pipe) == PIPE_BULK ||
  187. usb_pipetype(urb->pipe) == PIPE_INTERRUPT))
  188. return;
  189. /* Find the first active TD; that's the device's toggle state */
  190. list_for_each_entry(td, &urbp->td_list, list) {
  191. if (td_status(td) & TD_CTRL_ACTIVE) {
  192. qh->needs_fixup = 1;
  193. qh->initial_toggle = uhci_toggle(td_token(td));
  194. return;
  195. }
  196. }
  197. WARN_ON(1);
  198. }
  199. /*
  200. * Fix up the data toggles for URBs in a queue, when one of them
  201. * terminates early (short transfer, error, or dequeued).
  202. */
  203. static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
  204. {
  205. struct urb_priv *urbp = NULL;
  206. struct uhci_td *td;
  207. unsigned int toggle = qh->initial_toggle;
  208. unsigned int pipe;
  209. /* Fixups for a short transfer start with the second URB in the
  210. * queue (the short URB is the first). */
  211. if (skip_first)
  212. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  213. /* When starting with the first URB, if the QH element pointer is
  214. * still valid then we know the URB's toggles are okay. */
  215. else if (qh_element(qh) != UHCI_PTR_TERM)
  216. toggle = 2;
  217. /* Fix up the toggle for the URBs in the queue. Normally this
  218. * loop won't run more than once: When an error or short transfer
  219. * occurs, the queue usually gets emptied. */
  220. urbp = list_prepare_entry(urbp, &qh->queue, node);
  221. list_for_each_entry_continue(urbp, &qh->queue, node) {
  222. /* If the first TD has the right toggle value, we don't
  223. * need to change any toggles in this URB */
  224. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  225. if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
  226. td = list_entry(urbp->td_list.next, struct uhci_td,
  227. list);
  228. toggle = uhci_toggle(td_token(td)) ^ 1;
  229. /* Otherwise all the toggles in the URB have to be switched */
  230. } else {
  231. list_for_each_entry(td, &urbp->td_list, list) {
  232. td->token ^= __constant_cpu_to_le32(
  233. TD_TOKEN_TOGGLE);
  234. toggle ^= 1;
  235. }
  236. }
  237. }
  238. wmb();
  239. pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
  240. usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
  241. usb_pipeout(pipe), toggle);
  242. qh->needs_fixup = 0;
  243. }
  244. /*
  245. * Put a QH on the schedule in both hardware and software
  246. */
  247. static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  248. {
  249. struct uhci_qh *pqh;
  250. WARN_ON(list_empty(&qh->queue));
  251. /* Set the element pointer if it isn't set already.
  252. * This isn't needed for Isochronous queues, but it doesn't hurt. */
  253. if (qh_element(qh) == UHCI_PTR_TERM) {
  254. struct urb_priv *urbp = list_entry(qh->queue.next,
  255. struct urb_priv, node);
  256. struct uhci_td *td = list_entry(urbp->td_list.next,
  257. struct uhci_td, list);
  258. qh->element = cpu_to_le32(td->dma_handle);
  259. }
  260. if (qh->state == QH_STATE_ACTIVE)
  261. return;
  262. qh->state = QH_STATE_ACTIVE;
  263. /* Move the QH from its old list to the end of the appropriate
  264. * skeleton's list */
  265. if (qh == uhci->next_qh)
  266. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  267. node);
  268. list_move_tail(&qh->node, &qh->skel->node);
  269. /* Link it into the schedule */
  270. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  271. qh->link = pqh->link;
  272. wmb();
  273. pqh->link = UHCI_PTR_QH | cpu_to_le32(qh->dma_handle);
  274. }
  275. /*
  276. * Take a QH off the hardware schedule
  277. */
  278. static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  279. {
  280. struct uhci_qh *pqh;
  281. if (qh->state == QH_STATE_UNLINKING)
  282. return;
  283. WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
  284. qh->state = QH_STATE_UNLINKING;
  285. /* Unlink the QH from the schedule and record when we did it */
  286. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  287. pqh->link = qh->link;
  288. mb();
  289. uhci_get_current_frame_number(uhci);
  290. qh->unlink_frame = uhci->frame_number;
  291. /* Force an interrupt so we know when the QH is fully unlinked */
  292. if (list_empty(&uhci->skel_unlink_qh->node))
  293. uhci_set_next_interrupt(uhci);
  294. /* Move the QH from its old list to the end of the unlinking list */
  295. if (qh == uhci->next_qh)
  296. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  297. node);
  298. list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
  299. }
  300. /*
  301. * When we and the controller are through with a QH, it becomes IDLE.
  302. * This happens when a QH has been off the schedule (on the unlinking
  303. * list) for more than one frame, or when an error occurs while adding
  304. * the first URB onto a new QH.
  305. */
  306. static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
  307. {
  308. WARN_ON(qh->state == QH_STATE_ACTIVE);
  309. if (qh == uhci->next_qh)
  310. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  311. node);
  312. list_move(&qh->node, &uhci->idle_qh_list);
  313. qh->state = QH_STATE_IDLE;
  314. /* If anyone is waiting for a QH to become idle, wake them up */
  315. if (uhci->num_waiting)
  316. wake_up_all(&uhci->waitqh);
  317. }
  318. static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
  319. struct urb *urb)
  320. {
  321. struct urb_priv *urbp;
  322. urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC);
  323. if (!urbp)
  324. return NULL;
  325. memset((void *)urbp, 0, sizeof(*urbp));
  326. urbp->urb = urb;
  327. urb->hcpriv = urbp;
  328. INIT_LIST_HEAD(&urbp->node);
  329. INIT_LIST_HEAD(&urbp->td_list);
  330. return urbp;
  331. }
  332. static void uhci_add_td_to_urb(struct urb *urb, struct uhci_td *td)
  333. {
  334. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  335. list_add_tail(&td->list, &urbp->td_list);
  336. }
  337. static void uhci_remove_td_from_urb(struct uhci_td *td)
  338. {
  339. if (list_empty(&td->list))
  340. return;
  341. list_del_init(&td->list);
  342. }
  343. static void uhci_free_urb_priv(struct uhci_hcd *uhci,
  344. struct urb_priv *urbp)
  345. {
  346. struct uhci_td *td, *tmp;
  347. if (!list_empty(&urbp->node))
  348. dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n",
  349. urbp->urb);
  350. uhci_get_current_frame_number(uhci);
  351. if (uhci->frame_number + uhci->is_stopped != uhci->td_remove_age) {
  352. uhci_free_pending_tds(uhci);
  353. uhci->td_remove_age = uhci->frame_number;
  354. }
  355. /* Check to see if the remove list is empty. Set the IOC bit */
  356. /* to force an interrupt so we can remove the TDs. */
  357. if (list_empty(&uhci->td_remove_list))
  358. uhci_set_next_interrupt(uhci);
  359. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  360. uhci_remove_td_from_urb(td);
  361. list_add(&td->remove_list, &uhci->td_remove_list);
  362. }
  363. urbp->urb->hcpriv = NULL;
  364. kmem_cache_free(uhci_up_cachep, urbp);
  365. }
  366. static void uhci_inc_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  367. {
  368. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  369. if ((!(urb->transfer_flags & URB_NO_FSBR)) && !urbp->fsbr) {
  370. urbp->fsbr = 1;
  371. if (!uhci->fsbr++ && !uhci->fsbrtimeout)
  372. uhci->skel_term_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
  373. }
  374. }
  375. static void uhci_dec_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  376. {
  377. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  378. if ((!(urb->transfer_flags & URB_NO_FSBR)) && urbp->fsbr) {
  379. urbp->fsbr = 0;
  380. if (!--uhci->fsbr)
  381. uhci->fsbrtimeout = jiffies + FSBR_DELAY;
  382. }
  383. }
  384. /*
  385. * Map status to standard result codes
  386. *
  387. * <status> is (td_status(td) & 0xF60000), a.k.a.
  388. * uhci_status_bits(td_status(td)).
  389. * Note: <status> does not include the TD_CTRL_NAK bit.
  390. * <dir_out> is True for output TDs and False for input TDs.
  391. */
  392. static int uhci_map_status(int status, int dir_out)
  393. {
  394. if (!status)
  395. return 0;
  396. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  397. return -EPROTO;
  398. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  399. if (dir_out)
  400. return -EPROTO;
  401. else
  402. return -EILSEQ;
  403. }
  404. if (status & TD_CTRL_BABBLE) /* Babble */
  405. return -EOVERFLOW;
  406. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  407. return -ENOSR;
  408. if (status & TD_CTRL_STALLED) /* Stalled */
  409. return -EPIPE;
  410. WARN_ON(status & TD_CTRL_ACTIVE); /* Active */
  411. return 0;
  412. }
  413. /*
  414. * Control transfers
  415. */
  416. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
  417. struct uhci_qh *qh)
  418. {
  419. struct uhci_td *td;
  420. unsigned long destination, status;
  421. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  422. int len = urb->transfer_buffer_length;
  423. dma_addr_t data = urb->transfer_dma;
  424. __le32 *plink;
  425. /* The "pipe" thing contains the destination in bits 8--18 */
  426. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  427. /* 3 errors, dummy TD remains inactive */
  428. status = uhci_maxerr(3);
  429. if (urb->dev->speed == USB_SPEED_LOW)
  430. status |= TD_CTRL_LS;
  431. /*
  432. * Build the TD for the control request setup packet
  433. */
  434. td = qh->dummy_td;
  435. uhci_add_td_to_urb(urb, td);
  436. uhci_fill_td(td, status, destination | uhci_explen(8),
  437. urb->setup_dma);
  438. plink = &td->link;
  439. status |= TD_CTRL_ACTIVE;
  440. /*
  441. * If direction is "send", change the packet ID from SETUP (0x2D)
  442. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  443. * set Short Packet Detect (SPD) for all data packets.
  444. */
  445. if (usb_pipeout(urb->pipe))
  446. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  447. else {
  448. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  449. status |= TD_CTRL_SPD;
  450. }
  451. /*
  452. * Build the DATA TDs
  453. */
  454. while (len > 0) {
  455. int pktsze = min(len, maxsze);
  456. td = uhci_alloc_td(uhci);
  457. if (!td)
  458. goto nomem;
  459. *plink = cpu_to_le32(td->dma_handle);
  460. /* Alternate Data0/1 (start with Data1) */
  461. destination ^= TD_TOKEN_TOGGLE;
  462. uhci_add_td_to_urb(urb, td);
  463. uhci_fill_td(td, status, destination | uhci_explen(pktsze),
  464. data);
  465. plink = &td->link;
  466. data += pktsze;
  467. len -= pktsze;
  468. }
  469. /*
  470. * Build the final TD for control status
  471. */
  472. td = uhci_alloc_td(uhci);
  473. if (!td)
  474. goto nomem;
  475. *plink = cpu_to_le32(td->dma_handle);
  476. /*
  477. * It's IN if the pipe is an output pipe or we're not expecting
  478. * data back.
  479. */
  480. destination &= ~TD_TOKEN_PID_MASK;
  481. if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
  482. destination |= USB_PID_IN;
  483. else
  484. destination |= USB_PID_OUT;
  485. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  486. status &= ~TD_CTRL_SPD;
  487. uhci_add_td_to_urb(urb, td);
  488. uhci_fill_td(td, status | TD_CTRL_IOC,
  489. destination | uhci_explen(0), 0);
  490. plink = &td->link;
  491. /*
  492. * Build the new dummy TD and activate the old one
  493. */
  494. td = uhci_alloc_td(uhci);
  495. if (!td)
  496. goto nomem;
  497. *plink = cpu_to_le32(td->dma_handle);
  498. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  499. wmb();
  500. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  501. qh->dummy_td = td;
  502. /* Low-speed transfers get a different queue, and won't hog the bus.
  503. * Also, some devices enumerate better without FSBR; the easiest way
  504. * to do that is to put URBs on the low-speed queue while the device
  505. * isn't in the CONFIGURED state. */
  506. if (urb->dev->speed == USB_SPEED_LOW ||
  507. urb->dev->state != USB_STATE_CONFIGURED)
  508. qh->skel = uhci->skel_ls_control_qh;
  509. else {
  510. qh->skel = uhci->skel_fs_control_qh;
  511. uhci_inc_fsbr(uhci, urb);
  512. }
  513. return 0;
  514. nomem:
  515. /* Remove the dummy TD from the td_list so it doesn't get freed */
  516. uhci_remove_td_from_urb(qh->dummy_td);
  517. return -ENOMEM;
  518. }
  519. /*
  520. * If control-IN transfer was short, the status packet wasn't sent.
  521. * This routine changes the element pointer in the QH to point at the
  522. * status TD. It's safe to do this even while the QH is live, because
  523. * the hardware only updates the element pointer following a successful
  524. * transfer. The inactive TD for the short packet won't cause an update,
  525. * so the pointer won't get overwritten. The next time the controller
  526. * sees this QH, it will send the status packet.
  527. */
  528. static int usb_control_retrigger_status(struct uhci_hcd *uhci, struct urb *urb)
  529. {
  530. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  531. struct uhci_td *td;
  532. urbp->short_transfer = 1;
  533. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  534. urbp->qh->element = cpu_to_le32(td->dma_handle);
  535. return -EINPROGRESS;
  536. }
  537. static int uhci_result_control(struct uhci_hcd *uhci, struct urb *urb)
  538. {
  539. struct list_head *tmp, *head;
  540. struct urb_priv *urbp = urb->hcpriv;
  541. struct uhci_td *td;
  542. unsigned int status;
  543. int ret = 0;
  544. head = &urbp->td_list;
  545. if (urbp->short_transfer) {
  546. tmp = head->prev;
  547. goto status_stage;
  548. }
  549. urb->actual_length = 0;
  550. tmp = head->next;
  551. td = list_entry(tmp, struct uhci_td, list);
  552. /* The first TD is the SETUP stage, check the status, but skip */
  553. /* the count */
  554. status = uhci_status_bits(td_status(td));
  555. if (status & TD_CTRL_ACTIVE)
  556. return -EINPROGRESS;
  557. if (status)
  558. goto td_error;
  559. /* The rest of the TDs (but the last) are data */
  560. tmp = tmp->next;
  561. while (tmp != head && tmp->next != head) {
  562. unsigned int ctrlstat;
  563. td = list_entry(tmp, struct uhci_td, list);
  564. tmp = tmp->next;
  565. ctrlstat = td_status(td);
  566. status = uhci_status_bits(ctrlstat);
  567. if (status & TD_CTRL_ACTIVE)
  568. return -EINPROGRESS;
  569. urb->actual_length += uhci_actual_length(ctrlstat);
  570. if (status)
  571. goto td_error;
  572. /* Check to see if we received a short packet */
  573. if (uhci_actual_length(ctrlstat) <
  574. uhci_expected_length(td_token(td))) {
  575. if (urb->transfer_flags & URB_SHORT_NOT_OK) {
  576. ret = -EREMOTEIO;
  577. goto err;
  578. }
  579. return usb_control_retrigger_status(uhci, urb);
  580. }
  581. }
  582. status_stage:
  583. td = list_entry(tmp, struct uhci_td, list);
  584. /* Control status stage */
  585. status = td_status(td);
  586. #ifdef I_HAVE_BUGGY_APC_BACKUPS
  587. /* APC BackUPS Pro kludge */
  588. /* It tries to send all of the descriptor instead of the amount */
  589. /* we requested */
  590. if (status & TD_CTRL_IOC && /* IOC is masked out by uhci_status_bits */
  591. status & TD_CTRL_ACTIVE &&
  592. status & TD_CTRL_NAK)
  593. return 0;
  594. #endif
  595. status = uhci_status_bits(status);
  596. if (status & TD_CTRL_ACTIVE)
  597. return -EINPROGRESS;
  598. if (status)
  599. goto td_error;
  600. return 0;
  601. td_error:
  602. ret = uhci_map_status(status, uhci_packetout(td_token(td)));
  603. err:
  604. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  605. /* Some debugging code */
  606. dev_dbg(uhci_dev(uhci), "%s: failed with status %x\n",
  607. __FUNCTION__, status);
  608. if (errbuf) {
  609. /* Print the chain for debugging purposes */
  610. uhci_show_qh(urbp->qh, errbuf, ERRBUF_LEN, 0);
  611. lprintk(errbuf);
  612. }
  613. }
  614. /* Note that the queue has stopped */
  615. urbp->qh->element = UHCI_PTR_TERM;
  616. urbp->qh->is_stopped = 1;
  617. return ret;
  618. }
  619. /*
  620. * Common submit for bulk and interrupt
  621. */
  622. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
  623. struct uhci_qh *qh)
  624. {
  625. struct uhci_td *td;
  626. unsigned long destination, status;
  627. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  628. int len = urb->transfer_buffer_length;
  629. dma_addr_t data = urb->transfer_dma;
  630. __le32 *plink;
  631. unsigned int toggle;
  632. if (len < 0)
  633. return -EINVAL;
  634. /* The "pipe" thing contains the destination in bits 8--18 */
  635. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  636. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  637. usb_pipeout(urb->pipe));
  638. /* 3 errors, dummy TD remains inactive */
  639. status = uhci_maxerr(3);
  640. if (urb->dev->speed == USB_SPEED_LOW)
  641. status |= TD_CTRL_LS;
  642. if (usb_pipein(urb->pipe))
  643. status |= TD_CTRL_SPD;
  644. /*
  645. * Build the DATA TDs
  646. */
  647. plink = NULL;
  648. td = qh->dummy_td;
  649. do { /* Allow zero length packets */
  650. int pktsze = maxsze;
  651. if (len <= pktsze) { /* The last packet */
  652. pktsze = len;
  653. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  654. status &= ~TD_CTRL_SPD;
  655. }
  656. if (plink) {
  657. td = uhci_alloc_td(uhci);
  658. if (!td)
  659. goto nomem;
  660. *plink = cpu_to_le32(td->dma_handle);
  661. }
  662. uhci_add_td_to_urb(urb, td);
  663. uhci_fill_td(td, status,
  664. destination | uhci_explen(pktsze) |
  665. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  666. data);
  667. plink = &td->link;
  668. status |= TD_CTRL_ACTIVE;
  669. data += pktsze;
  670. len -= maxsze;
  671. toggle ^= 1;
  672. } while (len > 0);
  673. /*
  674. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  675. * is OUT and the transfer_length was an exact multiple of maxsze,
  676. * hence (len = transfer_length - N * maxsze) == 0
  677. * however, if transfer_length == 0, the zero packet was already
  678. * prepared above.
  679. */
  680. if ((urb->transfer_flags & URB_ZERO_PACKET) &&
  681. usb_pipeout(urb->pipe) && len == 0 &&
  682. urb->transfer_buffer_length > 0) {
  683. td = uhci_alloc_td(uhci);
  684. if (!td)
  685. goto nomem;
  686. *plink = cpu_to_le32(td->dma_handle);
  687. uhci_add_td_to_urb(urb, td);
  688. uhci_fill_td(td, status,
  689. destination | uhci_explen(0) |
  690. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  691. data);
  692. plink = &td->link;
  693. toggle ^= 1;
  694. }
  695. /* Set the interrupt-on-completion flag on the last packet.
  696. * A more-or-less typical 4 KB URB (= size of one memory page)
  697. * will require about 3 ms to transfer; that's a little on the
  698. * fast side but not enough to justify delaying an interrupt
  699. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  700. * flag setting. */
  701. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  702. /*
  703. * Build the new dummy TD and activate the old one
  704. */
  705. td = uhci_alloc_td(uhci);
  706. if (!td)
  707. goto nomem;
  708. *plink = cpu_to_le32(td->dma_handle);
  709. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  710. wmb();
  711. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  712. qh->dummy_td = td;
  713. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  714. usb_pipeout(urb->pipe), toggle);
  715. return 0;
  716. nomem:
  717. /* Remove the dummy TD from the td_list so it doesn't get freed */
  718. uhci_remove_td_from_urb(qh->dummy_td);
  719. return -ENOMEM;
  720. }
  721. /*
  722. * Common result for bulk and interrupt
  723. */
  724. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  725. {
  726. struct urb_priv *urbp = urb->hcpriv;
  727. struct uhci_td *td;
  728. unsigned int status = 0;
  729. int ret = 0;
  730. urb->actual_length = 0;
  731. list_for_each_entry(td, &urbp->td_list, list) {
  732. unsigned int ctrlstat = td_status(td);
  733. status = uhci_status_bits(ctrlstat);
  734. if (status & TD_CTRL_ACTIVE)
  735. return -EINPROGRESS;
  736. urb->actual_length += uhci_actual_length(ctrlstat);
  737. if (status)
  738. goto td_error;
  739. if (uhci_actual_length(ctrlstat) <
  740. uhci_expected_length(td_token(td))) {
  741. if (urb->transfer_flags & URB_SHORT_NOT_OK) {
  742. ret = -EREMOTEIO;
  743. goto err;
  744. }
  745. /*
  746. * This URB stopped short of its end. We have to
  747. * fix up the toggles of the following URBs on the
  748. * queue and restart the queue.
  749. *
  750. * Do this only the first time we encounter the
  751. * short URB.
  752. */
  753. if (!urbp->short_transfer) {
  754. urbp->short_transfer = 1;
  755. urbp->qh->initial_toggle =
  756. uhci_toggle(td_token(td)) ^ 1;
  757. uhci_fixup_toggles(urbp->qh, 1);
  758. td = list_entry(urbp->td_list.prev,
  759. struct uhci_td, list);
  760. urbp->qh->element = td->link;
  761. }
  762. break;
  763. }
  764. }
  765. return 0;
  766. td_error:
  767. ret = uhci_map_status(status, uhci_packetout(td_token(td)));
  768. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  769. /* Some debugging code */
  770. dev_dbg(uhci_dev(uhci), "%s: failed with status %x\n",
  771. __FUNCTION__, status);
  772. if (debug > 1 && errbuf) {
  773. /* Print the chain for debugging purposes */
  774. uhci_show_qh(urbp->qh, errbuf, ERRBUF_LEN, 0);
  775. lprintk(errbuf);
  776. }
  777. }
  778. err:
  779. /* Note that the queue has stopped and save the next toggle value */
  780. urbp->qh->element = UHCI_PTR_TERM;
  781. urbp->qh->is_stopped = 1;
  782. urbp->qh->needs_fixup = 1;
  783. urbp->qh->initial_toggle = uhci_toggle(td_token(td)) ^
  784. (ret == -EREMOTEIO);
  785. return ret;
  786. }
  787. static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
  788. struct uhci_qh *qh)
  789. {
  790. int ret;
  791. /* Can't have low-speed bulk transfers */
  792. if (urb->dev->speed == USB_SPEED_LOW)
  793. return -EINVAL;
  794. qh->skel = uhci->skel_bulk_qh;
  795. ret = uhci_submit_common(uhci, urb, qh);
  796. if (ret == 0)
  797. uhci_inc_fsbr(uhci, urb);
  798. return ret;
  799. }
  800. static inline int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
  801. struct uhci_qh *qh)
  802. {
  803. /* USB 1.1 interrupt transfers only involve one packet per interval.
  804. * Drivers can submit URBs of any length, but longer ones will need
  805. * multiple intervals to complete.
  806. */
  807. qh->skel = uhci->skelqh[__interval_to_skel(urb->interval)];
  808. return uhci_submit_common(uhci, urb, qh);
  809. }
  810. /*
  811. * Isochronous transfers
  812. */
  813. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
  814. struct uhci_qh *qh)
  815. {
  816. struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
  817. int i, frame;
  818. unsigned long destination, status;
  819. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  820. if (urb->number_of_packets > 900) /* 900? Why? */
  821. return -EFBIG;
  822. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  823. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  824. /* Figure out the starting frame number */
  825. if (urb->transfer_flags & URB_ISO_ASAP) {
  826. if (list_empty(&qh->queue)) {
  827. uhci_get_current_frame_number(uhci);
  828. urb->start_frame = (uhci->frame_number + 10);
  829. } else { /* Go right after the last one */
  830. struct urb *last_urb;
  831. last_urb = list_entry(qh->queue.prev,
  832. struct urb_priv, node)->urb;
  833. urb->start_frame = (last_urb->start_frame +
  834. last_urb->number_of_packets *
  835. last_urb->interval);
  836. }
  837. } else {
  838. /* FIXME: Sanity check */
  839. }
  840. urb->start_frame &= (UHCI_NUMFRAMES - 1);
  841. for (i = 0; i < urb->number_of_packets; i++) {
  842. td = uhci_alloc_td(uhci);
  843. if (!td)
  844. return -ENOMEM;
  845. uhci_add_td_to_urb(urb, td);
  846. uhci_fill_td(td, status, destination |
  847. uhci_explen(urb->iso_frame_desc[i].length),
  848. urb->transfer_dma +
  849. urb->iso_frame_desc[i].offset);
  850. }
  851. /* Set the interrupt-on-completion flag on the last packet. */
  852. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  853. qh->skel = uhci->skel_iso_qh;
  854. /* Add the TDs to the frame list */
  855. frame = urb->start_frame;
  856. list_for_each_entry(td, &urbp->td_list, list) {
  857. uhci_insert_td_in_frame_list(uhci, td, frame);
  858. frame += urb->interval;
  859. }
  860. return 0;
  861. }
  862. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  863. {
  864. struct uhci_td *td;
  865. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  866. int status;
  867. int i, ret = 0;
  868. urb->actual_length = urb->error_count = 0;
  869. i = 0;
  870. list_for_each_entry(td, &urbp->td_list, list) {
  871. int actlength;
  872. unsigned int ctrlstat = td_status(td);
  873. if (ctrlstat & TD_CTRL_ACTIVE)
  874. return -EINPROGRESS;
  875. actlength = uhci_actual_length(ctrlstat);
  876. urb->iso_frame_desc[i].actual_length = actlength;
  877. urb->actual_length += actlength;
  878. status = uhci_map_status(uhci_status_bits(ctrlstat),
  879. usb_pipeout(urb->pipe));
  880. urb->iso_frame_desc[i].status = status;
  881. if (status) {
  882. urb->error_count++;
  883. ret = status;
  884. }
  885. i++;
  886. }
  887. return ret;
  888. }
  889. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  890. struct usb_host_endpoint *hep,
  891. struct urb *urb, gfp_t mem_flags)
  892. {
  893. int ret;
  894. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  895. unsigned long flags;
  896. struct urb_priv *urbp;
  897. struct uhci_qh *qh;
  898. int bustime;
  899. spin_lock_irqsave(&uhci->lock, flags);
  900. ret = urb->status;
  901. if (ret != -EINPROGRESS) /* URB already unlinked! */
  902. goto done;
  903. ret = -ENOMEM;
  904. urbp = uhci_alloc_urb_priv(uhci, urb);
  905. if (!urbp)
  906. goto done;
  907. if (hep->hcpriv)
  908. qh = (struct uhci_qh *) hep->hcpriv;
  909. else {
  910. qh = uhci_alloc_qh(uhci, urb->dev, hep);
  911. if (!qh)
  912. goto err_no_qh;
  913. }
  914. urbp->qh = qh;
  915. switch (usb_pipetype(urb->pipe)) {
  916. case PIPE_CONTROL:
  917. ret = uhci_submit_control(uhci, urb, qh);
  918. break;
  919. case PIPE_BULK:
  920. ret = uhci_submit_bulk(uhci, urb, qh);
  921. break;
  922. case PIPE_INTERRUPT:
  923. if (list_empty(&qh->queue)) {
  924. bustime = usb_check_bandwidth(urb->dev, urb);
  925. if (bustime < 0)
  926. ret = bustime;
  927. else {
  928. ret = uhci_submit_interrupt(uhci, urb, qh);
  929. if (ret == 0)
  930. usb_claim_bandwidth(urb->dev, urb, bustime, 0);
  931. }
  932. } else { /* inherit from parent */
  933. struct urb_priv *eurbp;
  934. eurbp = list_entry(qh->queue.prev, struct urb_priv,
  935. node);
  936. urb->bandwidth = eurbp->urb->bandwidth;
  937. ret = uhci_submit_interrupt(uhci, urb, qh);
  938. }
  939. break;
  940. case PIPE_ISOCHRONOUS:
  941. bustime = usb_check_bandwidth(urb->dev, urb);
  942. if (bustime < 0) {
  943. ret = bustime;
  944. break;
  945. }
  946. ret = uhci_submit_isochronous(uhci, urb, qh);
  947. if (ret == 0)
  948. usb_claim_bandwidth(urb->dev, urb, bustime, 1);
  949. break;
  950. }
  951. if (ret != 0)
  952. goto err_submit_failed;
  953. /* Add this URB to the QH */
  954. urbp->qh = qh;
  955. list_add_tail(&urbp->node, &qh->queue);
  956. /* If the new URB is the first and only one on this QH then either
  957. * the QH is new and idle or else it's unlinked and waiting to
  958. * become idle, so we can activate it right away. */
  959. if (qh->queue.next == &urbp->node)
  960. uhci_activate_qh(uhci, qh);
  961. goto done;
  962. err_submit_failed:
  963. if (qh->state == QH_STATE_IDLE)
  964. uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
  965. err_no_qh:
  966. uhci_free_urb_priv(uhci, urbp);
  967. done:
  968. spin_unlock_irqrestore(&uhci->lock, flags);
  969. return ret;
  970. }
  971. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
  972. {
  973. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  974. unsigned long flags;
  975. struct urb_priv *urbp;
  976. spin_lock_irqsave(&uhci->lock, flags);
  977. urbp = urb->hcpriv;
  978. if (!urbp) /* URB was never linked! */
  979. goto done;
  980. /* Remove Isochronous TDs from the frame list ASAP */
  981. if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
  982. uhci_unlink_isochronous_tds(uhci, urb);
  983. uhci_unlink_qh(uhci, urbp->qh);
  984. done:
  985. spin_unlock_irqrestore(&uhci->lock, flags);
  986. return 0;
  987. }
  988. /*
  989. * Finish unlinking an URB and give it back
  990. */
  991. static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
  992. struct urb *urb, struct pt_regs *regs)
  993. __releases(uhci->lock)
  994. __acquires(uhci->lock)
  995. {
  996. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  997. /* Isochronous TDs get unlinked directly from the frame list */
  998. if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
  999. uhci_unlink_isochronous_tds(uhci, urb);
  1000. /* If the URB isn't first on its queue, adjust the link pointer
  1001. * of the last TD in the previous URB. */
  1002. else if (qh->queue.next != &urbp->node) {
  1003. struct urb_priv *purbp;
  1004. struct uhci_td *ptd, *ltd;
  1005. purbp = list_entry(urbp->node.prev, struct urb_priv, node);
  1006. ptd = list_entry(purbp->td_list.prev, struct uhci_td,
  1007. list);
  1008. ltd = list_entry(urbp->td_list.prev, struct uhci_td,
  1009. list);
  1010. ptd->link = ltd->link;
  1011. }
  1012. /* Take the URB off the QH's queue. If the queue is now empty,
  1013. * this is a perfect time for a toggle fixup. */
  1014. list_del_init(&urbp->node);
  1015. if (list_empty(&qh->queue) && qh->needs_fixup) {
  1016. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  1017. usb_pipeout(urb->pipe), qh->initial_toggle);
  1018. qh->needs_fixup = 0;
  1019. }
  1020. uhci_dec_fsbr(uhci, urb); /* Safe since it checks */
  1021. uhci_free_urb_priv(uhci, urbp);
  1022. switch (usb_pipetype(urb->pipe)) {
  1023. case PIPE_ISOCHRONOUS:
  1024. /* Release bandwidth for Interrupt or Isoc. transfers */
  1025. if (urb->bandwidth)
  1026. usb_release_bandwidth(urb->dev, urb, 1);
  1027. break;
  1028. case PIPE_INTERRUPT:
  1029. /* Release bandwidth for Interrupt or Isoc. transfers */
  1030. /* Make sure we don't release if we have a queued URB */
  1031. if (list_empty(&qh->queue) && urb->bandwidth)
  1032. usb_release_bandwidth(urb->dev, urb, 0);
  1033. else
  1034. /* bandwidth was passed on to queued URB, */
  1035. /* so don't let usb_unlink_urb() release it */
  1036. urb->bandwidth = 0;
  1037. break;
  1038. }
  1039. spin_unlock(&uhci->lock);
  1040. usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb, regs);
  1041. spin_lock(&uhci->lock);
  1042. /* If the queue is now empty, we can unlink the QH and give up its
  1043. * reserved bandwidth. */
  1044. if (list_empty(&qh->queue)) {
  1045. uhci_unlink_qh(uhci, qh);
  1046. /* Bandwidth stuff not yet implemented */
  1047. }
  1048. }
  1049. /*
  1050. * Scan the URBs in a QH's queue
  1051. */
  1052. #define QH_FINISHED_UNLINKING(qh) \
  1053. (qh->state == QH_STATE_UNLINKING && \
  1054. uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
  1055. static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh,
  1056. struct pt_regs *regs)
  1057. {
  1058. struct urb_priv *urbp;
  1059. struct urb *urb;
  1060. int status;
  1061. while (!list_empty(&qh->queue)) {
  1062. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1063. urb = urbp->urb;
  1064. switch (usb_pipetype(urb->pipe)) {
  1065. case PIPE_CONTROL:
  1066. status = uhci_result_control(uhci, urb);
  1067. break;
  1068. case PIPE_ISOCHRONOUS:
  1069. status = uhci_result_isochronous(uhci, urb);
  1070. break;
  1071. default: /* PIPE_BULK or PIPE_INTERRUPT */
  1072. status = uhci_result_common(uhci, urb);
  1073. break;
  1074. }
  1075. if (status == -EINPROGRESS)
  1076. break;
  1077. spin_lock(&urb->lock);
  1078. if (urb->status == -EINPROGRESS) /* Not dequeued */
  1079. urb->status = status;
  1080. else
  1081. status = -ECONNRESET;
  1082. spin_unlock(&urb->lock);
  1083. /* Dequeued but completed URBs can't be given back unless
  1084. * the QH is stopped or has finished unlinking. */
  1085. if (status == -ECONNRESET &&
  1086. !(qh->is_stopped || QH_FINISHED_UNLINKING(qh)))
  1087. return;
  1088. uhci_giveback_urb(uhci, qh, urb, regs);
  1089. if (qh->is_stopped)
  1090. break;
  1091. }
  1092. /* If the QH is neither stopped nor finished unlinking (normal case),
  1093. * our work here is done. */
  1094. restart:
  1095. if (!(qh->is_stopped || QH_FINISHED_UNLINKING(qh)))
  1096. return;
  1097. /* Otherwise give back each of the dequeued URBs */
  1098. list_for_each_entry(urbp, &qh->queue, node) {
  1099. urb = urbp->urb;
  1100. if (urb->status != -EINPROGRESS) {
  1101. uhci_save_toggle(qh, urb);
  1102. uhci_giveback_urb(uhci, qh, urb, regs);
  1103. goto restart;
  1104. }
  1105. }
  1106. qh->is_stopped = 0;
  1107. /* There are no more dequeued URBs. If there are still URBs on the
  1108. * queue, the QH can now be re-activated. */
  1109. if (!list_empty(&qh->queue)) {
  1110. if (qh->needs_fixup)
  1111. uhci_fixup_toggles(qh, 0);
  1112. uhci_activate_qh(uhci, qh);
  1113. }
  1114. /* The queue is empty. The QH can become idle if it is fully
  1115. * unlinked. */
  1116. else if (QH_FINISHED_UNLINKING(qh))
  1117. uhci_make_qh_idle(uhci, qh);
  1118. }
  1119. static void uhci_free_pending_tds(struct uhci_hcd *uhci)
  1120. {
  1121. struct uhci_td *td, *tmp;
  1122. list_for_each_entry_safe(td, tmp, &uhci->td_remove_list, remove_list) {
  1123. list_del_init(&td->remove_list);
  1124. uhci_free_td(uhci, td);
  1125. }
  1126. }
  1127. /*
  1128. * Process events in the schedule, but only in one thread at a time
  1129. */
  1130. static void uhci_scan_schedule(struct uhci_hcd *uhci, struct pt_regs *regs)
  1131. {
  1132. int i;
  1133. struct uhci_qh *qh;
  1134. /* Don't allow re-entrant calls */
  1135. if (uhci->scan_in_progress) {
  1136. uhci->need_rescan = 1;
  1137. return;
  1138. }
  1139. uhci->scan_in_progress = 1;
  1140. rescan:
  1141. uhci->need_rescan = 0;
  1142. uhci_clear_next_interrupt(uhci);
  1143. uhci_get_current_frame_number(uhci);
  1144. if (uhci->frame_number + uhci->is_stopped != uhci->td_remove_age)
  1145. uhci_free_pending_tds(uhci);
  1146. /* Go through all the QH queues and process the URBs in each one */
  1147. for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
  1148. uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
  1149. struct uhci_qh, node);
  1150. while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
  1151. uhci->next_qh = list_entry(qh->node.next,
  1152. struct uhci_qh, node);
  1153. uhci_scan_qh(uhci, qh, regs);
  1154. }
  1155. }
  1156. if (uhci->need_rescan)
  1157. goto rescan;
  1158. uhci->scan_in_progress = 0;
  1159. /* If the controller is stopped, we can finish these off right now */
  1160. if (uhci->is_stopped)
  1161. uhci_free_pending_tds(uhci);
  1162. if (list_empty(&uhci->td_remove_list) &&
  1163. list_empty(&uhci->skel_unlink_qh->node))
  1164. uhci_clear_next_interrupt(uhci);
  1165. else
  1166. uhci_set_next_interrupt(uhci);
  1167. }
  1168. static void check_fsbr(struct uhci_hcd *uhci)
  1169. {
  1170. /* For now, don't scan URBs for FSBR timeouts.
  1171. * Add it back in later... */
  1172. /* Really disable FSBR */
  1173. if (!uhci->fsbr && uhci->fsbrtimeout && time_after_eq(jiffies, uhci->fsbrtimeout)) {
  1174. uhci->fsbrtimeout = 0;
  1175. uhci->skel_term_qh->link = UHCI_PTR_TERM;
  1176. }
  1177. }