azt3328.c 62 KB

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  1. /*
  2. * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
  3. * Copyright (C) 2002, 2005 by Andreas Mohr <andi AT lisas.de>
  4. *
  5. * Framework borrowed from Bart Hartgers's als4000.c.
  6. * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
  7. * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
  8. * Other versions are:
  9. * PCI168 A(W), sub ID 1800
  10. * PCI168 A/AP, sub ID 8000
  11. * Please give me feedback in case you try my driver with one of these!!
  12. *
  13. * GPL LICENSE
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. *
  27. * NOTES
  28. * Since Aztech does not provide any chipset documentation,
  29. * even on repeated request to various addresses,
  30. * and the answer that was finally given was negative
  31. * (and I was stupid enough to manage to get hold of a PCI168 soundcard
  32. * in the first place >:-P}),
  33. * I was forced to base this driver on reverse engineering
  34. * (3 weeks' worth of evenings filled with driver work).
  35. * (and no, I did NOT go the easy way: to pick up a PCI128 for 9 Euros)
  36. *
  37. * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
  38. * for compatibility reasons) has the following features:
  39. *
  40. * - builtin AC97 conformant codec (SNR over 80dB)
  41. * Note that "conformant" != "compliant"!! this chip's mixer register layout
  42. * *differs* from the standard AC97 layout:
  43. * they chose to not implement the headphone register (which is not a
  44. * problem since it's merely optional), yet when doing this, they committed
  45. * the grave sin of letting other registers follow immediately instead of
  46. * keeping a headphone dummy register, thereby shifting the mixer register
  47. * addresses illegally. So far unfortunately it looks like the very flexible
  48. * ALSA AC97 support is still not enough to easily compensate for such a
  49. * grave layout violation despite all tweaks and quirks mechanisms it offers.
  50. * - builtin genuine OPL3
  51. * - full duplex 16bit playback/record at independent sampling rate
  52. * - MPU401 (+ legacy address support) FIXME: how to enable legacy addr??
  53. * - game port (legacy address support)
  54. * - built-in General DirectX timer having a 20 bits counter
  55. * with 1us resolution (see below!)
  56. * - I2S serial port for external DAC
  57. * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
  58. * - supports hardware volume control
  59. * - single chip low cost solution (128 pin QFP)
  60. * - supports programmable Sub-vendor and Sub-system ID
  61. * required for Microsoft's logo compliance (FIXME: where?)
  62. * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
  63. *
  64. * Note that this driver now is actually *better* than the Windows driver,
  65. * since it additionally supports the card's 1MHz DirectX timer - just try
  66. * the following snd-seq module parameters etc.:
  67. * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
  68. * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
  69. * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
  70. * - "timidity -iAv -B2,8 -Os -EFreverb=0"
  71. * - "pmidi -p 128:0 jazz.mid"
  72. *
  73. * Certain PCI versions of this card are susceptible to DMA traffic underruns
  74. * in some systems (resulting in sound crackling/clicking/popping),
  75. * probably because they don't have a DMA FIFO buffer or so.
  76. * Overview (PCI ID/PCI subID/PCI rev.):
  77. * - no DMA crackling on SiS735: 0x50DC/0x1801/16
  78. * - unknown performance: 0x50DC/0x1801/10
  79. * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
  80. *
  81. * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
  82. * supposed to be very fast and supposed to get rid of crackling much
  83. * better than a VIA, yet ironically I still get crackling, like many other
  84. * people with the same chipset.
  85. * Possible remedies:
  86. * - plug card into a different PCI slot, preferrably one that isn't shared
  87. * too much (this helps a lot, but not completely!)
  88. * - get rid of PCI VGA card, use AGP instead
  89. * - upgrade or downgrade BIOS
  90. * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
  91. * Not too helpful.
  92. * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
  93. *
  94. * BUGS
  95. * - full-duplex might *still* be problematic, not fully tested recently
  96. *
  97. * TODO
  98. * - test MPU401 MIDI playback etc.
  99. * - add some power micro-management (disable various units of the card
  100. * as long as they're unused). However this requires I/O ports which I
  101. * haven't figured out yet and which thus might not even exist...
  102. * The standard suspend/resume functionality could probably make use of
  103. * some improvement, too...
  104. * - figure out what all unknown port bits are responsible for
  105. * - figure out some cleverly evil scheme to possibly make ALSA AC97 code
  106. * fully accept our quite incompatible ""AC97"" mixer and thus save some
  107. * code (but I'm not too optimistic that doing this is possible at all)
  108. */
  109. #include <sound/driver.h>
  110. #include <asm/io.h>
  111. #include <linux/init.h>
  112. #include <linux/pci.h>
  113. #include <linux/delay.h>
  114. #include <linux/slab.h>
  115. #include <linux/gameport.h>
  116. #include <linux/moduleparam.h>
  117. #include <linux/dma-mapping.h>
  118. #include <sound/core.h>
  119. #include <sound/control.h>
  120. #include <sound/pcm.h>
  121. #include <sound/rawmidi.h>
  122. #include <sound/mpu401.h>
  123. #include <sound/opl3.h>
  124. #include <sound/initval.h>
  125. #include "azt3328.h"
  126. MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
  127. MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
  128. MODULE_LICENSE("GPL");
  129. MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
  130. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  131. #define SUPPORT_JOYSTICK 1
  132. #endif
  133. #define DEBUG_MISC 0
  134. #define DEBUG_CALLS 0
  135. #define DEBUG_MIXER 0
  136. #define DEBUG_PLAY_REC 0
  137. #define DEBUG_IO 0
  138. #define DEBUG_TIMER 0
  139. #define MIXER_TESTING 0
  140. #if DEBUG_MISC
  141. #define snd_azf3328_dbgmisc(format, args...) printk(KERN_ERR format, ##args)
  142. #else
  143. #define snd_azf3328_dbgmisc(format, args...)
  144. #endif
  145. #if DEBUG_CALLS
  146. #define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
  147. #define snd_azf3328_dbgcallenter() printk(KERN_ERR "--> %s\n", __FUNCTION__)
  148. #define snd_azf3328_dbgcallleave() printk(KERN_ERR "<-- %s\n", __FUNCTION__)
  149. #else
  150. #define snd_azf3328_dbgcalls(format, args...)
  151. #define snd_azf3328_dbgcallenter()
  152. #define snd_azf3328_dbgcallleave()
  153. #endif
  154. #if DEBUG_MIXER
  155. #define snd_azf3328_dbgmixer(format, args...) printk(format, ##args)
  156. #else
  157. #define snd_azf3328_dbgmixer(format, args...)
  158. #endif
  159. #if DEBUG_PLAY_REC
  160. #define snd_azf3328_dbgplay(format, args...) printk(KERN_ERR format, ##args)
  161. #else
  162. #define snd_azf3328_dbgplay(format, args...)
  163. #endif
  164. #if DEBUG_MISC
  165. #define snd_azf3328_dbgtimer(format, args...) printk(KERN_ERR format, ##args)
  166. #else
  167. #define snd_azf3328_dbgtimer(format, args...)
  168. #endif
  169. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  170. module_param_array(index, int, NULL, 0444);
  171. MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
  172. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  173. module_param_array(id, charp, NULL, 0444);
  174. MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
  175. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  176. module_param_array(enable, bool, NULL, 0444);
  177. MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
  178. #ifdef SUPPORT_JOYSTICK
  179. static int joystick[SNDRV_CARDS];
  180. module_param_array(joystick, bool, NULL, 0444);
  181. MODULE_PARM_DESC(joystick, "Enable joystick for AZF3328 soundcard.");
  182. #endif
  183. static int seqtimer_scaling = 128;
  184. module_param(seqtimer_scaling, int, 0444);
  185. MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
  186. struct snd_azf3328 {
  187. /* often-used fields towards beginning, then grouped */
  188. unsigned long codec_port;
  189. unsigned long io2_port;
  190. unsigned long mpu_port;
  191. unsigned long synth_port;
  192. unsigned long mixer_port;
  193. spinlock_t reg_lock;
  194. struct snd_timer *timer;
  195. struct snd_pcm *pcm;
  196. struct snd_pcm_substream *playback_substream;
  197. struct snd_pcm_substream *capture_substream;
  198. unsigned int is_playing;
  199. unsigned int is_recording;
  200. struct snd_card *card;
  201. struct snd_rawmidi *rmidi;
  202. #ifdef SUPPORT_JOYSTICK
  203. struct gameport *gameport;
  204. #endif
  205. struct pci_dev *pci;
  206. int irq;
  207. #ifdef CONFIG_PM
  208. /* register value containers for power management
  209. * Note: not always full I/O range preserved (just like Win driver!) */
  210. u16 saved_regs_codec [AZF_IO_SIZE_CODEC_PM / 2];
  211. u16 saved_regs_io2 [AZF_IO_SIZE_IO2_PM / 2];
  212. u16 saved_regs_mpu [AZF_IO_SIZE_MPU_PM / 2];
  213. u16 saved_regs_synth[AZF_IO_SIZE_SYNTH_PM / 2];
  214. u16 saved_regs_mixer[AZF_IO_SIZE_MIXER_PM / 2];
  215. #endif
  216. };
  217. static const struct pci_device_id snd_azf3328_ids[] __devinitdata = {
  218. { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
  219. { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
  220. { 0, }
  221. };
  222. MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
  223. static inline void
  224. snd_azf3328_codec_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  225. {
  226. outb(value, chip->codec_port + reg);
  227. }
  228. static inline u8
  229. snd_azf3328_codec_inb(const struct snd_azf3328 *chip, int reg)
  230. {
  231. return inb(chip->codec_port + reg);
  232. }
  233. static inline void
  234. snd_azf3328_codec_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  235. {
  236. outw(value, chip->codec_port + reg);
  237. }
  238. static inline u16
  239. snd_azf3328_codec_inw(const struct snd_azf3328 *chip, int reg)
  240. {
  241. return inw(chip->codec_port + reg);
  242. }
  243. static inline void
  244. snd_azf3328_codec_outl(const struct snd_azf3328 *chip, int reg, u32 value)
  245. {
  246. outl(value, chip->codec_port + reg);
  247. }
  248. static inline void
  249. snd_azf3328_io2_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  250. {
  251. outb(value, chip->io2_port + reg);
  252. }
  253. static inline u8
  254. snd_azf3328_io2_inb(const struct snd_azf3328 *chip, int reg)
  255. {
  256. return inb(chip->io2_port + reg);
  257. }
  258. static inline void
  259. snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  260. {
  261. outw(value, chip->mixer_port + reg);
  262. }
  263. static inline u16
  264. snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, int reg)
  265. {
  266. return inw(chip->mixer_port + reg);
  267. }
  268. static void
  269. snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip, int reg, int do_mute)
  270. {
  271. unsigned long portbase = chip->mixer_port + reg + 1;
  272. unsigned char oldval;
  273. /* the mute bit is on the *second* (i.e. right) register of a
  274. * left/right channel setting */
  275. oldval = inb(portbase);
  276. if (do_mute)
  277. oldval |= 0x80;
  278. else
  279. oldval &= ~0x80;
  280. outb(oldval, portbase);
  281. }
  282. static void
  283. snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, int reg, unsigned char dst_vol_left, unsigned char dst_vol_right, int chan_sel, int delay)
  284. {
  285. unsigned long portbase = chip->mixer_port + reg;
  286. unsigned char curr_vol_left = 0, curr_vol_right = 0;
  287. int left_done = 0, right_done = 0;
  288. snd_azf3328_dbgcallenter();
  289. if (chan_sel & SET_CHAN_LEFT)
  290. curr_vol_left = inb(portbase + 1);
  291. else
  292. left_done = 1;
  293. if (chan_sel & SET_CHAN_RIGHT)
  294. curr_vol_right = inb(portbase + 0);
  295. else
  296. right_done = 1;
  297. /* take care of muting flag (0x80) contained in left channel */
  298. if (curr_vol_left & 0x80)
  299. dst_vol_left |= 0x80;
  300. else
  301. dst_vol_left &= ~0x80;
  302. do
  303. {
  304. if (!left_done)
  305. {
  306. if (curr_vol_left > dst_vol_left)
  307. curr_vol_left--;
  308. else
  309. if (curr_vol_left < dst_vol_left)
  310. curr_vol_left++;
  311. else
  312. left_done = 1;
  313. outb(curr_vol_left, portbase + 1);
  314. }
  315. if (!right_done)
  316. {
  317. if (curr_vol_right > dst_vol_right)
  318. curr_vol_right--;
  319. else
  320. if (curr_vol_right < dst_vol_right)
  321. curr_vol_right++;
  322. else
  323. right_done = 1;
  324. /* during volume change, the right channel is crackling
  325. * somewhat more than the left channel, unfortunately.
  326. * This seems to be a hardware issue. */
  327. outb(curr_vol_right, portbase + 0);
  328. }
  329. if (delay)
  330. mdelay(delay);
  331. }
  332. while ((!left_done) || (!right_done));
  333. snd_azf3328_dbgcallleave();
  334. }
  335. /*
  336. * general mixer element
  337. */
  338. struct azf3328_mixer_reg {
  339. unsigned int reg;
  340. unsigned int lchan_shift, rchan_shift;
  341. unsigned int mask;
  342. unsigned int invert: 1;
  343. unsigned int stereo: 1;
  344. unsigned int enum_c: 4;
  345. };
  346. #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
  347. ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
  348. (mask << 16) | \
  349. (invert << 24) | \
  350. (stereo << 25) | \
  351. (enum_c << 26))
  352. static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
  353. {
  354. r->reg = val & 0xff;
  355. r->lchan_shift = (val >> 8) & 0x0f;
  356. r->rchan_shift = (val >> 12) & 0x0f;
  357. r->mask = (val >> 16) & 0xff;
  358. r->invert = (val >> 24) & 1;
  359. r->stereo = (val >> 25) & 1;
  360. r->enum_c = (val >> 26) & 0x0f;
  361. }
  362. /*
  363. * mixer switches/volumes
  364. */
  365. #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
  366. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  367. .info = snd_azf3328_info_mixer, \
  368. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  369. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
  370. }
  371. #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
  372. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  373. .info = snd_azf3328_info_mixer, \
  374. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  375. .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
  376. }
  377. #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
  378. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  379. .info = snd_azf3328_info_mixer, \
  380. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  381. .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
  382. }
  383. #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
  384. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  385. .info = snd_azf3328_info_mixer, \
  386. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  387. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
  388. }
  389. #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
  390. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  391. .info = snd_azf3328_info_mixer_enum, \
  392. .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
  393. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
  394. }
  395. static int
  396. snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
  397. struct snd_ctl_elem_info *uinfo)
  398. {
  399. struct azf3328_mixer_reg reg;
  400. snd_azf3328_dbgcallenter();
  401. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  402. uinfo->type = reg.mask == 1 ?
  403. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  404. uinfo->count = reg.stereo + 1;
  405. uinfo->value.integer.min = 0;
  406. uinfo->value.integer.max = reg.mask;
  407. snd_azf3328_dbgcallleave();
  408. return 0;
  409. }
  410. static int
  411. snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
  412. struct snd_ctl_elem_value *ucontrol)
  413. {
  414. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  415. struct azf3328_mixer_reg reg;
  416. unsigned int oreg, val;
  417. snd_azf3328_dbgcallenter();
  418. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  419. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  420. val = (oreg >> reg.lchan_shift) & reg.mask;
  421. if (reg.invert)
  422. val = reg.mask - val;
  423. ucontrol->value.integer.value[0] = val;
  424. if (reg.stereo) {
  425. val = (oreg >> reg.rchan_shift) & reg.mask;
  426. if (reg.invert)
  427. val = reg.mask - val;
  428. ucontrol->value.integer.value[1] = val;
  429. }
  430. snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
  431. "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
  432. reg.reg, oreg,
  433. ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  434. reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
  435. snd_azf3328_dbgcallleave();
  436. return 0;
  437. }
  438. static int
  439. snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
  440. struct snd_ctl_elem_value *ucontrol)
  441. {
  442. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  443. struct azf3328_mixer_reg reg;
  444. unsigned int oreg, nreg, val;
  445. snd_azf3328_dbgcallenter();
  446. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  447. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  448. val = ucontrol->value.integer.value[0] & reg.mask;
  449. if (reg.invert)
  450. val = reg.mask - val;
  451. nreg = oreg & ~(reg.mask << reg.lchan_shift);
  452. nreg |= (val << reg.lchan_shift);
  453. if (reg.stereo) {
  454. val = ucontrol->value.integer.value[1] & reg.mask;
  455. if (reg.invert)
  456. val = reg.mask - val;
  457. nreg &= ~(reg.mask << reg.rchan_shift);
  458. nreg |= (val << reg.rchan_shift);
  459. }
  460. if (reg.mask >= 0x07) /* it's a volume control, so better take care */
  461. snd_azf3328_mixer_write_volume_gradually(
  462. chip, reg.reg, nreg >> 8, nreg & 0xff,
  463. /* just set both channels, doesn't matter */
  464. SET_CHAN_LEFT|SET_CHAN_RIGHT,
  465. 0);
  466. else
  467. snd_azf3328_mixer_outw(chip, reg.reg, nreg);
  468. snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
  469. "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
  470. reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  471. oreg, reg.lchan_shift, reg.rchan_shift,
  472. nreg, snd_azf3328_mixer_inw(chip, reg.reg));
  473. snd_azf3328_dbgcallleave();
  474. return (nreg != oreg);
  475. }
  476. static int
  477. snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
  478. struct snd_ctl_elem_info *uinfo)
  479. {
  480. static const char * const texts1[] = {
  481. "Mic1", "Mic2"
  482. };
  483. static const char * const texts2[] = {
  484. "Mix", "Mic"
  485. };
  486. static const char * const texts3[] = {
  487. "Mic", "CD", "Video", "Aux",
  488. "Line", "Mix", "Mix Mono", "Phone"
  489. };
  490. static const char * const texts4[] = {
  491. "pre 3D", "post 3D"
  492. };
  493. struct azf3328_mixer_reg reg;
  494. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  495. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  496. uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
  497. uinfo->value.enumerated.items = reg.enum_c;
  498. if (uinfo->value.enumerated.item > reg.enum_c - 1U)
  499. uinfo->value.enumerated.item = reg.enum_c - 1U;
  500. if (reg.reg == IDX_MIXER_ADVCTL2)
  501. {
  502. switch(reg.lchan_shift) {
  503. case 8: /* modem out sel */
  504. strcpy(uinfo->value.enumerated.name, texts1[uinfo->value.enumerated.item]);
  505. break;
  506. case 9: /* mono sel source */
  507. strcpy(uinfo->value.enumerated.name, texts2[uinfo->value.enumerated.item]);
  508. break;
  509. case 15: /* PCM Out Path */
  510. strcpy(uinfo->value.enumerated.name, texts4[uinfo->value.enumerated.item]);
  511. break;
  512. }
  513. }
  514. else
  515. strcpy(uinfo->value.enumerated.name, texts3[uinfo->value.enumerated.item]
  516. );
  517. return 0;
  518. }
  519. static int
  520. snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
  521. struct snd_ctl_elem_value *ucontrol)
  522. {
  523. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  524. struct azf3328_mixer_reg reg;
  525. unsigned short val;
  526. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  527. val = snd_azf3328_mixer_inw(chip, reg.reg);
  528. if (reg.reg == IDX_MIXER_REC_SELECT)
  529. {
  530. ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
  531. ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
  532. }
  533. else
  534. ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
  535. snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
  536. reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
  537. reg.lchan_shift, reg.enum_c);
  538. return 0;
  539. }
  540. static int
  541. snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
  542. struct snd_ctl_elem_value *ucontrol)
  543. {
  544. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  545. struct azf3328_mixer_reg reg;
  546. unsigned int oreg, nreg, val;
  547. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  548. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  549. val = oreg;
  550. if (reg.reg == IDX_MIXER_REC_SELECT)
  551. {
  552. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
  553. ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
  554. return -EINVAL;
  555. val = (ucontrol->value.enumerated.item[0] << 8) |
  556. (ucontrol->value.enumerated.item[1] << 0);
  557. }
  558. else
  559. {
  560. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
  561. return -EINVAL;
  562. val &= ~((reg.enum_c - 1) << reg.lchan_shift);
  563. val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
  564. }
  565. snd_azf3328_mixer_outw(chip, reg.reg, val);
  566. nreg = val;
  567. snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
  568. return (nreg != oreg);
  569. }
  570. static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
  571. AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
  572. AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
  573. AZF3328_MIXER_SWITCH("Wave Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
  574. AZF3328_MIXER_VOL_STEREO("Wave Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1),
  575. AZF3328_MIXER_SWITCH("Wave 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1),
  576. AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
  577. AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
  578. AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
  579. AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
  580. AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
  581. AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
  582. AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
  583. AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
  584. AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
  585. AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
  586. AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
  587. AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
  588. AZF3328_MIXER_SWITCH("PC Speaker Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
  589. AZF3328_MIXER_VOL_SPECIAL("PC Speaker Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
  590. AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
  591. AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
  592. AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
  593. AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
  594. AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
  595. AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
  596. AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
  597. AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
  598. AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
  599. AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
  600. AZF3328_MIXER_ENUM("PCM", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
  601. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
  602. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
  603. AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
  604. AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
  605. AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
  606. #if MIXER_TESTING
  607. AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
  608. AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
  609. AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
  610. AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
  611. AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
  612. AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
  613. AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
  614. AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
  615. AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
  616. AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
  617. AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
  618. AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
  619. AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
  620. AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
  621. AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
  622. AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
  623. #endif
  624. };
  625. static const u16 __devinitdata snd_azf3328_init_values[][2] = {
  626. { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
  627. { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
  628. { IDX_MIXER_BASSTREBLE, 0x0000 },
  629. { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
  630. { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
  631. { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
  632. { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
  633. { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
  634. { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
  635. { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
  636. { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
  637. { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
  638. { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
  639. };
  640. static int __devinit
  641. snd_azf3328_mixer_new(struct snd_azf3328 *chip)
  642. {
  643. struct snd_card *card;
  644. const struct snd_kcontrol_new *sw;
  645. unsigned int idx;
  646. int err;
  647. snd_azf3328_dbgcallenter();
  648. snd_assert(chip != NULL && chip->card != NULL, return -EINVAL);
  649. card = chip->card;
  650. /* mixer reset */
  651. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  652. /* mute and zero volume channels */
  653. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); idx++) {
  654. snd_azf3328_mixer_outw(chip,
  655. snd_azf3328_init_values[idx][0],
  656. snd_azf3328_init_values[idx][1]);
  657. }
  658. /* add mixer controls */
  659. sw = snd_azf3328_mixer_controls;
  660. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); idx++, sw++) {
  661. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
  662. return err;
  663. }
  664. snd_component_add(card, "AZF3328 mixer");
  665. strcpy(card->mixername, "AZF3328 mixer");
  666. snd_azf3328_dbgcallleave();
  667. return 0;
  668. }
  669. static int
  670. snd_azf3328_hw_params(struct snd_pcm_substream *substream,
  671. struct snd_pcm_hw_params *hw_params)
  672. {
  673. int res;
  674. snd_azf3328_dbgcallenter();
  675. res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  676. snd_azf3328_dbgcallleave();
  677. return res;
  678. }
  679. static int
  680. snd_azf3328_hw_free(struct snd_pcm_substream *substream)
  681. {
  682. snd_azf3328_dbgcallenter();
  683. snd_pcm_lib_free_pages(substream);
  684. snd_azf3328_dbgcallleave();
  685. return 0;
  686. }
  687. static void
  688. snd_azf3328_setfmt(struct snd_azf3328 *chip,
  689. unsigned int reg,
  690. unsigned int bitrate,
  691. unsigned int format_width,
  692. unsigned int channels
  693. )
  694. {
  695. u16 val = 0xff00;
  696. unsigned long flags;
  697. snd_azf3328_dbgcallenter();
  698. switch (bitrate) {
  699. case 4000: val |= SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
  700. case 4800: val |= SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
  701. case 5512: val |= SOUNDFORMAT_FREQ_5510; break; /* the AZF3328 names it "5510" for some strange reason */
  702. case 6620: val |= SOUNDFORMAT_FREQ_6620; break;
  703. case 8000: val |= SOUNDFORMAT_FREQ_8000; break;
  704. case 9600: val |= SOUNDFORMAT_FREQ_9600; break;
  705. case 11025: val |= SOUNDFORMAT_FREQ_11025; break;
  706. case 13240: val |= SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
  707. case 16000: val |= SOUNDFORMAT_FREQ_16000; break;
  708. case 22050: val |= SOUNDFORMAT_FREQ_22050; break;
  709. case 32000: val |= SOUNDFORMAT_FREQ_32000; break;
  710. case 44100: val |= SOUNDFORMAT_FREQ_44100; break;
  711. case 48000: val |= SOUNDFORMAT_FREQ_48000; break;
  712. case 66200: val |= SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
  713. default:
  714. snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
  715. val |= SOUNDFORMAT_FREQ_44100;
  716. break;
  717. }
  718. /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
  719. /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
  720. /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
  721. /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
  722. /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
  723. /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
  724. /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
  725. /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
  726. /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
  727. if (channels == 2)
  728. val |= SOUNDFORMAT_FLAG_2CHANNELS;
  729. if (format_width == 16)
  730. val |= SOUNDFORMAT_FLAG_16BIT;
  731. spin_lock_irqsave(&chip->reg_lock, flags);
  732. /* set bitrate/format */
  733. snd_azf3328_codec_outw(chip, reg, val);
  734. /* changing the bitrate/format settings switches off the
  735. * audio output with an annoying click in case of 8/16bit format change
  736. * (maybe shutting down DAC/ADC?), thus immediately
  737. * do some tweaking to reenable it and get rid of the clicking
  738. * (FIXME: yes, it works, but what exactly am I doing here?? :)
  739. * FIXME: does this have some side effects for full-duplex
  740. * or other dramatic side effects? */
  741. if (reg == IDX_IO_PLAY_SOUNDFORMAT) /* only do it for playback */
  742. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  743. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) |
  744. DMA_PLAY_SOMETHING1 |
  745. DMA_PLAY_SOMETHING2 |
  746. SOMETHING_ALMOST_ALWAYS_SET |
  747. DMA_EPILOGUE_SOMETHING |
  748. DMA_SOMETHING_ELSE
  749. );
  750. spin_unlock_irqrestore(&chip->reg_lock, flags);
  751. snd_azf3328_dbgcallleave();
  752. }
  753. static void
  754. snd_azf3328_setdmaa(struct snd_azf3328 *chip,
  755. long unsigned int addr,
  756. unsigned int count,
  757. unsigned int size,
  758. int do_recording)
  759. {
  760. unsigned long flags, portbase;
  761. unsigned int is_running;
  762. snd_azf3328_dbgcallenter();
  763. if (do_recording)
  764. {
  765. /* access capture registers, i.e. skip playback reg section */
  766. portbase = chip->codec_port + 0x20;
  767. is_running = chip->is_recording;
  768. }
  769. else
  770. {
  771. /* access the playback register section */
  772. portbase = chip->codec_port + 0x00;
  773. is_running = chip->is_playing;
  774. }
  775. /* AZF3328 uses a two buffer pointer DMA playback approach */
  776. if (!is_running)
  777. {
  778. unsigned long addr_area2;
  779. unsigned long count_areas, count_tmp; /* width 32bit -- overflow!! */
  780. count_areas = size/2;
  781. addr_area2 = addr+count_areas;
  782. count_areas--; /* max. index */
  783. snd_azf3328_dbgplay("set DMA: buf1 %08lx[%lu], buf2 %08lx[%lu]\n", addr, count_areas, addr_area2, count_areas);
  784. /* build combined I/O buffer length word */
  785. count_tmp = count_areas;
  786. count_areas |= (count_tmp << 16);
  787. spin_lock_irqsave(&chip->reg_lock, flags);
  788. outl(addr, portbase + IDX_IO_PLAY_DMA_START_1);
  789. outl(addr_area2, portbase + IDX_IO_PLAY_DMA_START_2);
  790. outl(count_areas, portbase + IDX_IO_PLAY_DMA_LEN_1);
  791. spin_unlock_irqrestore(&chip->reg_lock, flags);
  792. }
  793. snd_azf3328_dbgcallleave();
  794. }
  795. static int
  796. snd_azf3328_playback_prepare(struct snd_pcm_substream *substream)
  797. {
  798. #if 0
  799. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  800. struct snd_pcm_runtime *runtime = substream->runtime;
  801. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  802. unsigned int count = snd_pcm_lib_period_bytes(substream);
  803. #endif
  804. snd_azf3328_dbgcallenter();
  805. #if 0
  806. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  807. runtime->rate,
  808. snd_pcm_format_width(runtime->format),
  809. runtime->channels);
  810. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 0);
  811. #endif
  812. snd_azf3328_dbgcallleave();
  813. return 0;
  814. }
  815. static int
  816. snd_azf3328_capture_prepare(struct snd_pcm_substream *substream)
  817. {
  818. #if 0
  819. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  820. struct snd_pcm_runtime *runtime = substream->runtime;
  821. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  822. unsigned int count = snd_pcm_lib_period_bytes(substream);
  823. #endif
  824. snd_azf3328_dbgcallenter();
  825. #if 0
  826. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  827. runtime->rate,
  828. snd_pcm_format_width(runtime->format),
  829. runtime->channels);
  830. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 1);
  831. #endif
  832. snd_azf3328_dbgcallleave();
  833. return 0;
  834. }
  835. static int
  836. snd_azf3328_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  837. {
  838. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  839. struct snd_pcm_runtime *runtime = substream->runtime;
  840. int result = 0;
  841. unsigned int status1;
  842. snd_azf3328_dbgcalls("snd_azf3328_playback_trigger cmd %d\n", cmd);
  843. switch (cmd) {
  844. case SNDRV_PCM_TRIGGER_START:
  845. snd_azf3328_dbgplay("START PLAYBACK\n");
  846. /* mute WaveOut */
  847. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  848. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  849. runtime->rate,
  850. snd_pcm_format_width(runtime->format),
  851. runtime->channels);
  852. spin_lock(&chip->reg_lock);
  853. /* stop playback */
  854. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  855. status1 &= ~DMA_RESUME;
  856. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  857. /* FIXME: clear interrupts or what??? */
  858. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_IRQTYPE, 0xffff);
  859. spin_unlock(&chip->reg_lock);
  860. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  861. snd_pcm_lib_period_bytes(substream),
  862. snd_pcm_lib_buffer_bytes(substream),
  863. 0);
  864. spin_lock(&chip->reg_lock);
  865. #ifdef WIN9X
  866. /* FIXME: enable playback/recording??? */
  867. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  868. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  869. /* start playback again */
  870. /* FIXME: what is this value (0x0010)??? */
  871. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  872. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  873. #else /* NT4 */
  874. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  875. 0x0000);
  876. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  877. DMA_PLAY_SOMETHING1);
  878. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  879. DMA_PLAY_SOMETHING1 |
  880. DMA_PLAY_SOMETHING2);
  881. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  882. DMA_RESUME |
  883. SOMETHING_ALMOST_ALWAYS_SET |
  884. DMA_EPILOGUE_SOMETHING |
  885. DMA_SOMETHING_ELSE);
  886. #endif
  887. spin_unlock(&chip->reg_lock);
  888. /* now unmute WaveOut */
  889. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  890. chip->is_playing = 1;
  891. snd_azf3328_dbgplay("STARTED PLAYBACK\n");
  892. break;
  893. case SNDRV_PCM_TRIGGER_RESUME:
  894. snd_azf3328_dbgplay("RESUME PLAYBACK\n");
  895. /* resume playback if we were active */
  896. if (chip->is_playing)
  897. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  898. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) | DMA_RESUME);
  899. break;
  900. case SNDRV_PCM_TRIGGER_STOP:
  901. snd_azf3328_dbgplay("STOP PLAYBACK\n");
  902. /* mute WaveOut */
  903. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  904. spin_lock(&chip->reg_lock);
  905. /* stop playback */
  906. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  907. status1 &= ~DMA_RESUME;
  908. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  909. /* hmm, is this really required? we're resetting the same bit
  910. * immediately thereafter... */
  911. status1 |= DMA_PLAY_SOMETHING1;
  912. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  913. status1 &= ~DMA_PLAY_SOMETHING1;
  914. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  915. spin_unlock(&chip->reg_lock);
  916. /* now unmute WaveOut */
  917. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  918. chip->is_playing = 0;
  919. snd_azf3328_dbgplay("STOPPED PLAYBACK\n");
  920. break;
  921. case SNDRV_PCM_TRIGGER_SUSPEND:
  922. snd_azf3328_dbgplay("SUSPEND PLAYBACK\n");
  923. /* make sure playback is stopped */
  924. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  925. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) & ~DMA_RESUME);
  926. break;
  927. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  928. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  929. break;
  930. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  931. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  932. break;
  933. default:
  934. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  935. return -EINVAL;
  936. }
  937. snd_azf3328_dbgcallleave();
  938. return result;
  939. }
  940. /* this is just analogous to playback; I'm not quite sure whether recording
  941. * should actually be triggered like that */
  942. static int
  943. snd_azf3328_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  944. {
  945. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  946. struct snd_pcm_runtime *runtime = substream->runtime;
  947. int result = 0;
  948. unsigned int status1;
  949. snd_azf3328_dbgcalls("snd_azf3328_capture_trigger cmd %d\n", cmd);
  950. switch (cmd) {
  951. case SNDRV_PCM_TRIGGER_START:
  952. snd_azf3328_dbgplay("START CAPTURE\n");
  953. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  954. runtime->rate,
  955. snd_pcm_format_width(runtime->format),
  956. runtime->channels);
  957. spin_lock(&chip->reg_lock);
  958. /* stop recording */
  959. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  960. status1 &= ~DMA_RESUME;
  961. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  962. /* FIXME: clear interrupts or what??? */
  963. snd_azf3328_codec_outw(chip, IDX_IO_REC_IRQTYPE, 0xffff);
  964. spin_unlock(&chip->reg_lock);
  965. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  966. snd_pcm_lib_period_bytes(substream),
  967. snd_pcm_lib_buffer_bytes(substream),
  968. 1);
  969. spin_lock(&chip->reg_lock);
  970. #ifdef WIN9X
  971. /* FIXME: enable playback/recording??? */
  972. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  973. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  974. /* start capture again */
  975. /* FIXME: what is this value (0x0010)??? */
  976. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  977. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  978. #else
  979. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  980. 0x0000);
  981. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  982. DMA_PLAY_SOMETHING1);
  983. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  984. DMA_PLAY_SOMETHING1 |
  985. DMA_PLAY_SOMETHING2);
  986. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  987. DMA_RESUME |
  988. SOMETHING_ALMOST_ALWAYS_SET |
  989. DMA_EPILOGUE_SOMETHING |
  990. DMA_SOMETHING_ELSE);
  991. #endif
  992. spin_unlock(&chip->reg_lock);
  993. chip->is_recording = 1;
  994. snd_azf3328_dbgplay("STARTED CAPTURE\n");
  995. break;
  996. case SNDRV_PCM_TRIGGER_RESUME:
  997. snd_azf3328_dbgplay("RESUME CAPTURE\n");
  998. /* resume recording if we were active */
  999. if (chip->is_recording)
  1000. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  1001. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) | DMA_RESUME);
  1002. break;
  1003. case SNDRV_PCM_TRIGGER_STOP:
  1004. snd_azf3328_dbgplay("STOP CAPTURE\n");
  1005. spin_lock(&chip->reg_lock);
  1006. /* stop recording */
  1007. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  1008. status1 &= ~DMA_RESUME;
  1009. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  1010. status1 |= DMA_PLAY_SOMETHING1;
  1011. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  1012. status1 &= ~DMA_PLAY_SOMETHING1;
  1013. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  1014. spin_unlock(&chip->reg_lock);
  1015. chip->is_recording = 0;
  1016. snd_azf3328_dbgplay("STOPPED CAPTURE\n");
  1017. break;
  1018. case SNDRV_PCM_TRIGGER_SUSPEND:
  1019. snd_azf3328_dbgplay("SUSPEND CAPTURE\n");
  1020. /* make sure recording is stopped */
  1021. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  1022. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) & ~DMA_RESUME);
  1023. break;
  1024. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1025. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  1026. break;
  1027. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1028. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  1029. break;
  1030. default:
  1031. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  1032. return -EINVAL;
  1033. }
  1034. snd_azf3328_dbgcallleave();
  1035. return result;
  1036. }
  1037. static snd_pcm_uframes_t
  1038. snd_azf3328_playback_pointer(struct snd_pcm_substream *substream)
  1039. {
  1040. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1041. unsigned long bufptr, result;
  1042. snd_pcm_uframes_t frmres;
  1043. #ifdef QUERY_HARDWARE
  1044. bufptr = inl(chip->codec_port+IDX_IO_PLAY_DMA_START_1);
  1045. #else
  1046. bufptr = substream->runtime->dma_addr;
  1047. #endif
  1048. result = inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS);
  1049. /* calculate offset */
  1050. result -= bufptr;
  1051. frmres = bytes_to_frames( substream->runtime, result);
  1052. snd_azf3328_dbgplay("PLAY @ 0x%8lx, frames %8ld\n", result, frmres);
  1053. return frmres;
  1054. }
  1055. static snd_pcm_uframes_t
  1056. snd_azf3328_capture_pointer(struct snd_pcm_substream *substream)
  1057. {
  1058. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1059. unsigned long bufptr, result;
  1060. snd_pcm_uframes_t frmres;
  1061. #ifdef QUERY_HARDWARE
  1062. bufptr = inl(chip->codec_port+IDX_IO_REC_DMA_START_1);
  1063. #else
  1064. bufptr = substream->runtime->dma_addr;
  1065. #endif
  1066. result = inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS);
  1067. /* calculate offset */
  1068. result -= bufptr;
  1069. frmres = bytes_to_frames( substream->runtime, result);
  1070. snd_azf3328_dbgplay("REC @ 0x%8lx, frames %8ld\n", result, frmres);
  1071. return frmres;
  1072. }
  1073. static irqreturn_t
  1074. snd_azf3328_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  1075. {
  1076. struct snd_azf3328 *chip = dev_id;
  1077. u8 status, which;
  1078. static unsigned long irq_count;
  1079. status = snd_azf3328_codec_inb(chip, IDX_IO_IRQSTATUS);
  1080. /* fast path out, to ease interrupt sharing */
  1081. if (!(status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_MPU401|IRQ_TIMER)))
  1082. return IRQ_NONE; /* must be interrupt for another device */
  1083. snd_azf3328_dbgplay("Interrupt %ld!\nIDX_IO_PLAY_FLAGS %04x, IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n",
  1084. irq_count,
  1085. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS),
  1086. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE),
  1087. status);
  1088. if (status & IRQ_TIMER)
  1089. {
  1090. /* snd_azf3328_dbgplay("timer %ld\n", inl(chip->codec_port+IDX_IO_TIMER_VALUE) & TIMER_VALUE_MASK); */
  1091. if (chip->timer)
  1092. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1093. /* ACK timer */
  1094. spin_lock(&chip->reg_lock);
  1095. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
  1096. spin_unlock(&chip->reg_lock);
  1097. snd_azf3328_dbgplay("azt3328: timer IRQ\n");
  1098. }
  1099. if (status & IRQ_PLAYBACK)
  1100. {
  1101. spin_lock(&chip->reg_lock);
  1102. which = snd_azf3328_codec_inb(chip, IDX_IO_PLAY_IRQTYPE);
  1103. /* ack all IRQ types immediately */
  1104. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_IRQTYPE, which);
  1105. spin_unlock(&chip->reg_lock);
  1106. if (chip->pcm && chip->playback_substream)
  1107. {
  1108. snd_pcm_period_elapsed(chip->playback_substream);
  1109. snd_azf3328_dbgplay("PLAY period done (#%x), @ %x\n",
  1110. which,
  1111. inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS));
  1112. }
  1113. else
  1114. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1115. if (which & IRQ_PLAY_SOMETHING)
  1116. snd_azf3328_dbgplay("azt3328: unknown play IRQ type occurred, please report!\n");
  1117. }
  1118. if (status & IRQ_RECORDING)
  1119. {
  1120. spin_lock(&chip->reg_lock);
  1121. which = snd_azf3328_codec_inb(chip, IDX_IO_REC_IRQTYPE);
  1122. /* ack all IRQ types immediately */
  1123. snd_azf3328_codec_outb(chip, IDX_IO_REC_IRQTYPE, which);
  1124. spin_unlock(&chip->reg_lock);
  1125. if (chip->pcm && chip->capture_substream)
  1126. {
  1127. snd_pcm_period_elapsed(chip->capture_substream);
  1128. snd_azf3328_dbgplay("REC period done (#%x), @ %x\n",
  1129. which,
  1130. inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS));
  1131. }
  1132. else
  1133. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1134. if (which & IRQ_REC_SOMETHING)
  1135. snd_azf3328_dbgplay("azt3328: unknown rec IRQ type occurred, please report!\n");
  1136. }
  1137. /* MPU401 has less critical IRQ requirements
  1138. * than timer and playback/recording, right? */
  1139. if (status & IRQ_MPU401)
  1140. {
  1141. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
  1142. /* hmm, do we have to ack the IRQ here somehow?
  1143. * If so, then I don't know how... */
  1144. snd_azf3328_dbgplay("azt3328: MPU401 IRQ\n");
  1145. }
  1146. irq_count++;
  1147. return IRQ_HANDLED;
  1148. }
  1149. /*****************************************************************/
  1150. static const struct snd_pcm_hardware snd_azf3328_playback =
  1151. {
  1152. /* FIXME!! Correct? */
  1153. .info = SNDRV_PCM_INFO_MMAP |
  1154. SNDRV_PCM_INFO_INTERLEAVED |
  1155. SNDRV_PCM_INFO_MMAP_VALID,
  1156. .formats = SNDRV_PCM_FMTBIT_S8 |
  1157. SNDRV_PCM_FMTBIT_U8 |
  1158. SNDRV_PCM_FMTBIT_S16_LE |
  1159. SNDRV_PCM_FMTBIT_U16_LE,
  1160. .rates = SNDRV_PCM_RATE_5512 |
  1161. SNDRV_PCM_RATE_8000_48000 |
  1162. SNDRV_PCM_RATE_KNOT,
  1163. .rate_min = 4000,
  1164. .rate_max = 66200,
  1165. .channels_min = 1,
  1166. .channels_max = 2,
  1167. .buffer_bytes_max = 65536,
  1168. .period_bytes_min = 64,
  1169. .period_bytes_max = 65536,
  1170. .periods_min = 1,
  1171. .periods_max = 1024,
  1172. /* FIXME: maybe that card actually has a FIFO?
  1173. * Hmm, it seems newer revisions do have one, but we still don't know
  1174. * its size... */
  1175. .fifo_size = 0,
  1176. };
  1177. static const struct snd_pcm_hardware snd_azf3328_capture =
  1178. {
  1179. /* FIXME */
  1180. .info = SNDRV_PCM_INFO_MMAP |
  1181. SNDRV_PCM_INFO_INTERLEAVED |
  1182. SNDRV_PCM_INFO_MMAP_VALID,
  1183. .formats = SNDRV_PCM_FMTBIT_S8 |
  1184. SNDRV_PCM_FMTBIT_U8 |
  1185. SNDRV_PCM_FMTBIT_S16_LE |
  1186. SNDRV_PCM_FMTBIT_U16_LE,
  1187. .rates = SNDRV_PCM_RATE_5512 |
  1188. SNDRV_PCM_RATE_8000_48000 |
  1189. SNDRV_PCM_RATE_KNOT,
  1190. .rate_min = 4000,
  1191. .rate_max = 66200,
  1192. .channels_min = 1,
  1193. .channels_max = 2,
  1194. .buffer_bytes_max = 65536,
  1195. .period_bytes_min = 64,
  1196. .period_bytes_max = 65536,
  1197. .periods_min = 1,
  1198. .periods_max = 1024,
  1199. .fifo_size = 0,
  1200. };
  1201. static unsigned int snd_azf3328_fixed_rates[] = {
  1202. 4000, 4800, 5512, 6620, 8000, 9600, 11025, 13240, 16000, 22050, 32000,
  1203. 44100, 48000, 66200 };
  1204. static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
  1205. .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
  1206. .list = snd_azf3328_fixed_rates,
  1207. .mask = 0,
  1208. };
  1209. /*****************************************************************/
  1210. static int
  1211. snd_azf3328_playback_open(struct snd_pcm_substream *substream)
  1212. {
  1213. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1214. struct snd_pcm_runtime *runtime = substream->runtime;
  1215. snd_azf3328_dbgcallenter();
  1216. chip->playback_substream = substream;
  1217. runtime->hw = snd_azf3328_playback;
  1218. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1219. &snd_azf3328_hw_constraints_rates);
  1220. snd_azf3328_dbgcallleave();
  1221. return 0;
  1222. }
  1223. static int
  1224. snd_azf3328_capture_open(struct snd_pcm_substream *substream)
  1225. {
  1226. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1227. struct snd_pcm_runtime *runtime = substream->runtime;
  1228. snd_azf3328_dbgcallenter();
  1229. chip->capture_substream = substream;
  1230. runtime->hw = snd_azf3328_capture;
  1231. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1232. &snd_azf3328_hw_constraints_rates);
  1233. snd_azf3328_dbgcallleave();
  1234. return 0;
  1235. }
  1236. static int
  1237. snd_azf3328_playback_close(struct snd_pcm_substream *substream)
  1238. {
  1239. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1240. snd_azf3328_dbgcallenter();
  1241. chip->playback_substream = NULL;
  1242. snd_azf3328_dbgcallleave();
  1243. return 0;
  1244. }
  1245. static int
  1246. snd_azf3328_capture_close(struct snd_pcm_substream *substream)
  1247. {
  1248. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1249. snd_azf3328_dbgcallenter();
  1250. chip->capture_substream = NULL;
  1251. snd_azf3328_dbgcallleave();
  1252. return 0;
  1253. }
  1254. /******************************************************************/
  1255. static struct snd_pcm_ops snd_azf3328_playback_ops = {
  1256. .open = snd_azf3328_playback_open,
  1257. .close = snd_azf3328_playback_close,
  1258. .ioctl = snd_pcm_lib_ioctl,
  1259. .hw_params = snd_azf3328_hw_params,
  1260. .hw_free = snd_azf3328_hw_free,
  1261. .prepare = snd_azf3328_playback_prepare,
  1262. .trigger = snd_azf3328_playback_trigger,
  1263. .pointer = snd_azf3328_playback_pointer
  1264. };
  1265. static struct snd_pcm_ops snd_azf3328_capture_ops = {
  1266. .open = snd_azf3328_capture_open,
  1267. .close = snd_azf3328_capture_close,
  1268. .ioctl = snd_pcm_lib_ioctl,
  1269. .hw_params = snd_azf3328_hw_params,
  1270. .hw_free = snd_azf3328_hw_free,
  1271. .prepare = snd_azf3328_capture_prepare,
  1272. .trigger = snd_azf3328_capture_trigger,
  1273. .pointer = snd_azf3328_capture_pointer
  1274. };
  1275. static int __devinit
  1276. snd_azf3328_pcm(struct snd_azf3328 *chip, int device)
  1277. {
  1278. struct snd_pcm *pcm;
  1279. int err;
  1280. snd_azf3328_dbgcallenter();
  1281. if ((err = snd_pcm_new(chip->card, "AZF3328 DSP", device, 1, 1, &pcm)) < 0)
  1282. return err;
  1283. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_playback_ops);
  1284. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_azf3328_capture_ops);
  1285. pcm->private_data = chip;
  1286. pcm->info_flags = 0;
  1287. strcpy(pcm->name, chip->card->shortname);
  1288. chip->pcm = pcm;
  1289. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1290. snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
  1291. snd_azf3328_dbgcallleave();
  1292. return 0;
  1293. }
  1294. /******************************************************************/
  1295. #ifdef SUPPORT_JOYSTICK
  1296. static int __devinit
  1297. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev)
  1298. {
  1299. struct gameport *gp;
  1300. struct resource *r;
  1301. if (!joystick[dev])
  1302. return -ENODEV;
  1303. if (!(r = request_region(0x200, 8, "AZF3328 gameport"))) {
  1304. printk(KERN_WARNING "azt3328: cannot reserve joystick ports\n");
  1305. return -EBUSY;
  1306. }
  1307. chip->gameport = gp = gameport_allocate_port();
  1308. if (!gp) {
  1309. printk(KERN_ERR "azt3328: cannot allocate memory for gameport\n");
  1310. release_and_free_resource(r);
  1311. return -ENOMEM;
  1312. }
  1313. gameport_set_name(gp, "AZF3328 Gameport");
  1314. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1315. gameport_set_dev_parent(gp, &chip->pci->dev);
  1316. gp->io = 0x200;
  1317. gameport_set_port_data(gp, r);
  1318. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1319. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) | LEGACY_JOY);
  1320. gameport_register_port(chip->gameport);
  1321. return 0;
  1322. }
  1323. static void
  1324. snd_azf3328_free_joystick(struct snd_azf3328 *chip)
  1325. {
  1326. if (chip->gameport) {
  1327. struct resource *r = gameport_get_port_data(chip->gameport);
  1328. gameport_unregister_port(chip->gameport);
  1329. chip->gameport = NULL;
  1330. /* disable gameport */
  1331. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1332. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1333. release_and_free_resource(r);
  1334. }
  1335. }
  1336. #else
  1337. static inline int
  1338. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
  1339. static inline void
  1340. snd_azf3328_free_joystick(struct snd_azf3328 *chip) { }
  1341. #endif
  1342. /******************************************************************/
  1343. static int
  1344. snd_azf3328_free(struct snd_azf3328 *chip)
  1345. {
  1346. if (chip->irq < 0)
  1347. goto __end_hw;
  1348. /* reset (close) mixer */
  1349. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); /* first mute master volume */
  1350. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  1351. /* interrupt setup - mask everything (FIXME!) */
  1352. /* well, at least we know how to disable the timer IRQ */
  1353. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00);
  1354. synchronize_irq(chip->irq);
  1355. __end_hw:
  1356. snd_azf3328_free_joystick(chip);
  1357. if (chip->irq >= 0)
  1358. free_irq(chip->irq, (void *)chip);
  1359. pci_release_regions(chip->pci);
  1360. pci_disable_device(chip->pci);
  1361. kfree(chip);
  1362. return 0;
  1363. }
  1364. static int
  1365. snd_azf3328_dev_free(struct snd_device *device)
  1366. {
  1367. struct snd_azf3328 *chip = device->device_data;
  1368. return snd_azf3328_free(chip);
  1369. }
  1370. /******************************************************************/
  1371. /*** NOTE: the physical timer resolution actually is 1024000 ticks per second,
  1372. *** but announcing those attributes to user-space would make programs
  1373. *** configure the timer to a 1 tick value, resulting in an absolutely fatal
  1374. *** timer IRQ storm.
  1375. *** Thus I chose to announce a down-scaled virtual timer to the outside and
  1376. *** calculate real timer countdown values internally.
  1377. *** (the scale factor can be set via module parameter "seqtimer_scaling").
  1378. ***/
  1379. static int
  1380. snd_azf3328_timer_start(struct snd_timer *timer)
  1381. {
  1382. struct snd_azf3328 *chip;
  1383. unsigned long flags;
  1384. unsigned int delay;
  1385. snd_azf3328_dbgcallenter();
  1386. chip = snd_timer_chip(timer);
  1387. delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
  1388. if (delay < 49)
  1389. {
  1390. /* uhoh, that's not good, since user-space won't know about
  1391. * this timing tweak
  1392. * (we need to do it to avoid a lockup, though) */
  1393. snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
  1394. delay = 49; /* minimum time is 49 ticks */
  1395. }
  1396. snd_azf3328_dbgtimer("setting timer countdown value %d, add COUNTDOWN|IRQ\n", delay);
  1397. delay |= TIMER_ENABLE_COUNTDOWN | TIMER_ENABLE_IRQ;
  1398. spin_lock_irqsave(&chip->reg_lock, flags);
  1399. snd_azf3328_codec_outl(chip, IDX_IO_TIMER_VALUE, delay);
  1400. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1401. snd_azf3328_dbgcallleave();
  1402. return 0;
  1403. }
  1404. static int
  1405. snd_azf3328_timer_stop(struct snd_timer *timer)
  1406. {
  1407. struct snd_azf3328 *chip;
  1408. unsigned long flags;
  1409. snd_azf3328_dbgcallenter();
  1410. chip = snd_timer_chip(timer);
  1411. spin_lock_irqsave(&chip->reg_lock, flags);
  1412. /* disable timer countdown and interrupt */
  1413. /* FIXME: should we write TIMER_ACK_IRQ here? */
  1414. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0);
  1415. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1416. snd_azf3328_dbgcallleave();
  1417. return 0;
  1418. }
  1419. static int
  1420. snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
  1421. unsigned long *num, unsigned long *den)
  1422. {
  1423. snd_azf3328_dbgcallenter();
  1424. *num = 1;
  1425. *den = 1024000 / seqtimer_scaling;
  1426. snd_azf3328_dbgcallleave();
  1427. return 0;
  1428. }
  1429. static struct snd_timer_hardware snd_azf3328_timer_hw = {
  1430. .flags = SNDRV_TIMER_HW_AUTO,
  1431. .resolution = 977, /* 1000000/1024000 = 0.9765625us */
  1432. .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
  1433. .start = snd_azf3328_timer_start,
  1434. .stop = snd_azf3328_timer_stop,
  1435. .precise_resolution = snd_azf3328_timer_precise_resolution,
  1436. };
  1437. static int __devinit
  1438. snd_azf3328_timer(struct snd_azf3328 *chip, int device)
  1439. {
  1440. struct snd_timer *timer = NULL;
  1441. struct snd_timer_id tid;
  1442. int err;
  1443. snd_azf3328_dbgcallenter();
  1444. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1445. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1446. tid.card = chip->card->number;
  1447. tid.device = device;
  1448. tid.subdevice = 0;
  1449. snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
  1450. snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
  1451. if ((err = snd_timer_new(chip->card, "AZF3328", &tid, &timer)) < 0) {
  1452. goto out;
  1453. }
  1454. strcpy(timer->name, "AZF3328 timer");
  1455. timer->private_data = chip;
  1456. timer->hw = snd_azf3328_timer_hw;
  1457. chip->timer = timer;
  1458. err = 0;
  1459. out:
  1460. snd_azf3328_dbgcallleave();
  1461. return err;
  1462. }
  1463. /******************************************************************/
  1464. #if 0
  1465. /* check whether a bit can be modified */
  1466. static void
  1467. snd_azf3328_test_bit(unsigned int reg, int bit)
  1468. {
  1469. unsigned char val, valoff, valon;
  1470. val = inb(reg);
  1471. outb(val & ~(1 << bit), reg);
  1472. valoff = inb(reg);
  1473. outb(val|(1 << bit), reg);
  1474. valon = inb(reg);
  1475. outb(val, reg);
  1476. printk(KERN_ERR "reg %04x bit %d: %02x %02x %02x\n", reg, bit, val, valoff, valon);
  1477. }
  1478. #endif
  1479. static void
  1480. snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
  1481. {
  1482. #if DEBUG_MISC
  1483. u16 tmp;
  1484. snd_azf3328_dbgmisc("codec_port 0x%lx, io2_port 0x%lx, mpu_port 0x%lx, synth_port 0x%lx, mixer_port 0x%lx, irq %d\n", chip->codec_port, chip->io2_port, chip->mpu_port, chip->synth_port, chip->mixer_port, chip->irq);
  1485. snd_azf3328_dbgmisc("io2 %02x %02x %02x %02x %02x %02x\n", snd_azf3328_io2_inb(chip, 0), snd_azf3328_io2_inb(chip, 1), snd_azf3328_io2_inb(chip, 2), snd_azf3328_io2_inb(chip, 3), snd_azf3328_io2_inb(chip, 4), snd_azf3328_io2_inb(chip, 5));
  1486. for (tmp=0; tmp <= 0x01; tmp += 1)
  1487. snd_azf3328_dbgmisc("0x%02x: opl 0x%04x, mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, mpu330 0x%04x\n", tmp, inb(0x388 + tmp), inb(0x300 + tmp), inb(0x310 + tmp), inb(0x320 + tmp), inb(0x330 + tmp));
  1488. for (tmp = 0; tmp <= 0x6E; tmp += 2)
  1489. snd_azf3328_dbgmisc("0x%02x: 0x%04x\n", tmp, snd_azf3328_codec_inb(chip, tmp));
  1490. #endif
  1491. }
  1492. static int __devinit
  1493. snd_azf3328_create(struct snd_card *card,
  1494. struct pci_dev *pci,
  1495. unsigned long device_type,
  1496. struct snd_azf3328 ** rchip)
  1497. {
  1498. struct snd_azf3328 *chip;
  1499. int err;
  1500. static struct snd_device_ops ops = {
  1501. .dev_free = snd_azf3328_dev_free,
  1502. };
  1503. u16 tmp;
  1504. *rchip = NULL;
  1505. if ((err = pci_enable_device(pci)) < 0)
  1506. return err;
  1507. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1508. if (chip == NULL) {
  1509. err = -ENOMEM;
  1510. goto out_err;
  1511. }
  1512. spin_lock_init(&chip->reg_lock);
  1513. chip->card = card;
  1514. chip->pci = pci;
  1515. chip->irq = -1;
  1516. /* check if we can restrict PCI DMA transfers to 24 bits */
  1517. if (pci_set_dma_mask(pci, DMA_24BIT_MASK) < 0 ||
  1518. pci_set_consistent_dma_mask(pci, DMA_24BIT_MASK) < 0) {
  1519. snd_printk(KERN_ERR "architecture does not support 24bit PCI busmaster DMA\n");
  1520. err = -ENXIO;
  1521. goto out_err;
  1522. }
  1523. if ((err = pci_request_regions(pci, "Aztech AZF3328")) < 0) {
  1524. goto out_err;
  1525. }
  1526. chip->codec_port = pci_resource_start(pci, 0);
  1527. chip->io2_port = pci_resource_start(pci, 1);
  1528. chip->mpu_port = pci_resource_start(pci, 2);
  1529. chip->synth_port = pci_resource_start(pci, 3);
  1530. chip->mixer_port = pci_resource_start(pci, 4);
  1531. if (request_irq(pci->irq, snd_azf3328_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
  1532. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1533. err = -EBUSY;
  1534. goto out_err;
  1535. }
  1536. chip->irq = pci->irq;
  1537. pci_set_master(pci);
  1538. synchronize_irq(chip->irq);
  1539. snd_azf3328_debug_show_ports(chip);
  1540. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1541. goto out_err;
  1542. }
  1543. /* create mixer interface & switches */
  1544. if ((err = snd_azf3328_mixer_new(chip)) < 0)
  1545. goto out_err;
  1546. #if 0
  1547. /* set very low bitrate to reduce noise and power consumption? */
  1548. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT, 5512, 8, 1);
  1549. #endif
  1550. /* standard chip init stuff */
  1551. /* default IRQ init value */
  1552. tmp = DMA_PLAY_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
  1553. spin_lock_irq(&chip->reg_lock);
  1554. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_FLAGS, tmp);
  1555. snd_azf3328_codec_outb(chip, IDX_IO_REC_FLAGS, tmp);
  1556. snd_azf3328_codec_outb(chip, IDX_IO_SOMETHING_FLAGS, tmp);
  1557. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00); /* disable timer */
  1558. spin_unlock_irq(&chip->reg_lock);
  1559. snd_card_set_dev(card, &pci->dev);
  1560. *rchip = chip;
  1561. err = 0;
  1562. goto out;
  1563. out_err:
  1564. if (chip)
  1565. snd_azf3328_free(chip);
  1566. pci_disable_device(pci);
  1567. out:
  1568. return err;
  1569. }
  1570. static int __devinit
  1571. snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1572. {
  1573. static int dev;
  1574. struct snd_card *card;
  1575. struct snd_azf3328 *chip;
  1576. struct snd_opl3 *opl3;
  1577. int err;
  1578. snd_azf3328_dbgcallenter();
  1579. if (dev >= SNDRV_CARDS)
  1580. return -ENODEV;
  1581. if (!enable[dev]) {
  1582. dev++;
  1583. return -ENOENT;
  1584. }
  1585. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0 );
  1586. if (card == NULL)
  1587. return -ENOMEM;
  1588. strcpy(card->driver, "AZF3328");
  1589. strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
  1590. if ((err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip)) < 0) {
  1591. goto out_err;
  1592. }
  1593. card->private_data = chip;
  1594. if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_MPU401,
  1595. chip->mpu_port, 1, pci->irq, 0,
  1596. &chip->rmidi)) < 0) {
  1597. snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n", chip->mpu_port);
  1598. goto out_err;
  1599. }
  1600. if ((err = snd_azf3328_timer(chip, 0)) < 0) {
  1601. goto out_err;
  1602. }
  1603. if ((err = snd_azf3328_pcm(chip, 0)) < 0) {
  1604. goto out_err;
  1605. }
  1606. if (snd_opl3_create(card, chip->synth_port, chip->synth_port+2,
  1607. OPL3_HW_AUTO, 1, &opl3) < 0) {
  1608. snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
  1609. chip->synth_port, chip->synth_port+2 );
  1610. } else {
  1611. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1612. goto out_err;
  1613. }
  1614. }
  1615. opl3->private_data = chip;
  1616. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1617. card->shortname, chip->codec_port, chip->irq);
  1618. if ((err = snd_card_register(card)) < 0) {
  1619. goto out_err;
  1620. }
  1621. #ifdef MODULE
  1622. printk(
  1623. "azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168\n"
  1624. "azt3328: (hardware was completely undocumented - ZERO support from Aztech).\n"
  1625. "azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
  1626. "azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
  1627. 1024000 / seqtimer_scaling, seqtimer_scaling);
  1628. #endif
  1629. if (snd_azf3328_config_joystick(chip, dev) < 0)
  1630. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1631. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1632. pci_set_drvdata(pci, card);
  1633. dev++;
  1634. err = 0;
  1635. goto out;
  1636. out_err:
  1637. snd_card_free(card);
  1638. out:
  1639. snd_azf3328_dbgcallleave();
  1640. return err;
  1641. }
  1642. static void __devexit
  1643. snd_azf3328_remove(struct pci_dev *pci)
  1644. {
  1645. snd_azf3328_dbgcallenter();
  1646. snd_card_free(pci_get_drvdata(pci));
  1647. pci_set_drvdata(pci, NULL);
  1648. snd_azf3328_dbgcallleave();
  1649. }
  1650. #ifdef CONFIG_PM
  1651. static int
  1652. snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
  1653. {
  1654. struct snd_card *card = pci_get_drvdata(pci);
  1655. struct snd_azf3328 *chip = card->private_data;
  1656. int reg;
  1657. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1658. snd_pcm_suspend_all(chip->pcm);
  1659. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1660. chip->saved_regs_mixer[reg] = inw(chip->mixer_port + reg * 2);
  1661. /* make sure to disable master volume etc. to prevent looping sound */
  1662. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
  1663. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  1664. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1665. chip->saved_regs_codec[reg] = inw(chip->codec_port + reg * 2);
  1666. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1667. chip->saved_regs_io2[reg] = inw(chip->io2_port + reg * 2);
  1668. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1669. chip->saved_regs_mpu[reg] = inw(chip->mpu_port + reg * 2);
  1670. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1671. chip->saved_regs_synth[reg] = inw(chip->synth_port + reg * 2);
  1672. pci_set_power_state(pci, PCI_D3hot);
  1673. pci_disable_device(pci);
  1674. pci_save_state(pci);
  1675. return 0;
  1676. }
  1677. static int
  1678. snd_azf3328_resume(struct pci_dev *pci)
  1679. {
  1680. struct snd_card *card = pci_get_drvdata(pci);
  1681. struct snd_azf3328 *chip = card->private_data;
  1682. int reg;
  1683. pci_restore_state(pci);
  1684. pci_enable_device(pci);
  1685. pci_set_power_state(pci, PCI_D0);
  1686. pci_set_master(pci);
  1687. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1688. outw(chip->saved_regs_io2[reg], chip->io2_port + reg * 2);
  1689. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1690. outw(chip->saved_regs_mpu[reg], chip->mpu_port + reg * 2);
  1691. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1692. outw(chip->saved_regs_synth[reg], chip->synth_port + reg * 2);
  1693. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1694. outw(chip->saved_regs_mixer[reg], chip->mixer_port + reg * 2);
  1695. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1696. outw(chip->saved_regs_codec[reg], chip->codec_port + reg * 2);
  1697. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1698. return 0;
  1699. }
  1700. #endif
  1701. static struct pci_driver driver = {
  1702. .name = "AZF3328",
  1703. .id_table = snd_azf3328_ids,
  1704. .probe = snd_azf3328_probe,
  1705. .remove = __devexit_p(snd_azf3328_remove),
  1706. #ifdef CONFIG_PM
  1707. .suspend = snd_azf3328_suspend,
  1708. .resume = snd_azf3328_resume,
  1709. #endif
  1710. };
  1711. static int __init
  1712. alsa_card_azf3328_init(void)
  1713. {
  1714. int err;
  1715. snd_azf3328_dbgcallenter();
  1716. err = pci_register_driver(&driver);
  1717. snd_azf3328_dbgcallleave();
  1718. return err;
  1719. }
  1720. static void __exit
  1721. alsa_card_azf3328_exit(void)
  1722. {
  1723. snd_azf3328_dbgcallenter();
  1724. pci_unregister_driver(&driver);
  1725. snd_azf3328_dbgcallleave();
  1726. }
  1727. module_init(alsa_card_azf3328_init)
  1728. module_exit(alsa_card_azf3328_exit)