paging_tmpl.h 13 KB

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  1. /*
  2. * Kernel-based Virtual Machine driver for Linux
  3. *
  4. * This module enables machines with Intel VT-x extensions to run virtual
  5. * machines without emulation or binary translation.
  6. *
  7. * MMU support
  8. *
  9. * Copyright (C) 2006 Qumranet, Inc.
  10. *
  11. * Authors:
  12. * Yaniv Kamay <yaniv@qumranet.com>
  13. * Avi Kivity <avi@qumranet.com>
  14. *
  15. * This work is licensed under the terms of the GNU GPL, version 2. See
  16. * the COPYING file in the top-level directory.
  17. *
  18. */
  19. /*
  20. * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  21. * so the code in this file is compiled twice, once per pte size.
  22. */
  23. #if PTTYPE == 64
  24. #define pt_element_t u64
  25. #define guest_walker guest_walker64
  26. #define FNAME(name) paging##64_##name
  27. #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  28. #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
  29. #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  30. #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  31. #define PT_LEVEL_BITS PT64_LEVEL_BITS
  32. #ifdef CONFIG_X86_64
  33. #define PT_MAX_FULL_LEVELS 4
  34. #define CMPXCHG cmpxchg
  35. #else
  36. #define CMPXCHG cmpxchg64
  37. #define PT_MAX_FULL_LEVELS 2
  38. #endif
  39. #elif PTTYPE == 32
  40. #define pt_element_t u32
  41. #define guest_walker guest_walker32
  42. #define FNAME(name) paging##32_##name
  43. #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  44. #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
  45. #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  46. #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  47. #define PT_LEVEL_BITS PT32_LEVEL_BITS
  48. #define PT_MAX_FULL_LEVELS 2
  49. #define CMPXCHG cmpxchg
  50. #else
  51. #error Invalid PTTYPE value
  52. #endif
  53. #define gpte_to_gfn FNAME(gpte_to_gfn)
  54. #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
  55. /*
  56. * The guest_walker structure emulates the behavior of the hardware page
  57. * table walker.
  58. */
  59. struct guest_walker {
  60. int level;
  61. gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  62. pt_element_t ptes[PT_MAX_FULL_LEVELS];
  63. gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
  64. unsigned pt_access;
  65. unsigned pte_access;
  66. gfn_t gfn;
  67. u32 error_code;
  68. };
  69. static gfn_t gpte_to_gfn(pt_element_t gpte)
  70. {
  71. return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
  72. }
  73. static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
  74. {
  75. return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
  76. }
  77. static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
  78. gfn_t table_gfn, unsigned index,
  79. pt_element_t orig_pte, pt_element_t new_pte)
  80. {
  81. pt_element_t ret;
  82. pt_element_t *table;
  83. struct page *page;
  84. down_read(&current->mm->mmap_sem);
  85. page = gfn_to_page(kvm, table_gfn);
  86. up_read(&current->mm->mmap_sem);
  87. table = kmap_atomic(page, KM_USER0);
  88. ret = CMPXCHG(&table[index], orig_pte, new_pte);
  89. kunmap_atomic(table, KM_USER0);
  90. kvm_release_page_dirty(page);
  91. return (ret != orig_pte);
  92. }
  93. static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
  94. {
  95. unsigned access;
  96. access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
  97. #if PTTYPE == 64
  98. if (is_nx(vcpu))
  99. access &= ~(gpte >> PT64_NX_SHIFT);
  100. #endif
  101. return access;
  102. }
  103. /*
  104. * Fetch a guest pte for a guest virtual address
  105. */
  106. static int FNAME(walk_addr)(struct guest_walker *walker,
  107. struct kvm_vcpu *vcpu, gva_t addr,
  108. int write_fault, int user_fault, int fetch_fault)
  109. {
  110. pt_element_t pte;
  111. gfn_t table_gfn;
  112. unsigned index, pt_access, pte_access;
  113. gpa_t pte_gpa;
  114. pgprintk("%s: addr %lx\n", __func__, addr);
  115. walk:
  116. walker->level = vcpu->arch.mmu.root_level;
  117. pte = vcpu->arch.cr3;
  118. #if PTTYPE == 64
  119. if (!is_long_mode(vcpu)) {
  120. pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
  121. if (!is_present_pte(pte))
  122. goto not_present;
  123. --walker->level;
  124. }
  125. #endif
  126. ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
  127. (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
  128. pt_access = ACC_ALL;
  129. for (;;) {
  130. index = PT_INDEX(addr, walker->level);
  131. table_gfn = gpte_to_gfn(pte);
  132. pte_gpa = gfn_to_gpa(table_gfn);
  133. pte_gpa += index * sizeof(pt_element_t);
  134. walker->table_gfn[walker->level - 1] = table_gfn;
  135. walker->pte_gpa[walker->level - 1] = pte_gpa;
  136. pgprintk("%s: table_gfn[%d] %lx\n", __func__,
  137. walker->level - 1, table_gfn);
  138. kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
  139. if (!is_present_pte(pte))
  140. goto not_present;
  141. if (write_fault && !is_writeble_pte(pte))
  142. if (user_fault || is_write_protection(vcpu))
  143. goto access_error;
  144. if (user_fault && !(pte & PT_USER_MASK))
  145. goto access_error;
  146. #if PTTYPE == 64
  147. if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
  148. goto access_error;
  149. #endif
  150. if (!(pte & PT_ACCESSED_MASK)) {
  151. mark_page_dirty(vcpu->kvm, table_gfn);
  152. if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
  153. index, pte, pte|PT_ACCESSED_MASK))
  154. goto walk;
  155. pte |= PT_ACCESSED_MASK;
  156. }
  157. pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
  158. walker->ptes[walker->level - 1] = pte;
  159. if (walker->level == PT_PAGE_TABLE_LEVEL) {
  160. walker->gfn = gpte_to_gfn(pte);
  161. break;
  162. }
  163. if (walker->level == PT_DIRECTORY_LEVEL
  164. && (pte & PT_PAGE_SIZE_MASK)
  165. && (PTTYPE == 64 || is_pse(vcpu))) {
  166. walker->gfn = gpte_to_gfn_pde(pte);
  167. walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
  168. if (PTTYPE == 32 && is_cpuid_PSE36())
  169. walker->gfn += pse36_gfn_delta(pte);
  170. break;
  171. }
  172. pt_access = pte_access;
  173. --walker->level;
  174. }
  175. if (write_fault && !is_dirty_pte(pte)) {
  176. bool ret;
  177. mark_page_dirty(vcpu->kvm, table_gfn);
  178. ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
  179. pte|PT_DIRTY_MASK);
  180. if (ret)
  181. goto walk;
  182. pte |= PT_DIRTY_MASK;
  183. kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
  184. walker->ptes[walker->level - 1] = pte;
  185. }
  186. walker->pt_access = pt_access;
  187. walker->pte_access = pte_access;
  188. pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
  189. __func__, (u64)pte, pt_access, pte_access);
  190. return 1;
  191. not_present:
  192. walker->error_code = 0;
  193. goto err;
  194. access_error:
  195. walker->error_code = PFERR_PRESENT_MASK;
  196. err:
  197. if (write_fault)
  198. walker->error_code |= PFERR_WRITE_MASK;
  199. if (user_fault)
  200. walker->error_code |= PFERR_USER_MASK;
  201. if (fetch_fault)
  202. walker->error_code |= PFERR_FETCH_MASK;
  203. return 0;
  204. }
  205. static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
  206. u64 *spte, const void *pte)
  207. {
  208. pt_element_t gpte;
  209. unsigned pte_access;
  210. pfn_t pfn;
  211. int largepage = vcpu->arch.update_pte.largepage;
  212. gpte = *(const pt_element_t *)pte;
  213. if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
  214. if (!is_present_pte(gpte))
  215. set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
  216. return;
  217. }
  218. pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
  219. pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
  220. if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
  221. return;
  222. pfn = vcpu->arch.update_pte.pfn;
  223. if (is_error_pfn(pfn))
  224. return;
  225. if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
  226. return;
  227. kvm_get_pfn(pfn);
  228. mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
  229. gpte & PT_DIRTY_MASK, NULL, largepage, gpte_to_gfn(gpte),
  230. pfn, true);
  231. }
  232. /*
  233. * Fetch a shadow pte for a specific level in the paging hierarchy.
  234. */
  235. static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
  236. struct guest_walker *walker,
  237. int user_fault, int write_fault, int largepage,
  238. int *ptwrite, pfn_t pfn)
  239. {
  240. hpa_t shadow_addr;
  241. int level;
  242. u64 *shadow_ent;
  243. unsigned access = walker->pt_access;
  244. if (!is_present_pte(walker->ptes[walker->level - 1]))
  245. return NULL;
  246. shadow_addr = vcpu->arch.mmu.root_hpa;
  247. level = vcpu->arch.mmu.shadow_root_level;
  248. if (level == PT32E_ROOT_LEVEL) {
  249. shadow_addr = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
  250. shadow_addr &= PT64_BASE_ADDR_MASK;
  251. --level;
  252. }
  253. for (; ; level--) {
  254. u32 index = SHADOW_PT_INDEX(addr, level);
  255. struct kvm_mmu_page *shadow_page;
  256. u64 shadow_pte;
  257. int metaphysical;
  258. gfn_t table_gfn;
  259. shadow_ent = ((u64 *)__va(shadow_addr)) + index;
  260. if (level == PT_PAGE_TABLE_LEVEL)
  261. break;
  262. if (largepage && level == PT_DIRECTORY_LEVEL)
  263. break;
  264. if (is_shadow_present_pte(*shadow_ent)
  265. && !is_large_pte(*shadow_ent)) {
  266. shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
  267. continue;
  268. }
  269. if (is_large_pte(*shadow_ent))
  270. rmap_remove(vcpu->kvm, shadow_ent);
  271. if (level - 1 == PT_PAGE_TABLE_LEVEL
  272. && walker->level == PT_DIRECTORY_LEVEL) {
  273. metaphysical = 1;
  274. if (!is_dirty_pte(walker->ptes[level - 1]))
  275. access &= ~ACC_WRITE_MASK;
  276. table_gfn = gpte_to_gfn(walker->ptes[level - 1]);
  277. } else {
  278. metaphysical = 0;
  279. table_gfn = walker->table_gfn[level - 2];
  280. }
  281. shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
  282. metaphysical, access,
  283. shadow_ent);
  284. if (!metaphysical) {
  285. int r;
  286. pt_element_t curr_pte;
  287. r = kvm_read_guest_atomic(vcpu->kvm,
  288. walker->pte_gpa[level - 2],
  289. &curr_pte, sizeof(curr_pte));
  290. if (r || curr_pte != walker->ptes[level - 2]) {
  291. kvm_release_pfn_clean(pfn);
  292. return NULL;
  293. }
  294. }
  295. shadow_addr = __pa(shadow_page->spt);
  296. shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
  297. | PT_WRITABLE_MASK | PT_USER_MASK;
  298. set_shadow_pte(shadow_ent, shadow_pte);
  299. }
  300. mmu_set_spte(vcpu, shadow_ent, access, walker->pte_access & access,
  301. user_fault, write_fault,
  302. walker->ptes[walker->level-1] & PT_DIRTY_MASK,
  303. ptwrite, largepage, walker->gfn, pfn, false);
  304. return shadow_ent;
  305. }
  306. /*
  307. * Page fault handler. There are several causes for a page fault:
  308. * - there is no shadow pte for the guest pte
  309. * - write access through a shadow pte marked read only so that we can set
  310. * the dirty bit
  311. * - write access to a shadow pte marked read only so we can update the page
  312. * dirty bitmap, when userspace requests it
  313. * - mmio access; in this case we will never install a present shadow pte
  314. * - normal guest page fault due to the guest pte marked not present, not
  315. * writable, or not executable
  316. *
  317. * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
  318. * a negative value on error.
  319. */
  320. static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
  321. u32 error_code)
  322. {
  323. int write_fault = error_code & PFERR_WRITE_MASK;
  324. int user_fault = error_code & PFERR_USER_MASK;
  325. int fetch_fault = error_code & PFERR_FETCH_MASK;
  326. struct guest_walker walker;
  327. u64 *shadow_pte;
  328. int write_pt = 0;
  329. int r;
  330. pfn_t pfn;
  331. int largepage = 0;
  332. unsigned long mmu_seq;
  333. pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
  334. kvm_mmu_audit(vcpu, "pre page fault");
  335. r = mmu_topup_memory_caches(vcpu);
  336. if (r)
  337. return r;
  338. /*
  339. * Look up the shadow pte for the faulting address.
  340. */
  341. r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
  342. fetch_fault);
  343. /*
  344. * The page is not mapped by the guest. Let the guest handle it.
  345. */
  346. if (!r) {
  347. pgprintk("%s: guest page fault\n", __func__);
  348. inject_page_fault(vcpu, addr, walker.error_code);
  349. vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
  350. return 0;
  351. }
  352. down_read(&current->mm->mmap_sem);
  353. if (walker.level == PT_DIRECTORY_LEVEL) {
  354. gfn_t large_gfn;
  355. large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
  356. if (is_largepage_backed(vcpu, large_gfn)) {
  357. walker.gfn = large_gfn;
  358. largepage = 1;
  359. }
  360. }
  361. mmu_seq = vcpu->kvm->mmu_notifier_seq;
  362. /* implicit mb(), we'll read before PT lock is unlocked */
  363. pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
  364. up_read(&current->mm->mmap_sem);
  365. /* mmio */
  366. if (is_error_pfn(pfn)) {
  367. pgprintk("gfn %lx is mmio\n", walker.gfn);
  368. kvm_release_pfn_clean(pfn);
  369. return 1;
  370. }
  371. spin_lock(&vcpu->kvm->mmu_lock);
  372. if (mmu_notifier_retry(vcpu, mmu_seq))
  373. goto out_unlock;
  374. kvm_mmu_free_some_pages(vcpu);
  375. shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
  376. largepage, &write_pt, pfn);
  377. pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
  378. shadow_pte, *shadow_pte, write_pt);
  379. if (!write_pt)
  380. vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
  381. ++vcpu->stat.pf_fixed;
  382. kvm_mmu_audit(vcpu, "post page fault (fixed)");
  383. spin_unlock(&vcpu->kvm->mmu_lock);
  384. return write_pt;
  385. out_unlock:
  386. spin_unlock(&vcpu->kvm->mmu_lock);
  387. kvm_release_pfn_clean(pfn);
  388. return 0;
  389. }
  390. static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
  391. {
  392. struct guest_walker walker;
  393. gpa_t gpa = UNMAPPED_GVA;
  394. int r;
  395. r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
  396. if (r) {
  397. gpa = gfn_to_gpa(walker.gfn);
  398. gpa |= vaddr & ~PAGE_MASK;
  399. }
  400. return gpa;
  401. }
  402. static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
  403. struct kvm_mmu_page *sp)
  404. {
  405. int i, j, offset, r;
  406. pt_element_t pt[256 / sizeof(pt_element_t)];
  407. gpa_t pte_gpa;
  408. if (sp->role.metaphysical
  409. || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
  410. nonpaging_prefetch_page(vcpu, sp);
  411. return;
  412. }
  413. pte_gpa = gfn_to_gpa(sp->gfn);
  414. if (PTTYPE == 32) {
  415. offset = sp->role.quadrant << PT64_LEVEL_BITS;
  416. pte_gpa += offset * sizeof(pt_element_t);
  417. }
  418. for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
  419. r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
  420. pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
  421. for (j = 0; j < ARRAY_SIZE(pt); ++j)
  422. if (r || is_present_pte(pt[j]))
  423. sp->spt[i+j] = shadow_trap_nonpresent_pte;
  424. else
  425. sp->spt[i+j] = shadow_notrap_nonpresent_pte;
  426. }
  427. }
  428. #undef pt_element_t
  429. #undef guest_walker
  430. #undef FNAME
  431. #undef PT_BASE_ADDR_MASK
  432. #undef PT_INDEX
  433. #undef PT_LEVEL_MASK
  434. #undef PT_DIR_BASE_ADDR_MASK
  435. #undef PT_LEVEL_BITS
  436. #undef PT_MAX_FULL_LEVELS
  437. #undef gpte_to_gfn
  438. #undef gpte_to_gfn_pde
  439. #undef CMPXCHG