qla_os.c 110 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222
  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/moduleparam.h>
  9. #include <linux/vmalloc.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/mutex.h>
  13. #include <linux/kobject.h>
  14. #include <linux/slab.h>
  15. #include <scsi/scsi_tcq.h>
  16. #include <scsi/scsicam.h>
  17. #include <scsi/scsi_transport.h>
  18. #include <scsi/scsi_transport_fc.h>
  19. /*
  20. * Driver version
  21. */
  22. char qla2x00_version_str[40];
  23. static int apidev_major;
  24. /*
  25. * SRB allocation cache
  26. */
  27. static struct kmem_cache *srb_cachep;
  28. /*
  29. * CT6 CTX allocation cache
  30. */
  31. static struct kmem_cache *ctx_cachep;
  32. int ql2xlogintimeout = 20;
  33. module_param(ql2xlogintimeout, int, S_IRUGO);
  34. MODULE_PARM_DESC(ql2xlogintimeout,
  35. "Login timeout value in seconds.");
  36. int qlport_down_retry;
  37. module_param(qlport_down_retry, int, S_IRUGO);
  38. MODULE_PARM_DESC(qlport_down_retry,
  39. "Maximum number of command retries to a port that returns "
  40. "a PORT-DOWN status.");
  41. int ql2xplogiabsentdevice;
  42. module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  43. MODULE_PARM_DESC(ql2xplogiabsentdevice,
  44. "Option to enable PLOGI to devices that are not present after "
  45. "a Fabric scan. This is needed for several broken switches. "
  46. "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  47. int ql2xloginretrycount = 0;
  48. module_param(ql2xloginretrycount, int, S_IRUGO);
  49. MODULE_PARM_DESC(ql2xloginretrycount,
  50. "Specify an alternate value for the NVRAM login retry count.");
  51. int ql2xallocfwdump = 1;
  52. module_param(ql2xallocfwdump, int, S_IRUGO);
  53. MODULE_PARM_DESC(ql2xallocfwdump,
  54. "Option to enable allocation of memory for a firmware dump "
  55. "during HBA initialization. Memory allocation requirements "
  56. "vary by ISP type. Default is 1 - allocate memory.");
  57. int ql2xextended_error_logging;
  58. module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  59. MODULE_PARM_DESC(ql2xextended_error_logging,
  60. "Option to enable extended error logging, "
  61. "Default is 0 - no logging. 1 - log errors.");
  62. int ql2xshiftctondsd = 6;
  63. module_param(ql2xshiftctondsd, int, S_IRUGO);
  64. MODULE_PARM_DESC(ql2xshiftctondsd,
  65. "Set to control shifting of command type processing "
  66. "based on total number of SG elements.");
  67. static void qla2x00_free_device(scsi_qla_host_t *);
  68. int ql2xfdmienable=1;
  69. module_param(ql2xfdmienable, int, S_IRUGO);
  70. MODULE_PARM_DESC(ql2xfdmienable,
  71. "Enables FDMI registrations. "
  72. "0 - no FDMI. Default is 1 - perform FDMI.");
  73. #define MAX_Q_DEPTH 32
  74. static int ql2xmaxqdepth = MAX_Q_DEPTH;
  75. module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
  76. MODULE_PARM_DESC(ql2xmaxqdepth,
  77. "Maximum queue depth to report for target devices.");
  78. /* Do not change the value of this after module load */
  79. int ql2xenabledif = 1;
  80. module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
  81. MODULE_PARM_DESC(ql2xenabledif,
  82. " Enable T10-CRC-DIF "
  83. " Default is 0 - No DIF Support. 1 - Enable it");
  84. int ql2xenablehba_err_chk;
  85. module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
  86. MODULE_PARM_DESC(ql2xenablehba_err_chk,
  87. " Enable T10-CRC-DIF Error isolation by HBA"
  88. " Default is 0 - Error isolation disabled, 1 - Enable it");
  89. int ql2xiidmaenable=1;
  90. module_param(ql2xiidmaenable, int, S_IRUGO);
  91. MODULE_PARM_DESC(ql2xiidmaenable,
  92. "Enables iIDMA settings "
  93. "Default is 1 - perform iIDMA. 0 - no iIDMA.");
  94. int ql2xmaxqueues = 1;
  95. module_param(ql2xmaxqueues, int, S_IRUGO);
  96. MODULE_PARM_DESC(ql2xmaxqueues,
  97. "Enables MQ settings "
  98. "Default is 1 for single queue. Set it to number "
  99. "of queues in MQ mode.");
  100. int ql2xmultique_tag;
  101. module_param(ql2xmultique_tag, int, S_IRUGO);
  102. MODULE_PARM_DESC(ql2xmultique_tag,
  103. "Enables CPU affinity settings for the driver "
  104. "Default is 0 for no affinity of request and response IO. "
  105. "Set it to 1 to turn on the cpu affinity.");
  106. int ql2xfwloadbin;
  107. module_param(ql2xfwloadbin, int, S_IRUGO);
  108. MODULE_PARM_DESC(ql2xfwloadbin,
  109. "Option to specify location from which to load ISP firmware:\n"
  110. " 2 -- load firmware via the request_firmware() (hotplug)\n"
  111. " interface.\n"
  112. " 1 -- load firmware from flash.\n"
  113. " 0 -- use default semantics.\n");
  114. int ql2xetsenable;
  115. module_param(ql2xetsenable, int, S_IRUGO);
  116. MODULE_PARM_DESC(ql2xetsenable,
  117. "Enables firmware ETS burst."
  118. "Default is 0 - skip ETS enablement.");
  119. int ql2xdbwr = 1;
  120. module_param(ql2xdbwr, int, S_IRUGO);
  121. MODULE_PARM_DESC(ql2xdbwr,
  122. "Option to specify scheme for request queue posting\n"
  123. " 0 -- Regular doorbell.\n"
  124. " 1 -- CAMRAM doorbell (faster).\n");
  125. int ql2xtargetreset = 1;
  126. module_param(ql2xtargetreset, int, S_IRUGO);
  127. MODULE_PARM_DESC(ql2xtargetreset,
  128. "Enable target reset."
  129. "Default is 1 - use hw defaults.");
  130. int ql2xgffidenable;
  131. module_param(ql2xgffidenable, int, S_IRUGO);
  132. MODULE_PARM_DESC(ql2xgffidenable,
  133. "Enables GFF_ID checks of port type. "
  134. "Default is 0 - Do not use GFF_ID information.");
  135. int ql2xasynctmfenable;
  136. module_param(ql2xasynctmfenable, int, S_IRUGO);
  137. MODULE_PARM_DESC(ql2xasynctmfenable,
  138. "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
  139. "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
  140. int ql2xdontresethba;
  141. module_param(ql2xdontresethba, int, S_IRUGO);
  142. MODULE_PARM_DESC(ql2xdontresethba,
  143. "Option to specify reset behaviour\n"
  144. " 0 (Default) -- Reset on failure.\n"
  145. " 1 -- Do not reset on failure.\n");
  146. /*
  147. * SCSI host template entry points
  148. */
  149. static int qla2xxx_slave_configure(struct scsi_device * device);
  150. static int qla2xxx_slave_alloc(struct scsi_device *);
  151. static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
  152. static void qla2xxx_scan_start(struct Scsi_Host *);
  153. static void qla2xxx_slave_destroy(struct scsi_device *);
  154. static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  155. static int qla2xxx_eh_abort(struct scsi_cmnd *);
  156. static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
  157. static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
  158. static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
  159. static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
  160. static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
  161. static int qla2x00_change_queue_type(struct scsi_device *, int);
  162. struct scsi_host_template qla2xxx_driver_template = {
  163. .module = THIS_MODULE,
  164. .name = QLA2XXX_DRIVER_NAME,
  165. .queuecommand = qla2xxx_queuecommand,
  166. .eh_abort_handler = qla2xxx_eh_abort,
  167. .eh_device_reset_handler = qla2xxx_eh_device_reset,
  168. .eh_target_reset_handler = qla2xxx_eh_target_reset,
  169. .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
  170. .eh_host_reset_handler = qla2xxx_eh_host_reset,
  171. .slave_configure = qla2xxx_slave_configure,
  172. .slave_alloc = qla2xxx_slave_alloc,
  173. .slave_destroy = qla2xxx_slave_destroy,
  174. .scan_finished = qla2xxx_scan_finished,
  175. .scan_start = qla2xxx_scan_start,
  176. .change_queue_depth = qla2x00_change_queue_depth,
  177. .change_queue_type = qla2x00_change_queue_type,
  178. .this_id = -1,
  179. .cmd_per_lun = 3,
  180. .use_clustering = ENABLE_CLUSTERING,
  181. .sg_tablesize = SG_ALL,
  182. .max_sectors = 0xFFFF,
  183. .shost_attrs = qla2x00_host_attrs,
  184. };
  185. static struct scsi_transport_template *qla2xxx_transport_template = NULL;
  186. struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
  187. /* TODO Convert to inlines
  188. *
  189. * Timer routines
  190. */
  191. __inline__ void
  192. qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
  193. {
  194. init_timer(&vha->timer);
  195. vha->timer.expires = jiffies + interval * HZ;
  196. vha->timer.data = (unsigned long)vha;
  197. vha->timer.function = (void (*)(unsigned long))func;
  198. add_timer(&vha->timer);
  199. vha->timer_active = 1;
  200. }
  201. static inline void
  202. qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
  203. {
  204. /* Currently used for 82XX only. */
  205. if (vha->device_flags & DFLG_DEV_FAILED)
  206. return;
  207. mod_timer(&vha->timer, jiffies + interval * HZ);
  208. }
  209. static __inline__ void
  210. qla2x00_stop_timer(scsi_qla_host_t *vha)
  211. {
  212. del_timer_sync(&vha->timer);
  213. vha->timer_active = 0;
  214. }
  215. static int qla2x00_do_dpc(void *data);
  216. static void qla2x00_rst_aen(scsi_qla_host_t *);
  217. static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
  218. struct req_que **, struct rsp_que **);
  219. static void qla2x00_free_fw_dump(struct qla_hw_data *);
  220. static void qla2x00_mem_free(struct qla_hw_data *);
  221. static void qla2x00_sp_free_dma(srb_t *);
  222. /* -------------------------------------------------------------------------- */
  223. static int qla2x00_alloc_queues(struct qla_hw_data *ha)
  224. {
  225. ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
  226. GFP_KERNEL);
  227. if (!ha->req_q_map) {
  228. qla_printk(KERN_WARNING, ha,
  229. "Unable to allocate memory for request queue ptrs\n");
  230. goto fail_req_map;
  231. }
  232. ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
  233. GFP_KERNEL);
  234. if (!ha->rsp_q_map) {
  235. qla_printk(KERN_WARNING, ha,
  236. "Unable to allocate memory for response queue ptrs\n");
  237. goto fail_rsp_map;
  238. }
  239. set_bit(0, ha->rsp_qid_map);
  240. set_bit(0, ha->req_qid_map);
  241. return 1;
  242. fail_rsp_map:
  243. kfree(ha->req_q_map);
  244. ha->req_q_map = NULL;
  245. fail_req_map:
  246. return -ENOMEM;
  247. }
  248. static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
  249. {
  250. if (req && req->ring)
  251. dma_free_coherent(&ha->pdev->dev,
  252. (req->length + 1) * sizeof(request_t),
  253. req->ring, req->dma);
  254. kfree(req);
  255. req = NULL;
  256. }
  257. static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
  258. {
  259. if (rsp && rsp->ring)
  260. dma_free_coherent(&ha->pdev->dev,
  261. (rsp->length + 1) * sizeof(response_t),
  262. rsp->ring, rsp->dma);
  263. kfree(rsp);
  264. rsp = NULL;
  265. }
  266. static void qla2x00_free_queues(struct qla_hw_data *ha)
  267. {
  268. struct req_que *req;
  269. struct rsp_que *rsp;
  270. int cnt;
  271. for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
  272. req = ha->req_q_map[cnt];
  273. qla2x00_free_req_que(ha, req);
  274. }
  275. kfree(ha->req_q_map);
  276. ha->req_q_map = NULL;
  277. for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
  278. rsp = ha->rsp_q_map[cnt];
  279. qla2x00_free_rsp_que(ha, rsp);
  280. }
  281. kfree(ha->rsp_q_map);
  282. ha->rsp_q_map = NULL;
  283. }
  284. static int qla25xx_setup_mode(struct scsi_qla_host *vha)
  285. {
  286. uint16_t options = 0;
  287. int ques, req, ret;
  288. struct qla_hw_data *ha = vha->hw;
  289. if (!(ha->fw_attributes & BIT_6)) {
  290. qla_printk(KERN_INFO, ha,
  291. "Firmware is not multi-queue capable\n");
  292. goto fail;
  293. }
  294. if (ql2xmultique_tag) {
  295. /* create a request queue for IO */
  296. options |= BIT_7;
  297. req = qla25xx_create_req_que(ha, options, 0, 0, -1,
  298. QLA_DEFAULT_QUE_QOS);
  299. if (!req) {
  300. qla_printk(KERN_WARNING, ha,
  301. "Can't create request queue\n");
  302. goto fail;
  303. }
  304. ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
  305. vha->req = ha->req_q_map[req];
  306. options |= BIT_1;
  307. for (ques = 1; ques < ha->max_rsp_queues; ques++) {
  308. ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
  309. if (!ret) {
  310. qla_printk(KERN_WARNING, ha,
  311. "Response Queue create failed\n");
  312. goto fail2;
  313. }
  314. }
  315. ha->flags.cpu_affinity_enabled = 1;
  316. DEBUG2(qla_printk(KERN_INFO, ha,
  317. "CPU affinity mode enabled, no. of response"
  318. " queues:%d, no. of request queues:%d\n",
  319. ha->max_rsp_queues, ha->max_req_queues));
  320. }
  321. return 0;
  322. fail2:
  323. qla25xx_delete_queues(vha);
  324. destroy_workqueue(ha->wq);
  325. ha->wq = NULL;
  326. fail:
  327. ha->mqenable = 0;
  328. kfree(ha->req_q_map);
  329. kfree(ha->rsp_q_map);
  330. ha->max_req_queues = ha->max_rsp_queues = 1;
  331. return 1;
  332. }
  333. static char *
  334. qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
  335. {
  336. struct qla_hw_data *ha = vha->hw;
  337. static char *pci_bus_modes[] = {
  338. "33", "66", "100", "133",
  339. };
  340. uint16_t pci_bus;
  341. strcpy(str, "PCI");
  342. pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
  343. if (pci_bus) {
  344. strcat(str, "-X (");
  345. strcat(str, pci_bus_modes[pci_bus]);
  346. } else {
  347. pci_bus = (ha->pci_attr & BIT_8) >> 8;
  348. strcat(str, " (");
  349. strcat(str, pci_bus_modes[pci_bus]);
  350. }
  351. strcat(str, " MHz)");
  352. return (str);
  353. }
  354. static char *
  355. qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
  356. {
  357. static char *pci_bus_modes[] = { "33", "66", "100", "133", };
  358. struct qla_hw_data *ha = vha->hw;
  359. uint32_t pci_bus;
  360. int pcie_reg;
  361. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  362. if (pcie_reg) {
  363. char lwstr[6];
  364. uint16_t pcie_lstat, lspeed, lwidth;
  365. pcie_reg += 0x12;
  366. pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
  367. lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
  368. lwidth = (pcie_lstat &
  369. (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
  370. strcpy(str, "PCIe (");
  371. if (lspeed == 1)
  372. strcat(str, "2.5GT/s ");
  373. else if (lspeed == 2)
  374. strcat(str, "5.0GT/s ");
  375. else
  376. strcat(str, "<unknown> ");
  377. snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
  378. strcat(str, lwstr);
  379. return str;
  380. }
  381. strcpy(str, "PCI");
  382. pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
  383. if (pci_bus == 0 || pci_bus == 8) {
  384. strcat(str, " (");
  385. strcat(str, pci_bus_modes[pci_bus >> 3]);
  386. } else {
  387. strcat(str, "-X ");
  388. if (pci_bus & BIT_2)
  389. strcat(str, "Mode 2");
  390. else
  391. strcat(str, "Mode 1");
  392. strcat(str, " (");
  393. strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
  394. }
  395. strcat(str, " MHz)");
  396. return str;
  397. }
  398. static char *
  399. qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
  400. {
  401. char un_str[10];
  402. struct qla_hw_data *ha = vha->hw;
  403. sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
  404. ha->fw_minor_version,
  405. ha->fw_subminor_version);
  406. if (ha->fw_attributes & BIT_9) {
  407. strcat(str, "FLX");
  408. return (str);
  409. }
  410. switch (ha->fw_attributes & 0xFF) {
  411. case 0x7:
  412. strcat(str, "EF");
  413. break;
  414. case 0x17:
  415. strcat(str, "TP");
  416. break;
  417. case 0x37:
  418. strcat(str, "IP");
  419. break;
  420. case 0x77:
  421. strcat(str, "VI");
  422. break;
  423. default:
  424. sprintf(un_str, "(%x)", ha->fw_attributes);
  425. strcat(str, un_str);
  426. break;
  427. }
  428. if (ha->fw_attributes & 0x100)
  429. strcat(str, "X");
  430. return (str);
  431. }
  432. static char *
  433. qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
  434. {
  435. struct qla_hw_data *ha = vha->hw;
  436. sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
  437. ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
  438. return str;
  439. }
  440. static inline srb_t *
  441. qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
  442. struct scsi_cmnd *cmd)
  443. {
  444. srb_t *sp;
  445. struct qla_hw_data *ha = vha->hw;
  446. sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
  447. if (!sp)
  448. return sp;
  449. atomic_set(&sp->ref_count, 1);
  450. sp->fcport = fcport;
  451. sp->cmd = cmd;
  452. sp->flags = 0;
  453. CMD_SP(cmd) = (void *)sp;
  454. sp->ctx = NULL;
  455. return sp;
  456. }
  457. static int
  458. qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  459. {
  460. scsi_qla_host_t *vha = shost_priv(host);
  461. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  462. struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
  463. struct qla_hw_data *ha = vha->hw;
  464. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  465. srb_t *sp;
  466. int rval;
  467. if (ha->flags.eeh_busy) {
  468. if (ha->flags.pci_channel_io_perm_failure)
  469. cmd->result = DID_NO_CONNECT << 16;
  470. else
  471. cmd->result = DID_REQUEUE << 16;
  472. goto qc24_fail_command;
  473. }
  474. rval = fc_remote_port_chkready(rport);
  475. if (rval) {
  476. cmd->result = rval;
  477. goto qc24_fail_command;
  478. }
  479. if (!vha->flags.difdix_supported &&
  480. scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
  481. DEBUG2(qla_printk(KERN_ERR, ha,
  482. "DIF Cap Not Reg, fail DIF capable cmd's:%x\n",
  483. cmd->cmnd[0]));
  484. cmd->result = DID_NO_CONNECT << 16;
  485. goto qc24_fail_command;
  486. }
  487. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  488. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
  489. atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  490. cmd->result = DID_NO_CONNECT << 16;
  491. goto qc24_fail_command;
  492. }
  493. goto qc24_target_busy;
  494. }
  495. sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
  496. if (!sp)
  497. goto qc24_host_busy;
  498. rval = ha->isp_ops->start_scsi(sp);
  499. if (rval != QLA_SUCCESS)
  500. goto qc24_host_busy_free_sp;
  501. return 0;
  502. qc24_host_busy_free_sp:
  503. qla2x00_sp_free_dma(sp);
  504. mempool_free(sp, ha->srb_mempool);
  505. qc24_host_busy:
  506. return SCSI_MLQUEUE_HOST_BUSY;
  507. qc24_target_busy:
  508. return SCSI_MLQUEUE_TARGET_BUSY;
  509. qc24_fail_command:
  510. cmd->scsi_done(cmd);
  511. return 0;
  512. }
  513. /*
  514. * qla2x00_eh_wait_on_command
  515. * Waits for the command to be returned by the Firmware for some
  516. * max time.
  517. *
  518. * Input:
  519. * cmd = Scsi Command to wait on.
  520. *
  521. * Return:
  522. * Not Found : 0
  523. * Found : 1
  524. */
  525. static int
  526. qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
  527. {
  528. #define ABORT_POLLING_PERIOD 1000
  529. #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
  530. unsigned long wait_iter = ABORT_WAIT_ITER;
  531. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  532. struct qla_hw_data *ha = vha->hw;
  533. int ret = QLA_SUCCESS;
  534. if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
  535. DEBUG17(qla_printk(KERN_WARNING, ha, "return:eh_wait\n"));
  536. return ret;
  537. }
  538. while (CMD_SP(cmd) && wait_iter--) {
  539. msleep(ABORT_POLLING_PERIOD);
  540. }
  541. if (CMD_SP(cmd))
  542. ret = QLA_FUNCTION_FAILED;
  543. return ret;
  544. }
  545. /*
  546. * qla2x00_wait_for_hba_online
  547. * Wait till the HBA is online after going through
  548. * <= MAX_RETRIES_OF_ISP_ABORT or
  549. * finally HBA is disabled ie marked offline
  550. *
  551. * Input:
  552. * ha - pointer to host adapter structure
  553. *
  554. * Note:
  555. * Does context switching-Release SPIN_LOCK
  556. * (if any) before calling this routine.
  557. *
  558. * Return:
  559. * Success (Adapter is online) : 0
  560. * Failed (Adapter is offline/disabled) : 1
  561. */
  562. int
  563. qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
  564. {
  565. int return_status;
  566. unsigned long wait_online;
  567. struct qla_hw_data *ha = vha->hw;
  568. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  569. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  570. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  571. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  572. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  573. ha->dpc_active) && time_before(jiffies, wait_online)) {
  574. msleep(1000);
  575. }
  576. if (base_vha->flags.online)
  577. return_status = QLA_SUCCESS;
  578. else
  579. return_status = QLA_FUNCTION_FAILED;
  580. return (return_status);
  581. }
  582. /*
  583. * qla2x00_wait_for_reset_ready
  584. * Wait till the HBA is online after going through
  585. * <= MAX_RETRIES_OF_ISP_ABORT or
  586. * finally HBA is disabled ie marked offline or flash
  587. * operations are in progress.
  588. *
  589. * Input:
  590. * ha - pointer to host adapter structure
  591. *
  592. * Note:
  593. * Does context switching-Release SPIN_LOCK
  594. * (if any) before calling this routine.
  595. *
  596. * Return:
  597. * Success (Adapter is online/no flash ops) : 0
  598. * Failed (Adapter is offline/disabled/flash ops in progress) : 1
  599. */
  600. static int
  601. qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
  602. {
  603. int return_status;
  604. unsigned long wait_online;
  605. struct qla_hw_data *ha = vha->hw;
  606. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  607. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  608. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  609. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  610. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  611. ha->optrom_state != QLA_SWAITING ||
  612. ha->dpc_active) && time_before(jiffies, wait_online))
  613. msleep(1000);
  614. if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
  615. return_status = QLA_SUCCESS;
  616. else
  617. return_status = QLA_FUNCTION_FAILED;
  618. DEBUG2(printk("%s return_status=%d\n", __func__, return_status));
  619. return return_status;
  620. }
  621. int
  622. qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
  623. {
  624. int return_status;
  625. unsigned long wait_reset;
  626. struct qla_hw_data *ha = vha->hw;
  627. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  628. wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  629. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  630. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  631. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  632. ha->dpc_active) && time_before(jiffies, wait_reset)) {
  633. msleep(1000);
  634. if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
  635. ha->flags.chip_reset_done)
  636. break;
  637. }
  638. if (ha->flags.chip_reset_done)
  639. return_status = QLA_SUCCESS;
  640. else
  641. return_status = QLA_FUNCTION_FAILED;
  642. return return_status;
  643. }
  644. /*
  645. * qla2x00_wait_for_loop_ready
  646. * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
  647. * to be in LOOP_READY state.
  648. * Input:
  649. * ha - pointer to host adapter structure
  650. *
  651. * Note:
  652. * Does context switching-Release SPIN_LOCK
  653. * (if any) before calling this routine.
  654. *
  655. *
  656. * Return:
  657. * Success (LOOP_READY) : 0
  658. * Failed (LOOP_NOT_READY) : 1
  659. */
  660. static inline int
  661. qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
  662. {
  663. int return_status = QLA_SUCCESS;
  664. unsigned long loop_timeout ;
  665. struct qla_hw_data *ha = vha->hw;
  666. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  667. /* wait for 5 min at the max for loop to be ready */
  668. loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  669. while ((!atomic_read(&base_vha->loop_down_timer) &&
  670. atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
  671. atomic_read(&base_vha->loop_state) != LOOP_READY) {
  672. if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  673. return_status = QLA_FUNCTION_FAILED;
  674. break;
  675. }
  676. msleep(1000);
  677. if (time_after_eq(jiffies, loop_timeout)) {
  678. return_status = QLA_FUNCTION_FAILED;
  679. break;
  680. }
  681. }
  682. return (return_status);
  683. }
  684. static void
  685. sp_get(struct srb *sp)
  686. {
  687. atomic_inc(&sp->ref_count);
  688. }
  689. /**************************************************************************
  690. * qla2xxx_eh_abort
  691. *
  692. * Description:
  693. * The abort function will abort the specified command.
  694. *
  695. * Input:
  696. * cmd = Linux SCSI command packet to be aborted.
  697. *
  698. * Returns:
  699. * Either SUCCESS or FAILED.
  700. *
  701. * Note:
  702. * Only return FAILED if command not returned by firmware.
  703. **************************************************************************/
  704. static int
  705. qla2xxx_eh_abort(struct scsi_cmnd *cmd)
  706. {
  707. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  708. srb_t *sp;
  709. int ret;
  710. unsigned int id, lun;
  711. unsigned long flags;
  712. int wait = 0;
  713. struct qla_hw_data *ha = vha->hw;
  714. if (!CMD_SP(cmd))
  715. return SUCCESS;
  716. ret = fc_block_scsi_eh(cmd);
  717. if (ret != 0)
  718. return ret;
  719. ret = SUCCESS;
  720. id = cmd->device->id;
  721. lun = cmd->device->lun;
  722. spin_lock_irqsave(&ha->hardware_lock, flags);
  723. sp = (srb_t *) CMD_SP(cmd);
  724. if (!sp) {
  725. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  726. return SUCCESS;
  727. }
  728. DEBUG2(printk("%s(%ld): aborting sp %p from RISC.",
  729. __func__, vha->host_no, sp));
  730. /* Get a reference to the sp and drop the lock.*/
  731. sp_get(sp);
  732. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  733. if (ha->isp_ops->abort_command(sp)) {
  734. DEBUG2(printk("%s(%ld): abort_command "
  735. "mbx failed.\n", __func__, vha->host_no));
  736. ret = FAILED;
  737. } else {
  738. DEBUG3(printk("%s(%ld): abort_command "
  739. "mbx success.\n", __func__, vha->host_no));
  740. wait = 1;
  741. }
  742. qla2x00_sp_compl(ha, sp);
  743. /* Wait for the command to be returned. */
  744. if (wait) {
  745. if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
  746. qla_printk(KERN_ERR, ha,
  747. "scsi(%ld:%d:%d): Abort handler timed out -- %x.\n",
  748. vha->host_no, id, lun, ret);
  749. ret = FAILED;
  750. }
  751. }
  752. qla_printk(KERN_INFO, ha,
  753. "scsi(%ld:%d:%d): Abort command issued -- %d %x.\n",
  754. vha->host_no, id, lun, wait, ret);
  755. return ret;
  756. }
  757. int
  758. qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
  759. unsigned int l, enum nexus_wait_type type)
  760. {
  761. int cnt, match, status;
  762. unsigned long flags;
  763. struct qla_hw_data *ha = vha->hw;
  764. struct req_que *req;
  765. srb_t *sp;
  766. status = QLA_SUCCESS;
  767. spin_lock_irqsave(&ha->hardware_lock, flags);
  768. req = vha->req;
  769. for (cnt = 1; status == QLA_SUCCESS &&
  770. cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  771. sp = req->outstanding_cmds[cnt];
  772. if (!sp)
  773. continue;
  774. if ((sp->ctx) && !IS_PROT_IO(sp))
  775. continue;
  776. if (vha->vp_idx != sp->fcport->vha->vp_idx)
  777. continue;
  778. match = 0;
  779. switch (type) {
  780. case WAIT_HOST:
  781. match = 1;
  782. break;
  783. case WAIT_TARGET:
  784. match = sp->cmd->device->id == t;
  785. break;
  786. case WAIT_LUN:
  787. match = (sp->cmd->device->id == t &&
  788. sp->cmd->device->lun == l);
  789. break;
  790. }
  791. if (!match)
  792. continue;
  793. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  794. status = qla2x00_eh_wait_on_command(sp->cmd);
  795. spin_lock_irqsave(&ha->hardware_lock, flags);
  796. }
  797. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  798. return status;
  799. }
  800. static char *reset_errors[] = {
  801. "HBA not online",
  802. "HBA not ready",
  803. "Task management failed",
  804. "Waiting for command completions",
  805. };
  806. static int
  807. __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
  808. struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
  809. {
  810. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  811. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  812. int err;
  813. if (!fcport)
  814. return FAILED;
  815. err = fc_block_scsi_eh(cmd);
  816. if (err != 0)
  817. return err;
  818. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET ISSUED.\n",
  819. vha->host_no, cmd->device->id, cmd->device->lun, name);
  820. err = 0;
  821. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  822. goto eh_reset_failed;
  823. err = 1;
  824. if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS)
  825. goto eh_reset_failed;
  826. err = 2;
  827. if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
  828. != QLA_SUCCESS)
  829. goto eh_reset_failed;
  830. err = 3;
  831. if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
  832. cmd->device->lun, type) != QLA_SUCCESS)
  833. goto eh_reset_failed;
  834. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET SUCCEEDED.\n",
  835. vha->host_no, cmd->device->id, cmd->device->lun, name);
  836. return SUCCESS;
  837. eh_reset_failed:
  838. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET FAILED: %s.\n"
  839. , vha->host_no, cmd->device->id, cmd->device->lun, name,
  840. reset_errors[err]);
  841. return FAILED;
  842. }
  843. static int
  844. qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
  845. {
  846. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  847. struct qla_hw_data *ha = vha->hw;
  848. return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
  849. ha->isp_ops->lun_reset);
  850. }
  851. static int
  852. qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
  853. {
  854. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  855. struct qla_hw_data *ha = vha->hw;
  856. return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
  857. ha->isp_ops->target_reset);
  858. }
  859. /**************************************************************************
  860. * qla2xxx_eh_bus_reset
  861. *
  862. * Description:
  863. * The bus reset function will reset the bus and abort any executing
  864. * commands.
  865. *
  866. * Input:
  867. * cmd = Linux SCSI command packet of the command that cause the
  868. * bus reset.
  869. *
  870. * Returns:
  871. * SUCCESS/FAILURE (defined as macro in scsi.h).
  872. *
  873. **************************************************************************/
  874. static int
  875. qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
  876. {
  877. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  878. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  879. int ret = FAILED;
  880. unsigned int id, lun;
  881. id = cmd->device->id;
  882. lun = cmd->device->lun;
  883. if (!fcport)
  884. return ret;
  885. ret = fc_block_scsi_eh(cmd);
  886. if (ret != 0)
  887. return ret;
  888. ret = FAILED;
  889. qla_printk(KERN_INFO, vha->hw,
  890. "scsi(%ld:%d:%d): BUS RESET ISSUED.\n", vha->host_no, id, lun);
  891. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  892. DEBUG2(printk("%s failed:board disabled\n",__func__));
  893. goto eh_bus_reset_done;
  894. }
  895. if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
  896. if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
  897. ret = SUCCESS;
  898. }
  899. if (ret == FAILED)
  900. goto eh_bus_reset_done;
  901. /* Flush outstanding commands. */
  902. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
  903. QLA_SUCCESS)
  904. ret = FAILED;
  905. eh_bus_reset_done:
  906. qla_printk(KERN_INFO, vha->hw, "%s: reset %s\n", __func__,
  907. (ret == FAILED) ? "failed" : "succeeded");
  908. return ret;
  909. }
  910. /**************************************************************************
  911. * qla2xxx_eh_host_reset
  912. *
  913. * Description:
  914. * The reset function will reset the Adapter.
  915. *
  916. * Input:
  917. * cmd = Linux SCSI command packet of the command that cause the
  918. * adapter reset.
  919. *
  920. * Returns:
  921. * Either SUCCESS or FAILED.
  922. *
  923. * Note:
  924. **************************************************************************/
  925. static int
  926. qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
  927. {
  928. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  929. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  930. struct qla_hw_data *ha = vha->hw;
  931. int ret = FAILED;
  932. unsigned int id, lun;
  933. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  934. id = cmd->device->id;
  935. lun = cmd->device->lun;
  936. if (!fcport)
  937. return ret;
  938. ret = fc_block_scsi_eh(cmd);
  939. if (ret != 0)
  940. return ret;
  941. ret = FAILED;
  942. qla_printk(KERN_INFO, ha,
  943. "scsi(%ld:%d:%d): ADAPTER RESET ISSUED.\n", vha->host_no, id, lun);
  944. if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
  945. goto eh_host_reset_lock;
  946. /*
  947. * Fixme-may be dpc thread is active and processing
  948. * loop_resync,so wait a while for it to
  949. * be completed and then issue big hammer.Otherwise
  950. * it may cause I/O failure as big hammer marks the
  951. * devices as lost kicking of the port_down_timer
  952. * while dpc is stuck for the mailbox to complete.
  953. */
  954. qla2x00_wait_for_loop_ready(vha);
  955. if (vha != base_vha) {
  956. if (qla2x00_vp_abort_isp(vha))
  957. goto eh_host_reset_lock;
  958. } else {
  959. if (IS_QLA82XX(vha->hw)) {
  960. if (!qla82xx_fcoe_ctx_reset(vha)) {
  961. /* Ctx reset success */
  962. ret = SUCCESS;
  963. goto eh_host_reset_lock;
  964. }
  965. /* fall thru if ctx reset failed */
  966. }
  967. if (ha->wq)
  968. flush_workqueue(ha->wq);
  969. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  970. if (ha->isp_ops->abort_isp(base_vha)) {
  971. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  972. /* failed. schedule dpc to try */
  973. set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
  974. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  975. goto eh_host_reset_lock;
  976. }
  977. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  978. }
  979. /* Waiting for command to be returned to OS.*/
  980. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
  981. QLA_SUCCESS)
  982. ret = SUCCESS;
  983. eh_host_reset_lock:
  984. qla_printk(KERN_INFO, ha, "%s: reset %s\n", __func__,
  985. (ret == FAILED) ? "failed" : "succeeded");
  986. return ret;
  987. }
  988. /*
  989. * qla2x00_loop_reset
  990. * Issue loop reset.
  991. *
  992. * Input:
  993. * ha = adapter block pointer.
  994. *
  995. * Returns:
  996. * 0 = success
  997. */
  998. int
  999. qla2x00_loop_reset(scsi_qla_host_t *vha)
  1000. {
  1001. int ret;
  1002. struct fc_port *fcport;
  1003. struct qla_hw_data *ha = vha->hw;
  1004. if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
  1005. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1006. if (fcport->port_type != FCT_TARGET)
  1007. continue;
  1008. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  1009. if (ret != QLA_SUCCESS) {
  1010. DEBUG2_3(printk("%s(%ld): bus_reset failed: "
  1011. "target_reset=%d d_id=%x.\n", __func__,
  1012. vha->host_no, ret, fcport->d_id.b24));
  1013. }
  1014. }
  1015. }
  1016. if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
  1017. ret = qla2x00_full_login_lip(vha);
  1018. if (ret != QLA_SUCCESS) {
  1019. DEBUG2_3(printk("%s(%ld): failed: "
  1020. "full_login_lip=%d.\n", __func__, vha->host_no,
  1021. ret));
  1022. }
  1023. atomic_set(&vha->loop_state, LOOP_DOWN);
  1024. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1025. qla2x00_mark_all_devices_lost(vha, 0);
  1026. qla2x00_wait_for_loop_ready(vha);
  1027. }
  1028. if (ha->flags.enable_lip_reset) {
  1029. ret = qla2x00_lip_reset(vha);
  1030. if (ret != QLA_SUCCESS) {
  1031. DEBUG2_3(printk("%s(%ld): failed: "
  1032. "lip_reset=%d.\n", __func__, vha->host_no, ret));
  1033. } else
  1034. qla2x00_wait_for_loop_ready(vha);
  1035. }
  1036. /* Issue marker command only when we are going to start the I/O */
  1037. vha->marker_needed = 1;
  1038. return QLA_SUCCESS;
  1039. }
  1040. void
  1041. qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
  1042. {
  1043. int que, cnt;
  1044. unsigned long flags;
  1045. srb_t *sp;
  1046. struct srb_ctx *ctx;
  1047. struct qla_hw_data *ha = vha->hw;
  1048. struct req_que *req;
  1049. spin_lock_irqsave(&ha->hardware_lock, flags);
  1050. for (que = 0; que < ha->max_req_queues; que++) {
  1051. req = ha->req_q_map[que];
  1052. if (!req)
  1053. continue;
  1054. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  1055. sp = req->outstanding_cmds[cnt];
  1056. if (sp) {
  1057. req->outstanding_cmds[cnt] = NULL;
  1058. if (!sp->ctx ||
  1059. (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
  1060. IS_PROT_IO(sp)) {
  1061. sp->cmd->result = res;
  1062. qla2x00_sp_compl(ha, sp);
  1063. } else {
  1064. ctx = sp->ctx;
  1065. if (ctx->type == SRB_LOGIN_CMD ||
  1066. ctx->type == SRB_LOGOUT_CMD) {
  1067. ctx->u.iocb_cmd->free(sp);
  1068. } else {
  1069. struct fc_bsg_job *bsg_job =
  1070. ctx->u.bsg_job;
  1071. if (bsg_job->request->msgcode
  1072. == FC_BSG_HST_CT)
  1073. kfree(sp->fcport);
  1074. bsg_job->req->errors = 0;
  1075. bsg_job->reply->result = res;
  1076. bsg_job->job_done(bsg_job);
  1077. kfree(sp->ctx);
  1078. mempool_free(sp,
  1079. ha->srb_mempool);
  1080. }
  1081. }
  1082. }
  1083. }
  1084. }
  1085. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1086. }
  1087. static int
  1088. qla2xxx_slave_alloc(struct scsi_device *sdev)
  1089. {
  1090. struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
  1091. if (!rport || fc_remote_port_chkready(rport))
  1092. return -ENXIO;
  1093. sdev->hostdata = *(fc_port_t **)rport->dd_data;
  1094. return 0;
  1095. }
  1096. static int
  1097. qla2xxx_slave_configure(struct scsi_device *sdev)
  1098. {
  1099. scsi_qla_host_t *vha = shost_priv(sdev->host);
  1100. struct req_que *req = vha->req;
  1101. if (sdev->tagged_supported)
  1102. scsi_activate_tcq(sdev, req->max_q_depth);
  1103. else
  1104. scsi_deactivate_tcq(sdev, req->max_q_depth);
  1105. return 0;
  1106. }
  1107. static void
  1108. qla2xxx_slave_destroy(struct scsi_device *sdev)
  1109. {
  1110. sdev->hostdata = NULL;
  1111. }
  1112. static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
  1113. {
  1114. fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
  1115. if (!scsi_track_queue_full(sdev, qdepth))
  1116. return;
  1117. DEBUG2(qla_printk(KERN_INFO, fcport->vha->hw,
  1118. "scsi(%ld:%d:%d:%d): Queue depth adjusted-down to %d.\n",
  1119. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1120. sdev->queue_depth));
  1121. }
  1122. static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
  1123. {
  1124. fc_port_t *fcport = sdev->hostdata;
  1125. struct scsi_qla_host *vha = fcport->vha;
  1126. struct qla_hw_data *ha = vha->hw;
  1127. struct req_que *req = NULL;
  1128. req = vha->req;
  1129. if (!req)
  1130. return;
  1131. if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
  1132. return;
  1133. if (sdev->ordered_tags)
  1134. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
  1135. else
  1136. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
  1137. DEBUG2(qla_printk(KERN_INFO, ha,
  1138. "scsi(%ld:%d:%d:%d): Queue depth adjusted-up to %d.\n",
  1139. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1140. sdev->queue_depth));
  1141. }
  1142. static int
  1143. qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
  1144. {
  1145. switch (reason) {
  1146. case SCSI_QDEPTH_DEFAULT:
  1147. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1148. break;
  1149. case SCSI_QDEPTH_QFULL:
  1150. qla2x00_handle_queue_full(sdev, qdepth);
  1151. break;
  1152. case SCSI_QDEPTH_RAMP_UP:
  1153. qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
  1154. break;
  1155. default:
  1156. return -EOPNOTSUPP;
  1157. }
  1158. return sdev->queue_depth;
  1159. }
  1160. static int
  1161. qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
  1162. {
  1163. if (sdev->tagged_supported) {
  1164. scsi_set_tag_type(sdev, tag_type);
  1165. if (tag_type)
  1166. scsi_activate_tcq(sdev, sdev->queue_depth);
  1167. else
  1168. scsi_deactivate_tcq(sdev, sdev->queue_depth);
  1169. } else
  1170. tag_type = 0;
  1171. return tag_type;
  1172. }
  1173. /**
  1174. * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
  1175. * @ha: HA context
  1176. *
  1177. * At exit, the @ha's flags.enable_64bit_addressing set to indicated
  1178. * supported addressing method.
  1179. */
  1180. static void
  1181. qla2x00_config_dma_addressing(struct qla_hw_data *ha)
  1182. {
  1183. /* Assume a 32bit DMA mask. */
  1184. ha->flags.enable_64bit_addressing = 0;
  1185. if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
  1186. /* Any upper-dword bits set? */
  1187. if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
  1188. !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
  1189. /* Ok, a 64bit DMA mask is applicable. */
  1190. ha->flags.enable_64bit_addressing = 1;
  1191. ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
  1192. ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
  1193. return;
  1194. }
  1195. }
  1196. dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
  1197. pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
  1198. }
  1199. static void
  1200. qla2x00_enable_intrs(struct qla_hw_data *ha)
  1201. {
  1202. unsigned long flags = 0;
  1203. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1204. spin_lock_irqsave(&ha->hardware_lock, flags);
  1205. ha->interrupts_on = 1;
  1206. /* enable risc and host interrupts */
  1207. WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
  1208. RD_REG_WORD(&reg->ictrl);
  1209. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1210. }
  1211. static void
  1212. qla2x00_disable_intrs(struct qla_hw_data *ha)
  1213. {
  1214. unsigned long flags = 0;
  1215. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1216. spin_lock_irqsave(&ha->hardware_lock, flags);
  1217. ha->interrupts_on = 0;
  1218. /* disable risc and host interrupts */
  1219. WRT_REG_WORD(&reg->ictrl, 0);
  1220. RD_REG_WORD(&reg->ictrl);
  1221. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1222. }
  1223. static void
  1224. qla24xx_enable_intrs(struct qla_hw_data *ha)
  1225. {
  1226. unsigned long flags = 0;
  1227. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1228. spin_lock_irqsave(&ha->hardware_lock, flags);
  1229. ha->interrupts_on = 1;
  1230. WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
  1231. RD_REG_DWORD(&reg->ictrl);
  1232. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1233. }
  1234. static void
  1235. qla24xx_disable_intrs(struct qla_hw_data *ha)
  1236. {
  1237. unsigned long flags = 0;
  1238. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1239. if (IS_NOPOLLING_TYPE(ha))
  1240. return;
  1241. spin_lock_irqsave(&ha->hardware_lock, flags);
  1242. ha->interrupts_on = 0;
  1243. WRT_REG_DWORD(&reg->ictrl, 0);
  1244. RD_REG_DWORD(&reg->ictrl);
  1245. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1246. }
  1247. static struct isp_operations qla2100_isp_ops = {
  1248. .pci_config = qla2100_pci_config,
  1249. .reset_chip = qla2x00_reset_chip,
  1250. .chip_diag = qla2x00_chip_diag,
  1251. .config_rings = qla2x00_config_rings,
  1252. .reset_adapter = qla2x00_reset_adapter,
  1253. .nvram_config = qla2x00_nvram_config,
  1254. .update_fw_options = qla2x00_update_fw_options,
  1255. .load_risc = qla2x00_load_risc,
  1256. .pci_info_str = qla2x00_pci_info_str,
  1257. .fw_version_str = qla2x00_fw_version_str,
  1258. .intr_handler = qla2100_intr_handler,
  1259. .enable_intrs = qla2x00_enable_intrs,
  1260. .disable_intrs = qla2x00_disable_intrs,
  1261. .abort_command = qla2x00_abort_command,
  1262. .target_reset = qla2x00_abort_target,
  1263. .lun_reset = qla2x00_lun_reset,
  1264. .fabric_login = qla2x00_login_fabric,
  1265. .fabric_logout = qla2x00_fabric_logout,
  1266. .calc_req_entries = qla2x00_calc_iocbs_32,
  1267. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1268. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1269. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1270. .read_nvram = qla2x00_read_nvram_data,
  1271. .write_nvram = qla2x00_write_nvram_data,
  1272. .fw_dump = qla2100_fw_dump,
  1273. .beacon_on = NULL,
  1274. .beacon_off = NULL,
  1275. .beacon_blink = NULL,
  1276. .read_optrom = qla2x00_read_optrom_data,
  1277. .write_optrom = qla2x00_write_optrom_data,
  1278. .get_flash_version = qla2x00_get_flash_version,
  1279. .start_scsi = qla2x00_start_scsi,
  1280. .abort_isp = qla2x00_abort_isp,
  1281. };
  1282. static struct isp_operations qla2300_isp_ops = {
  1283. .pci_config = qla2300_pci_config,
  1284. .reset_chip = qla2x00_reset_chip,
  1285. .chip_diag = qla2x00_chip_diag,
  1286. .config_rings = qla2x00_config_rings,
  1287. .reset_adapter = qla2x00_reset_adapter,
  1288. .nvram_config = qla2x00_nvram_config,
  1289. .update_fw_options = qla2x00_update_fw_options,
  1290. .load_risc = qla2x00_load_risc,
  1291. .pci_info_str = qla2x00_pci_info_str,
  1292. .fw_version_str = qla2x00_fw_version_str,
  1293. .intr_handler = qla2300_intr_handler,
  1294. .enable_intrs = qla2x00_enable_intrs,
  1295. .disable_intrs = qla2x00_disable_intrs,
  1296. .abort_command = qla2x00_abort_command,
  1297. .target_reset = qla2x00_abort_target,
  1298. .lun_reset = qla2x00_lun_reset,
  1299. .fabric_login = qla2x00_login_fabric,
  1300. .fabric_logout = qla2x00_fabric_logout,
  1301. .calc_req_entries = qla2x00_calc_iocbs_32,
  1302. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1303. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1304. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1305. .read_nvram = qla2x00_read_nvram_data,
  1306. .write_nvram = qla2x00_write_nvram_data,
  1307. .fw_dump = qla2300_fw_dump,
  1308. .beacon_on = qla2x00_beacon_on,
  1309. .beacon_off = qla2x00_beacon_off,
  1310. .beacon_blink = qla2x00_beacon_blink,
  1311. .read_optrom = qla2x00_read_optrom_data,
  1312. .write_optrom = qla2x00_write_optrom_data,
  1313. .get_flash_version = qla2x00_get_flash_version,
  1314. .start_scsi = qla2x00_start_scsi,
  1315. .abort_isp = qla2x00_abort_isp,
  1316. };
  1317. static struct isp_operations qla24xx_isp_ops = {
  1318. .pci_config = qla24xx_pci_config,
  1319. .reset_chip = qla24xx_reset_chip,
  1320. .chip_diag = qla24xx_chip_diag,
  1321. .config_rings = qla24xx_config_rings,
  1322. .reset_adapter = qla24xx_reset_adapter,
  1323. .nvram_config = qla24xx_nvram_config,
  1324. .update_fw_options = qla24xx_update_fw_options,
  1325. .load_risc = qla24xx_load_risc,
  1326. .pci_info_str = qla24xx_pci_info_str,
  1327. .fw_version_str = qla24xx_fw_version_str,
  1328. .intr_handler = qla24xx_intr_handler,
  1329. .enable_intrs = qla24xx_enable_intrs,
  1330. .disable_intrs = qla24xx_disable_intrs,
  1331. .abort_command = qla24xx_abort_command,
  1332. .target_reset = qla24xx_abort_target,
  1333. .lun_reset = qla24xx_lun_reset,
  1334. .fabric_login = qla24xx_login_fabric,
  1335. .fabric_logout = qla24xx_fabric_logout,
  1336. .calc_req_entries = NULL,
  1337. .build_iocbs = NULL,
  1338. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1339. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1340. .read_nvram = qla24xx_read_nvram_data,
  1341. .write_nvram = qla24xx_write_nvram_data,
  1342. .fw_dump = qla24xx_fw_dump,
  1343. .beacon_on = qla24xx_beacon_on,
  1344. .beacon_off = qla24xx_beacon_off,
  1345. .beacon_blink = qla24xx_beacon_blink,
  1346. .read_optrom = qla24xx_read_optrom_data,
  1347. .write_optrom = qla24xx_write_optrom_data,
  1348. .get_flash_version = qla24xx_get_flash_version,
  1349. .start_scsi = qla24xx_start_scsi,
  1350. .abort_isp = qla2x00_abort_isp,
  1351. };
  1352. static struct isp_operations qla25xx_isp_ops = {
  1353. .pci_config = qla25xx_pci_config,
  1354. .reset_chip = qla24xx_reset_chip,
  1355. .chip_diag = qla24xx_chip_diag,
  1356. .config_rings = qla24xx_config_rings,
  1357. .reset_adapter = qla24xx_reset_adapter,
  1358. .nvram_config = qla24xx_nvram_config,
  1359. .update_fw_options = qla24xx_update_fw_options,
  1360. .load_risc = qla24xx_load_risc,
  1361. .pci_info_str = qla24xx_pci_info_str,
  1362. .fw_version_str = qla24xx_fw_version_str,
  1363. .intr_handler = qla24xx_intr_handler,
  1364. .enable_intrs = qla24xx_enable_intrs,
  1365. .disable_intrs = qla24xx_disable_intrs,
  1366. .abort_command = qla24xx_abort_command,
  1367. .target_reset = qla24xx_abort_target,
  1368. .lun_reset = qla24xx_lun_reset,
  1369. .fabric_login = qla24xx_login_fabric,
  1370. .fabric_logout = qla24xx_fabric_logout,
  1371. .calc_req_entries = NULL,
  1372. .build_iocbs = NULL,
  1373. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1374. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1375. .read_nvram = qla25xx_read_nvram_data,
  1376. .write_nvram = qla25xx_write_nvram_data,
  1377. .fw_dump = qla25xx_fw_dump,
  1378. .beacon_on = qla24xx_beacon_on,
  1379. .beacon_off = qla24xx_beacon_off,
  1380. .beacon_blink = qla24xx_beacon_blink,
  1381. .read_optrom = qla25xx_read_optrom_data,
  1382. .write_optrom = qla24xx_write_optrom_data,
  1383. .get_flash_version = qla24xx_get_flash_version,
  1384. .start_scsi = qla24xx_dif_start_scsi,
  1385. .abort_isp = qla2x00_abort_isp,
  1386. };
  1387. static struct isp_operations qla81xx_isp_ops = {
  1388. .pci_config = qla25xx_pci_config,
  1389. .reset_chip = qla24xx_reset_chip,
  1390. .chip_diag = qla24xx_chip_diag,
  1391. .config_rings = qla24xx_config_rings,
  1392. .reset_adapter = qla24xx_reset_adapter,
  1393. .nvram_config = qla81xx_nvram_config,
  1394. .update_fw_options = qla81xx_update_fw_options,
  1395. .load_risc = qla81xx_load_risc,
  1396. .pci_info_str = qla24xx_pci_info_str,
  1397. .fw_version_str = qla24xx_fw_version_str,
  1398. .intr_handler = qla24xx_intr_handler,
  1399. .enable_intrs = qla24xx_enable_intrs,
  1400. .disable_intrs = qla24xx_disable_intrs,
  1401. .abort_command = qla24xx_abort_command,
  1402. .target_reset = qla24xx_abort_target,
  1403. .lun_reset = qla24xx_lun_reset,
  1404. .fabric_login = qla24xx_login_fabric,
  1405. .fabric_logout = qla24xx_fabric_logout,
  1406. .calc_req_entries = NULL,
  1407. .build_iocbs = NULL,
  1408. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1409. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1410. .read_nvram = NULL,
  1411. .write_nvram = NULL,
  1412. .fw_dump = qla81xx_fw_dump,
  1413. .beacon_on = qla24xx_beacon_on,
  1414. .beacon_off = qla24xx_beacon_off,
  1415. .beacon_blink = qla24xx_beacon_blink,
  1416. .read_optrom = qla25xx_read_optrom_data,
  1417. .write_optrom = qla24xx_write_optrom_data,
  1418. .get_flash_version = qla24xx_get_flash_version,
  1419. .start_scsi = qla24xx_dif_start_scsi,
  1420. .abort_isp = qla2x00_abort_isp,
  1421. };
  1422. static struct isp_operations qla82xx_isp_ops = {
  1423. .pci_config = qla82xx_pci_config,
  1424. .reset_chip = qla82xx_reset_chip,
  1425. .chip_diag = qla24xx_chip_diag,
  1426. .config_rings = qla82xx_config_rings,
  1427. .reset_adapter = qla24xx_reset_adapter,
  1428. .nvram_config = qla81xx_nvram_config,
  1429. .update_fw_options = qla24xx_update_fw_options,
  1430. .load_risc = qla82xx_load_risc,
  1431. .pci_info_str = qla82xx_pci_info_str,
  1432. .fw_version_str = qla24xx_fw_version_str,
  1433. .intr_handler = qla82xx_intr_handler,
  1434. .enable_intrs = qla82xx_enable_intrs,
  1435. .disable_intrs = qla82xx_disable_intrs,
  1436. .abort_command = qla24xx_abort_command,
  1437. .target_reset = qla24xx_abort_target,
  1438. .lun_reset = qla24xx_lun_reset,
  1439. .fabric_login = qla24xx_login_fabric,
  1440. .fabric_logout = qla24xx_fabric_logout,
  1441. .calc_req_entries = NULL,
  1442. .build_iocbs = NULL,
  1443. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1444. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1445. .read_nvram = qla24xx_read_nvram_data,
  1446. .write_nvram = qla24xx_write_nvram_data,
  1447. .fw_dump = qla24xx_fw_dump,
  1448. .beacon_on = qla24xx_beacon_on,
  1449. .beacon_off = qla24xx_beacon_off,
  1450. .beacon_blink = qla24xx_beacon_blink,
  1451. .read_optrom = qla82xx_read_optrom_data,
  1452. .write_optrom = qla82xx_write_optrom_data,
  1453. .get_flash_version = qla24xx_get_flash_version,
  1454. .start_scsi = qla82xx_start_scsi,
  1455. .abort_isp = qla82xx_abort_isp,
  1456. };
  1457. static inline void
  1458. qla2x00_set_isp_flags(struct qla_hw_data *ha)
  1459. {
  1460. ha->device_type = DT_EXTENDED_IDS;
  1461. switch (ha->pdev->device) {
  1462. case PCI_DEVICE_ID_QLOGIC_ISP2100:
  1463. ha->device_type |= DT_ISP2100;
  1464. ha->device_type &= ~DT_EXTENDED_IDS;
  1465. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1466. break;
  1467. case PCI_DEVICE_ID_QLOGIC_ISP2200:
  1468. ha->device_type |= DT_ISP2200;
  1469. ha->device_type &= ~DT_EXTENDED_IDS;
  1470. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1471. break;
  1472. case PCI_DEVICE_ID_QLOGIC_ISP2300:
  1473. ha->device_type |= DT_ISP2300;
  1474. ha->device_type |= DT_ZIO_SUPPORTED;
  1475. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1476. break;
  1477. case PCI_DEVICE_ID_QLOGIC_ISP2312:
  1478. ha->device_type |= DT_ISP2312;
  1479. ha->device_type |= DT_ZIO_SUPPORTED;
  1480. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1481. break;
  1482. case PCI_DEVICE_ID_QLOGIC_ISP2322:
  1483. ha->device_type |= DT_ISP2322;
  1484. ha->device_type |= DT_ZIO_SUPPORTED;
  1485. if (ha->pdev->subsystem_vendor == 0x1028 &&
  1486. ha->pdev->subsystem_device == 0x0170)
  1487. ha->device_type |= DT_OEM_001;
  1488. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1489. break;
  1490. case PCI_DEVICE_ID_QLOGIC_ISP6312:
  1491. ha->device_type |= DT_ISP6312;
  1492. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1493. break;
  1494. case PCI_DEVICE_ID_QLOGIC_ISP6322:
  1495. ha->device_type |= DT_ISP6322;
  1496. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1497. break;
  1498. case PCI_DEVICE_ID_QLOGIC_ISP2422:
  1499. ha->device_type |= DT_ISP2422;
  1500. ha->device_type |= DT_ZIO_SUPPORTED;
  1501. ha->device_type |= DT_FWI2;
  1502. ha->device_type |= DT_IIDMA;
  1503. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1504. break;
  1505. case PCI_DEVICE_ID_QLOGIC_ISP2432:
  1506. ha->device_type |= DT_ISP2432;
  1507. ha->device_type |= DT_ZIO_SUPPORTED;
  1508. ha->device_type |= DT_FWI2;
  1509. ha->device_type |= DT_IIDMA;
  1510. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1511. break;
  1512. case PCI_DEVICE_ID_QLOGIC_ISP8432:
  1513. ha->device_type |= DT_ISP8432;
  1514. ha->device_type |= DT_ZIO_SUPPORTED;
  1515. ha->device_type |= DT_FWI2;
  1516. ha->device_type |= DT_IIDMA;
  1517. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1518. break;
  1519. case PCI_DEVICE_ID_QLOGIC_ISP5422:
  1520. ha->device_type |= DT_ISP5422;
  1521. ha->device_type |= DT_FWI2;
  1522. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1523. break;
  1524. case PCI_DEVICE_ID_QLOGIC_ISP5432:
  1525. ha->device_type |= DT_ISP5432;
  1526. ha->device_type |= DT_FWI2;
  1527. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1528. break;
  1529. case PCI_DEVICE_ID_QLOGIC_ISP2532:
  1530. ha->device_type |= DT_ISP2532;
  1531. ha->device_type |= DT_ZIO_SUPPORTED;
  1532. ha->device_type |= DT_FWI2;
  1533. ha->device_type |= DT_IIDMA;
  1534. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1535. break;
  1536. case PCI_DEVICE_ID_QLOGIC_ISP8001:
  1537. ha->device_type |= DT_ISP8001;
  1538. ha->device_type |= DT_ZIO_SUPPORTED;
  1539. ha->device_type |= DT_FWI2;
  1540. ha->device_type |= DT_IIDMA;
  1541. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1542. break;
  1543. case PCI_DEVICE_ID_QLOGIC_ISP8021:
  1544. ha->device_type |= DT_ISP8021;
  1545. ha->device_type |= DT_ZIO_SUPPORTED;
  1546. ha->device_type |= DT_FWI2;
  1547. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1548. /* Initialize 82XX ISP flags */
  1549. qla82xx_init_flags(ha);
  1550. break;
  1551. }
  1552. if (IS_QLA82XX(ha))
  1553. ha->port_no = !(ha->portnum & 1);
  1554. else
  1555. /* Get adapter physical port no from interrupt pin register. */
  1556. pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
  1557. if (ha->port_no & 1)
  1558. ha->flags.port0 = 1;
  1559. else
  1560. ha->flags.port0 = 0;
  1561. }
  1562. static int
  1563. qla2x00_iospace_config(struct qla_hw_data *ha)
  1564. {
  1565. resource_size_t pio;
  1566. uint16_t msix;
  1567. int cpus;
  1568. if (IS_QLA82XX(ha))
  1569. return qla82xx_iospace_config(ha);
  1570. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1571. QLA2XXX_DRIVER_NAME)) {
  1572. qla_printk(KERN_WARNING, ha,
  1573. "Failed to reserve PIO/MMIO regions (%s)\n",
  1574. pci_name(ha->pdev));
  1575. goto iospace_error_exit;
  1576. }
  1577. if (!(ha->bars & 1))
  1578. goto skip_pio;
  1579. /* We only need PIO for Flash operations on ISP2312 v2 chips. */
  1580. pio = pci_resource_start(ha->pdev, 0);
  1581. if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
  1582. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1583. qla_printk(KERN_WARNING, ha,
  1584. "Invalid PCI I/O region size (%s)...\n",
  1585. pci_name(ha->pdev));
  1586. pio = 0;
  1587. }
  1588. } else {
  1589. qla_printk(KERN_WARNING, ha,
  1590. "region #0 not a PIO resource (%s)...\n",
  1591. pci_name(ha->pdev));
  1592. pio = 0;
  1593. }
  1594. ha->pio_address = pio;
  1595. skip_pio:
  1596. /* Use MMIO operations for all accesses. */
  1597. if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
  1598. qla_printk(KERN_ERR, ha,
  1599. "region #1 not an MMIO resource (%s), aborting\n",
  1600. pci_name(ha->pdev));
  1601. goto iospace_error_exit;
  1602. }
  1603. if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
  1604. qla_printk(KERN_ERR, ha,
  1605. "Invalid PCI mem region size (%s), aborting\n",
  1606. pci_name(ha->pdev));
  1607. goto iospace_error_exit;
  1608. }
  1609. ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
  1610. if (!ha->iobase) {
  1611. qla_printk(KERN_ERR, ha,
  1612. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  1613. goto iospace_error_exit;
  1614. }
  1615. /* Determine queue resources */
  1616. ha->max_req_queues = ha->max_rsp_queues = 1;
  1617. if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
  1618. (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
  1619. (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
  1620. goto mqiobase_exit;
  1621. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
  1622. pci_resource_len(ha->pdev, 3));
  1623. if (ha->mqiobase) {
  1624. /* Read MSIX vector size of the board */
  1625. pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
  1626. ha->msix_count = msix;
  1627. /* Max queues are bounded by available msix vectors */
  1628. /* queue 0 uses two msix vectors */
  1629. if (ql2xmultique_tag) {
  1630. cpus = num_online_cpus();
  1631. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1632. (cpus + 1) : (ha->msix_count - 1);
  1633. ha->max_req_queues = 2;
  1634. } else if (ql2xmaxqueues > 1) {
  1635. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1636. QLA_MQ_SIZE : ql2xmaxqueues;
  1637. DEBUG2(qla_printk(KERN_INFO, ha, "QoS mode set, max no"
  1638. " of request queues:%d\n", ha->max_req_queues));
  1639. }
  1640. qla_printk(KERN_INFO, ha,
  1641. "MSI-X vector count: %d\n", msix);
  1642. } else
  1643. qla_printk(KERN_INFO, ha, "BAR 3 not enabled\n");
  1644. mqiobase_exit:
  1645. ha->msix_count = ha->max_rsp_queues + 1;
  1646. return (0);
  1647. iospace_error_exit:
  1648. return (-ENOMEM);
  1649. }
  1650. static void
  1651. qla2xxx_scan_start(struct Scsi_Host *shost)
  1652. {
  1653. scsi_qla_host_t *vha = shost_priv(shost);
  1654. if (vha->hw->flags.running_gold_fw)
  1655. return;
  1656. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1657. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  1658. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  1659. set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
  1660. }
  1661. static int
  1662. qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
  1663. {
  1664. scsi_qla_host_t *vha = shost_priv(shost);
  1665. if (!vha->host)
  1666. return 1;
  1667. if (time > vha->hw->loop_reset_delay * HZ)
  1668. return 1;
  1669. return atomic_read(&vha->loop_state) == LOOP_READY;
  1670. }
  1671. /*
  1672. * PCI driver interface
  1673. */
  1674. static int __devinit
  1675. qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1676. {
  1677. int ret = -ENODEV;
  1678. struct Scsi_Host *host;
  1679. scsi_qla_host_t *base_vha = NULL;
  1680. struct qla_hw_data *ha;
  1681. char pci_info[30];
  1682. char fw_str[30];
  1683. struct scsi_host_template *sht;
  1684. int bars, max_id, mem_only = 0;
  1685. uint16_t req_length = 0, rsp_length = 0;
  1686. struct req_que *req = NULL;
  1687. struct rsp_que *rsp = NULL;
  1688. bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
  1689. sht = &qla2xxx_driver_template;
  1690. if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
  1691. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
  1692. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
  1693. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
  1694. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
  1695. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
  1696. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
  1697. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
  1698. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1699. mem_only = 1;
  1700. }
  1701. if (mem_only) {
  1702. if (pci_enable_device_mem(pdev))
  1703. goto probe_out;
  1704. } else {
  1705. if (pci_enable_device(pdev))
  1706. goto probe_out;
  1707. }
  1708. /* This may fail but that's ok */
  1709. pci_enable_pcie_error_reporting(pdev);
  1710. ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
  1711. if (!ha) {
  1712. DEBUG(printk("Unable to allocate memory for ha\n"));
  1713. goto probe_out;
  1714. }
  1715. ha->pdev = pdev;
  1716. /* Clear our data area */
  1717. ha->bars = bars;
  1718. ha->mem_only = mem_only;
  1719. spin_lock_init(&ha->hardware_lock);
  1720. spin_lock_init(&ha->vport_slock);
  1721. /* Set ISP-type information. */
  1722. qla2x00_set_isp_flags(ha);
  1723. /* Set EEH reset type to fundamental if required by hba */
  1724. if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
  1725. pdev->needs_freset = 1;
  1726. }
  1727. /* Configure PCI I/O space */
  1728. ret = qla2x00_iospace_config(ha);
  1729. if (ret)
  1730. goto probe_hw_failed;
  1731. qla_printk(KERN_INFO, ha,
  1732. "Found an ISP%04X, irq %d, iobase 0x%p\n", pdev->device, pdev->irq,
  1733. ha->iobase);
  1734. ha->prev_topology = 0;
  1735. ha->init_cb_size = sizeof(init_cb_t);
  1736. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  1737. ha->optrom_size = OPTROM_SIZE_2300;
  1738. /* Assign ISP specific operations. */
  1739. max_id = MAX_TARGETS_2200;
  1740. if (IS_QLA2100(ha)) {
  1741. max_id = MAX_TARGETS_2100;
  1742. ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
  1743. req_length = REQUEST_ENTRY_CNT_2100;
  1744. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1745. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1746. ha->gid_list_info_size = 4;
  1747. ha->flash_conf_off = ~0;
  1748. ha->flash_data_off = ~0;
  1749. ha->nvram_conf_off = ~0;
  1750. ha->nvram_data_off = ~0;
  1751. ha->isp_ops = &qla2100_isp_ops;
  1752. } else if (IS_QLA2200(ha)) {
  1753. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1754. req_length = REQUEST_ENTRY_CNT_2200;
  1755. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1756. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1757. ha->gid_list_info_size = 4;
  1758. ha->flash_conf_off = ~0;
  1759. ha->flash_data_off = ~0;
  1760. ha->nvram_conf_off = ~0;
  1761. ha->nvram_data_off = ~0;
  1762. ha->isp_ops = &qla2100_isp_ops;
  1763. } else if (IS_QLA23XX(ha)) {
  1764. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1765. req_length = REQUEST_ENTRY_CNT_2200;
  1766. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1767. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1768. ha->gid_list_info_size = 6;
  1769. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1770. ha->optrom_size = OPTROM_SIZE_2322;
  1771. ha->flash_conf_off = ~0;
  1772. ha->flash_data_off = ~0;
  1773. ha->nvram_conf_off = ~0;
  1774. ha->nvram_data_off = ~0;
  1775. ha->isp_ops = &qla2300_isp_ops;
  1776. } else if (IS_QLA24XX_TYPE(ha)) {
  1777. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1778. req_length = REQUEST_ENTRY_CNT_24XX;
  1779. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1780. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1781. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1782. ha->gid_list_info_size = 8;
  1783. ha->optrom_size = OPTROM_SIZE_24XX;
  1784. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
  1785. ha->isp_ops = &qla24xx_isp_ops;
  1786. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1787. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1788. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1789. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1790. } else if (IS_QLA25XX(ha)) {
  1791. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1792. req_length = REQUEST_ENTRY_CNT_24XX;
  1793. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1794. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1795. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1796. ha->gid_list_info_size = 8;
  1797. ha->optrom_size = OPTROM_SIZE_25XX;
  1798. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1799. ha->isp_ops = &qla25xx_isp_ops;
  1800. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1801. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1802. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1803. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1804. } else if (IS_QLA81XX(ha)) {
  1805. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1806. req_length = REQUEST_ENTRY_CNT_24XX;
  1807. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1808. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1809. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1810. ha->gid_list_info_size = 8;
  1811. ha->optrom_size = OPTROM_SIZE_81XX;
  1812. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1813. ha->isp_ops = &qla81xx_isp_ops;
  1814. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  1815. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  1816. ha->nvram_conf_off = ~0;
  1817. ha->nvram_data_off = ~0;
  1818. } else if (IS_QLA82XX(ha)) {
  1819. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1820. req_length = REQUEST_ENTRY_CNT_82XX;
  1821. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  1822. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1823. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1824. ha->gid_list_info_size = 8;
  1825. ha->optrom_size = OPTROM_SIZE_82XX;
  1826. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1827. ha->isp_ops = &qla82xx_isp_ops;
  1828. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1829. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1830. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1831. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1832. }
  1833. mutex_init(&ha->vport_lock);
  1834. init_completion(&ha->mbx_cmd_comp);
  1835. complete(&ha->mbx_cmd_comp);
  1836. init_completion(&ha->mbx_intr_comp);
  1837. init_completion(&ha->dcbx_comp);
  1838. set_bit(0, (unsigned long *) ha->vp_idx_map);
  1839. qla2x00_config_dma_addressing(ha);
  1840. ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
  1841. if (!ret) {
  1842. qla_printk(KERN_WARNING, ha,
  1843. "[ERROR] Failed to allocate memory for adapter\n");
  1844. goto probe_hw_failed;
  1845. }
  1846. req->max_q_depth = MAX_Q_DEPTH;
  1847. if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
  1848. req->max_q_depth = ql2xmaxqdepth;
  1849. base_vha = qla2x00_create_host(sht, ha);
  1850. if (!base_vha) {
  1851. qla_printk(KERN_WARNING, ha,
  1852. "[ERROR] Failed to allocate memory for scsi_host\n");
  1853. ret = -ENOMEM;
  1854. qla2x00_mem_free(ha);
  1855. qla2x00_free_req_que(ha, req);
  1856. qla2x00_free_rsp_que(ha, rsp);
  1857. goto probe_hw_failed;
  1858. }
  1859. pci_set_drvdata(pdev, base_vha);
  1860. host = base_vha->host;
  1861. base_vha->req = req;
  1862. host->can_queue = req->length + 128;
  1863. if (IS_QLA2XXX_MIDTYPE(ha))
  1864. base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
  1865. else
  1866. base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
  1867. base_vha->vp_idx;
  1868. /* Set the SG table size based on ISP type */
  1869. if (!IS_FWI2_CAPABLE(ha)) {
  1870. if (IS_QLA2100(ha))
  1871. host->sg_tablesize = 32;
  1872. } else {
  1873. if (!IS_QLA82XX(ha))
  1874. host->sg_tablesize = QLA_SG_ALL;
  1875. }
  1876. host->max_id = max_id;
  1877. host->this_id = 255;
  1878. host->cmd_per_lun = 3;
  1879. host->unique_id = host->host_no;
  1880. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif)
  1881. host->max_cmd_len = 32;
  1882. else
  1883. host->max_cmd_len = MAX_CMDSZ;
  1884. host->max_channel = MAX_BUSES - 1;
  1885. host->max_lun = MAX_LUNS;
  1886. host->transportt = qla2xxx_transport_template;
  1887. sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
  1888. /* Set up the irqs */
  1889. ret = qla2x00_request_irqs(ha, rsp);
  1890. if (ret)
  1891. goto probe_init_failed;
  1892. pci_save_state(pdev);
  1893. /* Alloc arrays of request and response ring ptrs */
  1894. que_init:
  1895. if (!qla2x00_alloc_queues(ha)) {
  1896. qla_printk(KERN_WARNING, ha,
  1897. "[ERROR] Failed to allocate memory for queue"
  1898. " pointers\n");
  1899. goto probe_init_failed;
  1900. }
  1901. ha->rsp_q_map[0] = rsp;
  1902. ha->req_q_map[0] = req;
  1903. rsp->req = req;
  1904. req->rsp = rsp;
  1905. set_bit(0, ha->req_qid_map);
  1906. set_bit(0, ha->rsp_qid_map);
  1907. /* FWI2-capable only. */
  1908. req->req_q_in = &ha->iobase->isp24.req_q_in;
  1909. req->req_q_out = &ha->iobase->isp24.req_q_out;
  1910. rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
  1911. rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
  1912. if (ha->mqenable) {
  1913. req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
  1914. req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
  1915. rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
  1916. rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
  1917. }
  1918. if (IS_QLA82XX(ha)) {
  1919. req->req_q_out = &ha->iobase->isp82.req_q_out[0];
  1920. rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
  1921. rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
  1922. }
  1923. if (qla2x00_initialize_adapter(base_vha)) {
  1924. qla_printk(KERN_WARNING, ha,
  1925. "Failed to initialize adapter\n");
  1926. DEBUG2(printk("scsi(%ld): Failed to initialize adapter - "
  1927. "Adapter flags %x.\n",
  1928. base_vha->host_no, base_vha->device_flags));
  1929. if (IS_QLA82XX(ha)) {
  1930. qla82xx_idc_lock(ha);
  1931. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  1932. QLA82XX_DEV_FAILED);
  1933. qla82xx_idc_unlock(ha);
  1934. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  1935. }
  1936. ret = -ENODEV;
  1937. goto probe_failed;
  1938. }
  1939. if (ha->mqenable) {
  1940. if (qla25xx_setup_mode(base_vha)) {
  1941. qla_printk(KERN_WARNING, ha,
  1942. "Can't create queues, falling back to single"
  1943. " queue mode\n");
  1944. goto que_init;
  1945. }
  1946. }
  1947. if (ha->flags.running_gold_fw)
  1948. goto skip_dpc;
  1949. /*
  1950. * Startup the kernel thread for this host adapter
  1951. */
  1952. ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
  1953. "%s_dpc", base_vha->host_str);
  1954. if (IS_ERR(ha->dpc_thread)) {
  1955. qla_printk(KERN_WARNING, ha,
  1956. "Unable to start DPC thread!\n");
  1957. ret = PTR_ERR(ha->dpc_thread);
  1958. goto probe_failed;
  1959. }
  1960. skip_dpc:
  1961. list_add_tail(&base_vha->list, &ha->vp_list);
  1962. base_vha->host->irq = ha->pdev->irq;
  1963. /* Initialized the timer */
  1964. qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
  1965. DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n",
  1966. base_vha->host_no, ha));
  1967. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif) {
  1968. if (ha->fw_attributes & BIT_4) {
  1969. base_vha->flags.difdix_supported = 1;
  1970. DEBUG18(qla_printk(KERN_INFO, ha,
  1971. "Registering for DIF/DIX type 1 and 3"
  1972. " protection.\n"));
  1973. scsi_host_set_prot(host,
  1974. SHOST_DIF_TYPE1_PROTECTION
  1975. | SHOST_DIF_TYPE2_PROTECTION
  1976. | SHOST_DIF_TYPE3_PROTECTION
  1977. | SHOST_DIX_TYPE1_PROTECTION
  1978. | SHOST_DIX_TYPE2_PROTECTION
  1979. | SHOST_DIX_TYPE3_PROTECTION);
  1980. scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
  1981. } else
  1982. base_vha->flags.difdix_supported = 0;
  1983. }
  1984. ha->isp_ops->enable_intrs(ha);
  1985. ret = scsi_add_host(host, &pdev->dev);
  1986. if (ret)
  1987. goto probe_failed;
  1988. base_vha->flags.init_done = 1;
  1989. base_vha->flags.online = 1;
  1990. scsi_scan_host(host);
  1991. qla2x00_alloc_sysfs_attr(base_vha);
  1992. qla2x00_init_host_attr(base_vha);
  1993. qla2x00_dfs_setup(base_vha);
  1994. qla_printk(KERN_INFO, ha, "\n"
  1995. " QLogic Fibre Channel HBA Driver: %s\n"
  1996. " QLogic %s - %s\n"
  1997. " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n",
  1998. qla2x00_version_str, ha->model_number,
  1999. ha->model_desc ? ha->model_desc : "", pdev->device,
  2000. ha->isp_ops->pci_info_str(base_vha, pci_info), pci_name(pdev),
  2001. ha->flags.enable_64bit_addressing ? '+' : '-', base_vha->host_no,
  2002. ha->isp_ops->fw_version_str(base_vha, fw_str));
  2003. return 0;
  2004. probe_init_failed:
  2005. qla2x00_free_req_que(ha, req);
  2006. qla2x00_free_rsp_que(ha, rsp);
  2007. ha->max_req_queues = ha->max_rsp_queues = 0;
  2008. probe_failed:
  2009. if (base_vha->timer_active)
  2010. qla2x00_stop_timer(base_vha);
  2011. base_vha->flags.online = 0;
  2012. if (ha->dpc_thread) {
  2013. struct task_struct *t = ha->dpc_thread;
  2014. ha->dpc_thread = NULL;
  2015. kthread_stop(t);
  2016. }
  2017. qla2x00_free_device(base_vha);
  2018. scsi_host_put(base_vha->host);
  2019. probe_hw_failed:
  2020. if (IS_QLA82XX(ha)) {
  2021. qla82xx_idc_lock(ha);
  2022. qla82xx_clear_drv_active(ha);
  2023. qla82xx_idc_unlock(ha);
  2024. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2025. if (!ql2xdbwr)
  2026. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2027. } else {
  2028. if (ha->iobase)
  2029. iounmap(ha->iobase);
  2030. }
  2031. pci_release_selected_regions(ha->pdev, ha->bars);
  2032. kfree(ha);
  2033. ha = NULL;
  2034. probe_out:
  2035. pci_disable_device(pdev);
  2036. return ret;
  2037. }
  2038. static void
  2039. qla2x00_shutdown(struct pci_dev *pdev)
  2040. {
  2041. scsi_qla_host_t *vha;
  2042. struct qla_hw_data *ha;
  2043. vha = pci_get_drvdata(pdev);
  2044. ha = vha->hw;
  2045. /* Turn-off FCE trace */
  2046. if (ha->flags.fce_enabled) {
  2047. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2048. ha->flags.fce_enabled = 0;
  2049. }
  2050. /* Turn-off EFT trace */
  2051. if (ha->eft)
  2052. qla2x00_disable_eft_trace(vha);
  2053. /* Stop currently executing firmware. */
  2054. qla2x00_try_to_stop_firmware(vha);
  2055. /* Turn adapter off line */
  2056. vha->flags.online = 0;
  2057. /* turn-off interrupts on the card */
  2058. if (ha->interrupts_on) {
  2059. vha->flags.init_done = 0;
  2060. ha->isp_ops->disable_intrs(ha);
  2061. }
  2062. qla2x00_free_irqs(vha);
  2063. qla2x00_free_fw_dump(ha);
  2064. }
  2065. static void
  2066. qla2x00_remove_one(struct pci_dev *pdev)
  2067. {
  2068. scsi_qla_host_t *base_vha, *vha;
  2069. struct qla_hw_data *ha;
  2070. unsigned long flags;
  2071. base_vha = pci_get_drvdata(pdev);
  2072. ha = base_vha->hw;
  2073. mutex_lock(&ha->vport_lock);
  2074. while (ha->cur_vport_count) {
  2075. struct Scsi_Host *scsi_host;
  2076. spin_lock_irqsave(&ha->vport_slock, flags);
  2077. BUG_ON(base_vha->list.next == &ha->vp_list);
  2078. /* This assumes first entry in ha->vp_list is always base vha */
  2079. vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
  2080. scsi_host = scsi_host_get(vha->host);
  2081. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2082. mutex_unlock(&ha->vport_lock);
  2083. fc_vport_terminate(vha->fc_vport);
  2084. scsi_host_put(vha->host);
  2085. mutex_lock(&ha->vport_lock);
  2086. }
  2087. mutex_unlock(&ha->vport_lock);
  2088. set_bit(UNLOADING, &base_vha->dpc_flags);
  2089. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2090. qla2x00_dfs_remove(base_vha);
  2091. qla84xx_put_chip(base_vha);
  2092. /* Disable timer */
  2093. if (base_vha->timer_active)
  2094. qla2x00_stop_timer(base_vha);
  2095. base_vha->flags.online = 0;
  2096. /* Flush the work queue and remove it */
  2097. if (ha->wq) {
  2098. flush_workqueue(ha->wq);
  2099. destroy_workqueue(ha->wq);
  2100. ha->wq = NULL;
  2101. }
  2102. /* Kill the kernel thread for this host */
  2103. if (ha->dpc_thread) {
  2104. struct task_struct *t = ha->dpc_thread;
  2105. /*
  2106. * qla2xxx_wake_dpc checks for ->dpc_thread
  2107. * so we need to zero it out.
  2108. */
  2109. ha->dpc_thread = NULL;
  2110. kthread_stop(t);
  2111. }
  2112. qla2x00_free_sysfs_attr(base_vha);
  2113. fc_remove_host(base_vha->host);
  2114. scsi_remove_host(base_vha->host);
  2115. qla2x00_free_device(base_vha);
  2116. scsi_host_put(base_vha->host);
  2117. if (IS_QLA82XX(ha)) {
  2118. qla82xx_idc_lock(ha);
  2119. qla82xx_clear_drv_active(ha);
  2120. qla82xx_idc_unlock(ha);
  2121. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2122. if (!ql2xdbwr)
  2123. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2124. } else {
  2125. if (ha->iobase)
  2126. iounmap(ha->iobase);
  2127. if (ha->mqiobase)
  2128. iounmap(ha->mqiobase);
  2129. }
  2130. pci_release_selected_regions(ha->pdev, ha->bars);
  2131. kfree(ha);
  2132. ha = NULL;
  2133. pci_disable_pcie_error_reporting(pdev);
  2134. pci_disable_device(pdev);
  2135. pci_set_drvdata(pdev, NULL);
  2136. }
  2137. static void
  2138. qla2x00_free_device(scsi_qla_host_t *vha)
  2139. {
  2140. struct qla_hw_data *ha = vha->hw;
  2141. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  2142. /* Disable timer */
  2143. if (vha->timer_active)
  2144. qla2x00_stop_timer(vha);
  2145. /* Kill the kernel thread for this host */
  2146. if (ha->dpc_thread) {
  2147. struct task_struct *t = ha->dpc_thread;
  2148. /*
  2149. * qla2xxx_wake_dpc checks for ->dpc_thread
  2150. * so we need to zero it out.
  2151. */
  2152. ha->dpc_thread = NULL;
  2153. kthread_stop(t);
  2154. }
  2155. qla25xx_delete_queues(vha);
  2156. if (ha->flags.fce_enabled)
  2157. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2158. if (ha->eft)
  2159. qla2x00_disable_eft_trace(vha);
  2160. /* Stop currently executing firmware. */
  2161. qla2x00_try_to_stop_firmware(vha);
  2162. vha->flags.online = 0;
  2163. /* turn-off interrupts on the card */
  2164. if (ha->interrupts_on) {
  2165. vha->flags.init_done = 0;
  2166. ha->isp_ops->disable_intrs(ha);
  2167. }
  2168. qla2x00_free_irqs(vha);
  2169. qla2x00_free_fcports(vha);
  2170. qla2x00_mem_free(ha);
  2171. qla2x00_free_queues(ha);
  2172. }
  2173. void qla2x00_free_fcports(struct scsi_qla_host *vha)
  2174. {
  2175. fc_port_t *fcport, *tfcport;
  2176. list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
  2177. list_del(&fcport->list);
  2178. kfree(fcport);
  2179. fcport = NULL;
  2180. }
  2181. }
  2182. static inline void
  2183. qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
  2184. int defer)
  2185. {
  2186. struct fc_rport *rport;
  2187. scsi_qla_host_t *base_vha;
  2188. unsigned long flags;
  2189. if (!fcport->rport)
  2190. return;
  2191. rport = fcport->rport;
  2192. if (defer) {
  2193. base_vha = pci_get_drvdata(vha->hw->pdev);
  2194. spin_lock_irqsave(vha->host->host_lock, flags);
  2195. fcport->drport = rport;
  2196. spin_unlock_irqrestore(vha->host->host_lock, flags);
  2197. set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2198. qla2xxx_wake_dpc(base_vha);
  2199. } else
  2200. fc_remote_port_delete(rport);
  2201. }
  2202. /*
  2203. * qla2x00_mark_device_lost Updates fcport state when device goes offline.
  2204. *
  2205. * Input: ha = adapter block pointer. fcport = port structure pointer.
  2206. *
  2207. * Return: None.
  2208. *
  2209. * Context:
  2210. */
  2211. void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
  2212. int do_login, int defer)
  2213. {
  2214. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2215. vha->vp_idx == fcport->vp_idx) {
  2216. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2217. qla2x00_schedule_rport_del(vha, fcport, defer);
  2218. }
  2219. /*
  2220. * We may need to retry the login, so don't change the state of the
  2221. * port but do the retries.
  2222. */
  2223. if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
  2224. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2225. if (!do_login)
  2226. return;
  2227. if (fcport->login_retry == 0) {
  2228. fcport->login_retry = vha->hw->login_retry_count;
  2229. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2230. DEBUG(printk("scsi(%ld): Port login retry: "
  2231. "%02x%02x%02x%02x%02x%02x%02x%02x, "
  2232. "id = 0x%04x retry cnt=%d\n",
  2233. vha->host_no,
  2234. fcport->port_name[0],
  2235. fcport->port_name[1],
  2236. fcport->port_name[2],
  2237. fcport->port_name[3],
  2238. fcport->port_name[4],
  2239. fcport->port_name[5],
  2240. fcport->port_name[6],
  2241. fcport->port_name[7],
  2242. fcport->loop_id,
  2243. fcport->login_retry));
  2244. }
  2245. }
  2246. /*
  2247. * qla2x00_mark_all_devices_lost
  2248. * Updates fcport state when device goes offline.
  2249. *
  2250. * Input:
  2251. * ha = adapter block pointer.
  2252. * fcport = port structure pointer.
  2253. *
  2254. * Return:
  2255. * None.
  2256. *
  2257. * Context:
  2258. */
  2259. void
  2260. qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
  2261. {
  2262. fc_port_t *fcport;
  2263. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2264. if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
  2265. continue;
  2266. /*
  2267. * No point in marking the device as lost, if the device is
  2268. * already DEAD.
  2269. */
  2270. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
  2271. continue;
  2272. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  2273. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2274. if (defer)
  2275. qla2x00_schedule_rport_del(vha, fcport, defer);
  2276. else if (vha->vp_idx == fcport->vp_idx)
  2277. qla2x00_schedule_rport_del(vha, fcport, defer);
  2278. }
  2279. }
  2280. }
  2281. /*
  2282. * qla2x00_mem_alloc
  2283. * Allocates adapter memory.
  2284. *
  2285. * Returns:
  2286. * 0 = success.
  2287. * !0 = failure.
  2288. */
  2289. static int
  2290. qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
  2291. struct req_que **req, struct rsp_que **rsp)
  2292. {
  2293. char name[16];
  2294. ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
  2295. &ha->init_cb_dma, GFP_KERNEL);
  2296. if (!ha->init_cb)
  2297. goto fail;
  2298. ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
  2299. &ha->gid_list_dma, GFP_KERNEL);
  2300. if (!ha->gid_list)
  2301. goto fail_free_init_cb;
  2302. ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  2303. if (!ha->srb_mempool)
  2304. goto fail_free_gid_list;
  2305. if (IS_QLA82XX(ha)) {
  2306. /* Allocate cache for CT6 Ctx. */
  2307. if (!ctx_cachep) {
  2308. ctx_cachep = kmem_cache_create("qla2xxx_ctx",
  2309. sizeof(struct ct6_dsd), 0,
  2310. SLAB_HWCACHE_ALIGN, NULL);
  2311. if (!ctx_cachep)
  2312. goto fail_free_gid_list;
  2313. }
  2314. ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
  2315. ctx_cachep);
  2316. if (!ha->ctx_mempool)
  2317. goto fail_free_srb_mempool;
  2318. }
  2319. /* Get memory for cached NVRAM */
  2320. ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
  2321. if (!ha->nvram)
  2322. goto fail_free_ctx_mempool;
  2323. snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
  2324. ha->pdev->device);
  2325. ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2326. DMA_POOL_SIZE, 8, 0);
  2327. if (!ha->s_dma_pool)
  2328. goto fail_free_nvram;
  2329. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2330. ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2331. DSD_LIST_DMA_POOL_SIZE, 8, 0);
  2332. if (!ha->dl_dma_pool) {
  2333. qla_printk(KERN_WARNING, ha,
  2334. "Memory Allocation failed - dl_dma_pool\n");
  2335. goto fail_s_dma_pool;
  2336. }
  2337. ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2338. FCP_CMND_DMA_POOL_SIZE, 8, 0);
  2339. if (!ha->fcp_cmnd_dma_pool) {
  2340. qla_printk(KERN_WARNING, ha,
  2341. "Memory Allocation failed - fcp_cmnd_dma_pool\n");
  2342. goto fail_dl_dma_pool;
  2343. }
  2344. }
  2345. /* Allocate memory for SNS commands */
  2346. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2347. /* Get consistent memory allocated for SNS commands */
  2348. ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
  2349. sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
  2350. if (!ha->sns_cmd)
  2351. goto fail_dma_pool;
  2352. } else {
  2353. /* Get consistent memory allocated for MS IOCB */
  2354. ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2355. &ha->ms_iocb_dma);
  2356. if (!ha->ms_iocb)
  2357. goto fail_dma_pool;
  2358. /* Get consistent memory allocated for CT SNS commands */
  2359. ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
  2360. sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
  2361. if (!ha->ct_sns)
  2362. goto fail_free_ms_iocb;
  2363. }
  2364. /* Allocate memory for request ring */
  2365. *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
  2366. if (!*req) {
  2367. DEBUG(printk("Unable to allocate memory for req\n"));
  2368. goto fail_req;
  2369. }
  2370. (*req)->length = req_len;
  2371. (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2372. ((*req)->length + 1) * sizeof(request_t),
  2373. &(*req)->dma, GFP_KERNEL);
  2374. if (!(*req)->ring) {
  2375. DEBUG(printk("Unable to allocate memory for req_ring\n"));
  2376. goto fail_req_ring;
  2377. }
  2378. /* Allocate memory for response ring */
  2379. *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
  2380. if (!*rsp) {
  2381. qla_printk(KERN_WARNING, ha,
  2382. "Unable to allocate memory for rsp\n");
  2383. goto fail_rsp;
  2384. }
  2385. (*rsp)->hw = ha;
  2386. (*rsp)->length = rsp_len;
  2387. (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2388. ((*rsp)->length + 1) * sizeof(response_t),
  2389. &(*rsp)->dma, GFP_KERNEL);
  2390. if (!(*rsp)->ring) {
  2391. qla_printk(KERN_WARNING, ha,
  2392. "Unable to allocate memory for rsp_ring\n");
  2393. goto fail_rsp_ring;
  2394. }
  2395. (*req)->rsp = *rsp;
  2396. (*rsp)->req = *req;
  2397. /* Allocate memory for NVRAM data for vports */
  2398. if (ha->nvram_npiv_size) {
  2399. ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
  2400. ha->nvram_npiv_size, GFP_KERNEL);
  2401. if (!ha->npiv_info) {
  2402. qla_printk(KERN_WARNING, ha,
  2403. "Unable to allocate memory for npiv info\n");
  2404. goto fail_npiv_info;
  2405. }
  2406. } else
  2407. ha->npiv_info = NULL;
  2408. /* Get consistent memory allocated for EX-INIT-CB. */
  2409. if (IS_QLA8XXX_TYPE(ha)) {
  2410. ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2411. &ha->ex_init_cb_dma);
  2412. if (!ha->ex_init_cb)
  2413. goto fail_ex_init_cb;
  2414. }
  2415. INIT_LIST_HEAD(&ha->gbl_dsd_list);
  2416. /* Get consistent memory allocated for Async Port-Database. */
  2417. if (!IS_FWI2_CAPABLE(ha)) {
  2418. ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2419. &ha->async_pd_dma);
  2420. if (!ha->async_pd)
  2421. goto fail_async_pd;
  2422. }
  2423. INIT_LIST_HEAD(&ha->vp_list);
  2424. return 1;
  2425. fail_async_pd:
  2426. dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
  2427. fail_ex_init_cb:
  2428. kfree(ha->npiv_info);
  2429. fail_npiv_info:
  2430. dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
  2431. sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
  2432. (*rsp)->ring = NULL;
  2433. (*rsp)->dma = 0;
  2434. fail_rsp_ring:
  2435. kfree(*rsp);
  2436. fail_rsp:
  2437. dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
  2438. sizeof(request_t), (*req)->ring, (*req)->dma);
  2439. (*req)->ring = NULL;
  2440. (*req)->dma = 0;
  2441. fail_req_ring:
  2442. kfree(*req);
  2443. fail_req:
  2444. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2445. ha->ct_sns, ha->ct_sns_dma);
  2446. ha->ct_sns = NULL;
  2447. ha->ct_sns_dma = 0;
  2448. fail_free_ms_iocb:
  2449. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2450. ha->ms_iocb = NULL;
  2451. ha->ms_iocb_dma = 0;
  2452. fail_dma_pool:
  2453. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2454. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2455. ha->fcp_cmnd_dma_pool = NULL;
  2456. }
  2457. fail_dl_dma_pool:
  2458. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2459. dma_pool_destroy(ha->dl_dma_pool);
  2460. ha->dl_dma_pool = NULL;
  2461. }
  2462. fail_s_dma_pool:
  2463. dma_pool_destroy(ha->s_dma_pool);
  2464. ha->s_dma_pool = NULL;
  2465. fail_free_nvram:
  2466. kfree(ha->nvram);
  2467. ha->nvram = NULL;
  2468. fail_free_ctx_mempool:
  2469. mempool_destroy(ha->ctx_mempool);
  2470. ha->ctx_mempool = NULL;
  2471. fail_free_srb_mempool:
  2472. mempool_destroy(ha->srb_mempool);
  2473. ha->srb_mempool = NULL;
  2474. fail_free_gid_list:
  2475. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2476. ha->gid_list_dma);
  2477. ha->gid_list = NULL;
  2478. ha->gid_list_dma = 0;
  2479. fail_free_init_cb:
  2480. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
  2481. ha->init_cb_dma);
  2482. ha->init_cb = NULL;
  2483. ha->init_cb_dma = 0;
  2484. fail:
  2485. DEBUG(printk("%s: Memory allocation failure\n", __func__));
  2486. return -ENOMEM;
  2487. }
  2488. /*
  2489. * qla2x00_free_fw_dump
  2490. * Frees fw dump stuff.
  2491. *
  2492. * Input:
  2493. * ha = adapter block pointer.
  2494. */
  2495. static void
  2496. qla2x00_free_fw_dump(struct qla_hw_data *ha)
  2497. {
  2498. if (ha->fce)
  2499. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  2500. ha->fce_dma);
  2501. if (ha->fw_dump) {
  2502. if (ha->eft)
  2503. dma_free_coherent(&ha->pdev->dev,
  2504. ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
  2505. vfree(ha->fw_dump);
  2506. }
  2507. ha->fce = NULL;
  2508. ha->fce_dma = 0;
  2509. ha->eft = NULL;
  2510. ha->eft_dma = 0;
  2511. ha->fw_dump = NULL;
  2512. ha->fw_dumped = 0;
  2513. ha->fw_dump_reading = 0;
  2514. }
  2515. /*
  2516. * qla2x00_mem_free
  2517. * Frees all adapter allocated memory.
  2518. *
  2519. * Input:
  2520. * ha = adapter block pointer.
  2521. */
  2522. static void
  2523. qla2x00_mem_free(struct qla_hw_data *ha)
  2524. {
  2525. qla2x00_free_fw_dump(ha);
  2526. if (ha->srb_mempool)
  2527. mempool_destroy(ha->srb_mempool);
  2528. if (ha->dcbx_tlv)
  2529. dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
  2530. ha->dcbx_tlv, ha->dcbx_tlv_dma);
  2531. if (ha->xgmac_data)
  2532. dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
  2533. ha->xgmac_data, ha->xgmac_data_dma);
  2534. if (ha->sns_cmd)
  2535. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  2536. ha->sns_cmd, ha->sns_cmd_dma);
  2537. if (ha->ct_sns)
  2538. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2539. ha->ct_sns, ha->ct_sns_dma);
  2540. if (ha->sfp_data)
  2541. dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
  2542. if (ha->edc_data)
  2543. dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
  2544. if (ha->ms_iocb)
  2545. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2546. if (ha->ex_init_cb)
  2547. dma_pool_free(ha->s_dma_pool,
  2548. ha->ex_init_cb, ha->ex_init_cb_dma);
  2549. if (ha->async_pd)
  2550. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  2551. if (ha->s_dma_pool)
  2552. dma_pool_destroy(ha->s_dma_pool);
  2553. if (ha->gid_list)
  2554. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2555. ha->gid_list_dma);
  2556. if (IS_QLA82XX(ha)) {
  2557. if (!list_empty(&ha->gbl_dsd_list)) {
  2558. struct dsd_dma *dsd_ptr, *tdsd_ptr;
  2559. /* clean up allocated prev pool */
  2560. list_for_each_entry_safe(dsd_ptr,
  2561. tdsd_ptr, &ha->gbl_dsd_list, list) {
  2562. dma_pool_free(ha->dl_dma_pool,
  2563. dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
  2564. list_del(&dsd_ptr->list);
  2565. kfree(dsd_ptr);
  2566. }
  2567. }
  2568. }
  2569. if (ha->dl_dma_pool)
  2570. dma_pool_destroy(ha->dl_dma_pool);
  2571. if (ha->fcp_cmnd_dma_pool)
  2572. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2573. if (ha->ctx_mempool)
  2574. mempool_destroy(ha->ctx_mempool);
  2575. if (ha->init_cb)
  2576. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
  2577. ha->init_cb, ha->init_cb_dma);
  2578. vfree(ha->optrom_buffer);
  2579. kfree(ha->nvram);
  2580. kfree(ha->npiv_info);
  2581. ha->srb_mempool = NULL;
  2582. ha->ctx_mempool = NULL;
  2583. ha->sns_cmd = NULL;
  2584. ha->sns_cmd_dma = 0;
  2585. ha->ct_sns = NULL;
  2586. ha->ct_sns_dma = 0;
  2587. ha->ms_iocb = NULL;
  2588. ha->ms_iocb_dma = 0;
  2589. ha->init_cb = NULL;
  2590. ha->init_cb_dma = 0;
  2591. ha->ex_init_cb = NULL;
  2592. ha->ex_init_cb_dma = 0;
  2593. ha->async_pd = NULL;
  2594. ha->async_pd_dma = 0;
  2595. ha->s_dma_pool = NULL;
  2596. ha->dl_dma_pool = NULL;
  2597. ha->fcp_cmnd_dma_pool = NULL;
  2598. ha->gid_list = NULL;
  2599. ha->gid_list_dma = 0;
  2600. }
  2601. struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
  2602. struct qla_hw_data *ha)
  2603. {
  2604. struct Scsi_Host *host;
  2605. struct scsi_qla_host *vha = NULL;
  2606. host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
  2607. if (host == NULL) {
  2608. printk(KERN_WARNING
  2609. "qla2xxx: Couldn't allocate host from scsi layer!\n");
  2610. goto fail;
  2611. }
  2612. /* Clear our data area */
  2613. vha = shost_priv(host);
  2614. memset(vha, 0, sizeof(scsi_qla_host_t));
  2615. vha->host = host;
  2616. vha->host_no = host->host_no;
  2617. vha->hw = ha;
  2618. INIT_LIST_HEAD(&vha->vp_fcports);
  2619. INIT_LIST_HEAD(&vha->work_list);
  2620. INIT_LIST_HEAD(&vha->list);
  2621. spin_lock_init(&vha->work_lock);
  2622. sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
  2623. return vha;
  2624. fail:
  2625. return vha;
  2626. }
  2627. static struct qla_work_evt *
  2628. qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
  2629. {
  2630. struct qla_work_evt *e;
  2631. uint8_t bail;
  2632. QLA_VHA_MARK_BUSY(vha, bail);
  2633. if (bail)
  2634. return NULL;
  2635. e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
  2636. if (!e) {
  2637. QLA_VHA_MARK_NOT_BUSY(vha);
  2638. return NULL;
  2639. }
  2640. INIT_LIST_HEAD(&e->list);
  2641. e->type = type;
  2642. e->flags = QLA_EVT_FLAG_FREE;
  2643. return e;
  2644. }
  2645. static int
  2646. qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
  2647. {
  2648. unsigned long flags;
  2649. spin_lock_irqsave(&vha->work_lock, flags);
  2650. list_add_tail(&e->list, &vha->work_list);
  2651. spin_unlock_irqrestore(&vha->work_lock, flags);
  2652. qla2xxx_wake_dpc(vha);
  2653. return QLA_SUCCESS;
  2654. }
  2655. int
  2656. qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
  2657. u32 data)
  2658. {
  2659. struct qla_work_evt *e;
  2660. e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
  2661. if (!e)
  2662. return QLA_FUNCTION_FAILED;
  2663. e->u.aen.code = code;
  2664. e->u.aen.data = data;
  2665. return qla2x00_post_work(vha, e);
  2666. }
  2667. int
  2668. qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
  2669. {
  2670. struct qla_work_evt *e;
  2671. e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
  2672. if (!e)
  2673. return QLA_FUNCTION_FAILED;
  2674. memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2675. return qla2x00_post_work(vha, e);
  2676. }
  2677. #define qla2x00_post_async_work(name, type) \
  2678. int qla2x00_post_async_##name##_work( \
  2679. struct scsi_qla_host *vha, \
  2680. fc_port_t *fcport, uint16_t *data) \
  2681. { \
  2682. struct qla_work_evt *e; \
  2683. \
  2684. e = qla2x00_alloc_work(vha, type); \
  2685. if (!e) \
  2686. return QLA_FUNCTION_FAILED; \
  2687. \
  2688. e->u.logio.fcport = fcport; \
  2689. if (data) { \
  2690. e->u.logio.data[0] = data[0]; \
  2691. e->u.logio.data[1] = data[1]; \
  2692. } \
  2693. return qla2x00_post_work(vha, e); \
  2694. }
  2695. qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
  2696. qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
  2697. qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
  2698. qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
  2699. qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
  2700. qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
  2701. int
  2702. qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
  2703. {
  2704. struct qla_work_evt *e;
  2705. e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
  2706. if (!e)
  2707. return QLA_FUNCTION_FAILED;
  2708. e->u.uevent.code = code;
  2709. return qla2x00_post_work(vha, e);
  2710. }
  2711. static void
  2712. qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
  2713. {
  2714. char event_string[40];
  2715. char *envp[] = { event_string, NULL };
  2716. switch (code) {
  2717. case QLA_UEVENT_CODE_FW_DUMP:
  2718. snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
  2719. vha->host_no);
  2720. break;
  2721. default:
  2722. /* do nothing */
  2723. break;
  2724. }
  2725. kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
  2726. }
  2727. void
  2728. qla2x00_do_work(struct scsi_qla_host *vha)
  2729. {
  2730. struct qla_work_evt *e, *tmp;
  2731. unsigned long flags;
  2732. LIST_HEAD(work);
  2733. spin_lock_irqsave(&vha->work_lock, flags);
  2734. list_splice_init(&vha->work_list, &work);
  2735. spin_unlock_irqrestore(&vha->work_lock, flags);
  2736. list_for_each_entry_safe(e, tmp, &work, list) {
  2737. list_del_init(&e->list);
  2738. switch (e->type) {
  2739. case QLA_EVT_AEN:
  2740. fc_host_post_event(vha->host, fc_get_event_number(),
  2741. e->u.aen.code, e->u.aen.data);
  2742. break;
  2743. case QLA_EVT_IDC_ACK:
  2744. qla81xx_idc_ack(vha, e->u.idc_ack.mb);
  2745. break;
  2746. case QLA_EVT_ASYNC_LOGIN:
  2747. qla2x00_async_login(vha, e->u.logio.fcport,
  2748. e->u.logio.data);
  2749. break;
  2750. case QLA_EVT_ASYNC_LOGIN_DONE:
  2751. qla2x00_async_login_done(vha, e->u.logio.fcport,
  2752. e->u.logio.data);
  2753. break;
  2754. case QLA_EVT_ASYNC_LOGOUT:
  2755. qla2x00_async_logout(vha, e->u.logio.fcport);
  2756. break;
  2757. case QLA_EVT_ASYNC_LOGOUT_DONE:
  2758. qla2x00_async_logout_done(vha, e->u.logio.fcport,
  2759. e->u.logio.data);
  2760. break;
  2761. case QLA_EVT_ASYNC_ADISC:
  2762. qla2x00_async_adisc(vha, e->u.logio.fcport,
  2763. e->u.logio.data);
  2764. break;
  2765. case QLA_EVT_ASYNC_ADISC_DONE:
  2766. qla2x00_async_adisc_done(vha, e->u.logio.fcport,
  2767. e->u.logio.data);
  2768. break;
  2769. case QLA_EVT_UEVENT:
  2770. qla2x00_uevent_emit(vha, e->u.uevent.code);
  2771. break;
  2772. }
  2773. if (e->flags & QLA_EVT_FLAG_FREE)
  2774. kfree(e);
  2775. /* For each work completed decrement vha ref count */
  2776. QLA_VHA_MARK_NOT_BUSY(vha);
  2777. }
  2778. }
  2779. /* Relogins all the fcports of a vport
  2780. * Context: dpc thread
  2781. */
  2782. void qla2x00_relogin(struct scsi_qla_host *vha)
  2783. {
  2784. fc_port_t *fcport;
  2785. int status;
  2786. uint16_t next_loopid = 0;
  2787. struct qla_hw_data *ha = vha->hw;
  2788. uint16_t data[2];
  2789. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2790. /*
  2791. * If the port is not ONLINE then try to login
  2792. * to it if we haven't run out of retries.
  2793. */
  2794. if (atomic_read(&fcport->state) != FCS_ONLINE &&
  2795. fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
  2796. fcport->login_retry--;
  2797. if (fcport->flags & FCF_FABRIC_DEVICE) {
  2798. if (fcport->flags & FCF_FCP2_DEVICE)
  2799. ha->isp_ops->fabric_logout(vha,
  2800. fcport->loop_id,
  2801. fcport->d_id.b.domain,
  2802. fcport->d_id.b.area,
  2803. fcport->d_id.b.al_pa);
  2804. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2805. fcport->loop_id = next_loopid =
  2806. ha->min_external_loopid;
  2807. status = qla2x00_find_new_loop_id(
  2808. vha, fcport);
  2809. if (status != QLA_SUCCESS) {
  2810. /* Ran out of IDs to use */
  2811. break;
  2812. }
  2813. }
  2814. if (IS_ALOGIO_CAPABLE(ha)) {
  2815. fcport->flags |= FCF_ASYNC_SENT;
  2816. data[0] = 0;
  2817. data[1] = QLA_LOGIO_LOGIN_RETRIED;
  2818. status = qla2x00_post_async_login_work(
  2819. vha, fcport, data);
  2820. if (status == QLA_SUCCESS)
  2821. continue;
  2822. /* Attempt a retry. */
  2823. status = 1;
  2824. } else
  2825. status = qla2x00_fabric_login(vha,
  2826. fcport, &next_loopid);
  2827. } else
  2828. status = qla2x00_local_device_login(vha,
  2829. fcport);
  2830. if (status == QLA_SUCCESS) {
  2831. fcport->old_loop_id = fcport->loop_id;
  2832. DEBUG(printk("scsi(%ld): port login OK: logged "
  2833. "in ID 0x%x\n", vha->host_no, fcport->loop_id));
  2834. qla2x00_update_fcport(vha, fcport);
  2835. } else if (status == 1) {
  2836. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2837. /* retry the login again */
  2838. DEBUG(printk("scsi(%ld): Retrying"
  2839. " %d login again loop_id 0x%x\n",
  2840. vha->host_no, fcport->login_retry,
  2841. fcport->loop_id));
  2842. } else {
  2843. fcport->login_retry = 0;
  2844. }
  2845. if (fcport->login_retry == 0 && status != QLA_SUCCESS)
  2846. fcport->loop_id = FC_NO_LOOP_ID;
  2847. }
  2848. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2849. break;
  2850. }
  2851. }
  2852. /**************************************************************************
  2853. * qla2x00_do_dpc
  2854. * This kernel thread is a task that is schedule by the interrupt handler
  2855. * to perform the background processing for interrupts.
  2856. *
  2857. * Notes:
  2858. * This task always run in the context of a kernel thread. It
  2859. * is kick-off by the driver's detect code and starts up
  2860. * up one per adapter. It immediately goes to sleep and waits for
  2861. * some fibre event. When either the interrupt handler or
  2862. * the timer routine detects a event it will one of the task
  2863. * bits then wake us up.
  2864. **************************************************************************/
  2865. static int
  2866. qla2x00_do_dpc(void *data)
  2867. {
  2868. int rval;
  2869. scsi_qla_host_t *base_vha;
  2870. struct qla_hw_data *ha;
  2871. ha = (struct qla_hw_data *)data;
  2872. base_vha = pci_get_drvdata(ha->pdev);
  2873. set_user_nice(current, -20);
  2874. set_current_state(TASK_INTERRUPTIBLE);
  2875. while (!kthread_should_stop()) {
  2876. DEBUG3(printk("qla2x00: DPC handler sleeping\n"));
  2877. schedule();
  2878. __set_current_state(TASK_RUNNING);
  2879. DEBUG3(printk("qla2x00: DPC handler waking up\n"));
  2880. /* Initialization not yet finished. Don't do anything yet. */
  2881. if (!base_vha->flags.init_done)
  2882. continue;
  2883. if (ha->flags.eeh_busy) {
  2884. DEBUG17(qla_printk(KERN_WARNING, ha,
  2885. "qla2x00_do_dpc: dpc_flags: %lx\n",
  2886. base_vha->dpc_flags));
  2887. continue;
  2888. }
  2889. DEBUG3(printk("scsi(%ld): DPC handler\n", base_vha->host_no));
  2890. ha->dpc_active = 1;
  2891. if (ha->flags.mbox_busy) {
  2892. ha->dpc_active = 0;
  2893. continue;
  2894. }
  2895. qla2x00_do_work(base_vha);
  2896. if (IS_QLA82XX(ha)) {
  2897. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  2898. &base_vha->dpc_flags)) {
  2899. qla82xx_idc_lock(ha);
  2900. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  2901. QLA82XX_DEV_FAILED);
  2902. qla82xx_idc_unlock(ha);
  2903. qla_printk(KERN_INFO, ha,
  2904. "HW State: FAILED\n");
  2905. qla82xx_device_state_handler(base_vha);
  2906. continue;
  2907. }
  2908. if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
  2909. &base_vha->dpc_flags)) {
  2910. DEBUG(printk(KERN_INFO
  2911. "scsi(%ld): dpc: sched "
  2912. "qla82xx_fcoe_ctx_reset ha = %p\n",
  2913. base_vha->host_no, ha));
  2914. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2915. &base_vha->dpc_flags))) {
  2916. if (qla82xx_fcoe_ctx_reset(base_vha)) {
  2917. /* FCoE-ctx reset failed.
  2918. * Escalate to chip-reset
  2919. */
  2920. set_bit(ISP_ABORT_NEEDED,
  2921. &base_vha->dpc_flags);
  2922. }
  2923. clear_bit(ABORT_ISP_ACTIVE,
  2924. &base_vha->dpc_flags);
  2925. }
  2926. DEBUG(printk("scsi(%ld): dpc:"
  2927. " qla82xx_fcoe_ctx_reset end\n",
  2928. base_vha->host_no));
  2929. }
  2930. }
  2931. if (test_and_clear_bit(ISP_ABORT_NEEDED,
  2932. &base_vha->dpc_flags)) {
  2933. DEBUG(printk("scsi(%ld): dpc: sched "
  2934. "qla2x00_abort_isp ha = %p\n",
  2935. base_vha->host_no, ha));
  2936. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2937. &base_vha->dpc_flags))) {
  2938. if (ha->isp_ops->abort_isp(base_vha)) {
  2939. /* failed. retry later */
  2940. set_bit(ISP_ABORT_NEEDED,
  2941. &base_vha->dpc_flags);
  2942. }
  2943. clear_bit(ABORT_ISP_ACTIVE,
  2944. &base_vha->dpc_flags);
  2945. }
  2946. DEBUG(printk("scsi(%ld): dpc: qla2x00_abort_isp end\n",
  2947. base_vha->host_no));
  2948. }
  2949. if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
  2950. qla2x00_update_fcports(base_vha);
  2951. clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2952. }
  2953. if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
  2954. DEBUG(printk(KERN_INFO "scsi(%ld): dpc: sched "
  2955. "qla2x00_quiesce_needed ha = %p\n",
  2956. base_vha->host_no, ha));
  2957. qla82xx_device_state_handler(base_vha);
  2958. clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
  2959. if (!ha->flags.quiesce_owner) {
  2960. qla2x00_perform_loop_resync(base_vha);
  2961. qla82xx_idc_lock(ha);
  2962. qla82xx_clear_qsnt_ready(base_vha);
  2963. qla82xx_idc_unlock(ha);
  2964. }
  2965. }
  2966. if (test_and_clear_bit(RESET_MARKER_NEEDED,
  2967. &base_vha->dpc_flags) &&
  2968. (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
  2969. DEBUG(printk("scsi(%ld): qla2x00_reset_marker()\n",
  2970. base_vha->host_no));
  2971. qla2x00_rst_aen(base_vha);
  2972. clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
  2973. }
  2974. /* Retry each device up to login retry count */
  2975. if ((test_and_clear_bit(RELOGIN_NEEDED,
  2976. &base_vha->dpc_flags)) &&
  2977. !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
  2978. atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
  2979. DEBUG(printk("scsi(%ld): qla2x00_port_login()\n",
  2980. base_vha->host_no));
  2981. qla2x00_relogin(base_vha);
  2982. DEBUG(printk("scsi(%ld): qla2x00_port_login - end\n",
  2983. base_vha->host_no));
  2984. }
  2985. if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
  2986. &base_vha->dpc_flags)) {
  2987. DEBUG(printk("scsi(%ld): qla2x00_loop_resync()\n",
  2988. base_vha->host_no));
  2989. if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
  2990. &base_vha->dpc_flags))) {
  2991. rval = qla2x00_loop_resync(base_vha);
  2992. clear_bit(LOOP_RESYNC_ACTIVE,
  2993. &base_vha->dpc_flags);
  2994. }
  2995. DEBUG(printk("scsi(%ld): qla2x00_loop_resync - end\n",
  2996. base_vha->host_no));
  2997. }
  2998. if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
  2999. atomic_read(&base_vha->loop_state) == LOOP_READY) {
  3000. clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
  3001. qla2xxx_flash_npiv_conf(base_vha);
  3002. }
  3003. if (!ha->interrupts_on)
  3004. ha->isp_ops->enable_intrs(ha);
  3005. if (test_and_clear_bit(BEACON_BLINK_NEEDED,
  3006. &base_vha->dpc_flags))
  3007. ha->isp_ops->beacon_blink(base_vha);
  3008. qla2x00_do_dpc_all_vps(base_vha);
  3009. ha->dpc_active = 0;
  3010. set_current_state(TASK_INTERRUPTIBLE);
  3011. } /* End of while(1) */
  3012. __set_current_state(TASK_RUNNING);
  3013. DEBUG(printk("scsi(%ld): DPC handler exiting\n", base_vha->host_no));
  3014. /*
  3015. * Make sure that nobody tries to wake us up again.
  3016. */
  3017. ha->dpc_active = 0;
  3018. /* Cleanup any residual CTX SRBs. */
  3019. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  3020. return 0;
  3021. }
  3022. void
  3023. qla2xxx_wake_dpc(struct scsi_qla_host *vha)
  3024. {
  3025. struct qla_hw_data *ha = vha->hw;
  3026. struct task_struct *t = ha->dpc_thread;
  3027. if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
  3028. wake_up_process(t);
  3029. }
  3030. /*
  3031. * qla2x00_rst_aen
  3032. * Processes asynchronous reset.
  3033. *
  3034. * Input:
  3035. * ha = adapter block pointer.
  3036. */
  3037. static void
  3038. qla2x00_rst_aen(scsi_qla_host_t *vha)
  3039. {
  3040. if (vha->flags.online && !vha->flags.reset_active &&
  3041. !atomic_read(&vha->loop_down_timer) &&
  3042. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
  3043. do {
  3044. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3045. /*
  3046. * Issue marker command only when we are going to start
  3047. * the I/O.
  3048. */
  3049. vha->marker_needed = 1;
  3050. } while (!atomic_read(&vha->loop_down_timer) &&
  3051. (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
  3052. }
  3053. }
  3054. static void
  3055. qla2x00_sp_free_dma(srb_t *sp)
  3056. {
  3057. struct scsi_cmnd *cmd = sp->cmd;
  3058. struct qla_hw_data *ha = sp->fcport->vha->hw;
  3059. if (sp->flags & SRB_DMA_VALID) {
  3060. scsi_dma_unmap(cmd);
  3061. sp->flags &= ~SRB_DMA_VALID;
  3062. }
  3063. if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
  3064. dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
  3065. scsi_prot_sg_count(cmd), cmd->sc_data_direction);
  3066. sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
  3067. }
  3068. if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
  3069. /* List assured to be having elements */
  3070. qla2x00_clean_dsd_pool(ha, sp);
  3071. sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
  3072. }
  3073. if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
  3074. dma_pool_free(ha->dl_dma_pool, sp->ctx,
  3075. ((struct crc_context *)sp->ctx)->crc_ctx_dma);
  3076. sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
  3077. }
  3078. CMD_SP(cmd) = NULL;
  3079. }
  3080. static void
  3081. qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
  3082. {
  3083. struct scsi_cmnd *cmd = sp->cmd;
  3084. qla2x00_sp_free_dma(sp);
  3085. if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
  3086. struct ct6_dsd *ctx = sp->ctx;
  3087. dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
  3088. ctx->fcp_cmnd_dma);
  3089. list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
  3090. ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
  3091. ha->gbl_dsd_avail += ctx->dsd_use_cnt;
  3092. mempool_free(sp->ctx, ha->ctx_mempool);
  3093. sp->ctx = NULL;
  3094. }
  3095. mempool_free(sp, ha->srb_mempool);
  3096. cmd->scsi_done(cmd);
  3097. }
  3098. void
  3099. qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
  3100. {
  3101. if (atomic_read(&sp->ref_count) == 0) {
  3102. DEBUG2(qla_printk(KERN_WARNING, ha,
  3103. "SP reference-count to ZERO -- sp=%p\n", sp));
  3104. DEBUG2(BUG());
  3105. return;
  3106. }
  3107. if (!atomic_dec_and_test(&sp->ref_count))
  3108. return;
  3109. qla2x00_sp_final_compl(ha, sp);
  3110. }
  3111. /**************************************************************************
  3112. * qla2x00_timer
  3113. *
  3114. * Description:
  3115. * One second timer
  3116. *
  3117. * Context: Interrupt
  3118. ***************************************************************************/
  3119. void
  3120. qla2x00_timer(scsi_qla_host_t *vha)
  3121. {
  3122. unsigned long cpu_flags = 0;
  3123. int start_dpc = 0;
  3124. int index;
  3125. srb_t *sp;
  3126. uint16_t w;
  3127. struct qla_hw_data *ha = vha->hw;
  3128. struct req_que *req;
  3129. if (ha->flags.eeh_busy) {
  3130. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3131. return;
  3132. }
  3133. /* Hardware read to raise pending EEH errors during mailbox waits. */
  3134. if (!pci_channel_offline(ha->pdev))
  3135. pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
  3136. /* Make sure qla82xx_watchdog is run only for physical port */
  3137. if (!vha->vp_idx && IS_QLA82XX(ha)) {
  3138. if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
  3139. start_dpc++;
  3140. qla82xx_watchdog(vha);
  3141. }
  3142. /* Loop down handler. */
  3143. if (atomic_read(&vha->loop_down_timer) > 0 &&
  3144. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  3145. !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
  3146. && vha->flags.online) {
  3147. if (atomic_read(&vha->loop_down_timer) ==
  3148. vha->loop_down_abort_time) {
  3149. DEBUG(printk("scsi(%ld): Loop Down - aborting the "
  3150. "queues before time expire\n",
  3151. vha->host_no));
  3152. if (!IS_QLA2100(ha) && vha->link_down_timeout)
  3153. atomic_set(&vha->loop_state, LOOP_DEAD);
  3154. /*
  3155. * Schedule an ISP abort to return any FCP2-device
  3156. * commands.
  3157. */
  3158. /* NPIV - scan physical port only */
  3159. if (!vha->vp_idx) {
  3160. spin_lock_irqsave(&ha->hardware_lock,
  3161. cpu_flags);
  3162. req = ha->req_q_map[0];
  3163. for (index = 1;
  3164. index < MAX_OUTSTANDING_COMMANDS;
  3165. index++) {
  3166. fc_port_t *sfcp;
  3167. sp = req->outstanding_cmds[index];
  3168. if (!sp)
  3169. continue;
  3170. if (sp->ctx && !IS_PROT_IO(sp))
  3171. continue;
  3172. sfcp = sp->fcport;
  3173. if (!(sfcp->flags & FCF_FCP2_DEVICE))
  3174. continue;
  3175. if (IS_QLA82XX(ha))
  3176. set_bit(FCOE_CTX_RESET_NEEDED,
  3177. &vha->dpc_flags);
  3178. else
  3179. set_bit(ISP_ABORT_NEEDED,
  3180. &vha->dpc_flags);
  3181. break;
  3182. }
  3183. spin_unlock_irqrestore(&ha->hardware_lock,
  3184. cpu_flags);
  3185. }
  3186. start_dpc++;
  3187. }
  3188. /* if the loop has been down for 4 minutes, reinit adapter */
  3189. if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
  3190. if (!(vha->device_flags & DFLG_NO_CABLE)) {
  3191. DEBUG(printk("scsi(%ld): Loop down - "
  3192. "aborting ISP.\n",
  3193. vha->host_no));
  3194. qla_printk(KERN_WARNING, ha,
  3195. "Loop down - aborting ISP.\n");
  3196. if (IS_QLA82XX(ha))
  3197. set_bit(FCOE_CTX_RESET_NEEDED,
  3198. &vha->dpc_flags);
  3199. else
  3200. set_bit(ISP_ABORT_NEEDED,
  3201. &vha->dpc_flags);
  3202. }
  3203. }
  3204. DEBUG3(printk("scsi(%ld): Loop Down - seconds remaining %d\n",
  3205. vha->host_no,
  3206. atomic_read(&vha->loop_down_timer)));
  3207. }
  3208. /* Check if beacon LED needs to be blinked for physical host only */
  3209. if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
  3210. set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
  3211. start_dpc++;
  3212. }
  3213. /* Process any deferred work. */
  3214. if (!list_empty(&vha->work_list))
  3215. start_dpc++;
  3216. /* Schedule the DPC routine if needed */
  3217. if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  3218. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
  3219. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
  3220. start_dpc ||
  3221. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
  3222. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
  3223. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
  3224. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
  3225. test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
  3226. test_bit(RELOGIN_NEEDED, &vha->dpc_flags)))
  3227. qla2xxx_wake_dpc(vha);
  3228. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3229. }
  3230. /* Firmware interface routines. */
  3231. #define FW_BLOBS 8
  3232. #define FW_ISP21XX 0
  3233. #define FW_ISP22XX 1
  3234. #define FW_ISP2300 2
  3235. #define FW_ISP2322 3
  3236. #define FW_ISP24XX 4
  3237. #define FW_ISP25XX 5
  3238. #define FW_ISP81XX 6
  3239. #define FW_ISP82XX 7
  3240. #define FW_FILE_ISP21XX "ql2100_fw.bin"
  3241. #define FW_FILE_ISP22XX "ql2200_fw.bin"
  3242. #define FW_FILE_ISP2300 "ql2300_fw.bin"
  3243. #define FW_FILE_ISP2322 "ql2322_fw.bin"
  3244. #define FW_FILE_ISP24XX "ql2400_fw.bin"
  3245. #define FW_FILE_ISP25XX "ql2500_fw.bin"
  3246. #define FW_FILE_ISP81XX "ql8100_fw.bin"
  3247. #define FW_FILE_ISP82XX "ql8200_fw.bin"
  3248. static DEFINE_MUTEX(qla_fw_lock);
  3249. static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
  3250. { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
  3251. { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
  3252. { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
  3253. { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
  3254. { .name = FW_FILE_ISP24XX, },
  3255. { .name = FW_FILE_ISP25XX, },
  3256. { .name = FW_FILE_ISP81XX, },
  3257. { .name = FW_FILE_ISP82XX, },
  3258. };
  3259. struct fw_blob *
  3260. qla2x00_request_firmware(scsi_qla_host_t *vha)
  3261. {
  3262. struct qla_hw_data *ha = vha->hw;
  3263. struct fw_blob *blob;
  3264. blob = NULL;
  3265. if (IS_QLA2100(ha)) {
  3266. blob = &qla_fw_blobs[FW_ISP21XX];
  3267. } else if (IS_QLA2200(ha)) {
  3268. blob = &qla_fw_blobs[FW_ISP22XX];
  3269. } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3270. blob = &qla_fw_blobs[FW_ISP2300];
  3271. } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  3272. blob = &qla_fw_blobs[FW_ISP2322];
  3273. } else if (IS_QLA24XX_TYPE(ha)) {
  3274. blob = &qla_fw_blobs[FW_ISP24XX];
  3275. } else if (IS_QLA25XX(ha)) {
  3276. blob = &qla_fw_blobs[FW_ISP25XX];
  3277. } else if (IS_QLA81XX(ha)) {
  3278. blob = &qla_fw_blobs[FW_ISP81XX];
  3279. } else if (IS_QLA82XX(ha)) {
  3280. blob = &qla_fw_blobs[FW_ISP82XX];
  3281. }
  3282. mutex_lock(&qla_fw_lock);
  3283. if (blob->fw)
  3284. goto out;
  3285. if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
  3286. DEBUG2(printk("scsi(%ld): Failed to load firmware image "
  3287. "(%s).\n", vha->host_no, blob->name));
  3288. blob->fw = NULL;
  3289. blob = NULL;
  3290. goto out;
  3291. }
  3292. out:
  3293. mutex_unlock(&qla_fw_lock);
  3294. return blob;
  3295. }
  3296. static void
  3297. qla2x00_release_firmware(void)
  3298. {
  3299. int idx;
  3300. mutex_lock(&qla_fw_lock);
  3301. for (idx = 0; idx < FW_BLOBS; idx++)
  3302. if (qla_fw_blobs[idx].fw)
  3303. release_firmware(qla_fw_blobs[idx].fw);
  3304. mutex_unlock(&qla_fw_lock);
  3305. }
  3306. static pci_ers_result_t
  3307. qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  3308. {
  3309. scsi_qla_host_t *vha = pci_get_drvdata(pdev);
  3310. struct qla_hw_data *ha = vha->hw;
  3311. DEBUG2(qla_printk(KERN_WARNING, ha, "error_detected:state %x\n",
  3312. state));
  3313. switch (state) {
  3314. case pci_channel_io_normal:
  3315. ha->flags.eeh_busy = 0;
  3316. return PCI_ERS_RESULT_CAN_RECOVER;
  3317. case pci_channel_io_frozen:
  3318. ha->flags.eeh_busy = 1;
  3319. /* For ISP82XX complete any pending mailbox cmd */
  3320. if (IS_QLA82XX(ha)) {
  3321. ha->flags.isp82xx_fw_hung = 1;
  3322. if (ha->flags.mbox_busy) {
  3323. ha->flags.mbox_int = 1;
  3324. DEBUG2(qla_printk(KERN_ERR, ha,
  3325. "Due to pci channel io frozen, doing premature "
  3326. "completion of mbx command\n"));
  3327. complete(&ha->mbx_intr_comp);
  3328. }
  3329. }
  3330. qla2x00_free_irqs(vha);
  3331. pci_disable_device(pdev);
  3332. /* Return back all IOs */
  3333. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3334. return PCI_ERS_RESULT_NEED_RESET;
  3335. case pci_channel_io_perm_failure:
  3336. ha->flags.pci_channel_io_perm_failure = 1;
  3337. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  3338. return PCI_ERS_RESULT_DISCONNECT;
  3339. }
  3340. return PCI_ERS_RESULT_NEED_RESET;
  3341. }
  3342. static pci_ers_result_t
  3343. qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
  3344. {
  3345. int risc_paused = 0;
  3346. uint32_t stat;
  3347. unsigned long flags;
  3348. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3349. struct qla_hw_data *ha = base_vha->hw;
  3350. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3351. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  3352. if (IS_QLA82XX(ha))
  3353. return PCI_ERS_RESULT_RECOVERED;
  3354. spin_lock_irqsave(&ha->hardware_lock, flags);
  3355. if (IS_QLA2100(ha) || IS_QLA2200(ha)){
  3356. stat = RD_REG_DWORD(&reg->hccr);
  3357. if (stat & HCCR_RISC_PAUSE)
  3358. risc_paused = 1;
  3359. } else if (IS_QLA23XX(ha)) {
  3360. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  3361. if (stat & HSR_RISC_PAUSED)
  3362. risc_paused = 1;
  3363. } else if (IS_FWI2_CAPABLE(ha)) {
  3364. stat = RD_REG_DWORD(&reg24->host_status);
  3365. if (stat & HSRX_RISC_PAUSED)
  3366. risc_paused = 1;
  3367. }
  3368. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3369. if (risc_paused) {
  3370. qla_printk(KERN_INFO, ha, "RISC paused -- mmio_enabled, "
  3371. "Dumping firmware!\n");
  3372. ha->isp_ops->fw_dump(base_vha, 0);
  3373. return PCI_ERS_RESULT_NEED_RESET;
  3374. } else
  3375. return PCI_ERS_RESULT_RECOVERED;
  3376. }
  3377. uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
  3378. {
  3379. uint32_t rval = QLA_FUNCTION_FAILED;
  3380. uint32_t drv_active = 0;
  3381. struct qla_hw_data *ha = base_vha->hw;
  3382. int fn;
  3383. struct pci_dev *other_pdev = NULL;
  3384. DEBUG17(qla_printk(KERN_INFO, ha,
  3385. "scsi(%ld): In qla82xx_error_recovery\n", base_vha->host_no));
  3386. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3387. if (base_vha->flags.online) {
  3388. /* Abort all outstanding commands,
  3389. * so as to be requeued later */
  3390. qla2x00_abort_isp_cleanup(base_vha);
  3391. }
  3392. fn = PCI_FUNC(ha->pdev->devfn);
  3393. while (fn > 0) {
  3394. fn--;
  3395. DEBUG17(qla_printk(KERN_INFO, ha,
  3396. "Finding pci device at function = 0x%x\n", fn));
  3397. other_pdev =
  3398. pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
  3399. ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
  3400. fn));
  3401. if (!other_pdev)
  3402. continue;
  3403. if (atomic_read(&other_pdev->enable_cnt)) {
  3404. DEBUG17(qla_printk(KERN_INFO, ha,
  3405. "Found PCI func available and enabled at 0x%x\n",
  3406. fn));
  3407. pci_dev_put(other_pdev);
  3408. break;
  3409. }
  3410. pci_dev_put(other_pdev);
  3411. }
  3412. if (!fn) {
  3413. /* Reset owner */
  3414. DEBUG17(qla_printk(KERN_INFO, ha,
  3415. "This devfn is reset owner = 0x%x\n", ha->pdev->devfn));
  3416. qla82xx_idc_lock(ha);
  3417. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3418. QLA82XX_DEV_INITIALIZING);
  3419. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
  3420. QLA82XX_IDC_VERSION);
  3421. drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  3422. DEBUG17(qla_printk(KERN_INFO, ha,
  3423. "drv_active = 0x%x\n", drv_active));
  3424. qla82xx_idc_unlock(ha);
  3425. /* Reset if device is not already reset
  3426. * drv_active would be 0 if a reset has already been done
  3427. */
  3428. if (drv_active)
  3429. rval = qla82xx_start_firmware(base_vha);
  3430. else
  3431. rval = QLA_SUCCESS;
  3432. qla82xx_idc_lock(ha);
  3433. if (rval != QLA_SUCCESS) {
  3434. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  3435. qla82xx_clear_drv_active(ha);
  3436. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3437. QLA82XX_DEV_FAILED);
  3438. } else {
  3439. qla_printk(KERN_INFO, ha, "HW State: READY\n");
  3440. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3441. QLA82XX_DEV_READY);
  3442. qla82xx_idc_unlock(ha);
  3443. ha->flags.isp82xx_fw_hung = 0;
  3444. rval = qla82xx_restart_isp(base_vha);
  3445. qla82xx_idc_lock(ha);
  3446. /* Clear driver state register */
  3447. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
  3448. qla82xx_set_drv_active(base_vha);
  3449. }
  3450. qla82xx_idc_unlock(ha);
  3451. } else {
  3452. DEBUG17(qla_printk(KERN_INFO, ha,
  3453. "This devfn is not reset owner = 0x%x\n", ha->pdev->devfn));
  3454. if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
  3455. QLA82XX_DEV_READY)) {
  3456. ha->flags.isp82xx_fw_hung = 0;
  3457. rval = qla82xx_restart_isp(base_vha);
  3458. qla82xx_idc_lock(ha);
  3459. qla82xx_set_drv_active(base_vha);
  3460. qla82xx_idc_unlock(ha);
  3461. }
  3462. }
  3463. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3464. return rval;
  3465. }
  3466. static pci_ers_result_t
  3467. qla2xxx_pci_slot_reset(struct pci_dev *pdev)
  3468. {
  3469. pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
  3470. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3471. struct qla_hw_data *ha = base_vha->hw;
  3472. struct rsp_que *rsp;
  3473. int rc, retries = 10;
  3474. DEBUG17(qla_printk(KERN_WARNING, ha, "slot_reset\n"));
  3475. /* Workaround: qla2xxx driver which access hardware earlier
  3476. * needs error state to be pci_channel_io_online.
  3477. * Otherwise mailbox command timesout.
  3478. */
  3479. pdev->error_state = pci_channel_io_normal;
  3480. pci_restore_state(pdev);
  3481. /* pci_restore_state() clears the saved_state flag of the device
  3482. * save restored state which resets saved_state flag
  3483. */
  3484. pci_save_state(pdev);
  3485. if (ha->mem_only)
  3486. rc = pci_enable_device_mem(pdev);
  3487. else
  3488. rc = pci_enable_device(pdev);
  3489. if (rc) {
  3490. qla_printk(KERN_WARNING, ha,
  3491. "Can't re-enable PCI device after reset.\n");
  3492. goto exit_slot_reset;
  3493. }
  3494. rsp = ha->rsp_q_map[0];
  3495. if (qla2x00_request_irqs(ha, rsp))
  3496. goto exit_slot_reset;
  3497. if (ha->isp_ops->pci_config(base_vha))
  3498. goto exit_slot_reset;
  3499. if (IS_QLA82XX(ha)) {
  3500. if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
  3501. ret = PCI_ERS_RESULT_RECOVERED;
  3502. goto exit_slot_reset;
  3503. } else
  3504. goto exit_slot_reset;
  3505. }
  3506. while (ha->flags.mbox_busy && retries--)
  3507. msleep(1000);
  3508. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3509. if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
  3510. ret = PCI_ERS_RESULT_RECOVERED;
  3511. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3512. exit_slot_reset:
  3513. DEBUG17(qla_printk(KERN_WARNING, ha,
  3514. "slot_reset-return:ret=%x\n", ret));
  3515. return ret;
  3516. }
  3517. static void
  3518. qla2xxx_pci_resume(struct pci_dev *pdev)
  3519. {
  3520. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3521. struct qla_hw_data *ha = base_vha->hw;
  3522. int ret;
  3523. DEBUG17(qla_printk(KERN_WARNING, ha, "pci_resume\n"));
  3524. ret = qla2x00_wait_for_hba_online(base_vha);
  3525. if (ret != QLA_SUCCESS) {
  3526. qla_printk(KERN_ERR, ha,
  3527. "the device failed to resume I/O "
  3528. "from slot/link_reset");
  3529. }
  3530. pci_cleanup_aer_uncorrect_error_status(pdev);
  3531. ha->flags.eeh_busy = 0;
  3532. }
  3533. static struct pci_error_handlers qla2xxx_err_handler = {
  3534. .error_detected = qla2xxx_pci_error_detected,
  3535. .mmio_enabled = qla2xxx_pci_mmio_enabled,
  3536. .slot_reset = qla2xxx_pci_slot_reset,
  3537. .resume = qla2xxx_pci_resume,
  3538. };
  3539. static struct pci_device_id qla2xxx_pci_tbl[] = {
  3540. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
  3541. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
  3542. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
  3543. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
  3544. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
  3545. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
  3546. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
  3547. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
  3548. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
  3549. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
  3550. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
  3551. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
  3552. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
  3553. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
  3554. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
  3555. { 0 },
  3556. };
  3557. MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
  3558. static struct pci_driver qla2xxx_pci_driver = {
  3559. .name = QLA2XXX_DRIVER_NAME,
  3560. .driver = {
  3561. .owner = THIS_MODULE,
  3562. },
  3563. .id_table = qla2xxx_pci_tbl,
  3564. .probe = qla2x00_probe_one,
  3565. .remove = qla2x00_remove_one,
  3566. .shutdown = qla2x00_shutdown,
  3567. .err_handler = &qla2xxx_err_handler,
  3568. };
  3569. static struct file_operations apidev_fops = {
  3570. .owner = THIS_MODULE,
  3571. .llseek = noop_llseek,
  3572. };
  3573. /**
  3574. * qla2x00_module_init - Module initialization.
  3575. **/
  3576. static int __init
  3577. qla2x00_module_init(void)
  3578. {
  3579. int ret = 0;
  3580. /* Allocate cache for SRBs. */
  3581. srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
  3582. SLAB_HWCACHE_ALIGN, NULL);
  3583. if (srb_cachep == NULL) {
  3584. printk(KERN_ERR
  3585. "qla2xxx: Unable to allocate SRB cache...Failing load!\n");
  3586. return -ENOMEM;
  3587. }
  3588. /* Derive version string. */
  3589. strcpy(qla2x00_version_str, QLA2XXX_VERSION);
  3590. if (ql2xextended_error_logging)
  3591. strcat(qla2x00_version_str, "-debug");
  3592. qla2xxx_transport_template =
  3593. fc_attach_transport(&qla2xxx_transport_functions);
  3594. if (!qla2xxx_transport_template) {
  3595. kmem_cache_destroy(srb_cachep);
  3596. return -ENODEV;
  3597. }
  3598. apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
  3599. if (apidev_major < 0) {
  3600. printk(KERN_WARNING "qla2xxx: Unable to register char device "
  3601. "%s\n", QLA2XXX_APIDEV);
  3602. }
  3603. qla2xxx_transport_vport_template =
  3604. fc_attach_transport(&qla2xxx_transport_vport_functions);
  3605. if (!qla2xxx_transport_vport_template) {
  3606. kmem_cache_destroy(srb_cachep);
  3607. fc_release_transport(qla2xxx_transport_template);
  3608. return -ENODEV;
  3609. }
  3610. printk(KERN_INFO "QLogic Fibre Channel HBA Driver: %s\n",
  3611. qla2x00_version_str);
  3612. ret = pci_register_driver(&qla2xxx_pci_driver);
  3613. if (ret) {
  3614. kmem_cache_destroy(srb_cachep);
  3615. fc_release_transport(qla2xxx_transport_template);
  3616. fc_release_transport(qla2xxx_transport_vport_template);
  3617. }
  3618. return ret;
  3619. }
  3620. /**
  3621. * qla2x00_module_exit - Module cleanup.
  3622. **/
  3623. static void __exit
  3624. qla2x00_module_exit(void)
  3625. {
  3626. unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
  3627. pci_unregister_driver(&qla2xxx_pci_driver);
  3628. qla2x00_release_firmware();
  3629. kmem_cache_destroy(srb_cachep);
  3630. if (ctx_cachep)
  3631. kmem_cache_destroy(ctx_cachep);
  3632. fc_release_transport(qla2xxx_transport_template);
  3633. fc_release_transport(qla2xxx_transport_vport_template);
  3634. }
  3635. module_init(qla2x00_module_init);
  3636. module_exit(qla2x00_module_exit);
  3637. MODULE_AUTHOR("QLogic Corporation");
  3638. MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
  3639. MODULE_LICENSE("GPL");
  3640. MODULE_VERSION(QLA2XXX_VERSION);
  3641. MODULE_FIRMWARE(FW_FILE_ISP21XX);
  3642. MODULE_FIRMWARE(FW_FILE_ISP22XX);
  3643. MODULE_FIRMWARE(FW_FILE_ISP2300);
  3644. MODULE_FIRMWARE(FW_FILE_ISP2322);
  3645. MODULE_FIRMWARE(FW_FILE_ISP24XX);
  3646. MODULE_FIRMWARE(FW_FILE_ISP25XX);