mwl8k.c 97 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120
  1. /*
  2. * drivers/net/wireless/mwl8k.c
  3. * Driver for Marvell TOPDOG 802.11 Wireless cards
  4. *
  5. * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/sched.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/list.h>
  17. #include <linux/pci.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <linux/etherdevice.h>
  21. #include <net/mac80211.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/firmware.h>
  24. #include <linux/workqueue.h>
  25. #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
  26. #define MWL8K_NAME KBUILD_MODNAME
  27. #define MWL8K_VERSION "0.11"
  28. /* Register definitions */
  29. #define MWL8K_HIU_GEN_PTR 0x00000c10
  30. #define MWL8K_MODE_STA 0x0000005a
  31. #define MWL8K_MODE_AP 0x000000a5
  32. #define MWL8K_HIU_INT_CODE 0x00000c14
  33. #define MWL8K_FWSTA_READY 0xf0f1f2f4
  34. #define MWL8K_FWAP_READY 0xf1f2f4a5
  35. #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
  36. #define MWL8K_HIU_SCRATCH 0x00000c40
  37. /* Host->device communications */
  38. #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
  39. #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
  40. #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
  41. #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
  42. #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
  43. #define MWL8K_H2A_INT_DUMMY (1 << 20)
  44. #define MWL8K_H2A_INT_RESET (1 << 15)
  45. #define MWL8K_H2A_INT_DOORBELL (1 << 1)
  46. #define MWL8K_H2A_INT_PPA_READY (1 << 0)
  47. /* Device->host communications */
  48. #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
  49. #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
  50. #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
  51. #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
  52. #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
  53. #define MWL8K_A2H_INT_DUMMY (1 << 20)
  54. #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
  55. #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
  56. #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
  57. #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
  58. #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
  59. #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
  60. #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
  61. #define MWL8K_A2H_INT_RX_READY (1 << 1)
  62. #define MWL8K_A2H_INT_TX_DONE (1 << 0)
  63. #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
  64. MWL8K_A2H_INT_CHNL_SWITCHED | \
  65. MWL8K_A2H_INT_QUEUE_EMPTY | \
  66. MWL8K_A2H_INT_RADAR_DETECT | \
  67. MWL8K_A2H_INT_RADIO_ON | \
  68. MWL8K_A2H_INT_RADIO_OFF | \
  69. MWL8K_A2H_INT_MAC_EVENT | \
  70. MWL8K_A2H_INT_OPC_DONE | \
  71. MWL8K_A2H_INT_RX_READY | \
  72. MWL8K_A2H_INT_TX_DONE)
  73. #define MWL8K_RX_QUEUES 1
  74. #define MWL8K_TX_QUEUES 4
  75. struct rxd_ops {
  76. int rxd_size;
  77. void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
  78. void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
  79. int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
  80. __le16 *qos);
  81. };
  82. struct mwl8k_device_info {
  83. char *part_name;
  84. char *helper_image;
  85. char *fw_image;
  86. struct rxd_ops *ap_rxd_ops;
  87. };
  88. struct mwl8k_rx_queue {
  89. int rxd_count;
  90. /* hw receives here */
  91. int head;
  92. /* refill descs here */
  93. int tail;
  94. void *rxd;
  95. dma_addr_t rxd_dma;
  96. struct {
  97. struct sk_buff *skb;
  98. DECLARE_PCI_UNMAP_ADDR(dma)
  99. } *buf;
  100. };
  101. struct mwl8k_tx_queue {
  102. /* hw transmits here */
  103. int head;
  104. /* sw appends here */
  105. int tail;
  106. struct ieee80211_tx_queue_stats stats;
  107. struct mwl8k_tx_desc *txd;
  108. dma_addr_t txd_dma;
  109. struct sk_buff **skb;
  110. };
  111. struct mwl8k_priv {
  112. struct ieee80211_hw *hw;
  113. struct pci_dev *pdev;
  114. struct mwl8k_device_info *device_info;
  115. void __iomem *sram;
  116. void __iomem *regs;
  117. /* firmware */
  118. struct firmware *fw_helper;
  119. struct firmware *fw_ucode;
  120. /* hardware/firmware parameters */
  121. bool ap_fw;
  122. struct rxd_ops *rxd_ops;
  123. struct ieee80211_supported_band band_24;
  124. struct ieee80211_channel channels_24[14];
  125. struct ieee80211_rate rates_24[14];
  126. /* firmware access */
  127. struct mutex fw_mutex;
  128. struct task_struct *fw_mutex_owner;
  129. int fw_mutex_depth;
  130. struct completion *hostcmd_wait;
  131. /* lock held over TX and TX reap */
  132. spinlock_t tx_lock;
  133. /* TX quiesce completion, protected by fw_mutex and tx_lock */
  134. struct completion *tx_wait;
  135. struct ieee80211_vif *vif;
  136. /* power management status cookie from firmware */
  137. u32 *cookie;
  138. dma_addr_t cookie_dma;
  139. u16 num_mcaddrs;
  140. u8 hw_rev;
  141. u32 fw_rev;
  142. /*
  143. * Running count of TX packets in flight, to avoid
  144. * iterating over the transmit rings each time.
  145. */
  146. int pending_tx_pkts;
  147. struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
  148. struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
  149. bool radio_on;
  150. bool radio_short_preamble;
  151. bool sniffer_enabled;
  152. bool wmm_enabled;
  153. struct work_struct sta_notify_worker;
  154. spinlock_t sta_notify_list_lock;
  155. struct list_head sta_notify_list;
  156. /* XXX need to convert this to handle multiple interfaces */
  157. bool capture_beacon;
  158. u8 capture_bssid[ETH_ALEN];
  159. struct sk_buff *beacon_skb;
  160. /*
  161. * This FJ worker has to be global as it is scheduled from the
  162. * RX handler. At this point we don't know which interface it
  163. * belongs to until the list of bssids waiting to complete join
  164. * is checked.
  165. */
  166. struct work_struct finalize_join_worker;
  167. /* Tasklet to perform TX reclaim. */
  168. struct tasklet_struct poll_tx_task;
  169. /* Tasklet to perform RX. */
  170. struct tasklet_struct poll_rx_task;
  171. };
  172. /* Per interface specific private data */
  173. struct mwl8k_vif {
  174. /* Non AMPDU sequence number assigned by driver. */
  175. u16 seqno;
  176. };
  177. #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
  178. struct mwl8k_sta {
  179. /* Index into station database. Returned by UPDATE_STADB. */
  180. u8 peer_id;
  181. };
  182. #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
  183. static const struct ieee80211_channel mwl8k_channels_24[] = {
  184. { .center_freq = 2412, .hw_value = 1, },
  185. { .center_freq = 2417, .hw_value = 2, },
  186. { .center_freq = 2422, .hw_value = 3, },
  187. { .center_freq = 2427, .hw_value = 4, },
  188. { .center_freq = 2432, .hw_value = 5, },
  189. { .center_freq = 2437, .hw_value = 6, },
  190. { .center_freq = 2442, .hw_value = 7, },
  191. { .center_freq = 2447, .hw_value = 8, },
  192. { .center_freq = 2452, .hw_value = 9, },
  193. { .center_freq = 2457, .hw_value = 10, },
  194. { .center_freq = 2462, .hw_value = 11, },
  195. { .center_freq = 2467, .hw_value = 12, },
  196. { .center_freq = 2472, .hw_value = 13, },
  197. { .center_freq = 2484, .hw_value = 14, },
  198. };
  199. static const struct ieee80211_rate mwl8k_rates_24[] = {
  200. { .bitrate = 10, .hw_value = 2, },
  201. { .bitrate = 20, .hw_value = 4, },
  202. { .bitrate = 55, .hw_value = 11, },
  203. { .bitrate = 110, .hw_value = 22, },
  204. { .bitrate = 220, .hw_value = 44, },
  205. { .bitrate = 60, .hw_value = 12, },
  206. { .bitrate = 90, .hw_value = 18, },
  207. { .bitrate = 120, .hw_value = 24, },
  208. { .bitrate = 180, .hw_value = 36, },
  209. { .bitrate = 240, .hw_value = 48, },
  210. { .bitrate = 360, .hw_value = 72, },
  211. { .bitrate = 480, .hw_value = 96, },
  212. { .bitrate = 540, .hw_value = 108, },
  213. { .bitrate = 720, .hw_value = 144, },
  214. };
  215. /* Set or get info from Firmware */
  216. #define MWL8K_CMD_SET 0x0001
  217. #define MWL8K_CMD_GET 0x0000
  218. /* Firmware command codes */
  219. #define MWL8K_CMD_CODE_DNLD 0x0001
  220. #define MWL8K_CMD_GET_HW_SPEC 0x0003
  221. #define MWL8K_CMD_SET_HW_SPEC 0x0004
  222. #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
  223. #define MWL8K_CMD_GET_STAT 0x0014
  224. #define MWL8K_CMD_RADIO_CONTROL 0x001c
  225. #define MWL8K_CMD_RF_TX_POWER 0x001e
  226. #define MWL8K_CMD_RF_ANTENNA 0x0020
  227. #define MWL8K_CMD_SET_BEACON 0x0100
  228. #define MWL8K_CMD_SET_PRE_SCAN 0x0107
  229. #define MWL8K_CMD_SET_POST_SCAN 0x0108
  230. #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
  231. #define MWL8K_CMD_SET_AID 0x010d
  232. #define MWL8K_CMD_SET_RATE 0x0110
  233. #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
  234. #define MWL8K_CMD_RTS_THRESHOLD 0x0113
  235. #define MWL8K_CMD_SET_SLOT 0x0114
  236. #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
  237. #define MWL8K_CMD_SET_WMM_MODE 0x0123
  238. #define MWL8K_CMD_MIMO_CONFIG 0x0125
  239. #define MWL8K_CMD_USE_FIXED_RATE 0x0126
  240. #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
  241. #define MWL8K_CMD_SET_MAC_ADDR 0x0202
  242. #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
  243. #define MWL8K_CMD_BSS_START 0x1100
  244. #define MWL8K_CMD_SET_NEW_STN 0x1111
  245. #define MWL8K_CMD_UPDATE_STADB 0x1123
  246. static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
  247. {
  248. #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
  249. snprintf(buf, bufsize, "%s", #x);\
  250. return buf;\
  251. } while (0)
  252. switch (cmd & ~0x8000) {
  253. MWL8K_CMDNAME(CODE_DNLD);
  254. MWL8K_CMDNAME(GET_HW_SPEC);
  255. MWL8K_CMDNAME(SET_HW_SPEC);
  256. MWL8K_CMDNAME(MAC_MULTICAST_ADR);
  257. MWL8K_CMDNAME(GET_STAT);
  258. MWL8K_CMDNAME(RADIO_CONTROL);
  259. MWL8K_CMDNAME(RF_TX_POWER);
  260. MWL8K_CMDNAME(RF_ANTENNA);
  261. MWL8K_CMDNAME(SET_BEACON);
  262. MWL8K_CMDNAME(SET_PRE_SCAN);
  263. MWL8K_CMDNAME(SET_POST_SCAN);
  264. MWL8K_CMDNAME(SET_RF_CHANNEL);
  265. MWL8K_CMDNAME(SET_AID);
  266. MWL8K_CMDNAME(SET_RATE);
  267. MWL8K_CMDNAME(SET_FINALIZE_JOIN);
  268. MWL8K_CMDNAME(RTS_THRESHOLD);
  269. MWL8K_CMDNAME(SET_SLOT);
  270. MWL8K_CMDNAME(SET_EDCA_PARAMS);
  271. MWL8K_CMDNAME(SET_WMM_MODE);
  272. MWL8K_CMDNAME(MIMO_CONFIG);
  273. MWL8K_CMDNAME(USE_FIXED_RATE);
  274. MWL8K_CMDNAME(ENABLE_SNIFFER);
  275. MWL8K_CMDNAME(SET_MAC_ADDR);
  276. MWL8K_CMDNAME(SET_RATEADAPT_MODE);
  277. MWL8K_CMDNAME(BSS_START);
  278. MWL8K_CMDNAME(SET_NEW_STN);
  279. MWL8K_CMDNAME(UPDATE_STADB);
  280. default:
  281. snprintf(buf, bufsize, "0x%x", cmd);
  282. }
  283. #undef MWL8K_CMDNAME
  284. return buf;
  285. }
  286. /* Hardware and firmware reset */
  287. static void mwl8k_hw_reset(struct mwl8k_priv *priv)
  288. {
  289. iowrite32(MWL8K_H2A_INT_RESET,
  290. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  291. iowrite32(MWL8K_H2A_INT_RESET,
  292. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  293. msleep(20);
  294. }
  295. /* Release fw image */
  296. static void mwl8k_release_fw(struct firmware **fw)
  297. {
  298. if (*fw == NULL)
  299. return;
  300. release_firmware(*fw);
  301. *fw = NULL;
  302. }
  303. static void mwl8k_release_firmware(struct mwl8k_priv *priv)
  304. {
  305. mwl8k_release_fw(&priv->fw_ucode);
  306. mwl8k_release_fw(&priv->fw_helper);
  307. }
  308. /* Request fw image */
  309. static int mwl8k_request_fw(struct mwl8k_priv *priv,
  310. const char *fname, struct firmware **fw)
  311. {
  312. /* release current image */
  313. if (*fw != NULL)
  314. mwl8k_release_fw(fw);
  315. return request_firmware((const struct firmware **)fw,
  316. fname, &priv->pdev->dev);
  317. }
  318. static int mwl8k_request_firmware(struct mwl8k_priv *priv)
  319. {
  320. struct mwl8k_device_info *di = priv->device_info;
  321. int rc;
  322. if (di->helper_image != NULL) {
  323. rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
  324. if (rc) {
  325. printk(KERN_ERR "%s: Error requesting helper "
  326. "firmware file %s\n", pci_name(priv->pdev),
  327. di->helper_image);
  328. return rc;
  329. }
  330. }
  331. rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
  332. if (rc) {
  333. printk(KERN_ERR "%s: Error requesting firmware file %s\n",
  334. pci_name(priv->pdev), di->fw_image);
  335. mwl8k_release_fw(&priv->fw_helper);
  336. return rc;
  337. }
  338. return 0;
  339. }
  340. struct mwl8k_cmd_pkt {
  341. __le16 code;
  342. __le16 length;
  343. __le16 seq_num;
  344. __le16 result;
  345. char payload[0];
  346. } __attribute__((packed));
  347. /*
  348. * Firmware loading.
  349. */
  350. static int
  351. mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
  352. {
  353. void __iomem *regs = priv->regs;
  354. dma_addr_t dma_addr;
  355. int loops;
  356. dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
  357. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  358. return -ENOMEM;
  359. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  360. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  361. iowrite32(MWL8K_H2A_INT_DOORBELL,
  362. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  363. iowrite32(MWL8K_H2A_INT_DUMMY,
  364. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  365. loops = 1000;
  366. do {
  367. u32 int_code;
  368. int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
  369. if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
  370. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  371. break;
  372. }
  373. cond_resched();
  374. udelay(1);
  375. } while (--loops);
  376. pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
  377. return loops ? 0 : -ETIMEDOUT;
  378. }
  379. static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
  380. const u8 *data, size_t length)
  381. {
  382. struct mwl8k_cmd_pkt *cmd;
  383. int done;
  384. int rc = 0;
  385. cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
  386. if (cmd == NULL)
  387. return -ENOMEM;
  388. cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
  389. cmd->seq_num = 0;
  390. cmd->result = 0;
  391. done = 0;
  392. while (length) {
  393. int block_size = length > 256 ? 256 : length;
  394. memcpy(cmd->payload, data + done, block_size);
  395. cmd->length = cpu_to_le16(block_size);
  396. rc = mwl8k_send_fw_load_cmd(priv, cmd,
  397. sizeof(*cmd) + block_size);
  398. if (rc)
  399. break;
  400. done += block_size;
  401. length -= block_size;
  402. }
  403. if (!rc) {
  404. cmd->length = 0;
  405. rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
  406. }
  407. kfree(cmd);
  408. return rc;
  409. }
  410. static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
  411. const u8 *data, size_t length)
  412. {
  413. unsigned char *buffer;
  414. int may_continue, rc = 0;
  415. u32 done, prev_block_size;
  416. buffer = kmalloc(1024, GFP_KERNEL);
  417. if (buffer == NULL)
  418. return -ENOMEM;
  419. done = 0;
  420. prev_block_size = 0;
  421. may_continue = 1000;
  422. while (may_continue > 0) {
  423. u32 block_size;
  424. block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
  425. if (block_size & 1) {
  426. block_size &= ~1;
  427. may_continue--;
  428. } else {
  429. done += prev_block_size;
  430. length -= prev_block_size;
  431. }
  432. if (block_size > 1024 || block_size > length) {
  433. rc = -EOVERFLOW;
  434. break;
  435. }
  436. if (length == 0) {
  437. rc = 0;
  438. break;
  439. }
  440. if (block_size == 0) {
  441. rc = -EPROTO;
  442. may_continue--;
  443. udelay(1);
  444. continue;
  445. }
  446. prev_block_size = block_size;
  447. memcpy(buffer, data + done, block_size);
  448. rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
  449. if (rc)
  450. break;
  451. }
  452. if (!rc && length != 0)
  453. rc = -EREMOTEIO;
  454. kfree(buffer);
  455. return rc;
  456. }
  457. static int mwl8k_load_firmware(struct ieee80211_hw *hw)
  458. {
  459. struct mwl8k_priv *priv = hw->priv;
  460. struct firmware *fw = priv->fw_ucode;
  461. int rc;
  462. int loops;
  463. if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
  464. struct firmware *helper = priv->fw_helper;
  465. if (helper == NULL) {
  466. printk(KERN_ERR "%s: helper image needed but none "
  467. "given\n", pci_name(priv->pdev));
  468. return -EINVAL;
  469. }
  470. rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
  471. if (rc) {
  472. printk(KERN_ERR "%s: unable to load firmware "
  473. "helper image\n", pci_name(priv->pdev));
  474. return rc;
  475. }
  476. msleep(5);
  477. rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
  478. } else {
  479. rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
  480. }
  481. if (rc) {
  482. printk(KERN_ERR "%s: unable to load firmware image\n",
  483. pci_name(priv->pdev));
  484. return rc;
  485. }
  486. iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
  487. loops = 500000;
  488. do {
  489. u32 ready_code;
  490. ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  491. if (ready_code == MWL8K_FWAP_READY) {
  492. priv->ap_fw = 1;
  493. break;
  494. } else if (ready_code == MWL8K_FWSTA_READY) {
  495. priv->ap_fw = 0;
  496. break;
  497. }
  498. cond_resched();
  499. udelay(1);
  500. } while (--loops);
  501. return loops ? 0 : -ETIMEDOUT;
  502. }
  503. /* DMA header used by firmware and hardware. */
  504. struct mwl8k_dma_data {
  505. __le16 fwlen;
  506. struct ieee80211_hdr wh;
  507. char data[0];
  508. } __attribute__((packed));
  509. /* Routines to add/remove DMA header from skb. */
  510. static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
  511. {
  512. struct mwl8k_dma_data *tr;
  513. int hdrlen;
  514. tr = (struct mwl8k_dma_data *)skb->data;
  515. hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
  516. if (hdrlen != sizeof(tr->wh)) {
  517. if (ieee80211_is_data_qos(tr->wh.frame_control)) {
  518. memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
  519. *((__le16 *)(tr->data - 2)) = qos;
  520. } else {
  521. memmove(tr->data - hdrlen, &tr->wh, hdrlen);
  522. }
  523. }
  524. if (hdrlen != sizeof(*tr))
  525. skb_pull(skb, sizeof(*tr) - hdrlen);
  526. }
  527. static inline void mwl8k_add_dma_header(struct sk_buff *skb)
  528. {
  529. struct ieee80211_hdr *wh;
  530. int hdrlen;
  531. struct mwl8k_dma_data *tr;
  532. /*
  533. * Add a firmware DMA header; the firmware requires that we
  534. * present a 2-byte payload length followed by a 4-address
  535. * header (without QoS field), followed (optionally) by any
  536. * WEP/ExtIV header (but only filled in for CCMP).
  537. */
  538. wh = (struct ieee80211_hdr *)skb->data;
  539. hdrlen = ieee80211_hdrlen(wh->frame_control);
  540. if (hdrlen != sizeof(*tr))
  541. skb_push(skb, sizeof(*tr) - hdrlen);
  542. if (ieee80211_is_data_qos(wh->frame_control))
  543. hdrlen -= 2;
  544. tr = (struct mwl8k_dma_data *)skb->data;
  545. if (wh != &tr->wh)
  546. memmove(&tr->wh, wh, hdrlen);
  547. if (hdrlen != sizeof(tr->wh))
  548. memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
  549. /*
  550. * Firmware length is the length of the fully formed "802.11
  551. * payload". That is, everything except for the 802.11 header.
  552. * This includes all crypto material including the MIC.
  553. */
  554. tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
  555. }
  556. /*
  557. * Packet reception for 88w8366 AP firmware.
  558. */
  559. struct mwl8k_rxd_8366_ap {
  560. __le16 pkt_len;
  561. __u8 sq2;
  562. __u8 rate;
  563. __le32 pkt_phys_addr;
  564. __le32 next_rxd_phys_addr;
  565. __le16 qos_control;
  566. __le16 htsig2;
  567. __le32 hw_rssi_info;
  568. __le32 hw_noise_floor_info;
  569. __u8 noise_floor;
  570. __u8 pad0[3];
  571. __u8 rssi;
  572. __u8 rx_status;
  573. __u8 channel;
  574. __u8 rx_ctrl;
  575. } __attribute__((packed));
  576. #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
  577. #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
  578. #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
  579. #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
  580. static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
  581. {
  582. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  583. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  584. rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
  585. }
  586. static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
  587. {
  588. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  589. rxd->pkt_len = cpu_to_le16(len);
  590. rxd->pkt_phys_addr = cpu_to_le32(addr);
  591. wmb();
  592. rxd->rx_ctrl = 0;
  593. }
  594. static int
  595. mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
  596. __le16 *qos)
  597. {
  598. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  599. if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
  600. return -1;
  601. rmb();
  602. memset(status, 0, sizeof(*status));
  603. status->signal = -rxd->rssi;
  604. status->noise = -rxd->noise_floor;
  605. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
  606. status->flag |= RX_FLAG_HT;
  607. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
  608. status->flag |= RX_FLAG_40MHZ;
  609. status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
  610. } else {
  611. int i;
  612. for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
  613. if (mwl8k_rates_24[i].hw_value == rxd->rate) {
  614. status->rate_idx = i;
  615. break;
  616. }
  617. }
  618. }
  619. status->band = IEEE80211_BAND_2GHZ;
  620. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  621. *qos = rxd->qos_control;
  622. return le16_to_cpu(rxd->pkt_len);
  623. }
  624. static struct rxd_ops rxd_8366_ap_ops = {
  625. .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
  626. .rxd_init = mwl8k_rxd_8366_ap_init,
  627. .rxd_refill = mwl8k_rxd_8366_ap_refill,
  628. .rxd_process = mwl8k_rxd_8366_ap_process,
  629. };
  630. /*
  631. * Packet reception for STA firmware.
  632. */
  633. struct mwl8k_rxd_sta {
  634. __le16 pkt_len;
  635. __u8 link_quality;
  636. __u8 noise_level;
  637. __le32 pkt_phys_addr;
  638. __le32 next_rxd_phys_addr;
  639. __le16 qos_control;
  640. __le16 rate_info;
  641. __le32 pad0[4];
  642. __u8 rssi;
  643. __u8 channel;
  644. __le16 pad1;
  645. __u8 rx_ctrl;
  646. __u8 rx_status;
  647. __u8 pad2[2];
  648. } __attribute__((packed));
  649. #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
  650. #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
  651. #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
  652. #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
  653. #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
  654. #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
  655. #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
  656. static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
  657. {
  658. struct mwl8k_rxd_sta *rxd = _rxd;
  659. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  660. rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
  661. }
  662. static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
  663. {
  664. struct mwl8k_rxd_sta *rxd = _rxd;
  665. rxd->pkt_len = cpu_to_le16(len);
  666. rxd->pkt_phys_addr = cpu_to_le32(addr);
  667. wmb();
  668. rxd->rx_ctrl = 0;
  669. }
  670. static int
  671. mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
  672. __le16 *qos)
  673. {
  674. struct mwl8k_rxd_sta *rxd = _rxd;
  675. u16 rate_info;
  676. if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
  677. return -1;
  678. rmb();
  679. rate_info = le16_to_cpu(rxd->rate_info);
  680. memset(status, 0, sizeof(*status));
  681. status->signal = -rxd->rssi;
  682. status->noise = -rxd->noise_level;
  683. status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
  684. status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
  685. if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
  686. status->flag |= RX_FLAG_SHORTPRE;
  687. if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
  688. status->flag |= RX_FLAG_40MHZ;
  689. if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
  690. status->flag |= RX_FLAG_SHORT_GI;
  691. if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
  692. status->flag |= RX_FLAG_HT;
  693. status->band = IEEE80211_BAND_2GHZ;
  694. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  695. *qos = rxd->qos_control;
  696. return le16_to_cpu(rxd->pkt_len);
  697. }
  698. static struct rxd_ops rxd_sta_ops = {
  699. .rxd_size = sizeof(struct mwl8k_rxd_sta),
  700. .rxd_init = mwl8k_rxd_sta_init,
  701. .rxd_refill = mwl8k_rxd_sta_refill,
  702. .rxd_process = mwl8k_rxd_sta_process,
  703. };
  704. #define MWL8K_RX_DESCS 256
  705. #define MWL8K_RX_MAXSZ 3800
  706. static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
  707. {
  708. struct mwl8k_priv *priv = hw->priv;
  709. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  710. int size;
  711. int i;
  712. rxq->rxd_count = 0;
  713. rxq->head = 0;
  714. rxq->tail = 0;
  715. size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
  716. rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
  717. if (rxq->rxd == NULL) {
  718. printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
  719. wiphy_name(hw->wiphy));
  720. return -ENOMEM;
  721. }
  722. memset(rxq->rxd, 0, size);
  723. rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
  724. if (rxq->buf == NULL) {
  725. printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
  726. wiphy_name(hw->wiphy));
  727. pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
  728. return -ENOMEM;
  729. }
  730. memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
  731. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  732. int desc_size;
  733. void *rxd;
  734. int nexti;
  735. dma_addr_t next_dma_addr;
  736. desc_size = priv->rxd_ops->rxd_size;
  737. rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
  738. nexti = i + 1;
  739. if (nexti == MWL8K_RX_DESCS)
  740. nexti = 0;
  741. next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
  742. priv->rxd_ops->rxd_init(rxd, next_dma_addr);
  743. }
  744. return 0;
  745. }
  746. static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
  747. {
  748. struct mwl8k_priv *priv = hw->priv;
  749. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  750. int refilled;
  751. refilled = 0;
  752. while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
  753. struct sk_buff *skb;
  754. dma_addr_t addr;
  755. int rx;
  756. void *rxd;
  757. skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
  758. if (skb == NULL)
  759. break;
  760. addr = pci_map_single(priv->pdev, skb->data,
  761. MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
  762. rxq->rxd_count++;
  763. rx = rxq->tail++;
  764. if (rxq->tail == MWL8K_RX_DESCS)
  765. rxq->tail = 0;
  766. rxq->buf[rx].skb = skb;
  767. pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
  768. rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
  769. priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
  770. refilled++;
  771. }
  772. return refilled;
  773. }
  774. /* Must be called only when the card's reception is completely halted */
  775. static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
  776. {
  777. struct mwl8k_priv *priv = hw->priv;
  778. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  779. int i;
  780. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  781. if (rxq->buf[i].skb != NULL) {
  782. pci_unmap_single(priv->pdev,
  783. pci_unmap_addr(&rxq->buf[i], dma),
  784. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  785. pci_unmap_addr_set(&rxq->buf[i], dma, 0);
  786. kfree_skb(rxq->buf[i].skb);
  787. rxq->buf[i].skb = NULL;
  788. }
  789. }
  790. kfree(rxq->buf);
  791. rxq->buf = NULL;
  792. pci_free_consistent(priv->pdev,
  793. MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
  794. rxq->rxd, rxq->rxd_dma);
  795. rxq->rxd = NULL;
  796. }
  797. /*
  798. * Scan a list of BSSIDs to process for finalize join.
  799. * Allows for extension to process multiple BSSIDs.
  800. */
  801. static inline int
  802. mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
  803. {
  804. return priv->capture_beacon &&
  805. ieee80211_is_beacon(wh->frame_control) &&
  806. !compare_ether_addr(wh->addr3, priv->capture_bssid);
  807. }
  808. static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
  809. struct sk_buff *skb)
  810. {
  811. struct mwl8k_priv *priv = hw->priv;
  812. priv->capture_beacon = false;
  813. memset(priv->capture_bssid, 0, ETH_ALEN);
  814. /*
  815. * Use GFP_ATOMIC as rxq_process is called from
  816. * the primary interrupt handler, memory allocation call
  817. * must not sleep.
  818. */
  819. priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
  820. if (priv->beacon_skb != NULL)
  821. ieee80211_queue_work(hw, &priv->finalize_join_worker);
  822. }
  823. static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
  824. {
  825. struct mwl8k_priv *priv = hw->priv;
  826. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  827. int processed;
  828. processed = 0;
  829. while (rxq->rxd_count && limit--) {
  830. struct sk_buff *skb;
  831. void *rxd;
  832. int pkt_len;
  833. struct ieee80211_rx_status status;
  834. __le16 qos;
  835. skb = rxq->buf[rxq->head].skb;
  836. if (skb == NULL)
  837. break;
  838. rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
  839. pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
  840. if (pkt_len < 0)
  841. break;
  842. rxq->buf[rxq->head].skb = NULL;
  843. pci_unmap_single(priv->pdev,
  844. pci_unmap_addr(&rxq->buf[rxq->head], dma),
  845. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  846. pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
  847. rxq->head++;
  848. if (rxq->head == MWL8K_RX_DESCS)
  849. rxq->head = 0;
  850. rxq->rxd_count--;
  851. skb_put(skb, pkt_len);
  852. mwl8k_remove_dma_header(skb, qos);
  853. /*
  854. * Check for a pending join operation. Save a
  855. * copy of the beacon and schedule a tasklet to
  856. * send a FINALIZE_JOIN command to the firmware.
  857. */
  858. if (mwl8k_capture_bssid(priv, (void *)skb->data))
  859. mwl8k_save_beacon(hw, skb);
  860. memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
  861. ieee80211_rx_irqsafe(hw, skb);
  862. processed++;
  863. }
  864. return processed;
  865. }
  866. /*
  867. * Packet transmission.
  868. */
  869. #define MWL8K_TXD_STATUS_OK 0x00000001
  870. #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
  871. #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
  872. #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
  873. #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
  874. #define MWL8K_QOS_QLEN_UNSPEC 0xff00
  875. #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
  876. #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
  877. #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
  878. #define MWL8K_QOS_EOSP 0x0010
  879. struct mwl8k_tx_desc {
  880. __le32 status;
  881. __u8 data_rate;
  882. __u8 tx_priority;
  883. __le16 qos_control;
  884. __le32 pkt_phys_addr;
  885. __le16 pkt_len;
  886. __u8 dest_MAC_addr[ETH_ALEN];
  887. __le32 next_txd_phys_addr;
  888. __le32 reserved;
  889. __le16 rate_info;
  890. __u8 peer_id;
  891. __u8 tx_frag_cnt;
  892. } __attribute__((packed));
  893. #define MWL8K_TX_DESCS 128
  894. static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
  895. {
  896. struct mwl8k_priv *priv = hw->priv;
  897. struct mwl8k_tx_queue *txq = priv->txq + index;
  898. int size;
  899. int i;
  900. memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
  901. txq->stats.limit = MWL8K_TX_DESCS;
  902. txq->head = 0;
  903. txq->tail = 0;
  904. size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
  905. txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
  906. if (txq->txd == NULL) {
  907. printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
  908. wiphy_name(hw->wiphy));
  909. return -ENOMEM;
  910. }
  911. memset(txq->txd, 0, size);
  912. txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
  913. if (txq->skb == NULL) {
  914. printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
  915. wiphy_name(hw->wiphy));
  916. pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
  917. return -ENOMEM;
  918. }
  919. memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
  920. for (i = 0; i < MWL8K_TX_DESCS; i++) {
  921. struct mwl8k_tx_desc *tx_desc;
  922. int nexti;
  923. tx_desc = txq->txd + i;
  924. nexti = (i + 1) % MWL8K_TX_DESCS;
  925. tx_desc->status = 0;
  926. tx_desc->next_txd_phys_addr =
  927. cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
  928. }
  929. return 0;
  930. }
  931. static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
  932. {
  933. iowrite32(MWL8K_H2A_INT_PPA_READY,
  934. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  935. iowrite32(MWL8K_H2A_INT_DUMMY,
  936. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  937. ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  938. }
  939. static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
  940. {
  941. struct mwl8k_priv *priv = hw->priv;
  942. int i;
  943. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  944. struct mwl8k_tx_queue *txq = priv->txq + i;
  945. int fw_owned = 0;
  946. int drv_owned = 0;
  947. int unused = 0;
  948. int desc;
  949. for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
  950. struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
  951. u32 status;
  952. status = le32_to_cpu(tx_desc->status);
  953. if (status & MWL8K_TXD_STATUS_FW_OWNED)
  954. fw_owned++;
  955. else
  956. drv_owned++;
  957. if (tx_desc->pkt_len == 0)
  958. unused++;
  959. }
  960. printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
  961. "fw_owned=%d drv_owned=%d unused=%d\n",
  962. wiphy_name(hw->wiphy), i,
  963. txq->stats.len, txq->head, txq->tail,
  964. fw_owned, drv_owned, unused);
  965. }
  966. }
  967. /*
  968. * Must be called with priv->fw_mutex held and tx queues stopped.
  969. */
  970. #define MWL8K_TX_WAIT_TIMEOUT_MS 5000
  971. static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
  972. {
  973. struct mwl8k_priv *priv = hw->priv;
  974. DECLARE_COMPLETION_ONSTACK(tx_wait);
  975. int retry;
  976. int rc;
  977. might_sleep();
  978. /*
  979. * The TX queues are stopped at this point, so this test
  980. * doesn't need to take ->tx_lock.
  981. */
  982. if (!priv->pending_tx_pkts)
  983. return 0;
  984. retry = 0;
  985. rc = 0;
  986. spin_lock_bh(&priv->tx_lock);
  987. priv->tx_wait = &tx_wait;
  988. while (!rc) {
  989. int oldcount;
  990. unsigned long timeout;
  991. oldcount = priv->pending_tx_pkts;
  992. spin_unlock_bh(&priv->tx_lock);
  993. timeout = wait_for_completion_timeout(&tx_wait,
  994. msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
  995. spin_lock_bh(&priv->tx_lock);
  996. if (timeout) {
  997. WARN_ON(priv->pending_tx_pkts);
  998. if (retry) {
  999. printk(KERN_NOTICE "%s: tx rings drained\n",
  1000. wiphy_name(hw->wiphy));
  1001. }
  1002. break;
  1003. }
  1004. if (priv->pending_tx_pkts < oldcount) {
  1005. printk(KERN_NOTICE "%s: waiting for tx rings "
  1006. "to drain (%d -> %d pkts)\n",
  1007. wiphy_name(hw->wiphy), oldcount,
  1008. priv->pending_tx_pkts);
  1009. retry = 1;
  1010. continue;
  1011. }
  1012. priv->tx_wait = NULL;
  1013. printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
  1014. wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
  1015. mwl8k_dump_tx_rings(hw);
  1016. rc = -ETIMEDOUT;
  1017. }
  1018. spin_unlock_bh(&priv->tx_lock);
  1019. return rc;
  1020. }
  1021. #define MWL8K_TXD_SUCCESS(status) \
  1022. ((status) & (MWL8K_TXD_STATUS_OK | \
  1023. MWL8K_TXD_STATUS_OK_RETRY | \
  1024. MWL8K_TXD_STATUS_OK_MORE_RETRY))
  1025. static int
  1026. mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
  1027. {
  1028. struct mwl8k_priv *priv = hw->priv;
  1029. struct mwl8k_tx_queue *txq = priv->txq + index;
  1030. int processed;
  1031. processed = 0;
  1032. while (txq->stats.len > 0 && limit--) {
  1033. int tx;
  1034. struct mwl8k_tx_desc *tx_desc;
  1035. unsigned long addr;
  1036. int size;
  1037. struct sk_buff *skb;
  1038. struct ieee80211_tx_info *info;
  1039. u32 status;
  1040. tx = txq->head;
  1041. tx_desc = txq->txd + tx;
  1042. status = le32_to_cpu(tx_desc->status);
  1043. if (status & MWL8K_TXD_STATUS_FW_OWNED) {
  1044. if (!force)
  1045. break;
  1046. tx_desc->status &=
  1047. ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
  1048. }
  1049. txq->head = (tx + 1) % MWL8K_TX_DESCS;
  1050. BUG_ON(txq->stats.len == 0);
  1051. txq->stats.len--;
  1052. priv->pending_tx_pkts--;
  1053. addr = le32_to_cpu(tx_desc->pkt_phys_addr);
  1054. size = le16_to_cpu(tx_desc->pkt_len);
  1055. skb = txq->skb[tx];
  1056. txq->skb[tx] = NULL;
  1057. BUG_ON(skb == NULL);
  1058. pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
  1059. mwl8k_remove_dma_header(skb, tx_desc->qos_control);
  1060. /* Mark descriptor as unused */
  1061. tx_desc->pkt_phys_addr = 0;
  1062. tx_desc->pkt_len = 0;
  1063. info = IEEE80211_SKB_CB(skb);
  1064. ieee80211_tx_info_clear_status(info);
  1065. if (MWL8K_TXD_SUCCESS(status))
  1066. info->flags |= IEEE80211_TX_STAT_ACK;
  1067. ieee80211_tx_status_irqsafe(hw, skb);
  1068. processed++;
  1069. }
  1070. if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
  1071. ieee80211_wake_queue(hw, index);
  1072. return processed;
  1073. }
  1074. /* must be called only when the card's transmit is completely halted */
  1075. static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
  1076. {
  1077. struct mwl8k_priv *priv = hw->priv;
  1078. struct mwl8k_tx_queue *txq = priv->txq + index;
  1079. mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
  1080. kfree(txq->skb);
  1081. txq->skb = NULL;
  1082. pci_free_consistent(priv->pdev,
  1083. MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
  1084. txq->txd, txq->txd_dma);
  1085. txq->txd = NULL;
  1086. }
  1087. static int
  1088. mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
  1089. {
  1090. struct mwl8k_priv *priv = hw->priv;
  1091. struct ieee80211_tx_info *tx_info;
  1092. struct mwl8k_vif *mwl8k_vif;
  1093. struct ieee80211_hdr *wh;
  1094. struct mwl8k_tx_queue *txq;
  1095. struct mwl8k_tx_desc *tx;
  1096. dma_addr_t dma;
  1097. u32 txstatus;
  1098. u8 txdatarate;
  1099. u16 qos;
  1100. wh = (struct ieee80211_hdr *)skb->data;
  1101. if (ieee80211_is_data_qos(wh->frame_control))
  1102. qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
  1103. else
  1104. qos = 0;
  1105. mwl8k_add_dma_header(skb);
  1106. wh = &((struct mwl8k_dma_data *)skb->data)->wh;
  1107. tx_info = IEEE80211_SKB_CB(skb);
  1108. mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
  1109. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1110. wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1111. wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
  1112. mwl8k_vif->seqno += 0x10;
  1113. }
  1114. /* Setup firmware control bit fields for each frame type. */
  1115. txstatus = 0;
  1116. txdatarate = 0;
  1117. if (ieee80211_is_mgmt(wh->frame_control) ||
  1118. ieee80211_is_ctl(wh->frame_control)) {
  1119. txdatarate = 0;
  1120. qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
  1121. } else if (ieee80211_is_data(wh->frame_control)) {
  1122. txdatarate = 1;
  1123. if (is_multicast_ether_addr(wh->addr1))
  1124. txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
  1125. qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
  1126. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
  1127. qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
  1128. else
  1129. qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
  1130. }
  1131. dma = pci_map_single(priv->pdev, skb->data,
  1132. skb->len, PCI_DMA_TODEVICE);
  1133. if (pci_dma_mapping_error(priv->pdev, dma)) {
  1134. printk(KERN_DEBUG "%s: failed to dma map skb, "
  1135. "dropping TX frame.\n", wiphy_name(hw->wiphy));
  1136. dev_kfree_skb(skb);
  1137. return NETDEV_TX_OK;
  1138. }
  1139. spin_lock_bh(&priv->tx_lock);
  1140. txq = priv->txq + index;
  1141. BUG_ON(txq->skb[txq->tail] != NULL);
  1142. txq->skb[txq->tail] = skb;
  1143. tx = txq->txd + txq->tail;
  1144. tx->data_rate = txdatarate;
  1145. tx->tx_priority = index;
  1146. tx->qos_control = cpu_to_le16(qos);
  1147. tx->pkt_phys_addr = cpu_to_le32(dma);
  1148. tx->pkt_len = cpu_to_le16(skb->len);
  1149. tx->rate_info = 0;
  1150. if (!priv->ap_fw && tx_info->control.sta != NULL)
  1151. tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
  1152. else
  1153. tx->peer_id = 0;
  1154. wmb();
  1155. tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
  1156. txq->stats.count++;
  1157. txq->stats.len++;
  1158. priv->pending_tx_pkts++;
  1159. txq->tail++;
  1160. if (txq->tail == MWL8K_TX_DESCS)
  1161. txq->tail = 0;
  1162. if (txq->head == txq->tail)
  1163. ieee80211_stop_queue(hw, index);
  1164. mwl8k_tx_start(priv);
  1165. spin_unlock_bh(&priv->tx_lock);
  1166. return NETDEV_TX_OK;
  1167. }
  1168. /*
  1169. * Firmware access.
  1170. *
  1171. * We have the following requirements for issuing firmware commands:
  1172. * - Some commands require that the packet transmit path is idle when
  1173. * the command is issued. (For simplicity, we'll just quiesce the
  1174. * transmit path for every command.)
  1175. * - There are certain sequences of commands that need to be issued to
  1176. * the hardware sequentially, with no other intervening commands.
  1177. *
  1178. * This leads to an implementation of a "firmware lock" as a mutex that
  1179. * can be taken recursively, and which is taken by both the low-level
  1180. * command submission function (mwl8k_post_cmd) as well as any users of
  1181. * that function that require issuing of an atomic sequence of commands,
  1182. * and quiesces the transmit path whenever it's taken.
  1183. */
  1184. static int mwl8k_fw_lock(struct ieee80211_hw *hw)
  1185. {
  1186. struct mwl8k_priv *priv = hw->priv;
  1187. if (priv->fw_mutex_owner != current) {
  1188. int rc;
  1189. mutex_lock(&priv->fw_mutex);
  1190. ieee80211_stop_queues(hw);
  1191. rc = mwl8k_tx_wait_empty(hw);
  1192. if (rc) {
  1193. ieee80211_wake_queues(hw);
  1194. mutex_unlock(&priv->fw_mutex);
  1195. return rc;
  1196. }
  1197. priv->fw_mutex_owner = current;
  1198. }
  1199. priv->fw_mutex_depth++;
  1200. return 0;
  1201. }
  1202. static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
  1203. {
  1204. struct mwl8k_priv *priv = hw->priv;
  1205. if (!--priv->fw_mutex_depth) {
  1206. ieee80211_wake_queues(hw);
  1207. priv->fw_mutex_owner = NULL;
  1208. mutex_unlock(&priv->fw_mutex);
  1209. }
  1210. }
  1211. /*
  1212. * Command processing.
  1213. */
  1214. /* Timeout firmware commands after 10s */
  1215. #define MWL8K_CMD_TIMEOUT_MS 10000
  1216. static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
  1217. {
  1218. DECLARE_COMPLETION_ONSTACK(cmd_wait);
  1219. struct mwl8k_priv *priv = hw->priv;
  1220. void __iomem *regs = priv->regs;
  1221. dma_addr_t dma_addr;
  1222. unsigned int dma_size;
  1223. int rc;
  1224. unsigned long timeout = 0;
  1225. u8 buf[32];
  1226. cmd->result = 0xffff;
  1227. dma_size = le16_to_cpu(cmd->length);
  1228. dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
  1229. PCI_DMA_BIDIRECTIONAL);
  1230. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  1231. return -ENOMEM;
  1232. rc = mwl8k_fw_lock(hw);
  1233. if (rc) {
  1234. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1235. PCI_DMA_BIDIRECTIONAL);
  1236. return rc;
  1237. }
  1238. priv->hostcmd_wait = &cmd_wait;
  1239. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  1240. iowrite32(MWL8K_H2A_INT_DOORBELL,
  1241. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1242. iowrite32(MWL8K_H2A_INT_DUMMY,
  1243. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1244. timeout = wait_for_completion_timeout(&cmd_wait,
  1245. msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
  1246. priv->hostcmd_wait = NULL;
  1247. mwl8k_fw_unlock(hw);
  1248. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1249. PCI_DMA_BIDIRECTIONAL);
  1250. if (!timeout) {
  1251. printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
  1252. wiphy_name(hw->wiphy),
  1253. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1254. MWL8K_CMD_TIMEOUT_MS);
  1255. rc = -ETIMEDOUT;
  1256. } else {
  1257. int ms;
  1258. ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
  1259. rc = cmd->result ? -EINVAL : 0;
  1260. if (rc)
  1261. printk(KERN_ERR "%s: Command %s error 0x%x\n",
  1262. wiphy_name(hw->wiphy),
  1263. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1264. le16_to_cpu(cmd->result));
  1265. else if (ms > 2000)
  1266. printk(KERN_NOTICE "%s: Command %s took %d ms\n",
  1267. wiphy_name(hw->wiphy),
  1268. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1269. ms);
  1270. }
  1271. return rc;
  1272. }
  1273. /*
  1274. * Setup code shared between STA and AP firmware images.
  1275. */
  1276. static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
  1277. {
  1278. struct mwl8k_priv *priv = hw->priv;
  1279. BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
  1280. memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
  1281. BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
  1282. memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
  1283. priv->band_24.band = IEEE80211_BAND_2GHZ;
  1284. priv->band_24.channels = priv->channels_24;
  1285. priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
  1286. priv->band_24.bitrates = priv->rates_24;
  1287. priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
  1288. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
  1289. }
  1290. /*
  1291. * CMD_GET_HW_SPEC (STA version).
  1292. */
  1293. struct mwl8k_cmd_get_hw_spec_sta {
  1294. struct mwl8k_cmd_pkt header;
  1295. __u8 hw_rev;
  1296. __u8 host_interface;
  1297. __le16 num_mcaddrs;
  1298. __u8 perm_addr[ETH_ALEN];
  1299. __le16 region_code;
  1300. __le32 fw_rev;
  1301. __le32 ps_cookie;
  1302. __le32 caps;
  1303. __u8 mcs_bitmap[16];
  1304. __le32 rx_queue_ptr;
  1305. __le32 num_tx_queues;
  1306. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1307. __le32 caps2;
  1308. __le32 num_tx_desc_per_queue;
  1309. __le32 total_rxd;
  1310. } __attribute__((packed));
  1311. #define MWL8K_CAP_MAX_AMSDU 0x20000000
  1312. #define MWL8K_CAP_GREENFIELD 0x08000000
  1313. #define MWL8K_CAP_AMPDU 0x04000000
  1314. #define MWL8K_CAP_RX_STBC 0x01000000
  1315. #define MWL8K_CAP_TX_STBC 0x00800000
  1316. #define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
  1317. #define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
  1318. #define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
  1319. #define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
  1320. #define MWL8K_CAP_DELAY_BA 0x00003000
  1321. #define MWL8K_CAP_MIMO 0x00000200
  1322. #define MWL8K_CAP_40MHZ 0x00000100
  1323. static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
  1324. {
  1325. struct mwl8k_priv *priv = hw->priv;
  1326. struct ieee80211_supported_band *band = &priv->band_24;
  1327. int rx_streams;
  1328. int tx_streams;
  1329. band->ht_cap.ht_supported = 1;
  1330. if (cap & MWL8K_CAP_MAX_AMSDU)
  1331. band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  1332. if (cap & MWL8K_CAP_GREENFIELD)
  1333. band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
  1334. if (cap & MWL8K_CAP_AMPDU) {
  1335. hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
  1336. band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  1337. band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
  1338. }
  1339. if (cap & MWL8K_CAP_RX_STBC)
  1340. band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
  1341. if (cap & MWL8K_CAP_TX_STBC)
  1342. band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
  1343. if (cap & MWL8K_CAP_SHORTGI_40MHZ)
  1344. band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
  1345. if (cap & MWL8K_CAP_SHORTGI_20MHZ)
  1346. band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
  1347. if (cap & MWL8K_CAP_DELAY_BA)
  1348. band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
  1349. if (cap & MWL8K_CAP_40MHZ)
  1350. band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  1351. rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
  1352. tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
  1353. band->ht_cap.mcs.rx_mask[0] = 0xff;
  1354. if (rx_streams >= 2)
  1355. band->ht_cap.mcs.rx_mask[1] = 0xff;
  1356. if (rx_streams >= 3)
  1357. band->ht_cap.mcs.rx_mask[2] = 0xff;
  1358. band->ht_cap.mcs.rx_mask[4] = 0x01;
  1359. band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  1360. if (rx_streams != tx_streams) {
  1361. band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  1362. band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
  1363. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1364. }
  1365. }
  1366. static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
  1367. {
  1368. struct mwl8k_priv *priv = hw->priv;
  1369. struct mwl8k_cmd_get_hw_spec_sta *cmd;
  1370. int rc;
  1371. int i;
  1372. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1373. if (cmd == NULL)
  1374. return -ENOMEM;
  1375. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1376. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1377. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1378. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1379. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1380. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1381. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1382. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1383. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1384. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1385. rc = mwl8k_post_cmd(hw, &cmd->header);
  1386. if (!rc) {
  1387. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1388. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1389. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1390. priv->hw_rev = cmd->hw_rev;
  1391. mwl8k_setup_2ghz_band(hw);
  1392. if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
  1393. mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
  1394. }
  1395. kfree(cmd);
  1396. return rc;
  1397. }
  1398. /*
  1399. * CMD_GET_HW_SPEC (AP version).
  1400. */
  1401. struct mwl8k_cmd_get_hw_spec_ap {
  1402. struct mwl8k_cmd_pkt header;
  1403. __u8 hw_rev;
  1404. __u8 host_interface;
  1405. __le16 num_wcb;
  1406. __le16 num_mcaddrs;
  1407. __u8 perm_addr[ETH_ALEN];
  1408. __le16 region_code;
  1409. __le16 num_antenna;
  1410. __le32 fw_rev;
  1411. __le32 wcbbase0;
  1412. __le32 rxwrptr;
  1413. __le32 rxrdptr;
  1414. __le32 ps_cookie;
  1415. __le32 wcbbase1;
  1416. __le32 wcbbase2;
  1417. __le32 wcbbase3;
  1418. } __attribute__((packed));
  1419. static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
  1420. {
  1421. struct mwl8k_priv *priv = hw->priv;
  1422. struct mwl8k_cmd_get_hw_spec_ap *cmd;
  1423. int rc;
  1424. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1425. if (cmd == NULL)
  1426. return -ENOMEM;
  1427. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1428. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1429. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1430. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1431. rc = mwl8k_post_cmd(hw, &cmd->header);
  1432. if (!rc) {
  1433. int off;
  1434. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1435. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1436. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1437. priv->hw_rev = cmd->hw_rev;
  1438. mwl8k_setup_2ghz_band(hw);
  1439. off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
  1440. iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
  1441. off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
  1442. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1443. off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
  1444. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1445. off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
  1446. iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
  1447. off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
  1448. iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
  1449. off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
  1450. iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
  1451. }
  1452. kfree(cmd);
  1453. return rc;
  1454. }
  1455. /*
  1456. * CMD_SET_HW_SPEC.
  1457. */
  1458. struct mwl8k_cmd_set_hw_spec {
  1459. struct mwl8k_cmd_pkt header;
  1460. __u8 hw_rev;
  1461. __u8 host_interface;
  1462. __le16 num_mcaddrs;
  1463. __u8 perm_addr[ETH_ALEN];
  1464. __le16 region_code;
  1465. __le32 fw_rev;
  1466. __le32 ps_cookie;
  1467. __le32 caps;
  1468. __le32 rx_queue_ptr;
  1469. __le32 num_tx_queues;
  1470. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1471. __le32 flags;
  1472. __le32 num_tx_desc_per_queue;
  1473. __le32 total_rxd;
  1474. } __attribute__((packed));
  1475. #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
  1476. #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
  1477. #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
  1478. static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
  1479. {
  1480. struct mwl8k_priv *priv = hw->priv;
  1481. struct mwl8k_cmd_set_hw_spec *cmd;
  1482. int rc;
  1483. int i;
  1484. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1485. if (cmd == NULL)
  1486. return -ENOMEM;
  1487. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
  1488. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1489. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1490. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1491. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1492. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1493. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1494. cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
  1495. MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
  1496. MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
  1497. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1498. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1499. rc = mwl8k_post_cmd(hw, &cmd->header);
  1500. kfree(cmd);
  1501. return rc;
  1502. }
  1503. /*
  1504. * CMD_MAC_MULTICAST_ADR.
  1505. */
  1506. struct mwl8k_cmd_mac_multicast_adr {
  1507. struct mwl8k_cmd_pkt header;
  1508. __le16 action;
  1509. __le16 numaddr;
  1510. __u8 addr[0][ETH_ALEN];
  1511. };
  1512. #define MWL8K_ENABLE_RX_DIRECTED 0x0001
  1513. #define MWL8K_ENABLE_RX_MULTICAST 0x0002
  1514. #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
  1515. #define MWL8K_ENABLE_RX_BROADCAST 0x0008
  1516. static struct mwl8k_cmd_pkt *
  1517. __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
  1518. int mc_count, struct dev_addr_list *mclist)
  1519. {
  1520. struct mwl8k_priv *priv = hw->priv;
  1521. struct mwl8k_cmd_mac_multicast_adr *cmd;
  1522. int size;
  1523. if (allmulti || mc_count > priv->num_mcaddrs) {
  1524. allmulti = 1;
  1525. mc_count = 0;
  1526. }
  1527. size = sizeof(*cmd) + mc_count * ETH_ALEN;
  1528. cmd = kzalloc(size, GFP_ATOMIC);
  1529. if (cmd == NULL)
  1530. return NULL;
  1531. cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
  1532. cmd->header.length = cpu_to_le16(size);
  1533. cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
  1534. MWL8K_ENABLE_RX_BROADCAST);
  1535. if (allmulti) {
  1536. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
  1537. } else if (mc_count) {
  1538. int i;
  1539. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
  1540. cmd->numaddr = cpu_to_le16(mc_count);
  1541. for (i = 0; i < mc_count && mclist; i++) {
  1542. if (mclist->da_addrlen != ETH_ALEN) {
  1543. kfree(cmd);
  1544. return NULL;
  1545. }
  1546. memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
  1547. mclist = mclist->next;
  1548. }
  1549. }
  1550. return &cmd->header;
  1551. }
  1552. /*
  1553. * CMD_GET_STAT.
  1554. */
  1555. struct mwl8k_cmd_get_stat {
  1556. struct mwl8k_cmd_pkt header;
  1557. __le32 stats[64];
  1558. } __attribute__((packed));
  1559. #define MWL8K_STAT_ACK_FAILURE 9
  1560. #define MWL8K_STAT_RTS_FAILURE 12
  1561. #define MWL8K_STAT_FCS_ERROR 24
  1562. #define MWL8K_STAT_RTS_SUCCESS 11
  1563. static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
  1564. struct ieee80211_low_level_stats *stats)
  1565. {
  1566. struct mwl8k_cmd_get_stat *cmd;
  1567. int rc;
  1568. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1569. if (cmd == NULL)
  1570. return -ENOMEM;
  1571. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
  1572. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1573. rc = mwl8k_post_cmd(hw, &cmd->header);
  1574. if (!rc) {
  1575. stats->dot11ACKFailureCount =
  1576. le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
  1577. stats->dot11RTSFailureCount =
  1578. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
  1579. stats->dot11FCSErrorCount =
  1580. le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
  1581. stats->dot11RTSSuccessCount =
  1582. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
  1583. }
  1584. kfree(cmd);
  1585. return rc;
  1586. }
  1587. /*
  1588. * CMD_RADIO_CONTROL.
  1589. */
  1590. struct mwl8k_cmd_radio_control {
  1591. struct mwl8k_cmd_pkt header;
  1592. __le16 action;
  1593. __le16 control;
  1594. __le16 radio_on;
  1595. } __attribute__((packed));
  1596. static int
  1597. mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
  1598. {
  1599. struct mwl8k_priv *priv = hw->priv;
  1600. struct mwl8k_cmd_radio_control *cmd;
  1601. int rc;
  1602. if (enable == priv->radio_on && !force)
  1603. return 0;
  1604. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1605. if (cmd == NULL)
  1606. return -ENOMEM;
  1607. cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
  1608. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1609. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1610. cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
  1611. cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
  1612. rc = mwl8k_post_cmd(hw, &cmd->header);
  1613. kfree(cmd);
  1614. if (!rc)
  1615. priv->radio_on = enable;
  1616. return rc;
  1617. }
  1618. static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
  1619. {
  1620. return mwl8k_cmd_radio_control(hw, 0, 0);
  1621. }
  1622. static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
  1623. {
  1624. return mwl8k_cmd_radio_control(hw, 1, 0);
  1625. }
  1626. static int
  1627. mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
  1628. {
  1629. struct mwl8k_priv *priv = hw->priv;
  1630. priv->radio_short_preamble = short_preamble;
  1631. return mwl8k_cmd_radio_control(hw, 1, 1);
  1632. }
  1633. /*
  1634. * CMD_RF_TX_POWER.
  1635. */
  1636. #define MWL8K_TX_POWER_LEVEL_TOTAL 8
  1637. struct mwl8k_cmd_rf_tx_power {
  1638. struct mwl8k_cmd_pkt header;
  1639. __le16 action;
  1640. __le16 support_level;
  1641. __le16 current_level;
  1642. __le16 reserved;
  1643. __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
  1644. } __attribute__((packed));
  1645. static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
  1646. {
  1647. struct mwl8k_cmd_rf_tx_power *cmd;
  1648. int rc;
  1649. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1650. if (cmd == NULL)
  1651. return -ENOMEM;
  1652. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
  1653. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1654. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1655. cmd->support_level = cpu_to_le16(dBm);
  1656. rc = mwl8k_post_cmd(hw, &cmd->header);
  1657. kfree(cmd);
  1658. return rc;
  1659. }
  1660. /*
  1661. * CMD_RF_ANTENNA.
  1662. */
  1663. struct mwl8k_cmd_rf_antenna {
  1664. struct mwl8k_cmd_pkt header;
  1665. __le16 antenna;
  1666. __le16 mode;
  1667. } __attribute__((packed));
  1668. #define MWL8K_RF_ANTENNA_RX 1
  1669. #define MWL8K_RF_ANTENNA_TX 2
  1670. static int
  1671. mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
  1672. {
  1673. struct mwl8k_cmd_rf_antenna *cmd;
  1674. int rc;
  1675. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1676. if (cmd == NULL)
  1677. return -ENOMEM;
  1678. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
  1679. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1680. cmd->antenna = cpu_to_le16(antenna);
  1681. cmd->mode = cpu_to_le16(mask);
  1682. rc = mwl8k_post_cmd(hw, &cmd->header);
  1683. kfree(cmd);
  1684. return rc;
  1685. }
  1686. /*
  1687. * CMD_SET_BEACON.
  1688. */
  1689. struct mwl8k_cmd_set_beacon {
  1690. struct mwl8k_cmd_pkt header;
  1691. __le16 beacon_len;
  1692. __u8 beacon[0];
  1693. };
  1694. static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
  1695. {
  1696. struct mwl8k_cmd_set_beacon *cmd;
  1697. int rc;
  1698. cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
  1699. if (cmd == NULL)
  1700. return -ENOMEM;
  1701. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
  1702. cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
  1703. cmd->beacon_len = cpu_to_le16(len);
  1704. memcpy(cmd->beacon, beacon, len);
  1705. rc = mwl8k_post_cmd(hw, &cmd->header);
  1706. kfree(cmd);
  1707. return rc;
  1708. }
  1709. /*
  1710. * CMD_SET_PRE_SCAN.
  1711. */
  1712. struct mwl8k_cmd_set_pre_scan {
  1713. struct mwl8k_cmd_pkt header;
  1714. } __attribute__((packed));
  1715. static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
  1716. {
  1717. struct mwl8k_cmd_set_pre_scan *cmd;
  1718. int rc;
  1719. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1720. if (cmd == NULL)
  1721. return -ENOMEM;
  1722. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
  1723. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1724. rc = mwl8k_post_cmd(hw, &cmd->header);
  1725. kfree(cmd);
  1726. return rc;
  1727. }
  1728. /*
  1729. * CMD_SET_POST_SCAN.
  1730. */
  1731. struct mwl8k_cmd_set_post_scan {
  1732. struct mwl8k_cmd_pkt header;
  1733. __le32 isibss;
  1734. __u8 bssid[ETH_ALEN];
  1735. } __attribute__((packed));
  1736. static int
  1737. mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
  1738. {
  1739. struct mwl8k_cmd_set_post_scan *cmd;
  1740. int rc;
  1741. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1742. if (cmd == NULL)
  1743. return -ENOMEM;
  1744. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
  1745. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1746. cmd->isibss = 0;
  1747. memcpy(cmd->bssid, mac, ETH_ALEN);
  1748. rc = mwl8k_post_cmd(hw, &cmd->header);
  1749. kfree(cmd);
  1750. return rc;
  1751. }
  1752. /*
  1753. * CMD_SET_RF_CHANNEL.
  1754. */
  1755. struct mwl8k_cmd_set_rf_channel {
  1756. struct mwl8k_cmd_pkt header;
  1757. __le16 action;
  1758. __u8 current_channel;
  1759. __le32 channel_flags;
  1760. } __attribute__((packed));
  1761. static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
  1762. struct ieee80211_conf *conf)
  1763. {
  1764. struct ieee80211_channel *channel = conf->channel;
  1765. struct mwl8k_cmd_set_rf_channel *cmd;
  1766. int rc;
  1767. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1768. if (cmd == NULL)
  1769. return -ENOMEM;
  1770. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
  1771. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1772. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1773. cmd->current_channel = channel->hw_value;
  1774. if (channel->band == IEEE80211_BAND_2GHZ)
  1775. cmd->channel_flags |= cpu_to_le32(0x00000001);
  1776. if (conf->channel_type == NL80211_CHAN_NO_HT ||
  1777. conf->channel_type == NL80211_CHAN_HT20)
  1778. cmd->channel_flags |= cpu_to_le32(0x00000080);
  1779. else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
  1780. cmd->channel_flags |= cpu_to_le32(0x000001900);
  1781. else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
  1782. cmd->channel_flags |= cpu_to_le32(0x000000900);
  1783. rc = mwl8k_post_cmd(hw, &cmd->header);
  1784. kfree(cmd);
  1785. return rc;
  1786. }
  1787. /*
  1788. * CMD_SET_AID.
  1789. */
  1790. #define MWL8K_FRAME_PROT_DISABLED 0x00
  1791. #define MWL8K_FRAME_PROT_11G 0x07
  1792. #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
  1793. #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
  1794. struct mwl8k_cmd_update_set_aid {
  1795. struct mwl8k_cmd_pkt header;
  1796. __le16 aid;
  1797. /* AP's MAC address (BSSID) */
  1798. __u8 bssid[ETH_ALEN];
  1799. __le16 protection_mode;
  1800. __u8 supp_rates[14];
  1801. } __attribute__((packed));
  1802. static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
  1803. {
  1804. int i;
  1805. int j;
  1806. /*
  1807. * Clear nonstandard rates 4 and 13.
  1808. */
  1809. mask &= 0x1fef;
  1810. for (i = 0, j = 0; i < 14; i++) {
  1811. if (mask & (1 << i))
  1812. rates[j++] = mwl8k_rates_24[i].hw_value;
  1813. }
  1814. }
  1815. static int
  1816. mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
  1817. struct ieee80211_vif *vif, u32 legacy_rate_mask)
  1818. {
  1819. struct mwl8k_cmd_update_set_aid *cmd;
  1820. u16 prot_mode;
  1821. int rc;
  1822. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1823. if (cmd == NULL)
  1824. return -ENOMEM;
  1825. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
  1826. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1827. cmd->aid = cpu_to_le16(vif->bss_conf.aid);
  1828. memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
  1829. if (vif->bss_conf.use_cts_prot) {
  1830. prot_mode = MWL8K_FRAME_PROT_11G;
  1831. } else {
  1832. switch (vif->bss_conf.ht_operation_mode &
  1833. IEEE80211_HT_OP_MODE_PROTECTION) {
  1834. case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
  1835. prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
  1836. break;
  1837. case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
  1838. prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
  1839. break;
  1840. default:
  1841. prot_mode = MWL8K_FRAME_PROT_DISABLED;
  1842. break;
  1843. }
  1844. }
  1845. cmd->protection_mode = cpu_to_le16(prot_mode);
  1846. legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
  1847. rc = mwl8k_post_cmd(hw, &cmd->header);
  1848. kfree(cmd);
  1849. return rc;
  1850. }
  1851. /*
  1852. * CMD_SET_RATE.
  1853. */
  1854. struct mwl8k_cmd_set_rate {
  1855. struct mwl8k_cmd_pkt header;
  1856. __u8 legacy_rates[14];
  1857. /* Bitmap for supported MCS codes. */
  1858. __u8 mcs_set[16];
  1859. __u8 reserved[16];
  1860. } __attribute__((packed));
  1861. static int
  1862. mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1863. u32 legacy_rate_mask, u8 *mcs_rates)
  1864. {
  1865. struct mwl8k_cmd_set_rate *cmd;
  1866. int rc;
  1867. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1868. if (cmd == NULL)
  1869. return -ENOMEM;
  1870. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
  1871. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1872. legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
  1873. memcpy(cmd->mcs_set, mcs_rates, 16);
  1874. rc = mwl8k_post_cmd(hw, &cmd->header);
  1875. kfree(cmd);
  1876. return rc;
  1877. }
  1878. /*
  1879. * CMD_FINALIZE_JOIN.
  1880. */
  1881. #define MWL8K_FJ_BEACON_MAXLEN 128
  1882. struct mwl8k_cmd_finalize_join {
  1883. struct mwl8k_cmd_pkt header;
  1884. __le32 sleep_interval; /* Number of beacon periods to sleep */
  1885. __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
  1886. } __attribute__((packed));
  1887. static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
  1888. int framelen, int dtim)
  1889. {
  1890. struct mwl8k_cmd_finalize_join *cmd;
  1891. struct ieee80211_mgmt *payload = frame;
  1892. int payload_len;
  1893. int rc;
  1894. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1895. if (cmd == NULL)
  1896. return -ENOMEM;
  1897. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
  1898. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1899. cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
  1900. payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
  1901. if (payload_len < 0)
  1902. payload_len = 0;
  1903. else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
  1904. payload_len = MWL8K_FJ_BEACON_MAXLEN;
  1905. memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
  1906. rc = mwl8k_post_cmd(hw, &cmd->header);
  1907. kfree(cmd);
  1908. return rc;
  1909. }
  1910. /*
  1911. * CMD_SET_RTS_THRESHOLD.
  1912. */
  1913. struct mwl8k_cmd_set_rts_threshold {
  1914. struct mwl8k_cmd_pkt header;
  1915. __le16 action;
  1916. __le16 threshold;
  1917. } __attribute__((packed));
  1918. static int
  1919. mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
  1920. {
  1921. struct mwl8k_cmd_set_rts_threshold *cmd;
  1922. int rc;
  1923. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1924. if (cmd == NULL)
  1925. return -ENOMEM;
  1926. cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
  1927. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1928. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1929. cmd->threshold = cpu_to_le16(rts_thresh);
  1930. rc = mwl8k_post_cmd(hw, &cmd->header);
  1931. kfree(cmd);
  1932. return rc;
  1933. }
  1934. /*
  1935. * CMD_SET_SLOT.
  1936. */
  1937. struct mwl8k_cmd_set_slot {
  1938. struct mwl8k_cmd_pkt header;
  1939. __le16 action;
  1940. __u8 short_slot;
  1941. } __attribute__((packed));
  1942. static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
  1943. {
  1944. struct mwl8k_cmd_set_slot *cmd;
  1945. int rc;
  1946. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1947. if (cmd == NULL)
  1948. return -ENOMEM;
  1949. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
  1950. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1951. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1952. cmd->short_slot = short_slot_time;
  1953. rc = mwl8k_post_cmd(hw, &cmd->header);
  1954. kfree(cmd);
  1955. return rc;
  1956. }
  1957. /*
  1958. * CMD_SET_EDCA_PARAMS.
  1959. */
  1960. struct mwl8k_cmd_set_edca_params {
  1961. struct mwl8k_cmd_pkt header;
  1962. /* See MWL8K_SET_EDCA_XXX below */
  1963. __le16 action;
  1964. /* TX opportunity in units of 32 us */
  1965. __le16 txop;
  1966. union {
  1967. struct {
  1968. /* Log exponent of max contention period: 0...15 */
  1969. __le32 log_cw_max;
  1970. /* Log exponent of min contention period: 0...15 */
  1971. __le32 log_cw_min;
  1972. /* Adaptive interframe spacing in units of 32us */
  1973. __u8 aifs;
  1974. /* TX queue to configure */
  1975. __u8 txq;
  1976. } ap;
  1977. struct {
  1978. /* Log exponent of max contention period: 0...15 */
  1979. __u8 log_cw_max;
  1980. /* Log exponent of min contention period: 0...15 */
  1981. __u8 log_cw_min;
  1982. /* Adaptive interframe spacing in units of 32us */
  1983. __u8 aifs;
  1984. /* TX queue to configure */
  1985. __u8 txq;
  1986. } sta;
  1987. };
  1988. } __attribute__((packed));
  1989. #define MWL8K_SET_EDCA_CW 0x01
  1990. #define MWL8K_SET_EDCA_TXOP 0x02
  1991. #define MWL8K_SET_EDCA_AIFS 0x04
  1992. #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
  1993. MWL8K_SET_EDCA_TXOP | \
  1994. MWL8K_SET_EDCA_AIFS)
  1995. static int
  1996. mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
  1997. __u16 cw_min, __u16 cw_max,
  1998. __u8 aifs, __u16 txop)
  1999. {
  2000. struct mwl8k_priv *priv = hw->priv;
  2001. struct mwl8k_cmd_set_edca_params *cmd;
  2002. int rc;
  2003. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2004. if (cmd == NULL)
  2005. return -ENOMEM;
  2006. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
  2007. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2008. cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
  2009. cmd->txop = cpu_to_le16(txop);
  2010. if (priv->ap_fw) {
  2011. cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
  2012. cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
  2013. cmd->ap.aifs = aifs;
  2014. cmd->ap.txq = qnum;
  2015. } else {
  2016. cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
  2017. cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
  2018. cmd->sta.aifs = aifs;
  2019. cmd->sta.txq = qnum;
  2020. }
  2021. rc = mwl8k_post_cmd(hw, &cmd->header);
  2022. kfree(cmd);
  2023. return rc;
  2024. }
  2025. /*
  2026. * CMD_SET_WMM_MODE.
  2027. */
  2028. struct mwl8k_cmd_set_wmm_mode {
  2029. struct mwl8k_cmd_pkt header;
  2030. __le16 action;
  2031. } __attribute__((packed));
  2032. static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
  2033. {
  2034. struct mwl8k_priv *priv = hw->priv;
  2035. struct mwl8k_cmd_set_wmm_mode *cmd;
  2036. int rc;
  2037. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2038. if (cmd == NULL)
  2039. return -ENOMEM;
  2040. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
  2041. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2042. cmd->action = cpu_to_le16(!!enable);
  2043. rc = mwl8k_post_cmd(hw, &cmd->header);
  2044. kfree(cmd);
  2045. if (!rc)
  2046. priv->wmm_enabled = enable;
  2047. return rc;
  2048. }
  2049. /*
  2050. * CMD_MIMO_CONFIG.
  2051. */
  2052. struct mwl8k_cmd_mimo_config {
  2053. struct mwl8k_cmd_pkt header;
  2054. __le32 action;
  2055. __u8 rx_antenna_map;
  2056. __u8 tx_antenna_map;
  2057. } __attribute__((packed));
  2058. static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
  2059. {
  2060. struct mwl8k_cmd_mimo_config *cmd;
  2061. int rc;
  2062. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2063. if (cmd == NULL)
  2064. return -ENOMEM;
  2065. cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
  2066. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2067. cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
  2068. cmd->rx_antenna_map = rx;
  2069. cmd->tx_antenna_map = tx;
  2070. rc = mwl8k_post_cmd(hw, &cmd->header);
  2071. kfree(cmd);
  2072. return rc;
  2073. }
  2074. /*
  2075. * CMD_USE_FIXED_RATE (STA version).
  2076. */
  2077. struct mwl8k_cmd_use_fixed_rate_sta {
  2078. struct mwl8k_cmd_pkt header;
  2079. __le32 action;
  2080. __le32 allow_rate_drop;
  2081. __le32 num_rates;
  2082. struct {
  2083. __le32 is_ht_rate;
  2084. __le32 enable_retry;
  2085. __le32 rate;
  2086. __le32 retry_count;
  2087. } rate_entry[8];
  2088. __le32 rate_type;
  2089. __le32 reserved1;
  2090. __le32 reserved2;
  2091. } __attribute__((packed));
  2092. #define MWL8K_USE_AUTO_RATE 0x0002
  2093. #define MWL8K_UCAST_RATE 0
  2094. static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
  2095. {
  2096. struct mwl8k_cmd_use_fixed_rate_sta *cmd;
  2097. int rc;
  2098. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2099. if (cmd == NULL)
  2100. return -ENOMEM;
  2101. cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
  2102. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2103. cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
  2104. cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
  2105. rc = mwl8k_post_cmd(hw, &cmd->header);
  2106. kfree(cmd);
  2107. return rc;
  2108. }
  2109. /*
  2110. * CMD_USE_FIXED_RATE (AP version).
  2111. */
  2112. struct mwl8k_cmd_use_fixed_rate_ap {
  2113. struct mwl8k_cmd_pkt header;
  2114. __le32 action;
  2115. __le32 allow_rate_drop;
  2116. __le32 num_rates;
  2117. struct mwl8k_rate_entry_ap {
  2118. __le32 is_ht_rate;
  2119. __le32 enable_retry;
  2120. __le32 rate;
  2121. __le32 retry_count;
  2122. } rate_entry[4];
  2123. u8 multicast_rate;
  2124. u8 multicast_rate_type;
  2125. u8 management_rate;
  2126. } __attribute__((packed));
  2127. static int
  2128. mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
  2129. {
  2130. struct mwl8k_cmd_use_fixed_rate_ap *cmd;
  2131. int rc;
  2132. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2133. if (cmd == NULL)
  2134. return -ENOMEM;
  2135. cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
  2136. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2137. cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
  2138. cmd->multicast_rate = mcast;
  2139. cmd->management_rate = mgmt;
  2140. rc = mwl8k_post_cmd(hw, &cmd->header);
  2141. kfree(cmd);
  2142. return rc;
  2143. }
  2144. /*
  2145. * CMD_ENABLE_SNIFFER.
  2146. */
  2147. struct mwl8k_cmd_enable_sniffer {
  2148. struct mwl8k_cmd_pkt header;
  2149. __le32 action;
  2150. } __attribute__((packed));
  2151. static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
  2152. {
  2153. struct mwl8k_cmd_enable_sniffer *cmd;
  2154. int rc;
  2155. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2156. if (cmd == NULL)
  2157. return -ENOMEM;
  2158. cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
  2159. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2160. cmd->action = cpu_to_le32(!!enable);
  2161. rc = mwl8k_post_cmd(hw, &cmd->header);
  2162. kfree(cmd);
  2163. return rc;
  2164. }
  2165. /*
  2166. * CMD_SET_MAC_ADDR.
  2167. */
  2168. struct mwl8k_cmd_set_mac_addr {
  2169. struct mwl8k_cmd_pkt header;
  2170. union {
  2171. struct {
  2172. __le16 mac_type;
  2173. __u8 mac_addr[ETH_ALEN];
  2174. } mbss;
  2175. __u8 mac_addr[ETH_ALEN];
  2176. };
  2177. } __attribute__((packed));
  2178. #define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
  2179. #define MWL8K_MAC_TYPE_PRIMARY_AP 2
  2180. static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
  2181. {
  2182. struct mwl8k_priv *priv = hw->priv;
  2183. struct mwl8k_cmd_set_mac_addr *cmd;
  2184. int rc;
  2185. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2186. if (cmd == NULL)
  2187. return -ENOMEM;
  2188. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
  2189. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2190. if (priv->ap_fw) {
  2191. cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
  2192. memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
  2193. } else {
  2194. memcpy(cmd->mac_addr, mac, ETH_ALEN);
  2195. }
  2196. rc = mwl8k_post_cmd(hw, &cmd->header);
  2197. kfree(cmd);
  2198. return rc;
  2199. }
  2200. /*
  2201. * CMD_SET_RATEADAPT_MODE.
  2202. */
  2203. struct mwl8k_cmd_set_rate_adapt_mode {
  2204. struct mwl8k_cmd_pkt header;
  2205. __le16 action;
  2206. __le16 mode;
  2207. } __attribute__((packed));
  2208. static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
  2209. {
  2210. struct mwl8k_cmd_set_rate_adapt_mode *cmd;
  2211. int rc;
  2212. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2213. if (cmd == NULL)
  2214. return -ENOMEM;
  2215. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
  2216. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2217. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  2218. cmd->mode = cpu_to_le16(mode);
  2219. rc = mwl8k_post_cmd(hw, &cmd->header);
  2220. kfree(cmd);
  2221. return rc;
  2222. }
  2223. /*
  2224. * CMD_BSS_START.
  2225. */
  2226. struct mwl8k_cmd_bss_start {
  2227. struct mwl8k_cmd_pkt header;
  2228. __le32 enable;
  2229. } __attribute__((packed));
  2230. static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
  2231. {
  2232. struct mwl8k_cmd_bss_start *cmd;
  2233. int rc;
  2234. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2235. if (cmd == NULL)
  2236. return -ENOMEM;
  2237. cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
  2238. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2239. cmd->enable = cpu_to_le32(enable);
  2240. rc = mwl8k_post_cmd(hw, &cmd->header);
  2241. kfree(cmd);
  2242. return rc;
  2243. }
  2244. /*
  2245. * CMD_SET_NEW_STN.
  2246. */
  2247. struct mwl8k_cmd_set_new_stn {
  2248. struct mwl8k_cmd_pkt header;
  2249. __le16 aid;
  2250. __u8 mac_addr[6];
  2251. __le16 stn_id;
  2252. __le16 action;
  2253. __le16 rsvd;
  2254. __le32 legacy_rates;
  2255. __u8 ht_rates[4];
  2256. __le16 cap_info;
  2257. __le16 ht_capabilities_info;
  2258. __u8 mac_ht_param_info;
  2259. __u8 rev;
  2260. __u8 control_channel;
  2261. __u8 add_channel;
  2262. __le16 op_mode;
  2263. __le16 stbc;
  2264. __u8 add_qos_info;
  2265. __u8 is_qos_sta;
  2266. __le32 fw_sta_ptr;
  2267. } __attribute__((packed));
  2268. #define MWL8K_STA_ACTION_ADD 0
  2269. #define MWL8K_STA_ACTION_REMOVE 2
  2270. static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
  2271. struct ieee80211_vif *vif,
  2272. struct ieee80211_sta *sta)
  2273. {
  2274. struct mwl8k_cmd_set_new_stn *cmd;
  2275. int rc;
  2276. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2277. if (cmd == NULL)
  2278. return -ENOMEM;
  2279. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
  2280. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2281. cmd->aid = cpu_to_le16(sta->aid);
  2282. memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
  2283. cmd->stn_id = cpu_to_le16(sta->aid);
  2284. cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
  2285. cmd->legacy_rates = cpu_to_le32(sta->supp_rates[IEEE80211_BAND_2GHZ]);
  2286. if (sta->ht_cap.ht_supported) {
  2287. cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
  2288. cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
  2289. cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
  2290. cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
  2291. cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
  2292. cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
  2293. ((sta->ht_cap.ampdu_density & 7) << 2);
  2294. cmd->is_qos_sta = 1;
  2295. }
  2296. rc = mwl8k_post_cmd(hw, &cmd->header);
  2297. kfree(cmd);
  2298. return rc;
  2299. }
  2300. static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
  2301. struct ieee80211_vif *vif)
  2302. {
  2303. struct mwl8k_cmd_set_new_stn *cmd;
  2304. int rc;
  2305. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2306. if (cmd == NULL)
  2307. return -ENOMEM;
  2308. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
  2309. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2310. memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
  2311. rc = mwl8k_post_cmd(hw, &cmd->header);
  2312. kfree(cmd);
  2313. return rc;
  2314. }
  2315. static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
  2316. struct ieee80211_vif *vif, u8 *addr)
  2317. {
  2318. struct mwl8k_cmd_set_new_stn *cmd;
  2319. int rc;
  2320. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2321. if (cmd == NULL)
  2322. return -ENOMEM;
  2323. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
  2324. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2325. memcpy(cmd->mac_addr, addr, ETH_ALEN);
  2326. cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
  2327. rc = mwl8k_post_cmd(hw, &cmd->header);
  2328. kfree(cmd);
  2329. return rc;
  2330. }
  2331. /*
  2332. * CMD_UPDATE_STADB.
  2333. */
  2334. struct ewc_ht_info {
  2335. __le16 control1;
  2336. __le16 control2;
  2337. __le16 control3;
  2338. } __attribute__((packed));
  2339. struct peer_capability_info {
  2340. /* Peer type - AP vs. STA. */
  2341. __u8 peer_type;
  2342. /* Basic 802.11 capabilities from assoc resp. */
  2343. __le16 basic_caps;
  2344. /* Set if peer supports 802.11n high throughput (HT). */
  2345. __u8 ht_support;
  2346. /* Valid if HT is supported. */
  2347. __le16 ht_caps;
  2348. __u8 extended_ht_caps;
  2349. struct ewc_ht_info ewc_info;
  2350. /* Legacy rate table. Intersection of our rates and peer rates. */
  2351. __u8 legacy_rates[12];
  2352. /* HT rate table. Intersection of our rates and peer rates. */
  2353. __u8 ht_rates[16];
  2354. __u8 pad[16];
  2355. /* If set, interoperability mode, no proprietary extensions. */
  2356. __u8 interop;
  2357. __u8 pad2;
  2358. __u8 station_id;
  2359. __le16 amsdu_enabled;
  2360. } __attribute__((packed));
  2361. struct mwl8k_cmd_update_stadb {
  2362. struct mwl8k_cmd_pkt header;
  2363. /* See STADB_ACTION_TYPE */
  2364. __le32 action;
  2365. /* Peer MAC address */
  2366. __u8 peer_addr[ETH_ALEN];
  2367. __le32 reserved;
  2368. /* Peer info - valid during add/update. */
  2369. struct peer_capability_info peer_info;
  2370. } __attribute__((packed));
  2371. #define MWL8K_STA_DB_MODIFY_ENTRY 1
  2372. #define MWL8K_STA_DB_DEL_ENTRY 2
  2373. /* Peer Entry flags - used to define the type of the peer node */
  2374. #define MWL8K_PEER_TYPE_ACCESSPOINT 2
  2375. static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
  2376. struct ieee80211_vif *vif,
  2377. struct ieee80211_sta *sta)
  2378. {
  2379. struct mwl8k_cmd_update_stadb *cmd;
  2380. struct peer_capability_info *p;
  2381. int rc;
  2382. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2383. if (cmd == NULL)
  2384. return -ENOMEM;
  2385. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2386. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2387. cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
  2388. memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
  2389. p = &cmd->peer_info;
  2390. p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
  2391. p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
  2392. p->ht_support = sta->ht_cap.ht_supported;
  2393. p->ht_caps = sta->ht_cap.cap;
  2394. p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
  2395. ((sta->ht_cap.ampdu_density & 7) << 2);
  2396. legacy_rate_mask_to_array(p->legacy_rates,
  2397. sta->supp_rates[IEEE80211_BAND_2GHZ]);
  2398. memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
  2399. p->interop = 1;
  2400. p->amsdu_enabled = 0;
  2401. rc = mwl8k_post_cmd(hw, &cmd->header);
  2402. kfree(cmd);
  2403. return rc ? rc : p->station_id;
  2404. }
  2405. static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
  2406. struct ieee80211_vif *vif, u8 *addr)
  2407. {
  2408. struct mwl8k_cmd_update_stadb *cmd;
  2409. int rc;
  2410. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2411. if (cmd == NULL)
  2412. return -ENOMEM;
  2413. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2414. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2415. cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
  2416. memcpy(cmd->peer_addr, addr, ETH_ALEN);
  2417. rc = mwl8k_post_cmd(hw, &cmd->header);
  2418. kfree(cmd);
  2419. return rc;
  2420. }
  2421. /*
  2422. * Interrupt handling.
  2423. */
  2424. static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
  2425. {
  2426. struct ieee80211_hw *hw = dev_id;
  2427. struct mwl8k_priv *priv = hw->priv;
  2428. u32 status;
  2429. status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2430. if (!status)
  2431. return IRQ_NONE;
  2432. if (status & MWL8K_A2H_INT_TX_DONE) {
  2433. status &= ~MWL8K_A2H_INT_TX_DONE;
  2434. tasklet_schedule(&priv->poll_tx_task);
  2435. }
  2436. if (status & MWL8K_A2H_INT_RX_READY) {
  2437. status &= ~MWL8K_A2H_INT_RX_READY;
  2438. tasklet_schedule(&priv->poll_rx_task);
  2439. }
  2440. if (status)
  2441. iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2442. if (status & MWL8K_A2H_INT_OPC_DONE) {
  2443. if (priv->hostcmd_wait != NULL)
  2444. complete(priv->hostcmd_wait);
  2445. }
  2446. if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
  2447. if (!mutex_is_locked(&priv->fw_mutex) &&
  2448. priv->radio_on && priv->pending_tx_pkts)
  2449. mwl8k_tx_start(priv);
  2450. }
  2451. return IRQ_HANDLED;
  2452. }
  2453. static void mwl8k_tx_poll(unsigned long data)
  2454. {
  2455. struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
  2456. struct mwl8k_priv *priv = hw->priv;
  2457. int limit;
  2458. int i;
  2459. limit = 32;
  2460. spin_lock_bh(&priv->tx_lock);
  2461. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2462. limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
  2463. if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
  2464. complete(priv->tx_wait);
  2465. priv->tx_wait = NULL;
  2466. }
  2467. spin_unlock_bh(&priv->tx_lock);
  2468. if (limit) {
  2469. writel(~MWL8K_A2H_INT_TX_DONE,
  2470. priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2471. } else {
  2472. tasklet_schedule(&priv->poll_tx_task);
  2473. }
  2474. }
  2475. static void mwl8k_rx_poll(unsigned long data)
  2476. {
  2477. struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
  2478. struct mwl8k_priv *priv = hw->priv;
  2479. int limit;
  2480. limit = 32;
  2481. limit -= rxq_process(hw, 0, limit);
  2482. limit -= rxq_refill(hw, 0, limit);
  2483. if (limit) {
  2484. writel(~MWL8K_A2H_INT_RX_READY,
  2485. priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2486. } else {
  2487. tasklet_schedule(&priv->poll_rx_task);
  2488. }
  2489. }
  2490. /*
  2491. * Core driver operations.
  2492. */
  2493. static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2494. {
  2495. struct mwl8k_priv *priv = hw->priv;
  2496. int index = skb_get_queue_mapping(skb);
  2497. int rc;
  2498. if (!priv->radio_on) {
  2499. printk(KERN_DEBUG "%s: dropped TX frame since radio "
  2500. "disabled\n", wiphy_name(hw->wiphy));
  2501. dev_kfree_skb(skb);
  2502. return NETDEV_TX_OK;
  2503. }
  2504. rc = mwl8k_txq_xmit(hw, index, skb);
  2505. return rc;
  2506. }
  2507. static int mwl8k_start(struct ieee80211_hw *hw)
  2508. {
  2509. struct mwl8k_priv *priv = hw->priv;
  2510. int rc;
  2511. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  2512. IRQF_SHARED, MWL8K_NAME, hw);
  2513. if (rc) {
  2514. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  2515. wiphy_name(hw->wiphy));
  2516. return -EIO;
  2517. }
  2518. /* Enable TX reclaim and RX tasklets. */
  2519. tasklet_enable(&priv->poll_tx_task);
  2520. tasklet_enable(&priv->poll_rx_task);
  2521. /* Enable interrupts */
  2522. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2523. rc = mwl8k_fw_lock(hw);
  2524. if (!rc) {
  2525. rc = mwl8k_cmd_radio_enable(hw);
  2526. if (!priv->ap_fw) {
  2527. if (!rc)
  2528. rc = mwl8k_cmd_enable_sniffer(hw, 0);
  2529. if (!rc)
  2530. rc = mwl8k_cmd_set_pre_scan(hw);
  2531. if (!rc)
  2532. rc = mwl8k_cmd_set_post_scan(hw,
  2533. "\x00\x00\x00\x00\x00\x00");
  2534. }
  2535. if (!rc)
  2536. rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
  2537. if (!rc)
  2538. rc = mwl8k_cmd_set_wmm_mode(hw, 0);
  2539. mwl8k_fw_unlock(hw);
  2540. }
  2541. if (rc) {
  2542. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2543. free_irq(priv->pdev->irq, hw);
  2544. tasklet_disable(&priv->poll_tx_task);
  2545. tasklet_disable(&priv->poll_rx_task);
  2546. }
  2547. return rc;
  2548. }
  2549. static void mwl8k_stop(struct ieee80211_hw *hw)
  2550. {
  2551. struct mwl8k_priv *priv = hw->priv;
  2552. int i;
  2553. mwl8k_cmd_radio_disable(hw);
  2554. ieee80211_stop_queues(hw);
  2555. /* Disable interrupts */
  2556. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2557. free_irq(priv->pdev->irq, hw);
  2558. /* Stop finalize join worker */
  2559. cancel_work_sync(&priv->finalize_join_worker);
  2560. if (priv->beacon_skb != NULL)
  2561. dev_kfree_skb(priv->beacon_skb);
  2562. /* Stop TX reclaim and RX tasklets. */
  2563. tasklet_disable(&priv->poll_tx_task);
  2564. tasklet_disable(&priv->poll_rx_task);
  2565. /* Return all skbs to mac80211 */
  2566. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2567. mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
  2568. }
  2569. static int mwl8k_add_interface(struct ieee80211_hw *hw,
  2570. struct ieee80211_vif *vif)
  2571. {
  2572. struct mwl8k_priv *priv = hw->priv;
  2573. struct mwl8k_vif *mwl8k_vif;
  2574. /*
  2575. * We only support one active interface at a time.
  2576. */
  2577. if (priv->vif != NULL)
  2578. return -EBUSY;
  2579. /*
  2580. * Reject interface creation if sniffer mode is active, as
  2581. * STA operation is mutually exclusive with hardware sniffer
  2582. * mode. (Sniffer mode is only used on STA firmware.)
  2583. */
  2584. if (priv->sniffer_enabled) {
  2585. printk(KERN_INFO "%s: unable to create STA "
  2586. "interface due to sniffer mode being enabled\n",
  2587. wiphy_name(hw->wiphy));
  2588. return -EINVAL;
  2589. }
  2590. /* Set the mac address. */
  2591. mwl8k_cmd_set_mac_addr(hw, vif->addr);
  2592. if (priv->ap_fw)
  2593. mwl8k_cmd_set_new_stn_add_self(hw, vif);
  2594. /* Clean out driver private area */
  2595. mwl8k_vif = MWL8K_VIF(vif);
  2596. memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
  2597. /* Set Initial sequence number to zero */
  2598. mwl8k_vif->seqno = 0;
  2599. priv->vif = vif;
  2600. return 0;
  2601. }
  2602. static void mwl8k_remove_interface(struct ieee80211_hw *hw,
  2603. struct ieee80211_vif *vif)
  2604. {
  2605. struct mwl8k_priv *priv = hw->priv;
  2606. if (priv->ap_fw)
  2607. mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
  2608. mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  2609. priv->vif = NULL;
  2610. }
  2611. static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
  2612. {
  2613. struct ieee80211_conf *conf = &hw->conf;
  2614. struct mwl8k_priv *priv = hw->priv;
  2615. int rc;
  2616. if (conf->flags & IEEE80211_CONF_IDLE) {
  2617. mwl8k_cmd_radio_disable(hw);
  2618. return 0;
  2619. }
  2620. rc = mwl8k_fw_lock(hw);
  2621. if (rc)
  2622. return rc;
  2623. rc = mwl8k_cmd_radio_enable(hw);
  2624. if (rc)
  2625. goto out;
  2626. rc = mwl8k_cmd_set_rf_channel(hw, conf);
  2627. if (rc)
  2628. goto out;
  2629. if (conf->power_level > 18)
  2630. conf->power_level = 18;
  2631. rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
  2632. if (rc)
  2633. goto out;
  2634. if (priv->ap_fw) {
  2635. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
  2636. if (!rc)
  2637. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
  2638. } else {
  2639. rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
  2640. }
  2641. out:
  2642. mwl8k_fw_unlock(hw);
  2643. return rc;
  2644. }
  2645. static void
  2646. mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2647. struct ieee80211_bss_conf *info, u32 changed)
  2648. {
  2649. struct mwl8k_priv *priv = hw->priv;
  2650. u32 ap_legacy_rates;
  2651. u8 ap_mcs_rates[16];
  2652. int rc;
  2653. if (mwl8k_fw_lock(hw))
  2654. return;
  2655. /*
  2656. * No need to capture a beacon if we're no longer associated.
  2657. */
  2658. if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
  2659. priv->capture_beacon = false;
  2660. /*
  2661. * Get the AP's legacy and MCS rates.
  2662. */
  2663. if (vif->bss_conf.assoc) {
  2664. struct ieee80211_sta *ap;
  2665. rcu_read_lock();
  2666. ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
  2667. if (ap == NULL) {
  2668. rcu_read_unlock();
  2669. goto out;
  2670. }
  2671. ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
  2672. memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
  2673. rcu_read_unlock();
  2674. }
  2675. if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
  2676. rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
  2677. if (rc)
  2678. goto out;
  2679. rc = mwl8k_cmd_use_fixed_rate_sta(hw);
  2680. if (rc)
  2681. goto out;
  2682. }
  2683. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  2684. rc = mwl8k_set_radio_preamble(hw,
  2685. vif->bss_conf.use_short_preamble);
  2686. if (rc)
  2687. goto out;
  2688. }
  2689. if (changed & BSS_CHANGED_ERP_SLOT) {
  2690. rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
  2691. if (rc)
  2692. goto out;
  2693. }
  2694. if (vif->bss_conf.assoc &&
  2695. (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
  2696. BSS_CHANGED_HT))) {
  2697. rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
  2698. if (rc)
  2699. goto out;
  2700. }
  2701. if (vif->bss_conf.assoc &&
  2702. (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
  2703. /*
  2704. * Finalize the join. Tell rx handler to process
  2705. * next beacon from our BSSID.
  2706. */
  2707. memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
  2708. priv->capture_beacon = true;
  2709. }
  2710. out:
  2711. mwl8k_fw_unlock(hw);
  2712. }
  2713. static void
  2714. mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2715. struct ieee80211_bss_conf *info, u32 changed)
  2716. {
  2717. int rc;
  2718. if (mwl8k_fw_lock(hw))
  2719. return;
  2720. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  2721. rc = mwl8k_set_radio_preamble(hw,
  2722. vif->bss_conf.use_short_preamble);
  2723. if (rc)
  2724. goto out;
  2725. }
  2726. if (changed & BSS_CHANGED_BASIC_RATES) {
  2727. int idx;
  2728. int rate;
  2729. /*
  2730. * Use lowest supported basic rate for multicasts
  2731. * and management frames (such as probe responses --
  2732. * beacons will always go out at 1 Mb/s).
  2733. */
  2734. idx = ffs(vif->bss_conf.basic_rates);
  2735. rate = idx ? mwl8k_rates_24[idx - 1].hw_value : 2;
  2736. mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
  2737. }
  2738. if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
  2739. struct sk_buff *skb;
  2740. skb = ieee80211_beacon_get(hw, vif);
  2741. if (skb != NULL) {
  2742. mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
  2743. kfree_skb(skb);
  2744. }
  2745. }
  2746. if (changed & BSS_CHANGED_BEACON_ENABLED)
  2747. mwl8k_cmd_bss_start(hw, info->enable_beacon);
  2748. out:
  2749. mwl8k_fw_unlock(hw);
  2750. }
  2751. static void
  2752. mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2753. struct ieee80211_bss_conf *info, u32 changed)
  2754. {
  2755. struct mwl8k_priv *priv = hw->priv;
  2756. if (!priv->ap_fw)
  2757. mwl8k_bss_info_changed_sta(hw, vif, info, changed);
  2758. else
  2759. mwl8k_bss_info_changed_ap(hw, vif, info, changed);
  2760. }
  2761. static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
  2762. int mc_count, struct dev_addr_list *mclist)
  2763. {
  2764. struct mwl8k_cmd_pkt *cmd;
  2765. /*
  2766. * Synthesize and return a command packet that programs the
  2767. * hardware multicast address filter. At this point we don't
  2768. * know whether FIF_ALLMULTI is being requested, but if it is,
  2769. * we'll end up throwing this packet away and creating a new
  2770. * one in mwl8k_configure_filter().
  2771. */
  2772. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
  2773. return (unsigned long)cmd;
  2774. }
  2775. static int
  2776. mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
  2777. unsigned int changed_flags,
  2778. unsigned int *total_flags)
  2779. {
  2780. struct mwl8k_priv *priv = hw->priv;
  2781. /*
  2782. * Hardware sniffer mode is mutually exclusive with STA
  2783. * operation, so refuse to enable sniffer mode if a STA
  2784. * interface is active.
  2785. */
  2786. if (priv->vif != NULL) {
  2787. if (net_ratelimit())
  2788. printk(KERN_INFO "%s: not enabling sniffer "
  2789. "mode because STA interface is active\n",
  2790. wiphy_name(hw->wiphy));
  2791. return 0;
  2792. }
  2793. if (!priv->sniffer_enabled) {
  2794. if (mwl8k_cmd_enable_sniffer(hw, 1))
  2795. return 0;
  2796. priv->sniffer_enabled = true;
  2797. }
  2798. *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
  2799. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
  2800. FIF_OTHER_BSS;
  2801. return 1;
  2802. }
  2803. static void mwl8k_configure_filter(struct ieee80211_hw *hw,
  2804. unsigned int changed_flags,
  2805. unsigned int *total_flags,
  2806. u64 multicast)
  2807. {
  2808. struct mwl8k_priv *priv = hw->priv;
  2809. struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
  2810. /*
  2811. * AP firmware doesn't allow fine-grained control over
  2812. * the receive filter.
  2813. */
  2814. if (priv->ap_fw) {
  2815. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2816. kfree(cmd);
  2817. return;
  2818. }
  2819. /*
  2820. * Enable hardware sniffer mode if FIF_CONTROL or
  2821. * FIF_OTHER_BSS is requested.
  2822. */
  2823. if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
  2824. mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
  2825. kfree(cmd);
  2826. return;
  2827. }
  2828. /* Clear unsupported feature flags */
  2829. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2830. if (mwl8k_fw_lock(hw)) {
  2831. kfree(cmd);
  2832. return;
  2833. }
  2834. if (priv->sniffer_enabled) {
  2835. mwl8k_cmd_enable_sniffer(hw, 0);
  2836. priv->sniffer_enabled = false;
  2837. }
  2838. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  2839. if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
  2840. /*
  2841. * Disable the BSS filter.
  2842. */
  2843. mwl8k_cmd_set_pre_scan(hw);
  2844. } else {
  2845. const u8 *bssid;
  2846. /*
  2847. * Enable the BSS filter.
  2848. *
  2849. * If there is an active STA interface, use that
  2850. * interface's BSSID, otherwise use a dummy one
  2851. * (where the OUI part needs to be nonzero for
  2852. * the BSSID to be accepted by POST_SCAN).
  2853. */
  2854. bssid = "\x01\x00\x00\x00\x00\x00";
  2855. if (priv->vif != NULL)
  2856. bssid = priv->vif->bss_conf.bssid;
  2857. mwl8k_cmd_set_post_scan(hw, bssid);
  2858. }
  2859. }
  2860. /*
  2861. * If FIF_ALLMULTI is being requested, throw away the command
  2862. * packet that ->prepare_multicast() built and replace it with
  2863. * a command packet that enables reception of all multicast
  2864. * packets.
  2865. */
  2866. if (*total_flags & FIF_ALLMULTI) {
  2867. kfree(cmd);
  2868. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
  2869. }
  2870. if (cmd != NULL) {
  2871. mwl8k_post_cmd(hw, cmd);
  2872. kfree(cmd);
  2873. }
  2874. mwl8k_fw_unlock(hw);
  2875. }
  2876. static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
  2877. {
  2878. return mwl8k_cmd_set_rts_threshold(hw, value);
  2879. }
  2880. struct mwl8k_sta_notify_item
  2881. {
  2882. struct list_head list;
  2883. struct ieee80211_vif *vif;
  2884. enum sta_notify_cmd cmd;
  2885. struct ieee80211_sta sta;
  2886. };
  2887. static void
  2888. mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
  2889. {
  2890. struct mwl8k_priv *priv = hw->priv;
  2891. /*
  2892. * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
  2893. */
  2894. if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
  2895. int rc;
  2896. rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
  2897. if (rc >= 0) {
  2898. struct ieee80211_sta *sta;
  2899. rcu_read_lock();
  2900. sta = ieee80211_find_sta(s->vif, s->sta.addr);
  2901. if (sta != NULL)
  2902. MWL8K_STA(sta)->peer_id = rc;
  2903. rcu_read_unlock();
  2904. }
  2905. } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
  2906. mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
  2907. } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
  2908. mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
  2909. } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
  2910. mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
  2911. }
  2912. }
  2913. static void mwl8k_sta_notify_worker(struct work_struct *work)
  2914. {
  2915. struct mwl8k_priv *priv =
  2916. container_of(work, struct mwl8k_priv, sta_notify_worker);
  2917. struct ieee80211_hw *hw = priv->hw;
  2918. spin_lock_bh(&priv->sta_notify_list_lock);
  2919. while (!list_empty(&priv->sta_notify_list)) {
  2920. struct mwl8k_sta_notify_item *s;
  2921. s = list_entry(priv->sta_notify_list.next,
  2922. struct mwl8k_sta_notify_item, list);
  2923. list_del(&s->list);
  2924. spin_unlock_bh(&priv->sta_notify_list_lock);
  2925. mwl8k_do_sta_notify(hw, s);
  2926. kfree(s);
  2927. spin_lock_bh(&priv->sta_notify_list_lock);
  2928. }
  2929. spin_unlock_bh(&priv->sta_notify_list_lock);
  2930. }
  2931. static void
  2932. mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2933. enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
  2934. {
  2935. struct mwl8k_priv *priv = hw->priv;
  2936. struct mwl8k_sta_notify_item *s;
  2937. if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
  2938. return;
  2939. s = kmalloc(sizeof(*s), GFP_ATOMIC);
  2940. if (s != NULL) {
  2941. s->vif = vif;
  2942. s->cmd = cmd;
  2943. s->sta = *sta;
  2944. spin_lock(&priv->sta_notify_list_lock);
  2945. list_add_tail(&s->list, &priv->sta_notify_list);
  2946. spin_unlock(&priv->sta_notify_list_lock);
  2947. ieee80211_queue_work(hw, &priv->sta_notify_worker);
  2948. }
  2949. }
  2950. static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  2951. const struct ieee80211_tx_queue_params *params)
  2952. {
  2953. struct mwl8k_priv *priv = hw->priv;
  2954. int rc;
  2955. rc = mwl8k_fw_lock(hw);
  2956. if (!rc) {
  2957. if (!priv->wmm_enabled)
  2958. rc = mwl8k_cmd_set_wmm_mode(hw, 1);
  2959. if (!rc)
  2960. rc = mwl8k_cmd_set_edca_params(hw, queue,
  2961. params->cw_min,
  2962. params->cw_max,
  2963. params->aifs,
  2964. params->txop);
  2965. mwl8k_fw_unlock(hw);
  2966. }
  2967. return rc;
  2968. }
  2969. static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
  2970. struct ieee80211_tx_queue_stats *stats)
  2971. {
  2972. struct mwl8k_priv *priv = hw->priv;
  2973. struct mwl8k_tx_queue *txq;
  2974. int index;
  2975. spin_lock_bh(&priv->tx_lock);
  2976. for (index = 0; index < MWL8K_TX_QUEUES; index++) {
  2977. txq = priv->txq + index;
  2978. memcpy(&stats[index], &txq->stats,
  2979. sizeof(struct ieee80211_tx_queue_stats));
  2980. }
  2981. spin_unlock_bh(&priv->tx_lock);
  2982. return 0;
  2983. }
  2984. static int mwl8k_get_stats(struct ieee80211_hw *hw,
  2985. struct ieee80211_low_level_stats *stats)
  2986. {
  2987. return mwl8k_cmd_get_stat(hw, stats);
  2988. }
  2989. static int
  2990. mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2991. enum ieee80211_ampdu_mlme_action action,
  2992. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2993. {
  2994. switch (action) {
  2995. case IEEE80211_AMPDU_RX_START:
  2996. case IEEE80211_AMPDU_RX_STOP:
  2997. if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
  2998. return -ENOTSUPP;
  2999. return 0;
  3000. default:
  3001. return -ENOTSUPP;
  3002. }
  3003. }
  3004. static const struct ieee80211_ops mwl8k_ops = {
  3005. .tx = mwl8k_tx,
  3006. .start = mwl8k_start,
  3007. .stop = mwl8k_stop,
  3008. .add_interface = mwl8k_add_interface,
  3009. .remove_interface = mwl8k_remove_interface,
  3010. .config = mwl8k_config,
  3011. .bss_info_changed = mwl8k_bss_info_changed,
  3012. .prepare_multicast = mwl8k_prepare_multicast,
  3013. .configure_filter = mwl8k_configure_filter,
  3014. .set_rts_threshold = mwl8k_set_rts_threshold,
  3015. .sta_notify = mwl8k_sta_notify,
  3016. .conf_tx = mwl8k_conf_tx,
  3017. .get_tx_stats = mwl8k_get_tx_stats,
  3018. .get_stats = mwl8k_get_stats,
  3019. .ampdu_action = mwl8k_ampdu_action,
  3020. };
  3021. static void mwl8k_finalize_join_worker(struct work_struct *work)
  3022. {
  3023. struct mwl8k_priv *priv =
  3024. container_of(work, struct mwl8k_priv, finalize_join_worker);
  3025. struct sk_buff *skb = priv->beacon_skb;
  3026. mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
  3027. priv->vif->bss_conf.dtim_period);
  3028. dev_kfree_skb(skb);
  3029. priv->beacon_skb = NULL;
  3030. }
  3031. enum {
  3032. MWL8363 = 0,
  3033. MWL8687,
  3034. MWL8366,
  3035. };
  3036. static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
  3037. [MWL8363] = {
  3038. .part_name = "88w8363",
  3039. .helper_image = "mwl8k/helper_8363.fw",
  3040. .fw_image = "mwl8k/fmimage_8363.fw",
  3041. },
  3042. [MWL8687] = {
  3043. .part_name = "88w8687",
  3044. .helper_image = "mwl8k/helper_8687.fw",
  3045. .fw_image = "mwl8k/fmimage_8687.fw",
  3046. },
  3047. [MWL8366] = {
  3048. .part_name = "88w8366",
  3049. .helper_image = "mwl8k/helper_8366.fw",
  3050. .fw_image = "mwl8k/fmimage_8366.fw",
  3051. .ap_rxd_ops = &rxd_8366_ap_ops,
  3052. },
  3053. };
  3054. MODULE_FIRMWARE("mwl8k/helper_8363.fw");
  3055. MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
  3056. MODULE_FIRMWARE("mwl8k/helper_8687.fw");
  3057. MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
  3058. MODULE_FIRMWARE("mwl8k/helper_8366.fw");
  3059. MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
  3060. static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
  3061. { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
  3062. { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
  3063. { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
  3064. { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
  3065. { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
  3066. { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
  3067. { },
  3068. };
  3069. MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
  3070. static int __devinit mwl8k_probe(struct pci_dev *pdev,
  3071. const struct pci_device_id *id)
  3072. {
  3073. static int printed_version = 0;
  3074. struct ieee80211_hw *hw;
  3075. struct mwl8k_priv *priv;
  3076. int rc;
  3077. int i;
  3078. if (!printed_version) {
  3079. printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
  3080. printed_version = 1;
  3081. }
  3082. rc = pci_enable_device(pdev);
  3083. if (rc) {
  3084. printk(KERN_ERR "%s: Cannot enable new PCI device\n",
  3085. MWL8K_NAME);
  3086. return rc;
  3087. }
  3088. rc = pci_request_regions(pdev, MWL8K_NAME);
  3089. if (rc) {
  3090. printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
  3091. MWL8K_NAME);
  3092. goto err_disable_device;
  3093. }
  3094. pci_set_master(pdev);
  3095. hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
  3096. if (hw == NULL) {
  3097. printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
  3098. rc = -ENOMEM;
  3099. goto err_free_reg;
  3100. }
  3101. SET_IEEE80211_DEV(hw, &pdev->dev);
  3102. pci_set_drvdata(pdev, hw);
  3103. priv = hw->priv;
  3104. priv->hw = hw;
  3105. priv->pdev = pdev;
  3106. priv->device_info = &mwl8k_info_tbl[id->driver_data];
  3107. priv->sram = pci_iomap(pdev, 0, 0x10000);
  3108. if (priv->sram == NULL) {
  3109. printk(KERN_ERR "%s: Cannot map device SRAM\n",
  3110. wiphy_name(hw->wiphy));
  3111. goto err_iounmap;
  3112. }
  3113. /*
  3114. * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
  3115. * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
  3116. */
  3117. priv->regs = pci_iomap(pdev, 1, 0x10000);
  3118. if (priv->regs == NULL) {
  3119. priv->regs = pci_iomap(pdev, 2, 0x10000);
  3120. if (priv->regs == NULL) {
  3121. printk(KERN_ERR "%s: Cannot map device registers\n",
  3122. wiphy_name(hw->wiphy));
  3123. goto err_iounmap;
  3124. }
  3125. }
  3126. /* Reset firmware and hardware */
  3127. mwl8k_hw_reset(priv);
  3128. /* Ask userland hotplug daemon for the device firmware */
  3129. rc = mwl8k_request_firmware(priv);
  3130. if (rc) {
  3131. printk(KERN_ERR "%s: Firmware files not found\n",
  3132. wiphy_name(hw->wiphy));
  3133. goto err_stop_firmware;
  3134. }
  3135. /* Load firmware into hardware */
  3136. rc = mwl8k_load_firmware(hw);
  3137. if (rc) {
  3138. printk(KERN_ERR "%s: Cannot start firmware\n",
  3139. wiphy_name(hw->wiphy));
  3140. goto err_stop_firmware;
  3141. }
  3142. /* Reclaim memory once firmware is successfully loaded */
  3143. mwl8k_release_firmware(priv);
  3144. if (priv->ap_fw) {
  3145. priv->rxd_ops = priv->device_info->ap_rxd_ops;
  3146. if (priv->rxd_ops == NULL) {
  3147. printk(KERN_ERR "%s: Driver does not have AP "
  3148. "firmware image support for this hardware\n",
  3149. wiphy_name(hw->wiphy));
  3150. goto err_stop_firmware;
  3151. }
  3152. } else {
  3153. priv->rxd_ops = &rxd_sta_ops;
  3154. }
  3155. priv->sniffer_enabled = false;
  3156. priv->wmm_enabled = false;
  3157. priv->pending_tx_pkts = 0;
  3158. /*
  3159. * Extra headroom is the size of the required DMA header
  3160. * minus the size of the smallest 802.11 frame (CTS frame).
  3161. */
  3162. hw->extra_tx_headroom =
  3163. sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
  3164. hw->channel_change_time = 10;
  3165. hw->queues = MWL8K_TX_QUEUES;
  3166. /* Set rssi and noise values to dBm */
  3167. hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
  3168. hw->vif_data_size = sizeof(struct mwl8k_vif);
  3169. hw->sta_data_size = sizeof(struct mwl8k_sta);
  3170. priv->vif = NULL;
  3171. /* Set default radio state and preamble */
  3172. priv->radio_on = 0;
  3173. priv->radio_short_preamble = 0;
  3174. /* Station database handling */
  3175. INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
  3176. spin_lock_init(&priv->sta_notify_list_lock);
  3177. INIT_LIST_HEAD(&priv->sta_notify_list);
  3178. /* Finalize join worker */
  3179. INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
  3180. /* TX reclaim and RX tasklets. */
  3181. tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
  3182. tasklet_disable(&priv->poll_tx_task);
  3183. tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
  3184. tasklet_disable(&priv->poll_rx_task);
  3185. /* Power management cookie */
  3186. priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
  3187. if (priv->cookie == NULL)
  3188. goto err_stop_firmware;
  3189. rc = mwl8k_rxq_init(hw, 0);
  3190. if (rc)
  3191. goto err_free_cookie;
  3192. rxq_refill(hw, 0, INT_MAX);
  3193. mutex_init(&priv->fw_mutex);
  3194. priv->fw_mutex_owner = NULL;
  3195. priv->fw_mutex_depth = 0;
  3196. priv->hostcmd_wait = NULL;
  3197. spin_lock_init(&priv->tx_lock);
  3198. priv->tx_wait = NULL;
  3199. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  3200. rc = mwl8k_txq_init(hw, i);
  3201. if (rc)
  3202. goto err_free_queues;
  3203. }
  3204. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  3205. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3206. iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
  3207. priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
  3208. iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
  3209. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  3210. IRQF_SHARED, MWL8K_NAME, hw);
  3211. if (rc) {
  3212. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  3213. wiphy_name(hw->wiphy));
  3214. goto err_free_queues;
  3215. }
  3216. /*
  3217. * Temporarily enable interrupts. Initial firmware host
  3218. * commands use interrupts and avoid polling. Disable
  3219. * interrupts when done.
  3220. */
  3221. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3222. /* Get config data, mac addrs etc */
  3223. if (priv->ap_fw) {
  3224. rc = mwl8k_cmd_get_hw_spec_ap(hw);
  3225. if (!rc)
  3226. rc = mwl8k_cmd_set_hw_spec(hw);
  3227. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
  3228. } else {
  3229. rc = mwl8k_cmd_get_hw_spec_sta(hw);
  3230. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
  3231. }
  3232. if (rc) {
  3233. printk(KERN_ERR "%s: Cannot initialise firmware\n",
  3234. wiphy_name(hw->wiphy));
  3235. goto err_free_irq;
  3236. }
  3237. /* Turn radio off */
  3238. rc = mwl8k_cmd_radio_disable(hw);
  3239. if (rc) {
  3240. printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
  3241. goto err_free_irq;
  3242. }
  3243. /* Clear MAC address */
  3244. rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  3245. if (rc) {
  3246. printk(KERN_ERR "%s: Cannot clear MAC address\n",
  3247. wiphy_name(hw->wiphy));
  3248. goto err_free_irq;
  3249. }
  3250. /* Disable interrupts */
  3251. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3252. free_irq(priv->pdev->irq, hw);
  3253. rc = ieee80211_register_hw(hw);
  3254. if (rc) {
  3255. printk(KERN_ERR "%s: Cannot register device\n",
  3256. wiphy_name(hw->wiphy));
  3257. goto err_free_queues;
  3258. }
  3259. printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
  3260. wiphy_name(hw->wiphy), priv->device_info->part_name,
  3261. priv->hw_rev, hw->wiphy->perm_addr,
  3262. priv->ap_fw ? "AP" : "STA",
  3263. (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
  3264. (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
  3265. return 0;
  3266. err_free_irq:
  3267. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3268. free_irq(priv->pdev->irq, hw);
  3269. err_free_queues:
  3270. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3271. mwl8k_txq_deinit(hw, i);
  3272. mwl8k_rxq_deinit(hw, 0);
  3273. err_free_cookie:
  3274. if (priv->cookie != NULL)
  3275. pci_free_consistent(priv->pdev, 4,
  3276. priv->cookie, priv->cookie_dma);
  3277. err_stop_firmware:
  3278. mwl8k_hw_reset(priv);
  3279. mwl8k_release_firmware(priv);
  3280. err_iounmap:
  3281. if (priv->regs != NULL)
  3282. pci_iounmap(pdev, priv->regs);
  3283. if (priv->sram != NULL)
  3284. pci_iounmap(pdev, priv->sram);
  3285. pci_set_drvdata(pdev, NULL);
  3286. ieee80211_free_hw(hw);
  3287. err_free_reg:
  3288. pci_release_regions(pdev);
  3289. err_disable_device:
  3290. pci_disable_device(pdev);
  3291. return rc;
  3292. }
  3293. static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
  3294. {
  3295. printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
  3296. }
  3297. static void __devexit mwl8k_remove(struct pci_dev *pdev)
  3298. {
  3299. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  3300. struct mwl8k_priv *priv;
  3301. int i;
  3302. if (hw == NULL)
  3303. return;
  3304. priv = hw->priv;
  3305. ieee80211_stop_queues(hw);
  3306. ieee80211_unregister_hw(hw);
  3307. /* Remove TX reclaim and RX tasklets. */
  3308. tasklet_kill(&priv->poll_tx_task);
  3309. tasklet_kill(&priv->poll_rx_task);
  3310. /* Stop hardware */
  3311. mwl8k_hw_reset(priv);
  3312. /* Return all skbs to mac80211 */
  3313. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3314. mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
  3315. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3316. mwl8k_txq_deinit(hw, i);
  3317. mwl8k_rxq_deinit(hw, 0);
  3318. pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
  3319. pci_iounmap(pdev, priv->regs);
  3320. pci_iounmap(pdev, priv->sram);
  3321. pci_set_drvdata(pdev, NULL);
  3322. ieee80211_free_hw(hw);
  3323. pci_release_regions(pdev);
  3324. pci_disable_device(pdev);
  3325. }
  3326. static struct pci_driver mwl8k_driver = {
  3327. .name = MWL8K_NAME,
  3328. .id_table = mwl8k_pci_id_table,
  3329. .probe = mwl8k_probe,
  3330. .remove = __devexit_p(mwl8k_remove),
  3331. .shutdown = __devexit_p(mwl8k_shutdown),
  3332. };
  3333. static int __init mwl8k_init(void)
  3334. {
  3335. return pci_register_driver(&mwl8k_driver);
  3336. }
  3337. static void __exit mwl8k_exit(void)
  3338. {
  3339. pci_unregister_driver(&mwl8k_driver);
  3340. }
  3341. module_init(mwl8k_init);
  3342. module_exit(mwl8k_exit);
  3343. MODULE_DESCRIPTION(MWL8K_DESC);
  3344. MODULE_VERSION(MWL8K_VERSION);
  3345. MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
  3346. MODULE_LICENSE("GPL");