ql4_mbx.c 54 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine issue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. uint32_t dev_state;
  33. /* Make sure that pointers are valid */
  34. if (!mbx_cmd || !mbx_sts) {
  35. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  36. "pointer\n", ha->host_no, __func__));
  37. return status;
  38. }
  39. if (is_qla40XX(ha)) {
  40. if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
  41. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  42. "prematurely completing mbx cmd as "
  43. "adapter removal detected\n",
  44. ha->host_no, __func__));
  45. return status;
  46. }
  47. }
  48. if (is_qla8022(ha)) {
  49. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  50. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  51. "prematurely completing mbx cmd as firmware "
  52. "recovery detected\n", ha->host_no, __func__));
  53. return status;
  54. }
  55. /* Do not send any mbx cmd if h/w is in failed state*/
  56. qla4_8xxx_idc_lock(ha);
  57. dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  58. qla4_8xxx_idc_unlock(ha);
  59. if (dev_state == QLA82XX_DEV_FAILED) {
  60. ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: H/W is in "
  61. "failed state, do not send any mailbox commands\n",
  62. ha->host_no, __func__);
  63. return status;
  64. }
  65. }
  66. if ((is_aer_supported(ha)) &&
  67. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  68. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  69. "timeout MBX Exiting.\n", ha->host_no, __func__));
  70. return status;
  71. }
  72. /* Mailbox code active */
  73. wait_count = MBOX_TOV * 100;
  74. while (wait_count--) {
  75. mutex_lock(&ha->mbox_sem);
  76. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  77. set_bit(AF_MBOX_COMMAND, &ha->flags);
  78. mutex_unlock(&ha->mbox_sem);
  79. break;
  80. }
  81. mutex_unlock(&ha->mbox_sem);
  82. if (!wait_count) {
  83. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  84. ha->host_no, __func__));
  85. return status;
  86. }
  87. msleep(10);
  88. }
  89. spin_lock_irqsave(&ha->hardware_lock, flags);
  90. ha->mbox_status_count = outCount;
  91. for (i = 0; i < outCount; i++)
  92. ha->mbox_status[i] = 0;
  93. if (is_qla8022(ha)) {
  94. /* Load all mailbox registers, except mailbox 0. */
  95. DEBUG5(
  96. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  97. for (i = 0; i < inCount; i++)
  98. printk("mb%d=%04x ", i, mbx_cmd[i]);
  99. printk("\n"));
  100. for (i = 1; i < inCount; i++)
  101. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  102. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  103. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  104. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  105. } else {
  106. /* Load all mailbox registers, except mailbox 0. */
  107. for (i = 1; i < inCount; i++)
  108. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  109. /* Wakeup firmware */
  110. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  111. readl(&ha->reg->mailbox[0]);
  112. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  113. readl(&ha->reg->ctrl_status);
  114. }
  115. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  116. /* Wait for completion */
  117. /*
  118. * If we don't want status, don't wait for the mailbox command to
  119. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  120. * you must poll the inbound Interrupt Mask for completion.
  121. */
  122. if (outCount == 0) {
  123. status = QLA_SUCCESS;
  124. goto mbox_exit;
  125. }
  126. /*
  127. * Wait for completion: Poll or completion queue
  128. */
  129. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  130. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  131. test_bit(AF_ONLINE, &ha->flags) &&
  132. !test_bit(AF_HA_REMOVAL, &ha->flags)) {
  133. /* Do not poll for completion. Use completion queue */
  134. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  135. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  136. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  137. } else {
  138. /* Poll for command to complete */
  139. wait_count = jiffies + MBOX_TOV * HZ;
  140. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  141. if (time_after_eq(jiffies, wait_count))
  142. break;
  143. /*
  144. * Service the interrupt.
  145. * The ISR will save the mailbox status registers
  146. * to a temporary storage location in the adapter
  147. * structure.
  148. */
  149. spin_lock_irqsave(&ha->hardware_lock, flags);
  150. if (is_qla8022(ha)) {
  151. intr_status =
  152. readl(&ha->qla4_8xxx_reg->host_int);
  153. if (intr_status & ISRX_82XX_RISC_INT) {
  154. ha->mbox_status_count = outCount;
  155. intr_status =
  156. readl(&ha->qla4_8xxx_reg->host_status);
  157. ha->isp_ops->interrupt_service_routine(
  158. ha, intr_status);
  159. if (test_bit(AF_INTERRUPTS_ON,
  160. &ha->flags) &&
  161. test_bit(AF_INTx_ENABLED,
  162. &ha->flags))
  163. qla4_8xxx_wr_32(ha,
  164. ha->nx_legacy_intr.tgt_mask_reg,
  165. 0xfbff);
  166. }
  167. } else {
  168. intr_status = readl(&ha->reg->ctrl_status);
  169. if (intr_status & INTR_PENDING) {
  170. /*
  171. * Service the interrupt.
  172. * The ISR will save the mailbox status
  173. * registers to a temporary storage
  174. * location in the adapter structure.
  175. */
  176. ha->mbox_status_count = outCount;
  177. ha->isp_ops->interrupt_service_routine(
  178. ha, intr_status);
  179. }
  180. }
  181. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  182. msleep(10);
  183. }
  184. }
  185. /* Check for mailbox timeout. */
  186. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  187. if (is_qla8022(ha) &&
  188. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  189. DEBUG2(ql4_printk(KERN_INFO, ha,
  190. "scsi%ld: %s: prematurely completing mbx cmd as "
  191. "firmware recovery detected\n",
  192. ha->host_no, __func__));
  193. goto mbox_exit;
  194. }
  195. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  196. " Scheduling Adapter Reset\n", ha->host_no,
  197. mbx_cmd[0]));
  198. ha->mailbox_timeout_count++;
  199. mbx_sts[0] = (-1);
  200. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  201. goto mbox_exit;
  202. }
  203. /*
  204. * Copy the mailbox out registers to the caller's mailbox in/out
  205. * structure.
  206. */
  207. spin_lock_irqsave(&ha->hardware_lock, flags);
  208. for (i = 0; i < outCount; i++)
  209. mbx_sts[i] = ha->mbox_status[i];
  210. /* Set return status and error flags (if applicable). */
  211. switch (ha->mbox_status[0]) {
  212. case MBOX_STS_COMMAND_COMPLETE:
  213. status = QLA_SUCCESS;
  214. break;
  215. case MBOX_STS_INTERMEDIATE_COMPLETION:
  216. status = QLA_SUCCESS;
  217. break;
  218. case MBOX_STS_BUSY:
  219. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  220. ha->host_no, __func__, mbx_cmd[0]));
  221. ha->mailbox_timeout_count++;
  222. break;
  223. default:
  224. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  225. "sts = %08X ****\n", ha->host_no, __func__,
  226. mbx_cmd[0], mbx_sts[0]));
  227. break;
  228. }
  229. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  230. mbox_exit:
  231. mutex_lock(&ha->mbox_sem);
  232. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  233. mutex_unlock(&ha->mbox_sem);
  234. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  235. return status;
  236. }
  237. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  238. {
  239. set_bit(AF_FW_RECOVERY, &ha->flags);
  240. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  241. ha->host_no, __func__);
  242. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  243. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  244. complete(&ha->mbx_intr_comp);
  245. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  246. "recovery, doing premature completion of "
  247. "mbx cmd\n", ha->host_no, __func__);
  248. } else {
  249. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  250. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  251. "recovery, doing premature completion of "
  252. "polling mbx cmd\n", ha->host_no, __func__);
  253. }
  254. }
  255. }
  256. static uint8_t
  257. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  258. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  259. {
  260. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  261. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  262. if (is_qla8022(ha))
  263. qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  264. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  265. mbox_cmd[1] = 0;
  266. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  267. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  268. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  269. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  270. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  271. QLA_SUCCESS) {
  272. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  273. "MBOX_CMD_INITIALIZE_FIRMWARE"
  274. " failed w/ status %04X\n",
  275. ha->host_no, __func__, mbox_sts[0]));
  276. return QLA_ERROR;
  277. }
  278. return QLA_SUCCESS;
  279. }
  280. uint8_t
  281. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  282. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  283. {
  284. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  285. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  286. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  287. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  288. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  289. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  290. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  291. QLA_SUCCESS) {
  292. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  293. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  294. " failed w/ status %04X\n",
  295. ha->host_no, __func__, mbox_sts[0]));
  296. return QLA_ERROR;
  297. }
  298. return QLA_SUCCESS;
  299. }
  300. static void
  301. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  302. struct addr_ctrl_blk *init_fw_cb)
  303. {
  304. ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  305. ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  306. ha->ip_config.ipv4_addr_state =
  307. le16_to_cpu(init_fw_cb->ipv4_addr_state);
  308. ha->ip_config.eth_mtu_size =
  309. le16_to_cpu(init_fw_cb->eth_mtu_size);
  310. ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
  311. if (ha->acb_version == ACB_SUPPORTED) {
  312. ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
  313. ha->ip_config.ipv6_addl_options =
  314. le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
  315. }
  316. /* Save IPv4 Address Info */
  317. memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
  318. min(sizeof(ha->ip_config.ip_address),
  319. sizeof(init_fw_cb->ipv4_addr)));
  320. memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
  321. min(sizeof(ha->ip_config.subnet_mask),
  322. sizeof(init_fw_cb->ipv4_subnet)));
  323. memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
  324. min(sizeof(ha->ip_config.gateway),
  325. sizeof(init_fw_cb->ipv4_gw_addr)));
  326. ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
  327. if (is_ipv6_enabled(ha)) {
  328. /* Save IPv6 Address */
  329. ha->ip_config.ipv6_link_local_state =
  330. le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
  331. ha->ip_config.ipv6_addr0_state =
  332. le16_to_cpu(init_fw_cb->ipv6_addr0_state);
  333. ha->ip_config.ipv6_addr1_state =
  334. le16_to_cpu(init_fw_cb->ipv6_addr1_state);
  335. ha->ip_config.ipv6_default_router_state =
  336. le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
  337. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  338. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  339. memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
  340. init_fw_cb->ipv6_if_id,
  341. min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
  342. sizeof(init_fw_cb->ipv6_if_id)));
  343. memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
  344. min(sizeof(ha->ip_config.ipv6_addr0),
  345. sizeof(init_fw_cb->ipv6_addr0)));
  346. memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
  347. min(sizeof(ha->ip_config.ipv6_addr1),
  348. sizeof(init_fw_cb->ipv6_addr1)));
  349. memcpy(&ha->ip_config.ipv6_default_router_addr,
  350. init_fw_cb->ipv6_dflt_rtr_addr,
  351. min(sizeof(ha->ip_config.ipv6_default_router_addr),
  352. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  353. ha->ip_config.ipv6_vlan_tag =
  354. be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
  355. ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
  356. }
  357. }
  358. uint8_t
  359. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  360. uint32_t *mbox_cmd,
  361. uint32_t *mbox_sts,
  362. struct addr_ctrl_blk *init_fw_cb,
  363. dma_addr_t init_fw_cb_dma)
  364. {
  365. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  366. != QLA_SUCCESS) {
  367. DEBUG2(printk(KERN_WARNING
  368. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  369. ha->host_no, __func__));
  370. return QLA_ERROR;
  371. }
  372. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  373. /* Save some info in adapter structure. */
  374. ha->acb_version = init_fw_cb->acb_version;
  375. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  376. ha->heartbeat_interval = init_fw_cb->hb_interval;
  377. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  378. min(sizeof(ha->name_string),
  379. sizeof(init_fw_cb->iscsi_name)));
  380. ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
  381. /*memcpy(ha->alias, init_fw_cb->Alias,
  382. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  383. qla4xxx_update_local_ip(ha, init_fw_cb);
  384. return QLA_SUCCESS;
  385. }
  386. /**
  387. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  388. * @ha: Pointer to host adapter structure.
  389. **/
  390. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  391. {
  392. struct addr_ctrl_blk *init_fw_cb;
  393. dma_addr_t init_fw_cb_dma;
  394. uint32_t mbox_cmd[MBOX_REG_COUNT];
  395. uint32_t mbox_sts[MBOX_REG_COUNT];
  396. int status = QLA_ERROR;
  397. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  398. sizeof(struct addr_ctrl_blk),
  399. &init_fw_cb_dma, GFP_KERNEL);
  400. if (init_fw_cb == NULL) {
  401. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  402. ha->host_no, __func__));
  403. goto exit_init_fw_cb_no_free;
  404. }
  405. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  406. /* Get Initialize Firmware Control Block. */
  407. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  408. memset(&mbox_sts, 0, sizeof(mbox_sts));
  409. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  410. QLA_SUCCESS) {
  411. dma_free_coherent(&ha->pdev->dev,
  412. sizeof(struct addr_ctrl_blk),
  413. init_fw_cb, init_fw_cb_dma);
  414. goto exit_init_fw_cb;
  415. }
  416. /* Initialize request and response queues. */
  417. qla4xxx_init_rings(ha);
  418. /* Fill in the request and response queue information. */
  419. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  420. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  421. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  422. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  423. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  424. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  425. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  426. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  427. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  428. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  429. /* Set up required options. */
  430. init_fw_cb->fw_options |=
  431. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  432. FWOPT_INITIATOR_MODE);
  433. if (is_qla8022(ha))
  434. init_fw_cb->fw_options |=
  435. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  436. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  437. init_fw_cb->add_fw_options = 0;
  438. init_fw_cb->add_fw_options |=
  439. __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
  440. init_fw_cb->add_fw_options |=
  441. __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
  442. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  443. != QLA_SUCCESS) {
  444. DEBUG2(printk(KERN_WARNING
  445. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  446. ha->host_no, __func__));
  447. goto exit_init_fw_cb;
  448. }
  449. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  450. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  451. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  452. ha->host_no, __func__));
  453. goto exit_init_fw_cb;
  454. }
  455. status = QLA_SUCCESS;
  456. exit_init_fw_cb:
  457. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  458. init_fw_cb, init_fw_cb_dma);
  459. exit_init_fw_cb_no_free:
  460. return status;
  461. }
  462. /**
  463. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  464. * @ha: Pointer to host adapter structure.
  465. **/
  466. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  467. {
  468. struct addr_ctrl_blk *init_fw_cb;
  469. dma_addr_t init_fw_cb_dma;
  470. uint32_t mbox_cmd[MBOX_REG_COUNT];
  471. uint32_t mbox_sts[MBOX_REG_COUNT];
  472. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  473. sizeof(struct addr_ctrl_blk),
  474. &init_fw_cb_dma, GFP_KERNEL);
  475. if (init_fw_cb == NULL) {
  476. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  477. __func__);
  478. return QLA_ERROR;
  479. }
  480. /* Get Initialize Firmware Control Block. */
  481. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  482. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  483. QLA_SUCCESS) {
  484. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  485. ha->host_no, __func__));
  486. dma_free_coherent(&ha->pdev->dev,
  487. sizeof(struct addr_ctrl_blk),
  488. init_fw_cb, init_fw_cb_dma);
  489. return QLA_ERROR;
  490. }
  491. /* Save IP Address. */
  492. qla4xxx_update_local_ip(ha, init_fw_cb);
  493. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  494. init_fw_cb, init_fw_cb_dma);
  495. return QLA_SUCCESS;
  496. }
  497. /**
  498. * qla4xxx_get_firmware_state - gets firmware state of HBA
  499. * @ha: Pointer to host adapter structure.
  500. **/
  501. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  502. {
  503. uint32_t mbox_cmd[MBOX_REG_COUNT];
  504. uint32_t mbox_sts[MBOX_REG_COUNT];
  505. /* Get firmware version */
  506. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  507. memset(&mbox_sts, 0, sizeof(mbox_sts));
  508. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  509. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  510. QLA_SUCCESS) {
  511. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  512. "status %04X\n", ha->host_no, __func__,
  513. mbox_sts[0]));
  514. return QLA_ERROR;
  515. }
  516. ha->firmware_state = mbox_sts[1];
  517. ha->board_id = mbox_sts[2];
  518. ha->addl_fw_state = mbox_sts[3];
  519. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  520. ha->host_no, __func__, ha->firmware_state);)
  521. return QLA_SUCCESS;
  522. }
  523. /**
  524. * qla4xxx_get_firmware_status - retrieves firmware status
  525. * @ha: Pointer to host adapter structure.
  526. **/
  527. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  528. {
  529. uint32_t mbox_cmd[MBOX_REG_COUNT];
  530. uint32_t mbox_sts[MBOX_REG_COUNT];
  531. /* Get firmware version */
  532. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  533. memset(&mbox_sts, 0, sizeof(mbox_sts));
  534. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  535. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  536. QLA_SUCCESS) {
  537. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  538. "status %04X\n", ha->host_no, __func__,
  539. mbox_sts[0]));
  540. return QLA_ERROR;
  541. }
  542. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  543. ha->host_no, mbox_sts[2]);
  544. return QLA_SUCCESS;
  545. }
  546. /**
  547. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  548. * @ha: Pointer to host adapter structure.
  549. * @fw_ddb_index: Firmware's device database index
  550. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  551. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  552. * @next_ddb_index: Pointer to next valid device database index
  553. * @fw_ddb_device_state: Pointer to device state
  554. **/
  555. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  556. uint16_t fw_ddb_index,
  557. struct dev_db_entry *fw_ddb_entry,
  558. dma_addr_t fw_ddb_entry_dma,
  559. uint32_t *num_valid_ddb_entries,
  560. uint32_t *next_ddb_index,
  561. uint32_t *fw_ddb_device_state,
  562. uint32_t *conn_err_detail,
  563. uint16_t *tcp_source_port_num,
  564. uint16_t *connection_id)
  565. {
  566. int status = QLA_ERROR;
  567. uint16_t options;
  568. uint32_t mbox_cmd[MBOX_REG_COUNT];
  569. uint32_t mbox_sts[MBOX_REG_COUNT];
  570. /* Make sure the device index is valid */
  571. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  572. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  573. ha->host_no, __func__, fw_ddb_index));
  574. goto exit_get_fwddb;
  575. }
  576. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  577. memset(&mbox_sts, 0, sizeof(mbox_sts));
  578. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  579. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  580. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  581. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  582. mbox_cmd[4] = sizeof(struct dev_db_entry);
  583. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  584. QLA_ERROR) {
  585. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  586. " with status 0x%04X\n", ha->host_no, __func__,
  587. mbox_sts[0]));
  588. goto exit_get_fwddb;
  589. }
  590. if (fw_ddb_index != mbox_sts[1]) {
  591. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  592. ha->host_no, __func__, fw_ddb_index,
  593. mbox_sts[1]));
  594. goto exit_get_fwddb;
  595. }
  596. if (fw_ddb_entry) {
  597. options = le16_to_cpu(fw_ddb_entry->options);
  598. if (options & DDB_OPT_IPV6_DEVICE) {
  599. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  600. "Next %d State %04x ConnErr %08x %pI6 "
  601. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  602. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  603. mbox_sts[4], mbox_sts[5],
  604. fw_ddb_entry->ip_addr,
  605. le16_to_cpu(fw_ddb_entry->port),
  606. fw_ddb_entry->iscsi_name);
  607. } else {
  608. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  609. "Next %d State %04x ConnErr %08x %pI4 "
  610. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  611. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  612. mbox_sts[4], mbox_sts[5],
  613. fw_ddb_entry->ip_addr,
  614. le16_to_cpu(fw_ddb_entry->port),
  615. fw_ddb_entry->iscsi_name);
  616. }
  617. }
  618. if (num_valid_ddb_entries)
  619. *num_valid_ddb_entries = mbox_sts[2];
  620. if (next_ddb_index)
  621. *next_ddb_index = mbox_sts[3];
  622. if (fw_ddb_device_state)
  623. *fw_ddb_device_state = mbox_sts[4];
  624. /*
  625. * RA: This mailbox has been changed to pass connection error and
  626. * details. Its true for ISP4010 as per Version E - Not sure when it
  627. * was changed. Get the time2wait from the fw_dd_entry field :
  628. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  629. * struct.
  630. */
  631. if (conn_err_detail)
  632. *conn_err_detail = mbox_sts[5];
  633. if (tcp_source_port_num)
  634. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  635. if (connection_id)
  636. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  637. status = QLA_SUCCESS;
  638. exit_get_fwddb:
  639. return status;
  640. }
  641. int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
  642. {
  643. uint32_t mbox_cmd[MBOX_REG_COUNT];
  644. uint32_t mbox_sts[MBOX_REG_COUNT];
  645. int status;
  646. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  647. memset(&mbox_sts, 0, sizeof(mbox_sts));
  648. mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
  649. mbox_cmd[1] = fw_ddb_index;
  650. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  651. &mbox_sts[0]);
  652. DEBUG2(ql4_printk(KERN_INFO, ha,
  653. "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
  654. __func__, status, mbox_sts[0], mbox_sts[1]));
  655. return status;
  656. }
  657. /**
  658. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  659. * @ha: Pointer to host adapter structure.
  660. * @fw_ddb_index: Firmware's device database index
  661. * @fw_ddb_entry_dma: dma address of ddb entry
  662. * @mbx_sts: mailbox 0 to be returned or NULL
  663. *
  664. * This routine initializes or updates the adapter's device database
  665. * entry for the specified device.
  666. **/
  667. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  668. dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
  669. {
  670. uint32_t mbox_cmd[MBOX_REG_COUNT];
  671. uint32_t mbox_sts[MBOX_REG_COUNT];
  672. int status;
  673. /* Do not wait for completion. The firmware will send us an
  674. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  675. */
  676. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  677. memset(&mbox_sts, 0, sizeof(mbox_sts));
  678. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  679. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  680. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  681. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  682. mbox_cmd[4] = sizeof(struct dev_db_entry);
  683. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  684. &mbox_sts[0]);
  685. if (mbx_sts)
  686. *mbx_sts = mbox_sts[0];
  687. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  688. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  689. return status;
  690. }
  691. int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
  692. struct ddb_entry *ddb_entry, int options)
  693. {
  694. int status;
  695. uint32_t mbox_cmd[MBOX_REG_COUNT];
  696. uint32_t mbox_sts[MBOX_REG_COUNT];
  697. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  698. memset(&mbox_sts, 0, sizeof(mbox_sts));
  699. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  700. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  701. mbox_cmd[3] = options;
  702. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  703. &mbox_sts[0]);
  704. if (status != QLA_SUCCESS) {
  705. DEBUG2(ql4_printk(KERN_INFO, ha,
  706. "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
  707. "failed sts %04X %04X", __func__,
  708. mbox_sts[0], mbox_sts[1]));
  709. }
  710. return status;
  711. }
  712. /**
  713. * qla4xxx_get_crash_record - retrieves crash record.
  714. * @ha: Pointer to host adapter structure.
  715. *
  716. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  717. **/
  718. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  719. {
  720. uint32_t mbox_cmd[MBOX_REG_COUNT];
  721. uint32_t mbox_sts[MBOX_REG_COUNT];
  722. struct crash_record *crash_record = NULL;
  723. dma_addr_t crash_record_dma = 0;
  724. uint32_t crash_record_size = 0;
  725. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  726. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  727. /* Get size of crash record. */
  728. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  729. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  730. QLA_SUCCESS) {
  731. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  732. ha->host_no, __func__));
  733. goto exit_get_crash_record;
  734. }
  735. crash_record_size = mbox_sts[4];
  736. if (crash_record_size == 0) {
  737. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  738. ha->host_no, __func__));
  739. goto exit_get_crash_record;
  740. }
  741. /* Alloc Memory for Crash Record. */
  742. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  743. &crash_record_dma, GFP_KERNEL);
  744. if (crash_record == NULL)
  745. goto exit_get_crash_record;
  746. /* Get Crash Record. */
  747. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  748. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  749. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  750. mbox_cmd[2] = LSDW(crash_record_dma);
  751. mbox_cmd[3] = MSDW(crash_record_dma);
  752. mbox_cmd[4] = crash_record_size;
  753. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  754. QLA_SUCCESS)
  755. goto exit_get_crash_record;
  756. /* Dump Crash Record. */
  757. exit_get_crash_record:
  758. if (crash_record)
  759. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  760. crash_record, crash_record_dma);
  761. }
  762. /**
  763. * qla4xxx_get_conn_event_log - retrieves connection event log
  764. * @ha: Pointer to host adapter structure.
  765. **/
  766. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  767. {
  768. uint32_t mbox_cmd[MBOX_REG_COUNT];
  769. uint32_t mbox_sts[MBOX_REG_COUNT];
  770. struct conn_event_log_entry *event_log = NULL;
  771. dma_addr_t event_log_dma = 0;
  772. uint32_t event_log_size = 0;
  773. uint32_t num_valid_entries;
  774. uint32_t oldest_entry = 0;
  775. uint32_t max_event_log_entries;
  776. uint8_t i;
  777. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  778. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  779. /* Get size of crash record. */
  780. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  781. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  782. QLA_SUCCESS)
  783. goto exit_get_event_log;
  784. event_log_size = mbox_sts[4];
  785. if (event_log_size == 0)
  786. goto exit_get_event_log;
  787. /* Alloc Memory for Crash Record. */
  788. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  789. &event_log_dma, GFP_KERNEL);
  790. if (event_log == NULL)
  791. goto exit_get_event_log;
  792. /* Get Crash Record. */
  793. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  794. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  795. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  796. mbox_cmd[2] = LSDW(event_log_dma);
  797. mbox_cmd[3] = MSDW(event_log_dma);
  798. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  799. QLA_SUCCESS) {
  800. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  801. "log!\n", ha->host_no, __func__));
  802. goto exit_get_event_log;
  803. }
  804. /* Dump Event Log. */
  805. num_valid_entries = mbox_sts[1];
  806. max_event_log_entries = event_log_size /
  807. sizeof(struct conn_event_log_entry);
  808. if (num_valid_entries > max_event_log_entries)
  809. oldest_entry = num_valid_entries % max_event_log_entries;
  810. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  811. ha->host_no, num_valid_entries));
  812. if (ql4xextended_error_logging == 3) {
  813. if (oldest_entry == 0) {
  814. /* Circular Buffer has not wrapped around */
  815. for (i=0; i < num_valid_entries; i++) {
  816. qla4xxx_dump_buffer((uint8_t *)event_log+
  817. (i*sizeof(*event_log)),
  818. sizeof(*event_log));
  819. }
  820. }
  821. else {
  822. /* Circular Buffer has wrapped around -
  823. * display accordingly*/
  824. for (i=oldest_entry; i < max_event_log_entries; i++) {
  825. qla4xxx_dump_buffer((uint8_t *)event_log+
  826. (i*sizeof(*event_log)),
  827. sizeof(*event_log));
  828. }
  829. for (i=0; i < oldest_entry; i++) {
  830. qla4xxx_dump_buffer((uint8_t *)event_log+
  831. (i*sizeof(*event_log)),
  832. sizeof(*event_log));
  833. }
  834. }
  835. }
  836. exit_get_event_log:
  837. if (event_log)
  838. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  839. event_log_dma);
  840. }
  841. /**
  842. * qla4xxx_abort_task - issues Abort Task
  843. * @ha: Pointer to host adapter structure.
  844. * @srb: Pointer to srb entry
  845. *
  846. * This routine performs a LUN RESET on the specified target/lun.
  847. * The caller must ensure that the ddb_entry and lun_entry pointers
  848. * are valid before calling this routine.
  849. **/
  850. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  851. {
  852. uint32_t mbox_cmd[MBOX_REG_COUNT];
  853. uint32_t mbox_sts[MBOX_REG_COUNT];
  854. struct scsi_cmnd *cmd = srb->cmd;
  855. int status = QLA_SUCCESS;
  856. unsigned long flags = 0;
  857. uint32_t index;
  858. /*
  859. * Send abort task command to ISP, so that the ISP will return
  860. * request with ABORT status
  861. */
  862. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  863. memset(&mbox_sts, 0, sizeof(mbox_sts));
  864. spin_lock_irqsave(&ha->hardware_lock, flags);
  865. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  866. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  867. /* Firmware already posted completion on response queue */
  868. if (index == MAX_SRBS)
  869. return status;
  870. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  871. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  872. mbox_cmd[2] = index;
  873. /* Immediate Command Enable */
  874. mbox_cmd[5] = 0x01;
  875. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  876. &mbox_sts[0]);
  877. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  878. status = QLA_ERROR;
  879. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  880. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  881. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  882. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  883. }
  884. return status;
  885. }
  886. /**
  887. * qla4xxx_reset_lun - issues LUN Reset
  888. * @ha: Pointer to host adapter structure.
  889. * @ddb_entry: Pointer to device database entry
  890. * @lun: lun number
  891. *
  892. * This routine performs a LUN RESET on the specified target/lun.
  893. * The caller must ensure that the ddb_entry and lun_entry pointers
  894. * are valid before calling this routine.
  895. **/
  896. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  897. int lun)
  898. {
  899. uint32_t mbox_cmd[MBOX_REG_COUNT];
  900. uint32_t mbox_sts[MBOX_REG_COUNT];
  901. int status = QLA_SUCCESS;
  902. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  903. ddb_entry->fw_ddb_index, lun));
  904. /*
  905. * Send lun reset command to ISP, so that the ISP will return all
  906. * outstanding requests with RESET status
  907. */
  908. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  909. memset(&mbox_sts, 0, sizeof(mbox_sts));
  910. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  911. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  912. mbox_cmd[2] = lun << 8;
  913. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  914. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  915. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  916. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  917. status = QLA_ERROR;
  918. return status;
  919. }
  920. /**
  921. * qla4xxx_reset_target - issues target Reset
  922. * @ha: Pointer to host adapter structure.
  923. * @db_entry: Pointer to device database entry
  924. * @un_entry: Pointer to lun entry structure
  925. *
  926. * This routine performs a TARGET RESET on the specified target.
  927. * The caller must ensure that the ddb_entry pointers
  928. * are valid before calling this routine.
  929. **/
  930. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  931. struct ddb_entry *ddb_entry)
  932. {
  933. uint32_t mbox_cmd[MBOX_REG_COUNT];
  934. uint32_t mbox_sts[MBOX_REG_COUNT];
  935. int status = QLA_SUCCESS;
  936. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  937. ddb_entry->fw_ddb_index));
  938. /*
  939. * Send target reset command to ISP, so that the ISP will return all
  940. * outstanding requests with RESET status
  941. */
  942. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  943. memset(&mbox_sts, 0, sizeof(mbox_sts));
  944. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  945. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  946. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  947. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  948. &mbox_sts[0]);
  949. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  950. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  951. status = QLA_ERROR;
  952. return status;
  953. }
  954. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  955. uint32_t offset, uint32_t len)
  956. {
  957. uint32_t mbox_cmd[MBOX_REG_COUNT];
  958. uint32_t mbox_sts[MBOX_REG_COUNT];
  959. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  960. memset(&mbox_sts, 0, sizeof(mbox_sts));
  961. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  962. mbox_cmd[1] = LSDW(dma_addr);
  963. mbox_cmd[2] = MSDW(dma_addr);
  964. mbox_cmd[3] = offset;
  965. mbox_cmd[4] = len;
  966. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  967. QLA_SUCCESS) {
  968. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  969. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  970. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  971. return QLA_ERROR;
  972. }
  973. return QLA_SUCCESS;
  974. }
  975. /**
  976. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  977. * @ha: Pointer to host adapter structure.
  978. *
  979. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  980. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  981. * those mailboxes, if unused.
  982. **/
  983. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  984. {
  985. struct about_fw_info *about_fw = NULL;
  986. dma_addr_t about_fw_dma;
  987. uint32_t mbox_cmd[MBOX_REG_COUNT];
  988. uint32_t mbox_sts[MBOX_REG_COUNT];
  989. int status = QLA_ERROR;
  990. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  991. sizeof(struct about_fw_info),
  992. &about_fw_dma, GFP_KERNEL);
  993. if (!about_fw) {
  994. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  995. "for about_fw\n", __func__));
  996. return status;
  997. }
  998. memset(about_fw, 0, sizeof(struct about_fw_info));
  999. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1000. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1001. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  1002. mbox_cmd[2] = LSDW(about_fw_dma);
  1003. mbox_cmd[3] = MSDW(about_fw_dma);
  1004. mbox_cmd[4] = sizeof(struct about_fw_info);
  1005. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1006. &mbox_cmd[0], &mbox_sts[0]);
  1007. if (status != QLA_SUCCESS) {
  1008. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  1009. "failed w/ status %04X\n", __func__,
  1010. mbox_sts[0]));
  1011. goto exit_about_fw;
  1012. }
  1013. /* Save version information. */
  1014. ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
  1015. ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
  1016. ha->patch_number = le16_to_cpu(about_fw->fw_patch);
  1017. ha->build_number = le16_to_cpu(about_fw->fw_build);
  1018. ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  1019. ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  1020. ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
  1021. ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  1022. ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  1023. ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
  1024. status = QLA_SUCCESS;
  1025. exit_about_fw:
  1026. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  1027. about_fw, about_fw_dma);
  1028. return status;
  1029. }
  1030. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
  1031. dma_addr_t dma_addr)
  1032. {
  1033. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1034. uint32_t mbox_sts[MBOX_REG_COUNT];
  1035. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1036. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1037. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  1038. mbox_cmd[1] = options;
  1039. mbox_cmd[2] = LSDW(dma_addr);
  1040. mbox_cmd[3] = MSDW(dma_addr);
  1041. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  1042. QLA_SUCCESS) {
  1043. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  1044. ha->host_no, __func__, mbox_sts[0]));
  1045. return QLA_ERROR;
  1046. }
  1047. return QLA_SUCCESS;
  1048. }
  1049. int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
  1050. uint32_t *mbx_sts)
  1051. {
  1052. int status;
  1053. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1054. uint32_t mbox_sts[MBOX_REG_COUNT];
  1055. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1056. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1057. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  1058. mbox_cmd[1] = ddb_index;
  1059. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1060. &mbox_sts[0]);
  1061. if (status != QLA_SUCCESS) {
  1062. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1063. __func__, mbox_sts[0]));
  1064. }
  1065. *mbx_sts = mbox_sts[0];
  1066. return status;
  1067. }
  1068. int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
  1069. {
  1070. int status;
  1071. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1072. uint32_t mbox_sts[MBOX_REG_COUNT];
  1073. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1074. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1075. mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
  1076. mbox_cmd[1] = ddb_index;
  1077. status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
  1078. &mbox_sts[0]);
  1079. if (status != QLA_SUCCESS) {
  1080. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1081. __func__, mbox_sts[0]));
  1082. }
  1083. return status;
  1084. }
  1085. int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
  1086. uint32_t offset, uint32_t length, uint32_t options)
  1087. {
  1088. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1089. uint32_t mbox_sts[MBOX_REG_COUNT];
  1090. int status = QLA_SUCCESS;
  1091. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1092. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1093. mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
  1094. mbox_cmd[1] = LSDW(dma_addr);
  1095. mbox_cmd[2] = MSDW(dma_addr);
  1096. mbox_cmd[3] = offset;
  1097. mbox_cmd[4] = length;
  1098. mbox_cmd[5] = options;
  1099. status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
  1100. if (status != QLA_SUCCESS) {
  1101. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
  1102. "failed w/ status %04X, mbx1 %04X\n",
  1103. __func__, mbox_sts[0], mbox_sts[1]));
  1104. }
  1105. return status;
  1106. }
  1107. int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
  1108. struct dev_db_entry *fw_ddb_entry,
  1109. dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
  1110. {
  1111. uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
  1112. uint32_t dev_db_end_offset;
  1113. int status = QLA_ERROR;
  1114. memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
  1115. dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
  1116. dev_db_end_offset = FLASH_OFFSET_DB_END;
  1117. if (dev_db_start_offset > dev_db_end_offset) {
  1118. DEBUG2(ql4_printk(KERN_ERR, ha,
  1119. "%s:Invalid DDB index %d", __func__,
  1120. ddb_index));
  1121. goto exit_bootdb_failed;
  1122. }
  1123. if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
  1124. sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
  1125. ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
  1126. "failed\n", ha->host_no, __func__);
  1127. goto exit_bootdb_failed;
  1128. }
  1129. if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
  1130. status = QLA_SUCCESS;
  1131. exit_bootdb_failed:
  1132. return status;
  1133. }
  1134. int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
  1135. uint16_t idx)
  1136. {
  1137. int ret = 0;
  1138. int rval = QLA_ERROR;
  1139. uint32_t offset = 0, chap_size;
  1140. struct ql4_chap_table *chap_table;
  1141. dma_addr_t chap_dma;
  1142. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1143. if (chap_table == NULL) {
  1144. ret = -ENOMEM;
  1145. goto exit_get_chap;
  1146. }
  1147. chap_size = sizeof(struct ql4_chap_table);
  1148. memset(chap_table, 0, chap_size);
  1149. if (is_qla40XX(ha))
  1150. offset = FLASH_CHAP_OFFSET | (idx * chap_size);
  1151. else {
  1152. offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
  1153. /* flt_chap_size is CHAP table size for both ports
  1154. * so divide it by 2 to calculate the offset for second port
  1155. */
  1156. if (ha->port_num == 1)
  1157. offset += (ha->hw.flt_chap_size / 2);
  1158. offset += (idx * chap_size);
  1159. }
  1160. rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
  1161. if (rval != QLA_SUCCESS) {
  1162. ret = -EINVAL;
  1163. goto exit_get_chap;
  1164. }
  1165. DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
  1166. __le16_to_cpu(chap_table->cookie)));
  1167. if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
  1168. ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
  1169. goto exit_get_chap;
  1170. }
  1171. strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
  1172. strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
  1173. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1174. exit_get_chap:
  1175. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1176. return ret;
  1177. }
  1178. static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
  1179. char *password, uint16_t idx, int bidi)
  1180. {
  1181. int ret = 0;
  1182. int rval = QLA_ERROR;
  1183. uint32_t offset = 0;
  1184. struct ql4_chap_table *chap_table;
  1185. dma_addr_t chap_dma;
  1186. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1187. if (chap_table == NULL) {
  1188. ret = -ENOMEM;
  1189. goto exit_set_chap;
  1190. }
  1191. memset(chap_table, 0, sizeof(struct ql4_chap_table));
  1192. if (bidi)
  1193. chap_table->flags |= BIT_6; /* peer */
  1194. else
  1195. chap_table->flags |= BIT_7; /* local */
  1196. chap_table->secret_len = strlen(password);
  1197. strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
  1198. strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
  1199. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1200. offset = FLASH_CHAP_OFFSET | (idx * sizeof(struct ql4_chap_table));
  1201. rval = qla4xxx_set_flash(ha, chap_dma, offset,
  1202. sizeof(struct ql4_chap_table),
  1203. FLASH_OPT_RMW_COMMIT);
  1204. if (rval == QLA_SUCCESS && ha->chap_list) {
  1205. /* Update ha chap_list cache */
  1206. memcpy((struct ql4_chap_table *)ha->chap_list + idx,
  1207. chap_table, sizeof(struct ql4_chap_table));
  1208. }
  1209. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1210. if (rval != QLA_SUCCESS)
  1211. ret = -EINVAL;
  1212. exit_set_chap:
  1213. return ret;
  1214. }
  1215. /**
  1216. * qla4xxx_get_chap_index - Get chap index given username and secret
  1217. * @ha: pointer to adapter structure
  1218. * @username: CHAP username to be searched
  1219. * @password: CHAP password to be searched
  1220. * @bidi: Is this a BIDI CHAP
  1221. * @chap_index: CHAP index to be returned
  1222. *
  1223. * Match the username and password in the chap_list, return the index if a
  1224. * match is found. If a match is not found then add the entry in FLASH and
  1225. * return the index at which entry is written in the FLASH.
  1226. **/
  1227. static int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
  1228. char *password, int bidi, uint16_t *chap_index)
  1229. {
  1230. int i, rval;
  1231. int free_index = -1;
  1232. int found_index = 0;
  1233. int max_chap_entries = 0;
  1234. struct ql4_chap_table *chap_table;
  1235. if (is_qla8022(ha))
  1236. max_chap_entries = (ha->hw.flt_chap_size / 2) /
  1237. sizeof(struct ql4_chap_table);
  1238. else
  1239. max_chap_entries = MAX_CHAP_ENTRIES_40XX;
  1240. if (!ha->chap_list) {
  1241. ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
  1242. return QLA_ERROR;
  1243. }
  1244. mutex_lock(&ha->chap_sem);
  1245. for (i = 0; i < max_chap_entries; i++) {
  1246. chap_table = (struct ql4_chap_table *)ha->chap_list + i;
  1247. if (chap_table->cookie !=
  1248. __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
  1249. if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
  1250. free_index = i;
  1251. continue;
  1252. }
  1253. if (bidi) {
  1254. if (chap_table->flags & BIT_7)
  1255. continue;
  1256. } else {
  1257. if (chap_table->flags & BIT_6)
  1258. continue;
  1259. }
  1260. if (!strncmp(chap_table->secret, password,
  1261. MAX_CHAP_SECRET_LEN) &&
  1262. !strncmp(chap_table->name, username,
  1263. MAX_CHAP_NAME_LEN)) {
  1264. *chap_index = i;
  1265. found_index = 1;
  1266. break;
  1267. }
  1268. }
  1269. /* If chap entry is not present and a free index is available then
  1270. * write the entry in flash
  1271. */
  1272. if (!found_index && free_index != -1) {
  1273. rval = qla4xxx_set_chap(ha, username, password,
  1274. free_index, bidi);
  1275. if (!rval) {
  1276. *chap_index = free_index;
  1277. found_index = 1;
  1278. }
  1279. }
  1280. mutex_unlock(&ha->chap_sem);
  1281. if (found_index)
  1282. return QLA_SUCCESS;
  1283. return QLA_ERROR;
  1284. }
  1285. int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
  1286. uint16_t fw_ddb_index,
  1287. uint16_t connection_id,
  1288. uint16_t option)
  1289. {
  1290. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1291. uint32_t mbox_sts[MBOX_REG_COUNT];
  1292. int status = QLA_SUCCESS;
  1293. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1294. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1295. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  1296. mbox_cmd[1] = fw_ddb_index;
  1297. mbox_cmd[2] = connection_id;
  1298. mbox_cmd[3] = option;
  1299. status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
  1300. if (status != QLA_SUCCESS) {
  1301. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
  1302. "option %04x failed w/ status %04X %04X\n",
  1303. __func__, option, mbox_sts[0], mbox_sts[1]));
  1304. }
  1305. return status;
  1306. }
  1307. int qla4xxx_disable_acb(struct scsi_qla_host *ha)
  1308. {
  1309. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1310. uint32_t mbox_sts[MBOX_REG_COUNT];
  1311. int status = QLA_SUCCESS;
  1312. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1313. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1314. mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
  1315. status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
  1316. if (status != QLA_SUCCESS) {
  1317. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
  1318. "failed w/ status %04X %04X %04X", __func__,
  1319. mbox_sts[0], mbox_sts[1], mbox_sts[2]));
  1320. }
  1321. return status;
  1322. }
  1323. int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
  1324. uint32_t acb_type, uint32_t len)
  1325. {
  1326. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1327. uint32_t mbox_sts[MBOX_REG_COUNT];
  1328. int status = QLA_SUCCESS;
  1329. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1330. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1331. mbox_cmd[0] = MBOX_CMD_GET_ACB;
  1332. mbox_cmd[1] = acb_type;
  1333. mbox_cmd[2] = LSDW(acb_dma);
  1334. mbox_cmd[3] = MSDW(acb_dma);
  1335. mbox_cmd[4] = len;
  1336. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1337. if (status != QLA_SUCCESS) {
  1338. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
  1339. "failed w/ status %04X\n", __func__,
  1340. mbox_sts[0]));
  1341. }
  1342. return status;
  1343. }
  1344. int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1345. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1346. {
  1347. int status = QLA_SUCCESS;
  1348. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1349. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1350. mbox_cmd[0] = MBOX_CMD_SET_ACB;
  1351. mbox_cmd[1] = 0; /* Primary ACB */
  1352. mbox_cmd[2] = LSDW(acb_dma);
  1353. mbox_cmd[3] = MSDW(acb_dma);
  1354. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1355. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1356. if (status != QLA_SUCCESS) {
  1357. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
  1358. "failed w/ status %04X\n", __func__,
  1359. mbox_sts[0]));
  1360. }
  1361. return status;
  1362. }
  1363. int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
  1364. struct ddb_entry *ddb_entry,
  1365. struct iscsi_cls_conn *cls_conn,
  1366. uint32_t *mbx_sts)
  1367. {
  1368. struct dev_db_entry *fw_ddb_entry;
  1369. struct iscsi_conn *conn;
  1370. struct iscsi_session *sess;
  1371. struct qla_conn *qla_conn;
  1372. struct sockaddr *dst_addr;
  1373. dma_addr_t fw_ddb_entry_dma;
  1374. int status = QLA_SUCCESS;
  1375. int rval = 0;
  1376. struct sockaddr_in *addr;
  1377. struct sockaddr_in6 *addr6;
  1378. char *ip;
  1379. uint16_t iscsi_opts = 0;
  1380. uint32_t options = 0;
  1381. uint16_t idx;
  1382. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1383. &fw_ddb_entry_dma, GFP_KERNEL);
  1384. if (!fw_ddb_entry) {
  1385. DEBUG2(ql4_printk(KERN_ERR, ha,
  1386. "%s: Unable to allocate dma buffer.\n",
  1387. __func__));
  1388. rval = -ENOMEM;
  1389. goto exit_set_param_no_free;
  1390. }
  1391. conn = cls_conn->dd_data;
  1392. qla_conn = conn->dd_data;
  1393. sess = conn->session;
  1394. dst_addr = &qla_conn->qla_ep->dst_addr;
  1395. if (dst_addr->sa_family == AF_INET6)
  1396. options |= IPV6_DEFAULT_DDB_ENTRY;
  1397. status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
  1398. if (status == QLA_ERROR) {
  1399. rval = -EINVAL;
  1400. goto exit_set_param;
  1401. }
  1402. iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
  1403. memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
  1404. memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
  1405. if (sess->targetname != NULL) {
  1406. memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
  1407. min(strlen(sess->targetname),
  1408. sizeof(fw_ddb_entry->iscsi_name)));
  1409. }
  1410. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1411. memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
  1412. fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
  1413. if (dst_addr->sa_family == AF_INET) {
  1414. addr = (struct sockaddr_in *)dst_addr;
  1415. ip = (char *)&addr->sin_addr;
  1416. memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
  1417. fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
  1418. DEBUG2(ql4_printk(KERN_INFO, ha,
  1419. "%s: Destination Address [%pI4]: index [%d]\n",
  1420. __func__, fw_ddb_entry->ip_addr,
  1421. ddb_entry->fw_ddb_index));
  1422. } else if (dst_addr->sa_family == AF_INET6) {
  1423. addr6 = (struct sockaddr_in6 *)dst_addr;
  1424. ip = (char *)&addr6->sin6_addr;
  1425. memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
  1426. fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
  1427. fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
  1428. DEBUG2(ql4_printk(KERN_INFO, ha,
  1429. "%s: Destination Address [%pI6]: index [%d]\n",
  1430. __func__, fw_ddb_entry->ip_addr,
  1431. ddb_entry->fw_ddb_index));
  1432. } else {
  1433. ql4_printk(KERN_ERR, ha,
  1434. "%s: Failed to get IP Address\n",
  1435. __func__);
  1436. rval = -EINVAL;
  1437. goto exit_set_param;
  1438. }
  1439. /* CHAP */
  1440. if (sess->username != NULL && sess->password != NULL) {
  1441. if (strlen(sess->username) && strlen(sess->password)) {
  1442. iscsi_opts |= BIT_7;
  1443. rval = qla4xxx_get_chap_index(ha, sess->username,
  1444. sess->password,
  1445. LOCAL_CHAP, &idx);
  1446. if (rval)
  1447. goto exit_set_param;
  1448. fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
  1449. }
  1450. }
  1451. if (sess->username_in != NULL && sess->password_in != NULL) {
  1452. /* Check if BIDI CHAP */
  1453. if (strlen(sess->username_in) && strlen(sess->password_in)) {
  1454. iscsi_opts |= BIT_4;
  1455. rval = qla4xxx_get_chap_index(ha, sess->username_in,
  1456. sess->password_in,
  1457. BIDI_CHAP, &idx);
  1458. if (rval)
  1459. goto exit_set_param;
  1460. }
  1461. }
  1462. if (sess->initial_r2t_en)
  1463. iscsi_opts |= BIT_10;
  1464. if (sess->imm_data_en)
  1465. iscsi_opts |= BIT_11;
  1466. fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
  1467. if (conn->max_recv_dlength)
  1468. fw_ddb_entry->iscsi_max_rcv_data_seg_len =
  1469. __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
  1470. if (sess->max_r2t)
  1471. fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
  1472. if (sess->first_burst)
  1473. fw_ddb_entry->iscsi_first_burst_len =
  1474. __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
  1475. if (sess->max_burst)
  1476. fw_ddb_entry->iscsi_max_burst_len =
  1477. __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
  1478. if (sess->time2wait)
  1479. fw_ddb_entry->iscsi_def_time2wait =
  1480. cpu_to_le16(sess->time2wait);
  1481. if (sess->time2retain)
  1482. fw_ddb_entry->iscsi_def_time2retain =
  1483. cpu_to_le16(sess->time2retain);
  1484. status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
  1485. fw_ddb_entry_dma, mbx_sts);
  1486. if (status != QLA_SUCCESS)
  1487. rval = -EINVAL;
  1488. exit_set_param:
  1489. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1490. fw_ddb_entry, fw_ddb_entry_dma);
  1491. exit_set_param_no_free:
  1492. return rval;
  1493. }
  1494. int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
  1495. uint16_t stats_size, dma_addr_t stats_dma)
  1496. {
  1497. int status = QLA_SUCCESS;
  1498. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1499. uint32_t mbox_sts[MBOX_REG_COUNT];
  1500. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1501. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1502. mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
  1503. mbox_cmd[1] = fw_ddb_index;
  1504. mbox_cmd[2] = LSDW(stats_dma);
  1505. mbox_cmd[3] = MSDW(stats_dma);
  1506. mbox_cmd[4] = stats_size;
  1507. status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
  1508. if (status != QLA_SUCCESS) {
  1509. DEBUG2(ql4_printk(KERN_WARNING, ha,
  1510. "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
  1511. "failed w/ status %04X\n", __func__,
  1512. mbox_sts[0]));
  1513. }
  1514. return status;
  1515. }
  1516. int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
  1517. uint32_t ip_idx, uint32_t *sts)
  1518. {
  1519. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1520. uint32_t mbox_sts[MBOX_REG_COUNT];
  1521. int status = QLA_SUCCESS;
  1522. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1523. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1524. mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
  1525. mbox_cmd[1] = acb_idx;
  1526. mbox_cmd[2] = ip_idx;
  1527. status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
  1528. if (status != QLA_SUCCESS) {
  1529. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
  1530. "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
  1531. "status %04X\n", __func__, mbox_sts[0]));
  1532. }
  1533. memcpy(sts, mbox_sts, sizeof(mbox_sts));
  1534. return status;
  1535. }
  1536. int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1537. uint32_t offset, uint32_t size)
  1538. {
  1539. int status = QLA_SUCCESS;
  1540. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1541. uint32_t mbox_sts[MBOX_REG_COUNT];
  1542. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1543. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1544. mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
  1545. mbox_cmd[1] = LSDW(nvram_dma);
  1546. mbox_cmd[2] = MSDW(nvram_dma);
  1547. mbox_cmd[3] = offset;
  1548. mbox_cmd[4] = size;
  1549. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1550. &mbox_sts[0]);
  1551. if (status != QLA_SUCCESS) {
  1552. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1553. "status %04X\n", ha->host_no, __func__,
  1554. mbox_sts[0]));
  1555. }
  1556. return status;
  1557. }
  1558. int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1559. uint32_t offset, uint32_t size)
  1560. {
  1561. int status = QLA_SUCCESS;
  1562. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1563. uint32_t mbox_sts[MBOX_REG_COUNT];
  1564. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1565. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1566. mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
  1567. mbox_cmd[1] = LSDW(nvram_dma);
  1568. mbox_cmd[2] = MSDW(nvram_dma);
  1569. mbox_cmd[3] = offset;
  1570. mbox_cmd[4] = size;
  1571. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1572. &mbox_sts[0]);
  1573. if (status != QLA_SUCCESS) {
  1574. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1575. "status %04X\n", ha->host_no, __func__,
  1576. mbox_sts[0]));
  1577. }
  1578. return status;
  1579. }
  1580. int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
  1581. uint32_t region, uint32_t field0,
  1582. uint32_t field1)
  1583. {
  1584. int status = QLA_SUCCESS;
  1585. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1586. uint32_t mbox_sts[MBOX_REG_COUNT];
  1587. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1588. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1589. mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
  1590. mbox_cmd[3] = region;
  1591. mbox_cmd[4] = field0;
  1592. mbox_cmd[5] = field1;
  1593. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
  1594. &mbox_sts[0]);
  1595. if (status != QLA_SUCCESS) {
  1596. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1597. "status %04X\n", ha->host_no, __func__,
  1598. mbox_sts[0]));
  1599. }
  1600. return status;
  1601. }