s3c-ac97.c 13 KB

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  1. /* sound/soc/s3c24xx/s3c-ac97.c
  2. *
  3. * ALSA SoC Audio Layer - S3C AC97 Controller driver
  4. * Evolved from s3c2443-ac97.c
  5. *
  6. * Copyright (c) 2010 Samsung Electronics Co. Ltd
  7. * Author: Jaswinder Singh <jassi.brar@samsung.com>
  8. * Credits: Graeme Gregory, Sean Choi
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/io.h>
  17. #include <linux/delay.h>
  18. #include <linux/clk.h>
  19. #include <sound/soc.h>
  20. #include <plat/regs-ac97.h>
  21. #include <mach/dma.h>
  22. #include <plat/audio.h>
  23. #include "s3c-dma.h"
  24. #include "s3c-ac97.h"
  25. #define AC_CMD_ADDR(x) (x << 16)
  26. #define AC_CMD_DATA(x) (x & 0xffff)
  27. struct s3c_ac97_info {
  28. struct clk *ac97_clk;
  29. void __iomem *regs;
  30. struct mutex lock;
  31. struct completion done;
  32. };
  33. static struct s3c_ac97_info s3c_ac97;
  34. static struct s3c2410_dma_client s3c_dma_client_out = {
  35. .name = "AC97 PCMOut"
  36. };
  37. static struct s3c2410_dma_client s3c_dma_client_in = {
  38. .name = "AC97 PCMIn"
  39. };
  40. static struct s3c2410_dma_client s3c_dma_client_micin = {
  41. .name = "AC97 MicIn"
  42. };
  43. static struct s3c_dma_params s3c_ac97_pcm_out = {
  44. .client = &s3c_dma_client_out,
  45. .dma_size = 4,
  46. };
  47. static struct s3c_dma_params s3c_ac97_pcm_in = {
  48. .client = &s3c_dma_client_in,
  49. .dma_size = 4,
  50. };
  51. static struct s3c_dma_params s3c_ac97_mic_in = {
  52. .client = &s3c_dma_client_micin,
  53. .dma_size = 4,
  54. };
  55. static void s3c_ac97_activate(struct snd_ac97 *ac97)
  56. {
  57. u32 ac_glbctrl, stat;
  58. stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
  59. if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
  60. return; /* Return if already active */
  61. INIT_COMPLETION(s3c_ac97.done);
  62. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  63. ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
  64. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  65. msleep(1);
  66. ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
  67. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  68. msleep(1);
  69. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  70. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  71. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  72. if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
  73. printk(KERN_ERR "AC97: Unable to activate!");
  74. }
  75. static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
  76. unsigned short reg)
  77. {
  78. u32 ac_glbctrl, ac_codec_cmd;
  79. u32 stat, addr, data;
  80. mutex_lock(&s3c_ac97.lock);
  81. s3c_ac97_activate(ac97);
  82. INIT_COMPLETION(s3c_ac97.done);
  83. ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  84. ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
  85. writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  86. udelay(50);
  87. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  88. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  89. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  90. if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
  91. printk(KERN_ERR "AC97: Unable to read!");
  92. stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
  93. addr = (stat >> 16) & 0x7f;
  94. data = (stat & 0xffff);
  95. if (addr != reg)
  96. printk(KERN_ERR "s3c-ac97: req addr = %02x, rep addr = %02x\n", reg, addr);
  97. mutex_unlock(&s3c_ac97.lock);
  98. return (unsigned short)data;
  99. }
  100. static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  101. unsigned short val)
  102. {
  103. u32 ac_glbctrl, ac_codec_cmd;
  104. mutex_lock(&s3c_ac97.lock);
  105. s3c_ac97_activate(ac97);
  106. INIT_COMPLETION(s3c_ac97.done);
  107. ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  108. ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
  109. writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  110. udelay(50);
  111. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  112. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  113. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  114. if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
  115. printk(KERN_ERR "AC97: Unable to write!");
  116. ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  117. ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
  118. writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  119. mutex_unlock(&s3c_ac97.lock);
  120. }
  121. static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
  122. {
  123. writel(S3C_AC97_GLBCTRL_COLDRESET,
  124. s3c_ac97.regs + S3C_AC97_GLBCTRL);
  125. msleep(1);
  126. writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  127. msleep(1);
  128. }
  129. static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
  130. {
  131. u32 stat;
  132. stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
  133. if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
  134. return; /* Return if already active */
  135. writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  136. msleep(1);
  137. writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  138. msleep(1);
  139. s3c_ac97_activate(ac97);
  140. }
  141. static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
  142. {
  143. u32 ac_glbctrl, ac_glbstat;
  144. ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
  145. if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
  146. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  147. ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
  148. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  149. complete(&s3c_ac97.done);
  150. }
  151. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  152. ac_glbctrl |= (1<<30); /* Clear interrupt */
  153. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  154. return IRQ_HANDLED;
  155. }
  156. struct snd_ac97_bus_ops soc_ac97_ops = {
  157. .read = s3c_ac97_read,
  158. .write = s3c_ac97_write,
  159. .warm_reset = s3c_ac97_warm_reset,
  160. .reset = s3c_ac97_cold_reset,
  161. };
  162. EXPORT_SYMBOL_GPL(soc_ac97_ops);
  163. static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
  164. struct snd_pcm_hw_params *params,
  165. struct snd_soc_dai *dai)
  166. {
  167. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  168. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  169. struct s3c_dma_params *dma_data;
  170. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  171. dma_data = &s3c_ac97_pcm_out;
  172. else
  173. dma_data = &s3c_ac97_pcm_in;
  174. snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
  175. return 0;
  176. }
  177. static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
  178. struct snd_soc_dai *dai)
  179. {
  180. u32 ac_glbctrl;
  181. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  182. struct s3c_dma_params *dma_data =
  183. snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
  184. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  185. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  186. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
  187. else
  188. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
  189. switch (cmd) {
  190. case SNDRV_PCM_TRIGGER_START:
  191. case SNDRV_PCM_TRIGGER_RESUME:
  192. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  193. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  194. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
  195. else
  196. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
  197. break;
  198. case SNDRV_PCM_TRIGGER_STOP:
  199. case SNDRV_PCM_TRIGGER_SUSPEND:
  200. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  201. break;
  202. }
  203. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  204. s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
  205. return 0;
  206. }
  207. static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
  208. struct snd_pcm_hw_params *params,
  209. struct snd_soc_dai *dai)
  210. {
  211. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  212. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  213. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  214. return -ENODEV;
  215. else
  216. snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);
  217. return 0;
  218. }
  219. static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
  220. int cmd, struct snd_soc_dai *dai)
  221. {
  222. u32 ac_glbctrl;
  223. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  224. struct s3c_dma_params *dma_data =
  225. snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
  226. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  227. ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
  228. switch (cmd) {
  229. case SNDRV_PCM_TRIGGER_START:
  230. case SNDRV_PCM_TRIGGER_RESUME:
  231. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  232. ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
  233. break;
  234. case SNDRV_PCM_TRIGGER_STOP:
  235. case SNDRV_PCM_TRIGGER_SUSPEND:
  236. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  237. break;
  238. }
  239. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  240. s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
  241. return 0;
  242. }
  243. static struct snd_soc_dai_ops s3c_ac97_dai_ops = {
  244. .hw_params = s3c_ac97_hw_params,
  245. .trigger = s3c_ac97_trigger,
  246. };
  247. static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
  248. .hw_params = s3c_ac97_hw_mic_params,
  249. .trigger = s3c_ac97_mic_trigger,
  250. };
  251. struct snd_soc_dai s3c_ac97_dai[] = {
  252. [S3C_AC97_DAI_PCM] = {
  253. .name = "s3c-ac97",
  254. .id = S3C_AC97_DAI_PCM,
  255. .ac97_control = 1,
  256. .playback = {
  257. .stream_name = "AC97 Playback",
  258. .channels_min = 2,
  259. .channels_max = 2,
  260. .rates = SNDRV_PCM_RATE_8000_48000,
  261. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  262. .capture = {
  263. .stream_name = "AC97 Capture",
  264. .channels_min = 2,
  265. .channels_max = 2,
  266. .rates = SNDRV_PCM_RATE_8000_48000,
  267. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  268. .ops = &s3c_ac97_dai_ops,
  269. },
  270. [S3C_AC97_DAI_MIC] = {
  271. .name = "s3c-ac97-mic",
  272. .id = S3C_AC97_DAI_MIC,
  273. .ac97_control = 1,
  274. .capture = {
  275. .stream_name = "AC97 Mic Capture",
  276. .channels_min = 1,
  277. .channels_max = 1,
  278. .rates = SNDRV_PCM_RATE_8000_48000,
  279. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  280. .ops = &s3c_ac97_mic_dai_ops,
  281. },
  282. };
  283. EXPORT_SYMBOL_GPL(s3c_ac97_dai);
  284. static __devinit int s3c_ac97_probe(struct platform_device *pdev)
  285. {
  286. struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
  287. struct s3c_audio_pdata *ac97_pdata;
  288. int ret;
  289. ac97_pdata = pdev->dev.platform_data;
  290. if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
  291. dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
  292. return -EINVAL;
  293. }
  294. /* Check for availability of necessary resource */
  295. dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  296. if (!dmatx_res) {
  297. dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
  298. return -ENXIO;
  299. }
  300. dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  301. if (!dmarx_res) {
  302. dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
  303. return -ENXIO;
  304. }
  305. dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
  306. if (!dmamic_res) {
  307. dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
  308. return -ENXIO;
  309. }
  310. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  311. if (!mem_res) {
  312. dev_err(&pdev->dev, "Unable to get register resource\n");
  313. return -ENXIO;
  314. }
  315. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  316. if (!irq_res) {
  317. dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
  318. return -ENXIO;
  319. }
  320. if (!request_mem_region(mem_res->start,
  321. resource_size(mem_res), "s3c-ac97")) {
  322. dev_err(&pdev->dev, "Unable to request register region\n");
  323. return -EBUSY;
  324. }
  325. s3c_ac97_pcm_out.channel = dmatx_res->start;
  326. s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
  327. s3c_ac97_pcm_in.channel = dmarx_res->start;
  328. s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
  329. s3c_ac97_mic_in.channel = dmamic_res->start;
  330. s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
  331. init_completion(&s3c_ac97.done);
  332. mutex_init(&s3c_ac97.lock);
  333. s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
  334. if (s3c_ac97.regs == NULL) {
  335. dev_err(&pdev->dev, "Unable to ioremap register region\n");
  336. ret = -ENXIO;
  337. goto err1;
  338. }
  339. s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
  340. if (IS_ERR(s3c_ac97.ac97_clk)) {
  341. dev_err(&pdev->dev, "s3c-ac97 failed to get ac97_clock\n");
  342. ret = -ENODEV;
  343. goto err2;
  344. }
  345. clk_enable(s3c_ac97.ac97_clk);
  346. if (ac97_pdata->cfg_gpio(pdev)) {
  347. dev_err(&pdev->dev, "Unable to configure gpio\n");
  348. ret = -EINVAL;
  349. goto err3;
  350. }
  351. ret = request_irq(irq_res->start, s3c_ac97_irq,
  352. IRQF_DISABLED, "AC97", NULL);
  353. if (ret < 0) {
  354. printk(KERN_ERR "s3c-ac97: interrupt request failed.\n");
  355. goto err4;
  356. }
  357. s3c_ac97_dai[S3C_AC97_DAI_PCM].dev = &pdev->dev;
  358. s3c_ac97_dai[S3C_AC97_DAI_MIC].dev = &pdev->dev;
  359. ret = snd_soc_register_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
  360. if (ret)
  361. goto err5;
  362. return 0;
  363. err5:
  364. free_irq(irq_res->start, NULL);
  365. err4:
  366. err3:
  367. clk_disable(s3c_ac97.ac97_clk);
  368. clk_put(s3c_ac97.ac97_clk);
  369. err2:
  370. iounmap(s3c_ac97.regs);
  371. err1:
  372. release_mem_region(mem_res->start, resource_size(mem_res));
  373. return ret;
  374. }
  375. static __devexit int s3c_ac97_remove(struct platform_device *pdev)
  376. {
  377. struct resource *mem_res, *irq_res;
  378. snd_soc_unregister_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
  379. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  380. if (irq_res)
  381. free_irq(irq_res->start, NULL);
  382. clk_disable(s3c_ac97.ac97_clk);
  383. clk_put(s3c_ac97.ac97_clk);
  384. iounmap(s3c_ac97.regs);
  385. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  386. if (mem_res)
  387. release_mem_region(mem_res->start, resource_size(mem_res));
  388. return 0;
  389. }
  390. static struct platform_driver s3c_ac97_driver = {
  391. .probe = s3c_ac97_probe,
  392. .remove = s3c_ac97_remove,
  393. .driver = {
  394. .name = "s3c-ac97",
  395. .owner = THIS_MODULE,
  396. },
  397. };
  398. static int __init s3c_ac97_init(void)
  399. {
  400. return platform_driver_register(&s3c_ac97_driver);
  401. }
  402. module_init(s3c_ac97_init);
  403. static void __exit s3c_ac97_exit(void)
  404. {
  405. platform_driver_unregister(&s3c_ac97_driver);
  406. }
  407. module_exit(s3c_ac97_exit);
  408. MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
  409. MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
  410. MODULE_LICENSE("GPL");