fm801.c 46 KB

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  1. /*
  2. * The driver for the ForteMedia FM801 based soundcards
  3. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  4. *
  5. * Support FM only card by Andy Shevchenko <andy@smile.org.ua>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/pci.h>
  26. #include <linux/slab.h>
  27. #include <linux/moduleparam.h>
  28. #include <sound/core.h>
  29. #include <sound/pcm.h>
  30. #include <sound/tlv.h>
  31. #include <sound/ac97_codec.h>
  32. #include <sound/mpu401.h>
  33. #include <sound/opl3.h>
  34. #include <sound/initval.h>
  35. #include <asm/io.h>
  36. #ifdef CONFIG_SND_FM801_TEA575X_BOOL
  37. #include <sound/tea575x-tuner.h>
  38. #define TEA575X_RADIO 1
  39. #endif
  40. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  41. MODULE_DESCRIPTION("ForteMedia FM801");
  42. MODULE_LICENSE("GPL");
  43. MODULE_SUPPORTED_DEVICE("{{ForteMedia,FM801},"
  44. "{Genius,SoundMaker Live 5.1}}");
  45. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  46. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  47. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  48. /*
  49. * Enable TEA575x tuner
  50. * 1 = MediaForte 256-PCS
  51. * 2 = MediaForte 256-PCPR
  52. * 3 = MediaForte 64-PCR
  53. * 16 = setup tuner only (this is additional bit), i.e. SF64-PCR FM card
  54. * High 16-bits are video (radio) device number + 1
  55. */
  56. static int tea575x_tuner[SNDRV_CARDS];
  57. module_param_array(index, int, NULL, 0444);
  58. MODULE_PARM_DESC(index, "Index value for the FM801 soundcard.");
  59. module_param_array(id, charp, NULL, 0444);
  60. MODULE_PARM_DESC(id, "ID string for the FM801 soundcard.");
  61. module_param_array(enable, bool, NULL, 0444);
  62. MODULE_PARM_DESC(enable, "Enable FM801 soundcard.");
  63. module_param_array(tea575x_tuner, int, NULL, 0444);
  64. MODULE_PARM_DESC(tea575x_tuner, "TEA575x tuner access method (1 = SF256-PCS, 2=SF256-PCPR, 3=SF64-PCR, +16=tuner-only).");
  65. #define TUNER_ONLY (1<<4)
  66. #define TUNER_TYPE_MASK (~TUNER_ONLY & 0xFFFF)
  67. /*
  68. * Direct registers
  69. */
  70. #define FM801_REG(chip, reg) (chip->port + FM801_##reg)
  71. #define FM801_PCM_VOL 0x00 /* PCM Output Volume */
  72. #define FM801_FM_VOL 0x02 /* FM Output Volume */
  73. #define FM801_I2S_VOL 0x04 /* I2S Volume */
  74. #define FM801_REC_SRC 0x06 /* Record Source */
  75. #define FM801_PLY_CTRL 0x08 /* Playback Control */
  76. #define FM801_PLY_COUNT 0x0a /* Playback Count */
  77. #define FM801_PLY_BUF1 0x0c /* Playback Bufer I */
  78. #define FM801_PLY_BUF2 0x10 /* Playback Buffer II */
  79. #define FM801_CAP_CTRL 0x14 /* Capture Control */
  80. #define FM801_CAP_COUNT 0x16 /* Capture Count */
  81. #define FM801_CAP_BUF1 0x18 /* Capture Buffer I */
  82. #define FM801_CAP_BUF2 0x1c /* Capture Buffer II */
  83. #define FM801_CODEC_CTRL 0x22 /* Codec Control */
  84. #define FM801_I2S_MODE 0x24 /* I2S Mode Control */
  85. #define FM801_VOLUME 0x26 /* Volume Up/Down/Mute Status */
  86. #define FM801_I2C_CTRL 0x29 /* I2C Control */
  87. #define FM801_AC97_CMD 0x2a /* AC'97 Command */
  88. #define FM801_AC97_DATA 0x2c /* AC'97 Data */
  89. #define FM801_MPU401_DATA 0x30 /* MPU401 Data */
  90. #define FM801_MPU401_CMD 0x31 /* MPU401 Command */
  91. #define FM801_GPIO_CTRL 0x52 /* General Purpose I/O Control */
  92. #define FM801_GEN_CTRL 0x54 /* General Control */
  93. #define FM801_IRQ_MASK 0x56 /* Interrupt Mask */
  94. #define FM801_IRQ_STATUS 0x5a /* Interrupt Status */
  95. #define FM801_OPL3_BANK0 0x68 /* OPL3 Status Read / Bank 0 Write */
  96. #define FM801_OPL3_DATA0 0x69 /* OPL3 Data 0 Write */
  97. #define FM801_OPL3_BANK1 0x6a /* OPL3 Bank 1 Write */
  98. #define FM801_OPL3_DATA1 0x6b /* OPL3 Bank 1 Write */
  99. #define FM801_POWERDOWN 0x70 /* Blocks Power Down Control */
  100. /* codec access */
  101. #define FM801_AC97_READ (1<<7) /* read=1, write=0 */
  102. #define FM801_AC97_VALID (1<<8) /* port valid=1 */
  103. #define FM801_AC97_BUSY (1<<9) /* busy=1 */
  104. #define FM801_AC97_ADDR_SHIFT 10 /* codec id (2bit) */
  105. /* playback and record control register bits */
  106. #define FM801_BUF1_LAST (1<<1)
  107. #define FM801_BUF2_LAST (1<<2)
  108. #define FM801_START (1<<5)
  109. #define FM801_PAUSE (1<<6)
  110. #define FM801_IMMED_STOP (1<<7)
  111. #define FM801_RATE_SHIFT 8
  112. #define FM801_RATE_MASK (15 << FM801_RATE_SHIFT)
  113. #define FM801_CHANNELS_4 (1<<12) /* playback only */
  114. #define FM801_CHANNELS_6 (2<<12) /* playback only */
  115. #define FM801_CHANNELS_6MS (3<<12) /* playback only */
  116. #define FM801_CHANNELS_MASK (3<<12)
  117. #define FM801_16BIT (1<<14)
  118. #define FM801_STEREO (1<<15)
  119. /* IRQ status bits */
  120. #define FM801_IRQ_PLAYBACK (1<<8)
  121. #define FM801_IRQ_CAPTURE (1<<9)
  122. #define FM801_IRQ_VOLUME (1<<14)
  123. #define FM801_IRQ_MPU (1<<15)
  124. /* GPIO control register */
  125. #define FM801_GPIO_GP0 (1<<0) /* read/write */
  126. #define FM801_GPIO_GP1 (1<<1)
  127. #define FM801_GPIO_GP2 (1<<2)
  128. #define FM801_GPIO_GP3 (1<<3)
  129. #define FM801_GPIO_GP(x) (1<<(0+(x)))
  130. #define FM801_GPIO_GD0 (1<<8) /* directions: 1 = input, 0 = output*/
  131. #define FM801_GPIO_GD1 (1<<9)
  132. #define FM801_GPIO_GD2 (1<<10)
  133. #define FM801_GPIO_GD3 (1<<11)
  134. #define FM801_GPIO_GD(x) (1<<(8+(x)))
  135. #define FM801_GPIO_GS0 (1<<12) /* function select: */
  136. #define FM801_GPIO_GS1 (1<<13) /* 1 = GPIO */
  137. #define FM801_GPIO_GS2 (1<<14) /* 0 = other (S/PDIF, VOL) */
  138. #define FM801_GPIO_GS3 (1<<15)
  139. #define FM801_GPIO_GS(x) (1<<(12+(x)))
  140. /*
  141. */
  142. struct fm801 {
  143. int irq;
  144. unsigned long port; /* I/O port number */
  145. unsigned int multichannel: 1, /* multichannel support */
  146. secondary: 1; /* secondary codec */
  147. unsigned char secondary_addr; /* address of the secondary codec */
  148. unsigned int tea575x_tuner; /* tuner access method & flags */
  149. unsigned short ply_ctrl; /* playback control */
  150. unsigned short cap_ctrl; /* capture control */
  151. unsigned long ply_buffer;
  152. unsigned int ply_buf;
  153. unsigned int ply_count;
  154. unsigned int ply_size;
  155. unsigned int ply_pos;
  156. unsigned long cap_buffer;
  157. unsigned int cap_buf;
  158. unsigned int cap_count;
  159. unsigned int cap_size;
  160. unsigned int cap_pos;
  161. struct snd_ac97_bus *ac97_bus;
  162. struct snd_ac97 *ac97;
  163. struct snd_ac97 *ac97_sec;
  164. struct pci_dev *pci;
  165. struct snd_card *card;
  166. struct snd_pcm *pcm;
  167. struct snd_rawmidi *rmidi;
  168. struct snd_pcm_substream *playback_substream;
  169. struct snd_pcm_substream *capture_substream;
  170. unsigned int p_dma_size;
  171. unsigned int c_dma_size;
  172. spinlock_t reg_lock;
  173. struct snd_info_entry *proc_entry;
  174. #ifdef TEA575X_RADIO
  175. struct snd_tea575x tea;
  176. #endif
  177. #ifdef CONFIG_PM
  178. u16 saved_regs[0x20];
  179. #endif
  180. };
  181. static DEFINE_PCI_DEVICE_TABLE(snd_fm801_ids) = {
  182. { 0x1319, 0x0801, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* FM801 */
  183. { 0x5213, 0x0510, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* Gallant Odyssey Sound 4 */
  184. { 0, }
  185. };
  186. MODULE_DEVICE_TABLE(pci, snd_fm801_ids);
  187. /*
  188. * common I/O routines
  189. */
  190. static int snd_fm801_update_bits(struct fm801 *chip, unsigned short reg,
  191. unsigned short mask, unsigned short value)
  192. {
  193. int change;
  194. unsigned long flags;
  195. unsigned short old, new;
  196. spin_lock_irqsave(&chip->reg_lock, flags);
  197. old = inw(chip->port + reg);
  198. new = (old & ~mask) | value;
  199. change = old != new;
  200. if (change)
  201. outw(new, chip->port + reg);
  202. spin_unlock_irqrestore(&chip->reg_lock, flags);
  203. return change;
  204. }
  205. static void snd_fm801_codec_write(struct snd_ac97 *ac97,
  206. unsigned short reg,
  207. unsigned short val)
  208. {
  209. struct fm801 *chip = ac97->private_data;
  210. int idx;
  211. /*
  212. * Wait until the codec interface is not ready..
  213. */
  214. for (idx = 0; idx < 100; idx++) {
  215. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  216. goto ok1;
  217. udelay(10);
  218. }
  219. snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
  220. return;
  221. ok1:
  222. /* write data and address */
  223. outw(val, FM801_REG(chip, AC97_DATA));
  224. outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT), FM801_REG(chip, AC97_CMD));
  225. /*
  226. * Wait until the write command is not completed..
  227. */
  228. for (idx = 0; idx < 1000; idx++) {
  229. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  230. return;
  231. udelay(10);
  232. }
  233. snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
  234. }
  235. static unsigned short snd_fm801_codec_read(struct snd_ac97 *ac97, unsigned short reg)
  236. {
  237. struct fm801 *chip = ac97->private_data;
  238. int idx;
  239. /*
  240. * Wait until the codec interface is not ready..
  241. */
  242. for (idx = 0; idx < 100; idx++) {
  243. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  244. goto ok1;
  245. udelay(10);
  246. }
  247. snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
  248. return 0;
  249. ok1:
  250. /* read command */
  251. outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT) | FM801_AC97_READ,
  252. FM801_REG(chip, AC97_CMD));
  253. for (idx = 0; idx < 100; idx++) {
  254. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  255. goto ok2;
  256. udelay(10);
  257. }
  258. snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
  259. return 0;
  260. ok2:
  261. for (idx = 0; idx < 1000; idx++) {
  262. if (inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_VALID)
  263. goto ok3;
  264. udelay(10);
  265. }
  266. snd_printk(KERN_ERR "AC'97 interface #%d is not valid (2)\n", ac97->num);
  267. return 0;
  268. ok3:
  269. return inw(FM801_REG(chip, AC97_DATA));
  270. }
  271. static unsigned int rates[] = {
  272. 5500, 8000, 9600, 11025,
  273. 16000, 19200, 22050, 32000,
  274. 38400, 44100, 48000
  275. };
  276. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  277. .count = ARRAY_SIZE(rates),
  278. .list = rates,
  279. .mask = 0,
  280. };
  281. static unsigned int channels[] = {
  282. 2, 4, 6
  283. };
  284. static struct snd_pcm_hw_constraint_list hw_constraints_channels = {
  285. .count = ARRAY_SIZE(channels),
  286. .list = channels,
  287. .mask = 0,
  288. };
  289. /*
  290. * Sample rate routines
  291. */
  292. static unsigned short snd_fm801_rate_bits(unsigned int rate)
  293. {
  294. unsigned int idx;
  295. for (idx = 0; idx < ARRAY_SIZE(rates); idx++)
  296. if (rates[idx] == rate)
  297. return idx;
  298. snd_BUG();
  299. return ARRAY_SIZE(rates) - 1;
  300. }
  301. /*
  302. * PCM part
  303. */
  304. static int snd_fm801_playback_trigger(struct snd_pcm_substream *substream,
  305. int cmd)
  306. {
  307. struct fm801 *chip = snd_pcm_substream_chip(substream);
  308. spin_lock(&chip->reg_lock);
  309. switch (cmd) {
  310. case SNDRV_PCM_TRIGGER_START:
  311. chip->ply_ctrl &= ~(FM801_BUF1_LAST |
  312. FM801_BUF2_LAST |
  313. FM801_PAUSE);
  314. chip->ply_ctrl |= FM801_START |
  315. FM801_IMMED_STOP;
  316. break;
  317. case SNDRV_PCM_TRIGGER_STOP:
  318. chip->ply_ctrl &= ~(FM801_START | FM801_PAUSE);
  319. break;
  320. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  321. case SNDRV_PCM_TRIGGER_SUSPEND:
  322. chip->ply_ctrl |= FM801_PAUSE;
  323. break;
  324. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  325. case SNDRV_PCM_TRIGGER_RESUME:
  326. chip->ply_ctrl &= ~FM801_PAUSE;
  327. break;
  328. default:
  329. spin_unlock(&chip->reg_lock);
  330. snd_BUG();
  331. return -EINVAL;
  332. }
  333. outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
  334. spin_unlock(&chip->reg_lock);
  335. return 0;
  336. }
  337. static int snd_fm801_capture_trigger(struct snd_pcm_substream *substream,
  338. int cmd)
  339. {
  340. struct fm801 *chip = snd_pcm_substream_chip(substream);
  341. spin_lock(&chip->reg_lock);
  342. switch (cmd) {
  343. case SNDRV_PCM_TRIGGER_START:
  344. chip->cap_ctrl &= ~(FM801_BUF1_LAST |
  345. FM801_BUF2_LAST |
  346. FM801_PAUSE);
  347. chip->cap_ctrl |= FM801_START |
  348. FM801_IMMED_STOP;
  349. break;
  350. case SNDRV_PCM_TRIGGER_STOP:
  351. chip->cap_ctrl &= ~(FM801_START | FM801_PAUSE);
  352. break;
  353. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  354. case SNDRV_PCM_TRIGGER_SUSPEND:
  355. chip->cap_ctrl |= FM801_PAUSE;
  356. break;
  357. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  358. case SNDRV_PCM_TRIGGER_RESUME:
  359. chip->cap_ctrl &= ~FM801_PAUSE;
  360. break;
  361. default:
  362. spin_unlock(&chip->reg_lock);
  363. snd_BUG();
  364. return -EINVAL;
  365. }
  366. outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
  367. spin_unlock(&chip->reg_lock);
  368. return 0;
  369. }
  370. static int snd_fm801_hw_params(struct snd_pcm_substream *substream,
  371. struct snd_pcm_hw_params *hw_params)
  372. {
  373. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  374. }
  375. static int snd_fm801_hw_free(struct snd_pcm_substream *substream)
  376. {
  377. return snd_pcm_lib_free_pages(substream);
  378. }
  379. static int snd_fm801_playback_prepare(struct snd_pcm_substream *substream)
  380. {
  381. struct fm801 *chip = snd_pcm_substream_chip(substream);
  382. struct snd_pcm_runtime *runtime = substream->runtime;
  383. chip->ply_size = snd_pcm_lib_buffer_bytes(substream);
  384. chip->ply_count = snd_pcm_lib_period_bytes(substream);
  385. spin_lock_irq(&chip->reg_lock);
  386. chip->ply_ctrl &= ~(FM801_START | FM801_16BIT |
  387. FM801_STEREO | FM801_RATE_MASK |
  388. FM801_CHANNELS_MASK);
  389. if (snd_pcm_format_width(runtime->format) == 16)
  390. chip->ply_ctrl |= FM801_16BIT;
  391. if (runtime->channels > 1) {
  392. chip->ply_ctrl |= FM801_STEREO;
  393. if (runtime->channels == 4)
  394. chip->ply_ctrl |= FM801_CHANNELS_4;
  395. else if (runtime->channels == 6)
  396. chip->ply_ctrl |= FM801_CHANNELS_6;
  397. }
  398. chip->ply_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
  399. chip->ply_buf = 0;
  400. outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
  401. outw(chip->ply_count - 1, FM801_REG(chip, PLY_COUNT));
  402. chip->ply_buffer = runtime->dma_addr;
  403. chip->ply_pos = 0;
  404. outl(chip->ply_buffer, FM801_REG(chip, PLY_BUF1));
  405. outl(chip->ply_buffer + (chip->ply_count % chip->ply_size), FM801_REG(chip, PLY_BUF2));
  406. spin_unlock_irq(&chip->reg_lock);
  407. return 0;
  408. }
  409. static int snd_fm801_capture_prepare(struct snd_pcm_substream *substream)
  410. {
  411. struct fm801 *chip = snd_pcm_substream_chip(substream);
  412. struct snd_pcm_runtime *runtime = substream->runtime;
  413. chip->cap_size = snd_pcm_lib_buffer_bytes(substream);
  414. chip->cap_count = snd_pcm_lib_period_bytes(substream);
  415. spin_lock_irq(&chip->reg_lock);
  416. chip->cap_ctrl &= ~(FM801_START | FM801_16BIT |
  417. FM801_STEREO | FM801_RATE_MASK);
  418. if (snd_pcm_format_width(runtime->format) == 16)
  419. chip->cap_ctrl |= FM801_16BIT;
  420. if (runtime->channels > 1)
  421. chip->cap_ctrl |= FM801_STEREO;
  422. chip->cap_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
  423. chip->cap_buf = 0;
  424. outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
  425. outw(chip->cap_count - 1, FM801_REG(chip, CAP_COUNT));
  426. chip->cap_buffer = runtime->dma_addr;
  427. chip->cap_pos = 0;
  428. outl(chip->cap_buffer, FM801_REG(chip, CAP_BUF1));
  429. outl(chip->cap_buffer + (chip->cap_count % chip->cap_size), FM801_REG(chip, CAP_BUF2));
  430. spin_unlock_irq(&chip->reg_lock);
  431. return 0;
  432. }
  433. static snd_pcm_uframes_t snd_fm801_playback_pointer(struct snd_pcm_substream *substream)
  434. {
  435. struct fm801 *chip = snd_pcm_substream_chip(substream);
  436. size_t ptr;
  437. if (!(chip->ply_ctrl & FM801_START))
  438. return 0;
  439. spin_lock(&chip->reg_lock);
  440. ptr = chip->ply_pos + (chip->ply_count - 1) - inw(FM801_REG(chip, PLY_COUNT));
  441. if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_PLAYBACK) {
  442. ptr += chip->ply_count;
  443. ptr %= chip->ply_size;
  444. }
  445. spin_unlock(&chip->reg_lock);
  446. return bytes_to_frames(substream->runtime, ptr);
  447. }
  448. static snd_pcm_uframes_t snd_fm801_capture_pointer(struct snd_pcm_substream *substream)
  449. {
  450. struct fm801 *chip = snd_pcm_substream_chip(substream);
  451. size_t ptr;
  452. if (!(chip->cap_ctrl & FM801_START))
  453. return 0;
  454. spin_lock(&chip->reg_lock);
  455. ptr = chip->cap_pos + (chip->cap_count - 1) - inw(FM801_REG(chip, CAP_COUNT));
  456. if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_CAPTURE) {
  457. ptr += chip->cap_count;
  458. ptr %= chip->cap_size;
  459. }
  460. spin_unlock(&chip->reg_lock);
  461. return bytes_to_frames(substream->runtime, ptr);
  462. }
  463. static irqreturn_t snd_fm801_interrupt(int irq, void *dev_id)
  464. {
  465. struct fm801 *chip = dev_id;
  466. unsigned short status;
  467. unsigned int tmp;
  468. status = inw(FM801_REG(chip, IRQ_STATUS));
  469. status &= FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU|FM801_IRQ_VOLUME;
  470. if (! status)
  471. return IRQ_NONE;
  472. /* ack first */
  473. outw(status, FM801_REG(chip, IRQ_STATUS));
  474. if (chip->pcm && (status & FM801_IRQ_PLAYBACK) && chip->playback_substream) {
  475. spin_lock(&chip->reg_lock);
  476. chip->ply_buf++;
  477. chip->ply_pos += chip->ply_count;
  478. chip->ply_pos %= chip->ply_size;
  479. tmp = chip->ply_pos + chip->ply_count;
  480. tmp %= chip->ply_size;
  481. outl(chip->ply_buffer + tmp,
  482. (chip->ply_buf & 1) ?
  483. FM801_REG(chip, PLY_BUF1) :
  484. FM801_REG(chip, PLY_BUF2));
  485. spin_unlock(&chip->reg_lock);
  486. snd_pcm_period_elapsed(chip->playback_substream);
  487. }
  488. if (chip->pcm && (status & FM801_IRQ_CAPTURE) && chip->capture_substream) {
  489. spin_lock(&chip->reg_lock);
  490. chip->cap_buf++;
  491. chip->cap_pos += chip->cap_count;
  492. chip->cap_pos %= chip->cap_size;
  493. tmp = chip->cap_pos + chip->cap_count;
  494. tmp %= chip->cap_size;
  495. outl(chip->cap_buffer + tmp,
  496. (chip->cap_buf & 1) ?
  497. FM801_REG(chip, CAP_BUF1) :
  498. FM801_REG(chip, CAP_BUF2));
  499. spin_unlock(&chip->reg_lock);
  500. snd_pcm_period_elapsed(chip->capture_substream);
  501. }
  502. if (chip->rmidi && (status & FM801_IRQ_MPU))
  503. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  504. if (status & FM801_IRQ_VOLUME)
  505. ;/* TODO */
  506. return IRQ_HANDLED;
  507. }
  508. static struct snd_pcm_hardware snd_fm801_playback =
  509. {
  510. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  511. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  512. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
  513. SNDRV_PCM_INFO_MMAP_VALID),
  514. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  515. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  516. .rate_min = 5500,
  517. .rate_max = 48000,
  518. .channels_min = 1,
  519. .channels_max = 2,
  520. .buffer_bytes_max = (128*1024),
  521. .period_bytes_min = 64,
  522. .period_bytes_max = (128*1024),
  523. .periods_min = 1,
  524. .periods_max = 1024,
  525. .fifo_size = 0,
  526. };
  527. static struct snd_pcm_hardware snd_fm801_capture =
  528. {
  529. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  530. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  531. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
  532. SNDRV_PCM_INFO_MMAP_VALID),
  533. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  534. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  535. .rate_min = 5500,
  536. .rate_max = 48000,
  537. .channels_min = 1,
  538. .channels_max = 2,
  539. .buffer_bytes_max = (128*1024),
  540. .period_bytes_min = 64,
  541. .period_bytes_max = (128*1024),
  542. .periods_min = 1,
  543. .periods_max = 1024,
  544. .fifo_size = 0,
  545. };
  546. static int snd_fm801_playback_open(struct snd_pcm_substream *substream)
  547. {
  548. struct fm801 *chip = snd_pcm_substream_chip(substream);
  549. struct snd_pcm_runtime *runtime = substream->runtime;
  550. int err;
  551. chip->playback_substream = substream;
  552. runtime->hw = snd_fm801_playback;
  553. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  554. &hw_constraints_rates);
  555. if (chip->multichannel) {
  556. runtime->hw.channels_max = 6;
  557. snd_pcm_hw_constraint_list(runtime, 0,
  558. SNDRV_PCM_HW_PARAM_CHANNELS,
  559. &hw_constraints_channels);
  560. }
  561. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  562. return err;
  563. return 0;
  564. }
  565. static int snd_fm801_capture_open(struct snd_pcm_substream *substream)
  566. {
  567. struct fm801 *chip = snd_pcm_substream_chip(substream);
  568. struct snd_pcm_runtime *runtime = substream->runtime;
  569. int err;
  570. chip->capture_substream = substream;
  571. runtime->hw = snd_fm801_capture;
  572. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  573. &hw_constraints_rates);
  574. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  575. return err;
  576. return 0;
  577. }
  578. static int snd_fm801_playback_close(struct snd_pcm_substream *substream)
  579. {
  580. struct fm801 *chip = snd_pcm_substream_chip(substream);
  581. chip->playback_substream = NULL;
  582. return 0;
  583. }
  584. static int snd_fm801_capture_close(struct snd_pcm_substream *substream)
  585. {
  586. struct fm801 *chip = snd_pcm_substream_chip(substream);
  587. chip->capture_substream = NULL;
  588. return 0;
  589. }
  590. static struct snd_pcm_ops snd_fm801_playback_ops = {
  591. .open = snd_fm801_playback_open,
  592. .close = snd_fm801_playback_close,
  593. .ioctl = snd_pcm_lib_ioctl,
  594. .hw_params = snd_fm801_hw_params,
  595. .hw_free = snd_fm801_hw_free,
  596. .prepare = snd_fm801_playback_prepare,
  597. .trigger = snd_fm801_playback_trigger,
  598. .pointer = snd_fm801_playback_pointer,
  599. };
  600. static struct snd_pcm_ops snd_fm801_capture_ops = {
  601. .open = snd_fm801_capture_open,
  602. .close = snd_fm801_capture_close,
  603. .ioctl = snd_pcm_lib_ioctl,
  604. .hw_params = snd_fm801_hw_params,
  605. .hw_free = snd_fm801_hw_free,
  606. .prepare = snd_fm801_capture_prepare,
  607. .trigger = snd_fm801_capture_trigger,
  608. .pointer = snd_fm801_capture_pointer,
  609. };
  610. static int __devinit snd_fm801_pcm(struct fm801 *chip, int device, struct snd_pcm ** rpcm)
  611. {
  612. struct snd_pcm *pcm;
  613. int err;
  614. if (rpcm)
  615. *rpcm = NULL;
  616. if ((err = snd_pcm_new(chip->card, "FM801", device, 1, 1, &pcm)) < 0)
  617. return err;
  618. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_fm801_playback_ops);
  619. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_fm801_capture_ops);
  620. pcm->private_data = chip;
  621. pcm->info_flags = 0;
  622. strcpy(pcm->name, "FM801");
  623. chip->pcm = pcm;
  624. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  625. snd_dma_pci_data(chip->pci),
  626. chip->multichannel ? 128*1024 : 64*1024, 128*1024);
  627. if (rpcm)
  628. *rpcm = pcm;
  629. return 0;
  630. }
  631. /*
  632. * TEA5757 radio
  633. */
  634. #ifdef TEA575X_RADIO
  635. /* 256PCS GPIO numbers */
  636. #define TEA_256PCS_DATA 1
  637. #define TEA_256PCS_WRITE_ENABLE 2 /* inverted */
  638. #define TEA_256PCS_BUS_CLOCK 3
  639. static void snd_fm801_tea575x_256pcs_write(struct snd_tea575x *tea, unsigned int val)
  640. {
  641. struct fm801 *chip = tea->private_data;
  642. unsigned short reg;
  643. int i = 25;
  644. spin_lock_irq(&chip->reg_lock);
  645. reg = inw(FM801_REG(chip, GPIO_CTRL));
  646. /* use GPIO lines and set write enable bit */
  647. reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
  648. FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
  649. FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK);
  650. /* all of lines are in the write direction */
  651. /* clear data and clock lines */
  652. reg &= ~(FM801_GPIO_GD(TEA_256PCS_DATA) |
  653. FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
  654. FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
  655. FM801_GPIO_GP(TEA_256PCS_DATA) |
  656. FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK) |
  657. FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE));
  658. outw(reg, FM801_REG(chip, GPIO_CTRL));
  659. udelay(1);
  660. while (i--) {
  661. if (val & (1 << i))
  662. reg |= FM801_GPIO_GP(TEA_256PCS_DATA);
  663. else
  664. reg &= ~FM801_GPIO_GP(TEA_256PCS_DATA);
  665. outw(reg, FM801_REG(chip, GPIO_CTRL));
  666. udelay(1);
  667. reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  668. outw(reg, FM801_REG(chip, GPIO_CTRL));
  669. reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  670. outw(reg, FM801_REG(chip, GPIO_CTRL));
  671. udelay(1);
  672. }
  673. /* and reset the write enable bit */
  674. reg |= FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE) |
  675. FM801_GPIO_GP(TEA_256PCS_DATA);
  676. outw(reg, FM801_REG(chip, GPIO_CTRL));
  677. spin_unlock_irq(&chip->reg_lock);
  678. }
  679. static unsigned int snd_fm801_tea575x_256pcs_read(struct snd_tea575x *tea)
  680. {
  681. struct fm801 *chip = tea->private_data;
  682. unsigned short reg;
  683. unsigned int val = 0;
  684. int i;
  685. spin_lock_irq(&chip->reg_lock);
  686. reg = inw(FM801_REG(chip, GPIO_CTRL));
  687. /* use GPIO lines, set data direction to input */
  688. reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
  689. FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
  690. FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK) |
  691. FM801_GPIO_GD(TEA_256PCS_DATA) |
  692. FM801_GPIO_GP(TEA_256PCS_DATA) |
  693. FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE);
  694. /* all of lines are in the write direction, except data */
  695. /* clear data, write enable and clock lines */
  696. reg &= ~(FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
  697. FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
  698. FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK));
  699. for (i = 0; i < 24; i++) {
  700. reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  701. outw(reg, FM801_REG(chip, GPIO_CTRL));
  702. udelay(1);
  703. reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  704. outw(reg, FM801_REG(chip, GPIO_CTRL));
  705. udelay(1);
  706. val <<= 1;
  707. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCS_DATA))
  708. val |= 1;
  709. }
  710. spin_unlock_irq(&chip->reg_lock);
  711. return val;
  712. }
  713. /* 256PCPR GPIO numbers */
  714. #define TEA_256PCPR_BUS_CLOCK 0
  715. #define TEA_256PCPR_DATA 1
  716. #define TEA_256PCPR_WRITE_ENABLE 2 /* inverted */
  717. static void snd_fm801_tea575x_256pcpr_write(struct snd_tea575x *tea, unsigned int val)
  718. {
  719. struct fm801 *chip = tea->private_data;
  720. unsigned short reg;
  721. int i = 25;
  722. spin_lock_irq(&chip->reg_lock);
  723. reg = inw(FM801_REG(chip, GPIO_CTRL));
  724. /* use GPIO lines and set write enable bit */
  725. reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
  726. FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
  727. FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK);
  728. /* all of lines are in the write direction */
  729. /* clear data and clock lines */
  730. reg &= ~(FM801_GPIO_GD(TEA_256PCPR_DATA) |
  731. FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
  732. FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
  733. FM801_GPIO_GP(TEA_256PCPR_DATA) |
  734. FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK) |
  735. FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE));
  736. outw(reg, FM801_REG(chip, GPIO_CTRL));
  737. udelay(1);
  738. while (i--) {
  739. if (val & (1 << i))
  740. reg |= FM801_GPIO_GP(TEA_256PCPR_DATA);
  741. else
  742. reg &= ~FM801_GPIO_GP(TEA_256PCPR_DATA);
  743. outw(reg, FM801_REG(chip, GPIO_CTRL));
  744. udelay(1);
  745. reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  746. outw(reg, FM801_REG(chip, GPIO_CTRL));
  747. reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  748. outw(reg, FM801_REG(chip, GPIO_CTRL));
  749. udelay(1);
  750. }
  751. /* and reset the write enable bit */
  752. reg |= FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE) |
  753. FM801_GPIO_GP(TEA_256PCPR_DATA);
  754. outw(reg, FM801_REG(chip, GPIO_CTRL));
  755. spin_unlock_irq(&chip->reg_lock);
  756. }
  757. static unsigned int snd_fm801_tea575x_256pcpr_read(struct snd_tea575x *tea)
  758. {
  759. struct fm801 *chip = tea->private_data;
  760. unsigned short reg;
  761. unsigned int val = 0;
  762. int i;
  763. spin_lock_irq(&chip->reg_lock);
  764. reg = inw(FM801_REG(chip, GPIO_CTRL));
  765. /* use GPIO lines, set data direction to input */
  766. reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
  767. FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
  768. FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK) |
  769. FM801_GPIO_GD(TEA_256PCPR_DATA) |
  770. FM801_GPIO_GP(TEA_256PCPR_DATA) |
  771. FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE);
  772. /* all of lines are in the write direction, except data */
  773. /* clear data, write enable and clock lines */
  774. reg &= ~(FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
  775. FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
  776. FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK));
  777. for (i = 0; i < 24; i++) {
  778. reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  779. outw(reg, FM801_REG(chip, GPIO_CTRL));
  780. udelay(1);
  781. reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  782. outw(reg, FM801_REG(chip, GPIO_CTRL));
  783. udelay(1);
  784. val <<= 1;
  785. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCPR_DATA))
  786. val |= 1;
  787. }
  788. spin_unlock_irq(&chip->reg_lock);
  789. return val;
  790. }
  791. /* 64PCR GPIO numbers */
  792. #define TEA_64PCR_BUS_CLOCK 0
  793. #define TEA_64PCR_WRITE_ENABLE 1 /* inverted */
  794. #define TEA_64PCR_DATA 2
  795. static void snd_fm801_tea575x_64pcr_write(struct snd_tea575x *tea, unsigned int val)
  796. {
  797. struct fm801 *chip = tea->private_data;
  798. unsigned short reg;
  799. int i = 25;
  800. spin_lock_irq(&chip->reg_lock);
  801. reg = inw(FM801_REG(chip, GPIO_CTRL));
  802. /* use GPIO lines and set write enable bit */
  803. reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
  804. FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
  805. FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK);
  806. /* all of lines are in the write direction */
  807. /* clear data and clock lines */
  808. reg &= ~(FM801_GPIO_GD(TEA_64PCR_DATA) |
  809. FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
  810. FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
  811. FM801_GPIO_GP(TEA_64PCR_DATA) |
  812. FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK) |
  813. FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE));
  814. outw(reg, FM801_REG(chip, GPIO_CTRL));
  815. udelay(1);
  816. while (i--) {
  817. if (val & (1 << i))
  818. reg |= FM801_GPIO_GP(TEA_64PCR_DATA);
  819. else
  820. reg &= ~FM801_GPIO_GP(TEA_64PCR_DATA);
  821. outw(reg, FM801_REG(chip, GPIO_CTRL));
  822. udelay(1);
  823. reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  824. outw(reg, FM801_REG(chip, GPIO_CTRL));
  825. reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  826. outw(reg, FM801_REG(chip, GPIO_CTRL));
  827. udelay(1);
  828. }
  829. /* and reset the write enable bit */
  830. reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE) |
  831. FM801_GPIO_GP(TEA_64PCR_DATA);
  832. outw(reg, FM801_REG(chip, GPIO_CTRL));
  833. spin_unlock_irq(&chip->reg_lock);
  834. }
  835. static unsigned int snd_fm801_tea575x_64pcr_read(struct snd_tea575x *tea)
  836. {
  837. struct fm801 *chip = tea->private_data;
  838. unsigned short reg;
  839. unsigned int val = 0;
  840. int i;
  841. spin_lock_irq(&chip->reg_lock);
  842. reg = inw(FM801_REG(chip, GPIO_CTRL));
  843. /* use GPIO lines, set data direction to input */
  844. reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
  845. FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
  846. FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK) |
  847. FM801_GPIO_GD(TEA_64PCR_DATA) |
  848. FM801_GPIO_GP(TEA_64PCR_DATA) |
  849. FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
  850. /* all of lines are in the write direction, except data */
  851. /* clear data, write enable and clock lines */
  852. reg &= ~(FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
  853. FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
  854. FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK));
  855. for (i = 0; i < 24; i++) {
  856. reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  857. outw(reg, FM801_REG(chip, GPIO_CTRL));
  858. udelay(1);
  859. reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  860. outw(reg, FM801_REG(chip, GPIO_CTRL));
  861. udelay(1);
  862. val <<= 1;
  863. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_64PCR_DATA))
  864. val |= 1;
  865. }
  866. spin_unlock_irq(&chip->reg_lock);
  867. return val;
  868. }
  869. static void snd_fm801_tea575x_64pcr_mute(struct snd_tea575x *tea,
  870. unsigned int mute)
  871. {
  872. struct fm801 *chip = tea->private_data;
  873. unsigned short reg;
  874. spin_lock_irq(&chip->reg_lock);
  875. reg = inw(FM801_REG(chip, GPIO_CTRL));
  876. if (mute)
  877. /* 0xf800 (mute) */
  878. reg &= ~FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
  879. else
  880. /* 0xf802 (unmute) */
  881. reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
  882. outw(reg, FM801_REG(chip, GPIO_CTRL));
  883. udelay(1);
  884. spin_unlock_irq(&chip->reg_lock);
  885. }
  886. static struct snd_tea575x_ops snd_fm801_tea_ops[3] = {
  887. {
  888. /* 1 = MediaForte 256-PCS */
  889. .write = snd_fm801_tea575x_256pcs_write,
  890. .read = snd_fm801_tea575x_256pcs_read,
  891. },
  892. {
  893. /* 2 = MediaForte 256-PCPR */
  894. .write = snd_fm801_tea575x_256pcpr_write,
  895. .read = snd_fm801_tea575x_256pcpr_read,
  896. },
  897. {
  898. /* 3 = MediaForte 64-PCR */
  899. .write = snd_fm801_tea575x_64pcr_write,
  900. .read = snd_fm801_tea575x_64pcr_read,
  901. .mute = snd_fm801_tea575x_64pcr_mute,
  902. }
  903. };
  904. #endif
  905. /*
  906. * Mixer routines
  907. */
  908. #define FM801_SINGLE(xname, reg, shift, mask, invert) \
  909. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_single, \
  910. .get = snd_fm801_get_single, .put = snd_fm801_put_single, \
  911. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
  912. static int snd_fm801_info_single(struct snd_kcontrol *kcontrol,
  913. struct snd_ctl_elem_info *uinfo)
  914. {
  915. int mask = (kcontrol->private_value >> 16) & 0xff;
  916. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  917. uinfo->count = 1;
  918. uinfo->value.integer.min = 0;
  919. uinfo->value.integer.max = mask;
  920. return 0;
  921. }
  922. static int snd_fm801_get_single(struct snd_kcontrol *kcontrol,
  923. struct snd_ctl_elem_value *ucontrol)
  924. {
  925. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  926. int reg = kcontrol->private_value & 0xff;
  927. int shift = (kcontrol->private_value >> 8) & 0xff;
  928. int mask = (kcontrol->private_value >> 16) & 0xff;
  929. int invert = (kcontrol->private_value >> 24) & 0xff;
  930. ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift) & mask;
  931. if (invert)
  932. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  933. return 0;
  934. }
  935. static int snd_fm801_put_single(struct snd_kcontrol *kcontrol,
  936. struct snd_ctl_elem_value *ucontrol)
  937. {
  938. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  939. int reg = kcontrol->private_value & 0xff;
  940. int shift = (kcontrol->private_value >> 8) & 0xff;
  941. int mask = (kcontrol->private_value >> 16) & 0xff;
  942. int invert = (kcontrol->private_value >> 24) & 0xff;
  943. unsigned short val;
  944. val = (ucontrol->value.integer.value[0] & mask);
  945. if (invert)
  946. val = mask - val;
  947. return snd_fm801_update_bits(chip, reg, mask << shift, val << shift);
  948. }
  949. #define FM801_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \
  950. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_double, \
  951. .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
  952. .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) }
  953. #define FM801_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \
  954. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  955. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  956. .name = xname, .info = snd_fm801_info_double, \
  957. .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
  958. .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \
  959. .tlv = { .p = (xtlv) } }
  960. static int snd_fm801_info_double(struct snd_kcontrol *kcontrol,
  961. struct snd_ctl_elem_info *uinfo)
  962. {
  963. int mask = (kcontrol->private_value >> 16) & 0xff;
  964. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  965. uinfo->count = 2;
  966. uinfo->value.integer.min = 0;
  967. uinfo->value.integer.max = mask;
  968. return 0;
  969. }
  970. static int snd_fm801_get_double(struct snd_kcontrol *kcontrol,
  971. struct snd_ctl_elem_value *ucontrol)
  972. {
  973. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  974. int reg = kcontrol->private_value & 0xff;
  975. int shift_left = (kcontrol->private_value >> 8) & 0x0f;
  976. int shift_right = (kcontrol->private_value >> 12) & 0x0f;
  977. int mask = (kcontrol->private_value >> 16) & 0xff;
  978. int invert = (kcontrol->private_value >> 24) & 0xff;
  979. spin_lock_irq(&chip->reg_lock);
  980. ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift_left) & mask;
  981. ucontrol->value.integer.value[1] = (inw(chip->port + reg) >> shift_right) & mask;
  982. spin_unlock_irq(&chip->reg_lock);
  983. if (invert) {
  984. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  985. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  986. }
  987. return 0;
  988. }
  989. static int snd_fm801_put_double(struct snd_kcontrol *kcontrol,
  990. struct snd_ctl_elem_value *ucontrol)
  991. {
  992. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  993. int reg = kcontrol->private_value & 0xff;
  994. int shift_left = (kcontrol->private_value >> 8) & 0x0f;
  995. int shift_right = (kcontrol->private_value >> 12) & 0x0f;
  996. int mask = (kcontrol->private_value >> 16) & 0xff;
  997. int invert = (kcontrol->private_value >> 24) & 0xff;
  998. unsigned short val1, val2;
  999. val1 = ucontrol->value.integer.value[0] & mask;
  1000. val2 = ucontrol->value.integer.value[1] & mask;
  1001. if (invert) {
  1002. val1 = mask - val1;
  1003. val2 = mask - val2;
  1004. }
  1005. return snd_fm801_update_bits(chip, reg,
  1006. (mask << shift_left) | (mask << shift_right),
  1007. (val1 << shift_left ) | (val2 << shift_right));
  1008. }
  1009. static int snd_fm801_info_mux(struct snd_kcontrol *kcontrol,
  1010. struct snd_ctl_elem_info *uinfo)
  1011. {
  1012. static char *texts[5] = {
  1013. "AC97 Primary", "FM", "I2S", "PCM", "AC97 Secondary"
  1014. };
  1015. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1016. uinfo->count = 1;
  1017. uinfo->value.enumerated.items = 5;
  1018. if (uinfo->value.enumerated.item > 4)
  1019. uinfo->value.enumerated.item = 4;
  1020. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1021. return 0;
  1022. }
  1023. static int snd_fm801_get_mux(struct snd_kcontrol *kcontrol,
  1024. struct snd_ctl_elem_value *ucontrol)
  1025. {
  1026. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  1027. unsigned short val;
  1028. val = inw(FM801_REG(chip, REC_SRC)) & 7;
  1029. if (val > 4)
  1030. val = 4;
  1031. ucontrol->value.enumerated.item[0] = val;
  1032. return 0;
  1033. }
  1034. static int snd_fm801_put_mux(struct snd_kcontrol *kcontrol,
  1035. struct snd_ctl_elem_value *ucontrol)
  1036. {
  1037. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  1038. unsigned short val;
  1039. if ((val = ucontrol->value.enumerated.item[0]) > 4)
  1040. return -EINVAL;
  1041. return snd_fm801_update_bits(chip, FM801_REC_SRC, 7, val);
  1042. }
  1043. static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -3450, 150, 0);
  1044. #define FM801_CONTROLS ARRAY_SIZE(snd_fm801_controls)
  1045. static struct snd_kcontrol_new snd_fm801_controls[] __devinitdata = {
  1046. FM801_DOUBLE_TLV("Wave Playback Volume", FM801_PCM_VOL, 0, 8, 31, 1,
  1047. db_scale_dsp),
  1048. FM801_SINGLE("Wave Playback Switch", FM801_PCM_VOL, 15, 1, 1),
  1049. FM801_DOUBLE_TLV("I2S Playback Volume", FM801_I2S_VOL, 0, 8, 31, 1,
  1050. db_scale_dsp),
  1051. FM801_SINGLE("I2S Playback Switch", FM801_I2S_VOL, 15, 1, 1),
  1052. FM801_DOUBLE_TLV("FM Playback Volume", FM801_FM_VOL, 0, 8, 31, 1,
  1053. db_scale_dsp),
  1054. FM801_SINGLE("FM Playback Switch", FM801_FM_VOL, 15, 1, 1),
  1055. {
  1056. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1057. .name = "Digital Capture Source",
  1058. .info = snd_fm801_info_mux,
  1059. .get = snd_fm801_get_mux,
  1060. .put = snd_fm801_put_mux,
  1061. }
  1062. };
  1063. #define FM801_CONTROLS_MULTI ARRAY_SIZE(snd_fm801_controls_multi)
  1064. static struct snd_kcontrol_new snd_fm801_controls_multi[] __devinitdata = {
  1065. FM801_SINGLE("AC97 2ch->4ch Copy Switch", FM801_CODEC_CTRL, 7, 1, 0),
  1066. FM801_SINGLE("AC97 18-bit Switch", FM801_CODEC_CTRL, 10, 1, 0),
  1067. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), FM801_I2S_MODE, 8, 1, 0),
  1068. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",PLAYBACK,SWITCH), FM801_I2S_MODE, 9, 1, 0),
  1069. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",CAPTURE,SWITCH), FM801_I2S_MODE, 10, 1, 0),
  1070. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), FM801_GEN_CTRL, 2, 1, 0),
  1071. };
  1072. static void snd_fm801_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1073. {
  1074. struct fm801 *chip = bus->private_data;
  1075. chip->ac97_bus = NULL;
  1076. }
  1077. static void snd_fm801_mixer_free_ac97(struct snd_ac97 *ac97)
  1078. {
  1079. struct fm801 *chip = ac97->private_data;
  1080. if (ac97->num == 0) {
  1081. chip->ac97 = NULL;
  1082. } else {
  1083. chip->ac97_sec = NULL;
  1084. }
  1085. }
  1086. static int __devinit snd_fm801_mixer(struct fm801 *chip)
  1087. {
  1088. struct snd_ac97_template ac97;
  1089. unsigned int i;
  1090. int err;
  1091. static struct snd_ac97_bus_ops ops = {
  1092. .write = snd_fm801_codec_write,
  1093. .read = snd_fm801_codec_read,
  1094. };
  1095. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1096. return err;
  1097. chip->ac97_bus->private_free = snd_fm801_mixer_free_ac97_bus;
  1098. memset(&ac97, 0, sizeof(ac97));
  1099. ac97.private_data = chip;
  1100. ac97.private_free = snd_fm801_mixer_free_ac97;
  1101. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1102. return err;
  1103. if (chip->secondary) {
  1104. ac97.num = 1;
  1105. ac97.addr = chip->secondary_addr;
  1106. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_sec)) < 0)
  1107. return err;
  1108. }
  1109. for (i = 0; i < FM801_CONTROLS; i++)
  1110. snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls[i], chip));
  1111. if (chip->multichannel) {
  1112. for (i = 0; i < FM801_CONTROLS_MULTI; i++)
  1113. snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls_multi[i], chip));
  1114. }
  1115. return 0;
  1116. }
  1117. /*
  1118. * initialization routines
  1119. */
  1120. static int wait_for_codec(struct fm801 *chip, unsigned int codec_id,
  1121. unsigned short reg, unsigned long waits)
  1122. {
  1123. unsigned long timeout = jiffies + waits;
  1124. outw(FM801_AC97_READ | (codec_id << FM801_AC97_ADDR_SHIFT) | reg,
  1125. FM801_REG(chip, AC97_CMD));
  1126. udelay(5);
  1127. do {
  1128. if ((inw(FM801_REG(chip, AC97_CMD)) & (FM801_AC97_VALID|FM801_AC97_BUSY))
  1129. == FM801_AC97_VALID)
  1130. return 0;
  1131. schedule_timeout_uninterruptible(1);
  1132. } while (time_after(timeout, jiffies));
  1133. return -EIO;
  1134. }
  1135. static int snd_fm801_chip_init(struct fm801 *chip, int resume)
  1136. {
  1137. unsigned short cmdw;
  1138. if (chip->tea575x_tuner & TUNER_ONLY)
  1139. goto __ac97_ok;
  1140. /* codec cold reset + AC'97 warm reset */
  1141. outw((1<<5) | (1<<6), FM801_REG(chip, CODEC_CTRL));
  1142. inw(FM801_REG(chip, CODEC_CTRL)); /* flush posting data */
  1143. udelay(100);
  1144. outw(0, FM801_REG(chip, CODEC_CTRL));
  1145. if (wait_for_codec(chip, 0, AC97_RESET, msecs_to_jiffies(750)) < 0)
  1146. if (!resume) {
  1147. snd_printk(KERN_INFO "Primary AC'97 codec not found, "
  1148. "assume SF64-PCR (tuner-only)\n");
  1149. chip->tea575x_tuner = 3 | TUNER_ONLY;
  1150. goto __ac97_ok;
  1151. }
  1152. if (chip->multichannel) {
  1153. if (chip->secondary_addr) {
  1154. wait_for_codec(chip, chip->secondary_addr,
  1155. AC97_VENDOR_ID1, msecs_to_jiffies(50));
  1156. } else {
  1157. /* my card has the secondary codec */
  1158. /* at address #3, so the loop is inverted */
  1159. int i;
  1160. for (i = 3; i > 0; i--) {
  1161. if (!wait_for_codec(chip, i, AC97_VENDOR_ID1,
  1162. msecs_to_jiffies(50))) {
  1163. cmdw = inw(FM801_REG(chip, AC97_DATA));
  1164. if (cmdw != 0xffff && cmdw != 0) {
  1165. chip->secondary = 1;
  1166. chip->secondary_addr = i;
  1167. break;
  1168. }
  1169. }
  1170. }
  1171. }
  1172. /* the recovery phase, it seems that probing for non-existing codec might */
  1173. /* cause timeout problems */
  1174. wait_for_codec(chip, 0, AC97_VENDOR_ID1, msecs_to_jiffies(750));
  1175. }
  1176. __ac97_ok:
  1177. /* init volume */
  1178. outw(0x0808, FM801_REG(chip, PCM_VOL));
  1179. outw(0x9f1f, FM801_REG(chip, FM_VOL));
  1180. outw(0x8808, FM801_REG(chip, I2S_VOL));
  1181. /* I2S control - I2S mode */
  1182. outw(0x0003, FM801_REG(chip, I2S_MODE));
  1183. /* interrupt setup */
  1184. cmdw = inw(FM801_REG(chip, IRQ_MASK));
  1185. if (chip->irq < 0)
  1186. cmdw |= 0x00c3; /* mask everything, no PCM nor MPU */
  1187. else
  1188. cmdw &= ~0x0083; /* unmask MPU, PLAYBACK & CAPTURE */
  1189. outw(cmdw, FM801_REG(chip, IRQ_MASK));
  1190. /* interrupt clear */
  1191. outw(FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU, FM801_REG(chip, IRQ_STATUS));
  1192. return 0;
  1193. }
  1194. static int snd_fm801_free(struct fm801 *chip)
  1195. {
  1196. unsigned short cmdw;
  1197. if (chip->irq < 0)
  1198. goto __end_hw;
  1199. /* interrupt setup - mask everything */
  1200. cmdw = inw(FM801_REG(chip, IRQ_MASK));
  1201. cmdw |= 0x00c3;
  1202. outw(cmdw, FM801_REG(chip, IRQ_MASK));
  1203. __end_hw:
  1204. #ifdef TEA575X_RADIO
  1205. snd_tea575x_exit(&chip->tea);
  1206. #endif
  1207. if (chip->irq >= 0)
  1208. free_irq(chip->irq, chip);
  1209. pci_release_regions(chip->pci);
  1210. pci_disable_device(chip->pci);
  1211. kfree(chip);
  1212. return 0;
  1213. }
  1214. static int snd_fm801_dev_free(struct snd_device *device)
  1215. {
  1216. struct fm801 *chip = device->device_data;
  1217. return snd_fm801_free(chip);
  1218. }
  1219. static int __devinit snd_fm801_create(struct snd_card *card,
  1220. struct pci_dev * pci,
  1221. int tea575x_tuner,
  1222. struct fm801 ** rchip)
  1223. {
  1224. struct fm801 *chip;
  1225. int err;
  1226. static struct snd_device_ops ops = {
  1227. .dev_free = snd_fm801_dev_free,
  1228. };
  1229. *rchip = NULL;
  1230. if ((err = pci_enable_device(pci)) < 0)
  1231. return err;
  1232. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1233. if (chip == NULL) {
  1234. pci_disable_device(pci);
  1235. return -ENOMEM;
  1236. }
  1237. spin_lock_init(&chip->reg_lock);
  1238. chip->card = card;
  1239. chip->pci = pci;
  1240. chip->irq = -1;
  1241. chip->tea575x_tuner = tea575x_tuner;
  1242. if ((err = pci_request_regions(pci, "FM801")) < 0) {
  1243. kfree(chip);
  1244. pci_disable_device(pci);
  1245. return err;
  1246. }
  1247. chip->port = pci_resource_start(pci, 0);
  1248. if ((tea575x_tuner & TUNER_ONLY) == 0) {
  1249. if (request_irq(pci->irq, snd_fm801_interrupt, IRQF_SHARED,
  1250. "FM801", chip)) {
  1251. snd_printk(KERN_ERR "unable to grab IRQ %d\n", chip->irq);
  1252. snd_fm801_free(chip);
  1253. return -EBUSY;
  1254. }
  1255. chip->irq = pci->irq;
  1256. pci_set_master(pci);
  1257. }
  1258. if (pci->revision >= 0xb1) /* FM801-AU */
  1259. chip->multichannel = 1;
  1260. snd_fm801_chip_init(chip, 0);
  1261. /* init might set tuner access method */
  1262. tea575x_tuner = chip->tea575x_tuner;
  1263. if (chip->irq >= 0 && (tea575x_tuner & TUNER_ONLY)) {
  1264. pci_clear_master(pci);
  1265. free_irq(chip->irq, chip);
  1266. chip->irq = -1;
  1267. }
  1268. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1269. snd_fm801_free(chip);
  1270. return err;
  1271. }
  1272. snd_card_set_dev(card, &pci->dev);
  1273. #ifdef TEA575X_RADIO
  1274. if ((tea575x_tuner & TUNER_TYPE_MASK) > 0 &&
  1275. (tea575x_tuner & TUNER_TYPE_MASK) < 4) {
  1276. chip->tea.dev_nr = tea575x_tuner >> 16;
  1277. chip->tea.card = card;
  1278. chip->tea.freq_fixup = 10700;
  1279. chip->tea.private_data = chip;
  1280. chip->tea.ops = &snd_fm801_tea_ops[(tea575x_tuner & TUNER_TYPE_MASK) - 1];
  1281. snd_tea575x_init(&chip->tea);
  1282. }
  1283. #endif
  1284. *rchip = chip;
  1285. return 0;
  1286. }
  1287. static int __devinit snd_card_fm801_probe(struct pci_dev *pci,
  1288. const struct pci_device_id *pci_id)
  1289. {
  1290. static int dev;
  1291. struct snd_card *card;
  1292. struct fm801 *chip;
  1293. struct snd_opl3 *opl3;
  1294. int err;
  1295. if (dev >= SNDRV_CARDS)
  1296. return -ENODEV;
  1297. if (!enable[dev]) {
  1298. dev++;
  1299. return -ENOENT;
  1300. }
  1301. err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
  1302. if (err < 0)
  1303. return err;
  1304. if ((err = snd_fm801_create(card, pci, tea575x_tuner[dev], &chip)) < 0) {
  1305. snd_card_free(card);
  1306. return err;
  1307. }
  1308. card->private_data = chip;
  1309. strcpy(card->driver, "FM801");
  1310. strcpy(card->shortname, "ForteMedia FM801-");
  1311. strcat(card->shortname, chip->multichannel ? "AU" : "AS");
  1312. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1313. card->shortname, chip->port, chip->irq);
  1314. if (chip->tea575x_tuner & TUNER_ONLY)
  1315. goto __fm801_tuner_only;
  1316. if ((err = snd_fm801_pcm(chip, 0, NULL)) < 0) {
  1317. snd_card_free(card);
  1318. return err;
  1319. }
  1320. if ((err = snd_fm801_mixer(chip)) < 0) {
  1321. snd_card_free(card);
  1322. return err;
  1323. }
  1324. if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_FM801,
  1325. FM801_REG(chip, MPU401_DATA),
  1326. MPU401_INFO_INTEGRATED,
  1327. chip->irq, 0, &chip->rmidi)) < 0) {
  1328. snd_card_free(card);
  1329. return err;
  1330. }
  1331. if ((err = snd_opl3_create(card, FM801_REG(chip, OPL3_BANK0),
  1332. FM801_REG(chip, OPL3_BANK1),
  1333. OPL3_HW_OPL3_FM801, 1, &opl3)) < 0) {
  1334. snd_card_free(card);
  1335. return err;
  1336. }
  1337. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1338. snd_card_free(card);
  1339. return err;
  1340. }
  1341. __fm801_tuner_only:
  1342. if ((err = snd_card_register(card)) < 0) {
  1343. snd_card_free(card);
  1344. return err;
  1345. }
  1346. pci_set_drvdata(pci, card);
  1347. dev++;
  1348. return 0;
  1349. }
  1350. static void __devexit snd_card_fm801_remove(struct pci_dev *pci)
  1351. {
  1352. snd_card_free(pci_get_drvdata(pci));
  1353. pci_set_drvdata(pci, NULL);
  1354. }
  1355. #ifdef CONFIG_PM
  1356. static unsigned char saved_regs[] = {
  1357. FM801_PCM_VOL, FM801_I2S_VOL, FM801_FM_VOL, FM801_REC_SRC,
  1358. FM801_PLY_CTRL, FM801_PLY_COUNT, FM801_PLY_BUF1, FM801_PLY_BUF2,
  1359. FM801_CAP_CTRL, FM801_CAP_COUNT, FM801_CAP_BUF1, FM801_CAP_BUF2,
  1360. FM801_CODEC_CTRL, FM801_I2S_MODE, FM801_VOLUME, FM801_GEN_CTRL,
  1361. };
  1362. static int snd_fm801_suspend(struct pci_dev *pci, pm_message_t state)
  1363. {
  1364. struct snd_card *card = pci_get_drvdata(pci);
  1365. struct fm801 *chip = card->private_data;
  1366. int i;
  1367. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1368. snd_pcm_suspend_all(chip->pcm);
  1369. snd_ac97_suspend(chip->ac97);
  1370. snd_ac97_suspend(chip->ac97_sec);
  1371. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1372. chip->saved_regs[i] = inw(chip->port + saved_regs[i]);
  1373. /* FIXME: tea575x suspend */
  1374. pci_disable_device(pci);
  1375. pci_save_state(pci);
  1376. pci_set_power_state(pci, pci_choose_state(pci, state));
  1377. return 0;
  1378. }
  1379. static int snd_fm801_resume(struct pci_dev *pci)
  1380. {
  1381. struct snd_card *card = pci_get_drvdata(pci);
  1382. struct fm801 *chip = card->private_data;
  1383. int i;
  1384. pci_set_power_state(pci, PCI_D0);
  1385. pci_restore_state(pci);
  1386. if (pci_enable_device(pci) < 0) {
  1387. printk(KERN_ERR "fm801: pci_enable_device failed, "
  1388. "disabling device\n");
  1389. snd_card_disconnect(card);
  1390. return -EIO;
  1391. }
  1392. pci_set_master(pci);
  1393. snd_fm801_chip_init(chip, 1);
  1394. snd_ac97_resume(chip->ac97);
  1395. snd_ac97_resume(chip->ac97_sec);
  1396. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1397. outw(chip->saved_regs[i], chip->port + saved_regs[i]);
  1398. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1399. return 0;
  1400. }
  1401. #endif
  1402. static struct pci_driver driver = {
  1403. .name = "FM801",
  1404. .id_table = snd_fm801_ids,
  1405. .probe = snd_card_fm801_probe,
  1406. .remove = __devexit_p(snd_card_fm801_remove),
  1407. #ifdef CONFIG_PM
  1408. .suspend = snd_fm801_suspend,
  1409. .resume = snd_fm801_resume,
  1410. #endif
  1411. };
  1412. static int __init alsa_card_fm801_init(void)
  1413. {
  1414. return pci_register_driver(&driver);
  1415. }
  1416. static void __exit alsa_card_fm801_exit(void)
  1417. {
  1418. pci_unregister_driver(&driver);
  1419. }
  1420. module_init(alsa_card_fm801_init)
  1421. module_exit(alsa_card_fm801_exit)