emufx.c 99 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Creative Labs, Inc.
  4. * Routines for effect processor FX8010
  5. *
  6. * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
  7. * Added EMU 1010 support.
  8. *
  9. * BUGS:
  10. * --
  11. *
  12. * TODO:
  13. * --
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  28. *
  29. */
  30. #include <linux/pci.h>
  31. #include <linux/capability.h>
  32. #include <linux/delay.h>
  33. #include <linux/slab.h>
  34. #include <linux/vmalloc.h>
  35. #include <linux/init.h>
  36. #include <linux/mutex.h>
  37. #include <linux/moduleparam.h>
  38. #include <sound/core.h>
  39. #include <sound/tlv.h>
  40. #include <sound/emu10k1.h>
  41. #if 0 /* for testing purposes - digital out -> capture */
  42. #define EMU10K1_CAPTURE_DIGITAL_OUT
  43. #endif
  44. #if 0 /* for testing purposes - set S/PDIF to AC3 output */
  45. #define EMU10K1_SET_AC3_IEC958
  46. #endif
  47. #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
  48. #define EMU10K1_CENTER_LFE_FROM_FRONT
  49. #endif
  50. static bool high_res_gpr_volume;
  51. module_param(high_res_gpr_volume, bool, 0444);
  52. MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
  53. /*
  54. * Tables
  55. */
  56. static char *fxbuses[16] = {
  57. /* 0x00 */ "PCM Left",
  58. /* 0x01 */ "PCM Right",
  59. /* 0x02 */ "PCM Surround Left",
  60. /* 0x03 */ "PCM Surround Right",
  61. /* 0x04 */ "MIDI Left",
  62. /* 0x05 */ "MIDI Right",
  63. /* 0x06 */ "Center",
  64. /* 0x07 */ "LFE",
  65. /* 0x08 */ NULL,
  66. /* 0x09 */ NULL,
  67. /* 0x0a */ NULL,
  68. /* 0x0b */ NULL,
  69. /* 0x0c */ "MIDI Reverb",
  70. /* 0x0d */ "MIDI Chorus",
  71. /* 0x0e */ NULL,
  72. /* 0x0f */ NULL
  73. };
  74. static char *creative_ins[16] = {
  75. /* 0x00 */ "AC97 Left",
  76. /* 0x01 */ "AC97 Right",
  77. /* 0x02 */ "TTL IEC958 Left",
  78. /* 0x03 */ "TTL IEC958 Right",
  79. /* 0x04 */ "Zoom Video Left",
  80. /* 0x05 */ "Zoom Video Right",
  81. /* 0x06 */ "Optical IEC958 Left",
  82. /* 0x07 */ "Optical IEC958 Right",
  83. /* 0x08 */ "Line/Mic 1 Left",
  84. /* 0x09 */ "Line/Mic 1 Right",
  85. /* 0x0a */ "Coaxial IEC958 Left",
  86. /* 0x0b */ "Coaxial IEC958 Right",
  87. /* 0x0c */ "Line/Mic 2 Left",
  88. /* 0x0d */ "Line/Mic 2 Right",
  89. /* 0x0e */ NULL,
  90. /* 0x0f */ NULL
  91. };
  92. static char *audigy_ins[16] = {
  93. /* 0x00 */ "AC97 Left",
  94. /* 0x01 */ "AC97 Right",
  95. /* 0x02 */ "Audigy CD Left",
  96. /* 0x03 */ "Audigy CD Right",
  97. /* 0x04 */ "Optical IEC958 Left",
  98. /* 0x05 */ "Optical IEC958 Right",
  99. /* 0x06 */ NULL,
  100. /* 0x07 */ NULL,
  101. /* 0x08 */ "Line/Mic 2 Left",
  102. /* 0x09 */ "Line/Mic 2 Right",
  103. /* 0x0a */ "SPDIF Left",
  104. /* 0x0b */ "SPDIF Right",
  105. /* 0x0c */ "Aux2 Left",
  106. /* 0x0d */ "Aux2 Right",
  107. /* 0x0e */ NULL,
  108. /* 0x0f */ NULL
  109. };
  110. static char *creative_outs[32] = {
  111. /* 0x00 */ "AC97 Left",
  112. /* 0x01 */ "AC97 Right",
  113. /* 0x02 */ "Optical IEC958 Left",
  114. /* 0x03 */ "Optical IEC958 Right",
  115. /* 0x04 */ "Center",
  116. /* 0x05 */ "LFE",
  117. /* 0x06 */ "Headphone Left",
  118. /* 0x07 */ "Headphone Right",
  119. /* 0x08 */ "Surround Left",
  120. /* 0x09 */ "Surround Right",
  121. /* 0x0a */ "PCM Capture Left",
  122. /* 0x0b */ "PCM Capture Right",
  123. /* 0x0c */ "MIC Capture",
  124. /* 0x0d */ "AC97 Surround Left",
  125. /* 0x0e */ "AC97 Surround Right",
  126. /* 0x0f */ NULL,
  127. /* 0x10 */ NULL,
  128. /* 0x11 */ "Analog Center",
  129. /* 0x12 */ "Analog LFE",
  130. /* 0x13 */ NULL,
  131. /* 0x14 */ NULL,
  132. /* 0x15 */ NULL,
  133. /* 0x16 */ NULL,
  134. /* 0x17 */ NULL,
  135. /* 0x18 */ NULL,
  136. /* 0x19 */ NULL,
  137. /* 0x1a */ NULL,
  138. /* 0x1b */ NULL,
  139. /* 0x1c */ NULL,
  140. /* 0x1d */ NULL,
  141. /* 0x1e */ NULL,
  142. /* 0x1f */ NULL,
  143. };
  144. static char *audigy_outs[32] = {
  145. /* 0x00 */ "Digital Front Left",
  146. /* 0x01 */ "Digital Front Right",
  147. /* 0x02 */ "Digital Center",
  148. /* 0x03 */ "Digital LEF",
  149. /* 0x04 */ "Headphone Left",
  150. /* 0x05 */ "Headphone Right",
  151. /* 0x06 */ "Digital Rear Left",
  152. /* 0x07 */ "Digital Rear Right",
  153. /* 0x08 */ "Front Left",
  154. /* 0x09 */ "Front Right",
  155. /* 0x0a */ "Center",
  156. /* 0x0b */ "LFE",
  157. /* 0x0c */ NULL,
  158. /* 0x0d */ NULL,
  159. /* 0x0e */ "Rear Left",
  160. /* 0x0f */ "Rear Right",
  161. /* 0x10 */ "AC97 Front Left",
  162. /* 0x11 */ "AC97 Front Right",
  163. /* 0x12 */ "ADC Caputre Left",
  164. /* 0x13 */ "ADC Capture Right",
  165. /* 0x14 */ NULL,
  166. /* 0x15 */ NULL,
  167. /* 0x16 */ NULL,
  168. /* 0x17 */ NULL,
  169. /* 0x18 */ NULL,
  170. /* 0x19 */ NULL,
  171. /* 0x1a */ NULL,
  172. /* 0x1b */ NULL,
  173. /* 0x1c */ NULL,
  174. /* 0x1d */ NULL,
  175. /* 0x1e */ NULL,
  176. /* 0x1f */ NULL,
  177. };
  178. static const u32 bass_table[41][5] = {
  179. { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
  180. { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
  181. { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
  182. { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
  183. { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
  184. { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
  185. { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
  186. { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
  187. { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
  188. { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
  189. { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
  190. { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
  191. { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
  192. { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
  193. { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
  194. { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
  195. { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
  196. { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
  197. { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
  198. { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
  199. { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
  200. { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
  201. { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
  202. { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
  203. { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
  204. { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
  205. { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
  206. { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
  207. { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
  208. { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
  209. { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
  210. { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
  211. { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
  212. { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
  213. { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
  214. { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
  215. { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
  216. { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
  217. { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
  218. { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
  219. { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
  220. };
  221. static const u32 treble_table[41][5] = {
  222. { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
  223. { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
  224. { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
  225. { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
  226. { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
  227. { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
  228. { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
  229. { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
  230. { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
  231. { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
  232. { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
  233. { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
  234. { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
  235. { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
  236. { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
  237. { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
  238. { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
  239. { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
  240. { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
  241. { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
  242. { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
  243. { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
  244. { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
  245. { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
  246. { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
  247. { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
  248. { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
  249. { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
  250. { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
  251. { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
  252. { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
  253. { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
  254. { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
  255. { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
  256. { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
  257. { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
  258. { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
  259. { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
  260. { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
  261. { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
  262. { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
  263. };
  264. /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
  265. static const u32 db_table[101] = {
  266. 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
  267. 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
  268. 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
  269. 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
  270. 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
  271. 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
  272. 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
  273. 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
  274. 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
  275. 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
  276. 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
  277. 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
  278. 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
  279. 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
  280. 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
  281. 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
  282. 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
  283. 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
  284. 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
  285. 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
  286. 0x7fffffff,
  287. };
  288. /* EMU10k1/EMU10k2 DSP control db gain */
  289. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
  290. static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
  291. static const u32 onoff_table[2] = {
  292. 0x00000000, 0x00000001
  293. };
  294. /*
  295. */
  296. static inline mm_segment_t snd_enter_user(void)
  297. {
  298. mm_segment_t fs = get_fs();
  299. set_fs(get_ds());
  300. return fs;
  301. }
  302. static inline void snd_leave_user(mm_segment_t fs)
  303. {
  304. set_fs(fs);
  305. }
  306. /*
  307. * controls
  308. */
  309. static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  310. {
  311. struct snd_emu10k1_fx8010_ctl *ctl =
  312. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  313. if (ctl->min == 0 && ctl->max == 1)
  314. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  315. else
  316. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  317. uinfo->count = ctl->vcount;
  318. uinfo->value.integer.min = ctl->min;
  319. uinfo->value.integer.max = ctl->max;
  320. return 0;
  321. }
  322. static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  323. {
  324. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  325. struct snd_emu10k1_fx8010_ctl *ctl =
  326. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  327. unsigned long flags;
  328. unsigned int i;
  329. spin_lock_irqsave(&emu->reg_lock, flags);
  330. for (i = 0; i < ctl->vcount; i++)
  331. ucontrol->value.integer.value[i] = ctl->value[i];
  332. spin_unlock_irqrestore(&emu->reg_lock, flags);
  333. return 0;
  334. }
  335. static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  336. {
  337. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  338. struct snd_emu10k1_fx8010_ctl *ctl =
  339. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  340. unsigned long flags;
  341. unsigned int nval, val;
  342. unsigned int i, j;
  343. int change = 0;
  344. spin_lock_irqsave(&emu->reg_lock, flags);
  345. for (i = 0; i < ctl->vcount; i++) {
  346. nval = ucontrol->value.integer.value[i];
  347. if (nval < ctl->min)
  348. nval = ctl->min;
  349. if (nval > ctl->max)
  350. nval = ctl->max;
  351. if (nval != ctl->value[i])
  352. change = 1;
  353. val = ctl->value[i] = nval;
  354. switch (ctl->translation) {
  355. case EMU10K1_GPR_TRANSLATION_NONE:
  356. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
  357. break;
  358. case EMU10K1_GPR_TRANSLATION_TABLE100:
  359. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
  360. break;
  361. case EMU10K1_GPR_TRANSLATION_BASS:
  362. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  363. change = -EIO;
  364. goto __error;
  365. }
  366. for (j = 0; j < 5; j++)
  367. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
  368. break;
  369. case EMU10K1_GPR_TRANSLATION_TREBLE:
  370. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  371. change = -EIO;
  372. goto __error;
  373. }
  374. for (j = 0; j < 5; j++)
  375. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
  376. break;
  377. case EMU10K1_GPR_TRANSLATION_ONOFF:
  378. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
  379. break;
  380. }
  381. }
  382. __error:
  383. spin_unlock_irqrestore(&emu->reg_lock, flags);
  384. return change;
  385. }
  386. /*
  387. * Interrupt handler
  388. */
  389. static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
  390. {
  391. struct snd_emu10k1_fx8010_irq *irq, *nirq;
  392. irq = emu->fx8010.irq_handlers;
  393. while (irq) {
  394. nirq = irq->next; /* irq ptr can be removed from list */
  395. if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
  396. if (irq->handler)
  397. irq->handler(emu, irq->private_data);
  398. snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
  399. }
  400. irq = nirq;
  401. }
  402. }
  403. int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
  404. snd_fx8010_irq_handler_t *handler,
  405. unsigned char gpr_running,
  406. void *private_data,
  407. struct snd_emu10k1_fx8010_irq **r_irq)
  408. {
  409. struct snd_emu10k1_fx8010_irq *irq;
  410. unsigned long flags;
  411. irq = kmalloc(sizeof(*irq), GFP_ATOMIC);
  412. if (irq == NULL)
  413. return -ENOMEM;
  414. irq->handler = handler;
  415. irq->gpr_running = gpr_running;
  416. irq->private_data = private_data;
  417. irq->next = NULL;
  418. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  419. if (emu->fx8010.irq_handlers == NULL) {
  420. emu->fx8010.irq_handlers = irq;
  421. emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
  422. snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
  423. } else {
  424. irq->next = emu->fx8010.irq_handlers;
  425. emu->fx8010.irq_handlers = irq;
  426. }
  427. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  428. if (r_irq)
  429. *r_irq = irq;
  430. return 0;
  431. }
  432. int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
  433. struct snd_emu10k1_fx8010_irq *irq)
  434. {
  435. struct snd_emu10k1_fx8010_irq *tmp;
  436. unsigned long flags;
  437. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  438. if ((tmp = emu->fx8010.irq_handlers) == irq) {
  439. emu->fx8010.irq_handlers = tmp->next;
  440. if (emu->fx8010.irq_handlers == NULL) {
  441. snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
  442. emu->dsp_interrupt = NULL;
  443. }
  444. } else {
  445. while (tmp && tmp->next != irq)
  446. tmp = tmp->next;
  447. if (tmp)
  448. tmp->next = tmp->next->next;
  449. }
  450. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  451. kfree(irq);
  452. return 0;
  453. }
  454. /*************************************************************************
  455. * EMU10K1 effect manager
  456. *************************************************************************/
  457. static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
  458. unsigned int *ptr,
  459. u32 op, u32 r, u32 a, u32 x, u32 y)
  460. {
  461. u_int32_t *code;
  462. if (snd_BUG_ON(*ptr >= 512))
  463. return;
  464. code = (u_int32_t __force *)icode->code + (*ptr) * 2;
  465. set_bit(*ptr, icode->code_valid);
  466. code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
  467. code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
  468. (*ptr)++;
  469. }
  470. #define OP(icode, ptr, op, r, a, x, y) \
  471. snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
  472. static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
  473. unsigned int *ptr,
  474. u32 op, u32 r, u32 a, u32 x, u32 y)
  475. {
  476. u_int32_t *code;
  477. if (snd_BUG_ON(*ptr >= 1024))
  478. return;
  479. code = (u_int32_t __force *)icode->code + (*ptr) * 2;
  480. set_bit(*ptr, icode->code_valid);
  481. code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
  482. code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
  483. (*ptr)++;
  484. }
  485. #define A_OP(icode, ptr, op, r, a, x, y) \
  486. snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
  487. static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
  488. {
  489. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  490. snd_emu10k1_ptr_write(emu, pc, 0, data);
  491. }
  492. unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
  493. {
  494. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  495. return snd_emu10k1_ptr_read(emu, pc, 0);
  496. }
  497. static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
  498. struct snd_emu10k1_fx8010_code *icode)
  499. {
  500. int gpr;
  501. u32 val;
  502. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  503. if (!test_bit(gpr, icode->gpr_valid))
  504. continue;
  505. if (get_user(val, &icode->gpr_map[gpr]))
  506. return -EFAULT;
  507. snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
  508. }
  509. return 0;
  510. }
  511. static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
  512. struct snd_emu10k1_fx8010_code *icode)
  513. {
  514. int gpr;
  515. u32 val;
  516. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  517. set_bit(gpr, icode->gpr_valid);
  518. val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
  519. if (put_user(val, &icode->gpr_map[gpr]))
  520. return -EFAULT;
  521. }
  522. return 0;
  523. }
  524. static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
  525. struct snd_emu10k1_fx8010_code *icode)
  526. {
  527. int tram;
  528. u32 addr, val;
  529. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  530. if (!test_bit(tram, icode->tram_valid))
  531. continue;
  532. if (get_user(val, &icode->tram_data_map[tram]) ||
  533. get_user(addr, &icode->tram_addr_map[tram]))
  534. return -EFAULT;
  535. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
  536. if (!emu->audigy) {
  537. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
  538. } else {
  539. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
  540. snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
  541. }
  542. }
  543. return 0;
  544. }
  545. static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
  546. struct snd_emu10k1_fx8010_code *icode)
  547. {
  548. int tram;
  549. u32 val, addr;
  550. memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
  551. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  552. set_bit(tram, icode->tram_valid);
  553. val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
  554. if (!emu->audigy) {
  555. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
  556. } else {
  557. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
  558. addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
  559. }
  560. if (put_user(val, &icode->tram_data_map[tram]) ||
  561. put_user(addr, &icode->tram_addr_map[tram]))
  562. return -EFAULT;
  563. }
  564. return 0;
  565. }
  566. static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
  567. struct snd_emu10k1_fx8010_code *icode)
  568. {
  569. u32 pc, lo, hi;
  570. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  571. if (!test_bit(pc / 2, icode->code_valid))
  572. continue;
  573. if (get_user(lo, &icode->code[pc + 0]) ||
  574. get_user(hi, &icode->code[pc + 1]))
  575. return -EFAULT;
  576. snd_emu10k1_efx_write(emu, pc + 0, lo);
  577. snd_emu10k1_efx_write(emu, pc + 1, hi);
  578. }
  579. return 0;
  580. }
  581. static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
  582. struct snd_emu10k1_fx8010_code *icode)
  583. {
  584. u32 pc;
  585. memset(icode->code_valid, 0, sizeof(icode->code_valid));
  586. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  587. set_bit(pc / 2, icode->code_valid);
  588. if (put_user(snd_emu10k1_efx_read(emu, pc + 0), &icode->code[pc + 0]))
  589. return -EFAULT;
  590. if (put_user(snd_emu10k1_efx_read(emu, pc + 1), &icode->code[pc + 1]))
  591. return -EFAULT;
  592. }
  593. return 0;
  594. }
  595. static struct snd_emu10k1_fx8010_ctl *
  596. snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, struct snd_ctl_elem_id *id)
  597. {
  598. struct snd_emu10k1_fx8010_ctl *ctl;
  599. struct snd_kcontrol *kcontrol;
  600. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  601. kcontrol = ctl->kcontrol;
  602. if (kcontrol->id.iface == id->iface &&
  603. !strcmp(kcontrol->id.name, id->name) &&
  604. kcontrol->id.index == id->index)
  605. return ctl;
  606. }
  607. return NULL;
  608. }
  609. #define MAX_TLV_SIZE 256
  610. static unsigned int *copy_tlv(const unsigned int __user *_tlv)
  611. {
  612. unsigned int data[2];
  613. unsigned int *tlv;
  614. if (!_tlv)
  615. return NULL;
  616. if (copy_from_user(data, _tlv, sizeof(data)))
  617. return NULL;
  618. if (data[1] >= MAX_TLV_SIZE)
  619. return NULL;
  620. tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
  621. if (!tlv)
  622. return NULL;
  623. memcpy(tlv, data, sizeof(data));
  624. if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
  625. kfree(tlv);
  626. return NULL;
  627. }
  628. return tlv;
  629. }
  630. static int copy_gctl(struct snd_emu10k1 *emu,
  631. struct snd_emu10k1_fx8010_control_gpr *gctl,
  632. struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
  633. int idx)
  634. {
  635. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  636. if (emu->support_tlv)
  637. return copy_from_user(gctl, &_gctl[idx], sizeof(*gctl));
  638. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
  639. if (copy_from_user(gctl, &octl[idx], sizeof(*octl)))
  640. return -EFAULT;
  641. gctl->tlv = NULL;
  642. return 0;
  643. }
  644. static int copy_gctl_to_user(struct snd_emu10k1 *emu,
  645. struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
  646. struct snd_emu10k1_fx8010_control_gpr *gctl,
  647. int idx)
  648. {
  649. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  650. if (emu->support_tlv)
  651. return copy_to_user(&_gctl[idx], gctl, sizeof(*gctl));
  652. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
  653. return copy_to_user(&octl[idx], gctl, sizeof(*octl));
  654. }
  655. static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
  656. struct snd_emu10k1_fx8010_code *icode)
  657. {
  658. unsigned int i;
  659. struct snd_ctl_elem_id __user *_id;
  660. struct snd_ctl_elem_id id;
  661. struct snd_emu10k1_fx8010_control_gpr *gctl;
  662. int err;
  663. for (i = 0, _id = icode->gpr_del_controls;
  664. i < icode->gpr_del_control_count; i++, _id++) {
  665. if (copy_from_user(&id, _id, sizeof(id)))
  666. return -EFAULT;
  667. if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
  668. return -ENOENT;
  669. }
  670. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  671. if (! gctl)
  672. return -ENOMEM;
  673. err = 0;
  674. for (i = 0; i < icode->gpr_add_control_count; i++) {
  675. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
  676. err = -EFAULT;
  677. goto __error;
  678. }
  679. if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
  680. continue;
  681. down_read(&emu->card->controls_rwsem);
  682. if (snd_ctl_find_id(emu->card, &gctl->id) != NULL) {
  683. up_read(&emu->card->controls_rwsem);
  684. err = -EEXIST;
  685. goto __error;
  686. }
  687. up_read(&emu->card->controls_rwsem);
  688. if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  689. gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  690. err = -EINVAL;
  691. goto __error;
  692. }
  693. }
  694. for (i = 0; i < icode->gpr_list_control_count; i++) {
  695. /* FIXME: we need to check the WRITE access */
  696. if (copy_gctl(emu, gctl, icode->gpr_list_controls, i)) {
  697. err = -EFAULT;
  698. goto __error;
  699. }
  700. }
  701. __error:
  702. kfree(gctl);
  703. return err;
  704. }
  705. static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
  706. {
  707. struct snd_emu10k1_fx8010_ctl *ctl;
  708. ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
  709. kctl->private_value = 0;
  710. list_del(&ctl->list);
  711. kfree(ctl);
  712. if (kctl->tlv.p)
  713. kfree(kctl->tlv.p);
  714. }
  715. static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
  716. struct snd_emu10k1_fx8010_code *icode)
  717. {
  718. unsigned int i, j;
  719. struct snd_emu10k1_fx8010_control_gpr *gctl;
  720. struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
  721. struct snd_kcontrol_new knew;
  722. struct snd_kcontrol *kctl;
  723. struct snd_ctl_elem_value *val;
  724. int err = 0;
  725. val = kmalloc(sizeof(*val), GFP_KERNEL);
  726. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  727. nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
  728. if (!val || !gctl || !nctl) {
  729. err = -ENOMEM;
  730. goto __error;
  731. }
  732. for (i = 0; i < icode->gpr_add_control_count; i++) {
  733. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
  734. err = -EFAULT;
  735. goto __error;
  736. }
  737. if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  738. gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  739. err = -EINVAL;
  740. goto __error;
  741. }
  742. if (! gctl->id.name[0]) {
  743. err = -EINVAL;
  744. goto __error;
  745. }
  746. ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
  747. memset(&knew, 0, sizeof(knew));
  748. knew.iface = gctl->id.iface;
  749. knew.name = gctl->id.name;
  750. knew.index = gctl->id.index;
  751. knew.device = gctl->id.device;
  752. knew.subdevice = gctl->id.subdevice;
  753. knew.info = snd_emu10k1_gpr_ctl_info;
  754. knew.tlv.p = copy_tlv(gctl->tlv);
  755. if (knew.tlv.p)
  756. knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  757. SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  758. knew.get = snd_emu10k1_gpr_ctl_get;
  759. knew.put = snd_emu10k1_gpr_ctl_put;
  760. memset(nctl, 0, sizeof(*nctl));
  761. nctl->vcount = gctl->vcount;
  762. nctl->count = gctl->count;
  763. for (j = 0; j < 32; j++) {
  764. nctl->gpr[j] = gctl->gpr[j];
  765. nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
  766. val->value.integer.value[j] = gctl->value[j];
  767. }
  768. nctl->min = gctl->min;
  769. nctl->max = gctl->max;
  770. nctl->translation = gctl->translation;
  771. if (ctl == NULL) {
  772. ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
  773. if (ctl == NULL) {
  774. err = -ENOMEM;
  775. kfree(knew.tlv.p);
  776. goto __error;
  777. }
  778. knew.private_value = (unsigned long)ctl;
  779. *ctl = *nctl;
  780. if ((err = snd_ctl_add(emu->card, kctl = snd_ctl_new1(&knew, emu))) < 0) {
  781. kfree(ctl);
  782. kfree(knew.tlv.p);
  783. goto __error;
  784. }
  785. kctl->private_free = snd_emu10k1_ctl_private_free;
  786. ctl->kcontrol = kctl;
  787. list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
  788. } else {
  789. /* overwrite */
  790. nctl->list = ctl->list;
  791. nctl->kcontrol = ctl->kcontrol;
  792. *ctl = *nctl;
  793. snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
  794. SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
  795. }
  796. snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
  797. }
  798. __error:
  799. kfree(nctl);
  800. kfree(gctl);
  801. kfree(val);
  802. return err;
  803. }
  804. static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
  805. struct snd_emu10k1_fx8010_code *icode)
  806. {
  807. unsigned int i;
  808. struct snd_ctl_elem_id id;
  809. struct snd_ctl_elem_id __user *_id;
  810. struct snd_emu10k1_fx8010_ctl *ctl;
  811. struct snd_card *card = emu->card;
  812. for (i = 0, _id = icode->gpr_del_controls;
  813. i < icode->gpr_del_control_count; i++, _id++) {
  814. if (copy_from_user(&id, _id, sizeof(id)))
  815. return -EFAULT;
  816. down_write(&card->controls_rwsem);
  817. ctl = snd_emu10k1_look_for_ctl(emu, &id);
  818. if (ctl)
  819. snd_ctl_remove(card, ctl->kcontrol);
  820. up_write(&card->controls_rwsem);
  821. }
  822. return 0;
  823. }
  824. static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
  825. struct snd_emu10k1_fx8010_code *icode)
  826. {
  827. unsigned int i = 0, j;
  828. unsigned int total = 0;
  829. struct snd_emu10k1_fx8010_control_gpr *gctl;
  830. struct snd_emu10k1_fx8010_ctl *ctl;
  831. struct snd_ctl_elem_id *id;
  832. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  833. if (! gctl)
  834. return -ENOMEM;
  835. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  836. total++;
  837. if (icode->gpr_list_controls &&
  838. i < icode->gpr_list_control_count) {
  839. memset(gctl, 0, sizeof(*gctl));
  840. id = &ctl->kcontrol->id;
  841. gctl->id.iface = id->iface;
  842. strlcpy(gctl->id.name, id->name, sizeof(gctl->id.name));
  843. gctl->id.index = id->index;
  844. gctl->id.device = id->device;
  845. gctl->id.subdevice = id->subdevice;
  846. gctl->vcount = ctl->vcount;
  847. gctl->count = ctl->count;
  848. for (j = 0; j < 32; j++) {
  849. gctl->gpr[j] = ctl->gpr[j];
  850. gctl->value[j] = ctl->value[j];
  851. }
  852. gctl->min = ctl->min;
  853. gctl->max = ctl->max;
  854. gctl->translation = ctl->translation;
  855. if (copy_gctl_to_user(emu, icode->gpr_list_controls,
  856. gctl, i)) {
  857. kfree(gctl);
  858. return -EFAULT;
  859. }
  860. i++;
  861. }
  862. }
  863. icode->gpr_list_control_total = total;
  864. kfree(gctl);
  865. return 0;
  866. }
  867. static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
  868. struct snd_emu10k1_fx8010_code *icode)
  869. {
  870. int err = 0;
  871. mutex_lock(&emu->fx8010.lock);
  872. if ((err = snd_emu10k1_verify_controls(emu, icode)) < 0)
  873. goto __error;
  874. strlcpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
  875. /* stop FX processor - this may be dangerous, but it's better to miss
  876. some samples than generate wrong ones - [jk] */
  877. if (emu->audigy)
  878. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  879. else
  880. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  881. /* ok, do the main job */
  882. if ((err = snd_emu10k1_del_controls(emu, icode)) < 0 ||
  883. (err = snd_emu10k1_gpr_poke(emu, icode)) < 0 ||
  884. (err = snd_emu10k1_tram_poke(emu, icode)) < 0 ||
  885. (err = snd_emu10k1_code_poke(emu, icode)) < 0 ||
  886. (err = snd_emu10k1_add_controls(emu, icode)) < 0)
  887. goto __error;
  888. /* start FX processor when the DSP code is updated */
  889. if (emu->audigy)
  890. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  891. else
  892. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  893. __error:
  894. mutex_unlock(&emu->fx8010.lock);
  895. return err;
  896. }
  897. static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
  898. struct snd_emu10k1_fx8010_code *icode)
  899. {
  900. int err;
  901. mutex_lock(&emu->fx8010.lock);
  902. strlcpy(icode->name, emu->fx8010.name, sizeof(icode->name));
  903. /* ok, do the main job */
  904. err = snd_emu10k1_gpr_peek(emu, icode);
  905. if (err >= 0)
  906. err = snd_emu10k1_tram_peek(emu, icode);
  907. if (err >= 0)
  908. err = snd_emu10k1_code_peek(emu, icode);
  909. if (err >= 0)
  910. err = snd_emu10k1_list_controls(emu, icode);
  911. mutex_unlock(&emu->fx8010.lock);
  912. return err;
  913. }
  914. static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
  915. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  916. {
  917. unsigned int i;
  918. int err = 0;
  919. struct snd_emu10k1_fx8010_pcm *pcm;
  920. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  921. return -EINVAL;
  922. if (ipcm->channels > 32)
  923. return -EINVAL;
  924. pcm = &emu->fx8010.pcm[ipcm->substream];
  925. mutex_lock(&emu->fx8010.lock);
  926. spin_lock_irq(&emu->reg_lock);
  927. if (pcm->opened) {
  928. err = -EBUSY;
  929. goto __error;
  930. }
  931. if (ipcm->channels == 0) { /* remove */
  932. pcm->valid = 0;
  933. } else {
  934. /* FIXME: we need to add universal code to the PCM transfer routine */
  935. if (ipcm->channels != 2) {
  936. err = -EINVAL;
  937. goto __error;
  938. }
  939. pcm->valid = 1;
  940. pcm->opened = 0;
  941. pcm->channels = ipcm->channels;
  942. pcm->tram_start = ipcm->tram_start;
  943. pcm->buffer_size = ipcm->buffer_size;
  944. pcm->gpr_size = ipcm->gpr_size;
  945. pcm->gpr_count = ipcm->gpr_count;
  946. pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
  947. pcm->gpr_ptr = ipcm->gpr_ptr;
  948. pcm->gpr_trigger = ipcm->gpr_trigger;
  949. pcm->gpr_running = ipcm->gpr_running;
  950. for (i = 0; i < pcm->channels; i++)
  951. pcm->etram[i] = ipcm->etram[i];
  952. }
  953. __error:
  954. spin_unlock_irq(&emu->reg_lock);
  955. mutex_unlock(&emu->fx8010.lock);
  956. return err;
  957. }
  958. static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
  959. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  960. {
  961. unsigned int i;
  962. int err = 0;
  963. struct snd_emu10k1_fx8010_pcm *pcm;
  964. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  965. return -EINVAL;
  966. pcm = &emu->fx8010.pcm[ipcm->substream];
  967. mutex_lock(&emu->fx8010.lock);
  968. spin_lock_irq(&emu->reg_lock);
  969. ipcm->channels = pcm->channels;
  970. ipcm->tram_start = pcm->tram_start;
  971. ipcm->buffer_size = pcm->buffer_size;
  972. ipcm->gpr_size = pcm->gpr_size;
  973. ipcm->gpr_ptr = pcm->gpr_ptr;
  974. ipcm->gpr_count = pcm->gpr_count;
  975. ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
  976. ipcm->gpr_trigger = pcm->gpr_trigger;
  977. ipcm->gpr_running = pcm->gpr_running;
  978. for (i = 0; i < pcm->channels; i++)
  979. ipcm->etram[i] = pcm->etram[i];
  980. ipcm->res1 = ipcm->res2 = 0;
  981. ipcm->pad = 0;
  982. spin_unlock_irq(&emu->reg_lock);
  983. mutex_unlock(&emu->fx8010.lock);
  984. return err;
  985. }
  986. #define SND_EMU10K1_GPR_CONTROLS 44
  987. #define SND_EMU10K1_INPUTS 12
  988. #define SND_EMU10K1_PLAYBACK_CHANNELS 8
  989. #define SND_EMU10K1_CAPTURE_CHANNELS 4
  990. static void __devinit
  991. snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  992. const char *name, int gpr, int defval)
  993. {
  994. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  995. strcpy(ctl->id.name, name);
  996. ctl->vcount = ctl->count = 1;
  997. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  998. if (high_res_gpr_volume) {
  999. ctl->min = 0;
  1000. ctl->max = 0x7fffffff;
  1001. ctl->tlv = snd_emu10k1_db_linear;
  1002. ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
  1003. } else {
  1004. ctl->min = 0;
  1005. ctl->max = 100;
  1006. ctl->tlv = snd_emu10k1_db_scale1;
  1007. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1008. }
  1009. }
  1010. static void __devinit
  1011. snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1012. const char *name, int gpr, int defval)
  1013. {
  1014. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1015. strcpy(ctl->id.name, name);
  1016. ctl->vcount = ctl->count = 2;
  1017. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1018. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1019. if (high_res_gpr_volume) {
  1020. ctl->min = 0;
  1021. ctl->max = 0x7fffffff;
  1022. ctl->tlv = snd_emu10k1_db_linear;
  1023. ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
  1024. } else {
  1025. ctl->min = 0;
  1026. ctl->max = 100;
  1027. ctl->tlv = snd_emu10k1_db_scale1;
  1028. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1029. }
  1030. }
  1031. static void __devinit
  1032. snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1033. const char *name, int gpr, int defval)
  1034. {
  1035. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1036. strcpy(ctl->id.name, name);
  1037. ctl->vcount = ctl->count = 1;
  1038. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1039. ctl->min = 0;
  1040. ctl->max = 1;
  1041. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1042. }
  1043. static void __devinit
  1044. snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1045. const char *name, int gpr, int defval)
  1046. {
  1047. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1048. strcpy(ctl->id.name, name);
  1049. ctl->vcount = ctl->count = 2;
  1050. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1051. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1052. ctl->min = 0;
  1053. ctl->max = 1;
  1054. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1055. }
  1056. /*
  1057. * Used for emu1010 - conversion from 32-bit capture inputs from HANA
  1058. * to 2 x 16-bit registers in audigy - their values are read via DMA.
  1059. * Conversion is performed by Audigy DSP instructions of FX8010.
  1060. */
  1061. static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
  1062. struct snd_emu10k1_fx8010_code *icode,
  1063. u32 *ptr, int tmp, int bit_shifter16,
  1064. int reg_in, int reg_out)
  1065. {
  1066. A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000);
  1067. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000);
  1068. A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2));
  1069. A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000);
  1070. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000);
  1071. A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000);
  1072. A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2));
  1073. A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000);
  1074. return 1;
  1075. }
  1076. /*
  1077. * initial DSP configuration for Audigy
  1078. */
  1079. static int __devinit _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
  1080. {
  1081. int err, i, z, gpr, nctl;
  1082. int bit_shifter16;
  1083. const int playback = 10;
  1084. const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */
  1085. const int stereo_mix = capture + 2;
  1086. const int tmp = 0x88;
  1087. u32 ptr;
  1088. struct snd_emu10k1_fx8010_code *icode = NULL;
  1089. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1090. u32 *gpr_map;
  1091. mm_segment_t seg;
  1092. if ((icode = kzalloc(sizeof(*icode), GFP_KERNEL)) == NULL ||
  1093. (icode->gpr_map = (u_int32_t __user *)
  1094. kcalloc(512 + 256 + 256 + 2 * 1024, sizeof(u_int32_t),
  1095. GFP_KERNEL)) == NULL ||
  1096. (controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1097. sizeof(*controls), GFP_KERNEL)) == NULL) {
  1098. err = -ENOMEM;
  1099. goto __err;
  1100. }
  1101. gpr_map = (u32 __force *)icode->gpr_map;
  1102. icode->tram_data_map = icode->gpr_map + 512;
  1103. icode->tram_addr_map = icode->tram_data_map + 256;
  1104. icode->code = icode->tram_addr_map + 256;
  1105. /* clear free GPRs */
  1106. for (i = 0; i < 512; i++)
  1107. set_bit(i, icode->gpr_valid);
  1108. /* clear TRAM data & address lines */
  1109. for (i = 0; i < 256; i++)
  1110. set_bit(i, icode->tram_valid);
  1111. strcpy(icode->name, "Audigy DSP code for ALSA");
  1112. ptr = 0;
  1113. nctl = 0;
  1114. gpr = stereo_mix + 10;
  1115. gpr_map[gpr++] = 0x00007fff;
  1116. gpr_map[gpr++] = 0x00008000;
  1117. gpr_map[gpr++] = 0x0000ffff;
  1118. bit_shifter16 = gpr;
  1119. /* stop FX processor */
  1120. snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
  1121. #if 1
  1122. /* PCM front Playback Volume (independent from stereo mix)
  1123. * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
  1124. * where gpr contains attenuation from corresponding mixer control
  1125. * (snd_emu10k1_init_stereo_control)
  1126. */
  1127. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
  1128. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
  1129. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
  1130. gpr += 2;
  1131. /* PCM Surround Playback (independent from stereo mix) */
  1132. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
  1133. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
  1134. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
  1135. gpr += 2;
  1136. /* PCM Side Playback (independent from stereo mix) */
  1137. if (emu->card_capabilities->spk71) {
  1138. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
  1139. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
  1140. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
  1141. gpr += 2;
  1142. }
  1143. /* PCM Center Playback (independent from stereo mix) */
  1144. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
  1145. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
  1146. gpr++;
  1147. /* PCM LFE Playback (independent from stereo mix) */
  1148. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
  1149. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
  1150. gpr++;
  1151. /*
  1152. * Stereo Mix
  1153. */
  1154. /* Wave (PCM) Playback Volume (will be renamed later) */
  1155. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1156. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1157. snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
  1158. gpr += 2;
  1159. /* Synth Playback */
  1160. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1161. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1162. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
  1163. gpr += 2;
  1164. /* Wave (PCM) Capture */
  1165. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1166. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1167. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
  1168. gpr += 2;
  1169. /* Synth Capture */
  1170. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1171. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1172. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
  1173. gpr += 2;
  1174. /*
  1175. * inputs
  1176. */
  1177. #define A_ADD_VOLUME_IN(var,vol,input) \
  1178. A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
  1179. /* emu1212 DSP 0 and DSP 1 Capture */
  1180. if (emu->card_capabilities->emu_model) {
  1181. if (emu->card_capabilities->ca0108_chip) {
  1182. /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */
  1183. A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);
  1184. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp));
  1185. A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001);
  1186. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp));
  1187. } else {
  1188. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));
  1189. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));
  1190. }
  1191. snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
  1192. gpr += 2;
  1193. }
  1194. /* AC'97 Playback Volume - used only for mic (renamed later) */
  1195. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
  1196. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
  1197. snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
  1198. gpr += 2;
  1199. /* AC'97 Capture Volume - used only for mic */
  1200. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
  1201. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
  1202. snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
  1203. gpr += 2;
  1204. /* mic capture buffer */
  1205. A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
  1206. /* Audigy CD Playback Volume */
  1207. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
  1208. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1209. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1210. emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
  1211. gpr, 0);
  1212. gpr += 2;
  1213. /* Audigy CD Capture Volume */
  1214. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
  1215. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1216. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1217. emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
  1218. gpr, 0);
  1219. gpr += 2;
  1220. /* Optical SPDIF Playback Volume */
  1221. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
  1222. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1223. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
  1224. gpr += 2;
  1225. /* Optical SPDIF Capture Volume */
  1226. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
  1227. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1228. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
  1229. gpr += 2;
  1230. /* Line2 Playback Volume */
  1231. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
  1232. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
  1233. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1234. emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
  1235. gpr, 0);
  1236. gpr += 2;
  1237. /* Line2 Capture Volume */
  1238. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
  1239. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
  1240. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1241. emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
  1242. gpr, 0);
  1243. gpr += 2;
  1244. /* Philips ADC Playback Volume */
  1245. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
  1246. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
  1247. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
  1248. gpr += 2;
  1249. /* Philips ADC Capture Volume */
  1250. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
  1251. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
  1252. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
  1253. gpr += 2;
  1254. /* Aux2 Playback Volume */
  1255. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
  1256. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
  1257. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1258. emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
  1259. gpr, 0);
  1260. gpr += 2;
  1261. /* Aux2 Capture Volume */
  1262. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
  1263. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
  1264. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1265. emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
  1266. gpr, 0);
  1267. gpr += 2;
  1268. /* Stereo Mix Front Playback Volume */
  1269. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
  1270. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1271. snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
  1272. gpr += 2;
  1273. /* Stereo Mix Surround Playback */
  1274. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
  1275. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1276. snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
  1277. gpr += 2;
  1278. /* Stereo Mix Center Playback */
  1279. /* Center = sub = Left/2 + Right/2 */
  1280. A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
  1281. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
  1282. snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
  1283. gpr++;
  1284. /* Stereo Mix LFE Playback */
  1285. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
  1286. snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
  1287. gpr++;
  1288. if (emu->card_capabilities->spk71) {
  1289. /* Stereo Mix Side Playback */
  1290. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
  1291. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1292. snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
  1293. gpr += 2;
  1294. }
  1295. /*
  1296. * outputs
  1297. */
  1298. #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
  1299. #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
  1300. {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
  1301. #define _A_SWITCH(icode, ptr, dst, src, sw) \
  1302. A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
  1303. #define A_SWITCH(icode, ptr, dst, src, sw) \
  1304. _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
  1305. #define _A_SWITCH_NEG(icode, ptr, dst, src) \
  1306. A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
  1307. #define A_SWITCH_NEG(icode, ptr, dst, src) \
  1308. _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
  1309. /*
  1310. * Process tone control
  1311. */
  1312. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */
  1313. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */
  1314. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */
  1315. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */
  1316. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */
  1317. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */
  1318. if (emu->card_capabilities->spk71) {
  1319. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */
  1320. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */
  1321. }
  1322. ctl = &controls[nctl + 0];
  1323. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1324. strcpy(ctl->id.name, "Tone Control - Bass");
  1325. ctl->vcount = 2;
  1326. ctl->count = 10;
  1327. ctl->min = 0;
  1328. ctl->max = 40;
  1329. ctl->value[0] = ctl->value[1] = 20;
  1330. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1331. ctl = &controls[nctl + 1];
  1332. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1333. strcpy(ctl->id.name, "Tone Control - Treble");
  1334. ctl->vcount = 2;
  1335. ctl->count = 10;
  1336. ctl->min = 0;
  1337. ctl->max = 40;
  1338. ctl->value[0] = ctl->value[1] = 20;
  1339. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1340. #define BASS_GPR 0x8c
  1341. #define TREBLE_GPR 0x96
  1342. for (z = 0; z < 5; z++) {
  1343. int j;
  1344. for (j = 0; j < 2; j++) {
  1345. controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1346. controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1347. }
  1348. }
  1349. for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
  1350. int j, k, l, d;
  1351. for (j = 0; j < 2; j++) { /* left/right */
  1352. k = 0xb0 + (z * 8) + (j * 4);
  1353. l = 0xe0 + (z * 8) + (j * 4);
  1354. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  1355. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));
  1356. A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));
  1357. A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));
  1358. A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));
  1359. A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));
  1360. A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
  1361. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));
  1362. A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));
  1363. A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));
  1364. A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));
  1365. A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));
  1366. A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
  1367. A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
  1368. if (z == 2) /* center */
  1369. break;
  1370. }
  1371. }
  1372. nctl += 2;
  1373. #undef BASS_GPR
  1374. #undef TREBLE_GPR
  1375. for (z = 0; z < 8; z++) {
  1376. A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  1377. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  1378. A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  1379. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1380. }
  1381. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
  1382. gpr += 2;
  1383. /* Master volume (will be renamed later) */
  1384. A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS));
  1385. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS));
  1386. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS));
  1387. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS));
  1388. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS));
  1389. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS));
  1390. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS));
  1391. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS));
  1392. snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
  1393. gpr += 2;
  1394. /* analog speakers */
  1395. A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1396. A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1397. A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1398. A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1399. if (emu->card_capabilities->spk71)
  1400. A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1401. /* headphone */
  1402. A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1403. /* digital outputs */
  1404. /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */
  1405. if (emu->card_capabilities->emu_model) {
  1406. /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
  1407. snd_printk(KERN_INFO "EMU outputs on\n");
  1408. for (z = 0; z < 8; z++) {
  1409. if (emu->card_capabilities->ca0108_chip) {
  1410. A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
  1411. } else {
  1412. A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
  1413. }
  1414. }
  1415. }
  1416. /* IEC958 Optical Raw Playback Switch */
  1417. gpr_map[gpr++] = 0;
  1418. gpr_map[gpr++] = 0x1008;
  1419. gpr_map[gpr++] = 0xffff0000;
  1420. for (z = 0; z < 2; z++) {
  1421. A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
  1422. A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
  1423. A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
  1424. A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
  1425. A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
  1426. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  1427. A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  1428. if ((z==1) && (emu->card_capabilities->spdif_bug)) {
  1429. /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
  1430. snd_printk(KERN_INFO "Installing spdif_bug patch: %s\n", emu->card_capabilities->name);
  1431. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
  1432. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1433. } else {
  1434. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1435. }
  1436. }
  1437. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  1438. gpr += 2;
  1439. A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1440. A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1441. A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1442. /* ADC buffer */
  1443. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  1444. A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1445. #else
  1446. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
  1447. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
  1448. #endif
  1449. if (emu->card_capabilities->emu_model) {
  1450. if (emu->card_capabilities->ca0108_chip) {
  1451. snd_printk(KERN_INFO "EMU2 inputs on\n");
  1452. for (z = 0; z < 0x10; z++) {
  1453. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
  1454. bit_shifter16,
  1455. A3_EMU32IN(z),
  1456. A_FXBUS2(z*2) );
  1457. }
  1458. } else {
  1459. snd_printk(KERN_INFO "EMU inputs on\n");
  1460. /* Capture 16 (originally 8) channels of S32_LE sound */
  1461. /*
  1462. printk(KERN_DEBUG "emufx.c: gpr=0x%x, tmp=0x%x\n",
  1463. gpr, tmp);
  1464. */
  1465. /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */
  1466. /* A_P16VIN(0) is delayed by one sample,
  1467. * so all other A_P16VIN channels will need to also be delayed
  1468. */
  1469. /* Left ADC in. 1 of 2 */
  1470. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
  1471. /* Right ADC in 1 of 2 */
  1472. gpr_map[gpr++] = 0x00000000;
  1473. /* Delaying by one sample: instead of copying the input
  1474. * value A_P16VIN to output A_FXBUS2 as in the first channel,
  1475. * we use an auxiliary register, delaying the value by one
  1476. * sample
  1477. */
  1478. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );
  1479. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
  1480. gpr_map[gpr++] = 0x00000000;
  1481. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) );
  1482. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000);
  1483. gpr_map[gpr++] = 0x00000000;
  1484. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) );
  1485. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000);
  1486. /* For 96kHz mode */
  1487. /* Left ADC in. 2 of 2 */
  1488. gpr_map[gpr++] = 0x00000000;
  1489. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) );
  1490. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000);
  1491. /* Right ADC in 2 of 2 */
  1492. gpr_map[gpr++] = 0x00000000;
  1493. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) );
  1494. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000);
  1495. gpr_map[gpr++] = 0x00000000;
  1496. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) );
  1497. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000);
  1498. gpr_map[gpr++] = 0x00000000;
  1499. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );
  1500. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);
  1501. /* Pavel Hofman - we still have voices, A_FXBUS2s, and
  1502. * A_P16VINs available -
  1503. * let's add 8 more capture channels - total of 16
  1504. */
  1505. gpr_map[gpr++] = 0x00000000;
  1506. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1507. bit_shifter16,
  1508. A_GPR(gpr - 1),
  1509. A_FXBUS2(0x10));
  1510. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),
  1511. A_C_00000000, A_C_00000000);
  1512. gpr_map[gpr++] = 0x00000000;
  1513. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1514. bit_shifter16,
  1515. A_GPR(gpr - 1),
  1516. A_FXBUS2(0x12));
  1517. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),
  1518. A_C_00000000, A_C_00000000);
  1519. gpr_map[gpr++] = 0x00000000;
  1520. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1521. bit_shifter16,
  1522. A_GPR(gpr - 1),
  1523. A_FXBUS2(0x14));
  1524. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),
  1525. A_C_00000000, A_C_00000000);
  1526. gpr_map[gpr++] = 0x00000000;
  1527. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1528. bit_shifter16,
  1529. A_GPR(gpr - 1),
  1530. A_FXBUS2(0x16));
  1531. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),
  1532. A_C_00000000, A_C_00000000);
  1533. gpr_map[gpr++] = 0x00000000;
  1534. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1535. bit_shifter16,
  1536. A_GPR(gpr - 1),
  1537. A_FXBUS2(0x18));
  1538. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),
  1539. A_C_00000000, A_C_00000000);
  1540. gpr_map[gpr++] = 0x00000000;
  1541. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1542. bit_shifter16,
  1543. A_GPR(gpr - 1),
  1544. A_FXBUS2(0x1a));
  1545. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),
  1546. A_C_00000000, A_C_00000000);
  1547. gpr_map[gpr++] = 0x00000000;
  1548. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1549. bit_shifter16,
  1550. A_GPR(gpr - 1),
  1551. A_FXBUS2(0x1c));
  1552. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),
  1553. A_C_00000000, A_C_00000000);
  1554. gpr_map[gpr++] = 0x00000000;
  1555. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1556. bit_shifter16,
  1557. A_GPR(gpr - 1),
  1558. A_FXBUS2(0x1e));
  1559. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),
  1560. A_C_00000000, A_C_00000000);
  1561. }
  1562. #if 0
  1563. for (z = 4; z < 8; z++) {
  1564. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1565. }
  1566. for (z = 0xc; z < 0x10; z++) {
  1567. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1568. }
  1569. #endif
  1570. } else {
  1571. /* EFX capture - capture the 16 EXTINs */
  1572. /* Capture 16 channels of S16_LE sound */
  1573. for (z = 0; z < 16; z++) {
  1574. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
  1575. }
  1576. }
  1577. #endif /* JCD test */
  1578. /*
  1579. * ok, set up done..
  1580. */
  1581. if (gpr > tmp) {
  1582. snd_BUG();
  1583. err = -EIO;
  1584. goto __err;
  1585. }
  1586. /* clear remaining instruction memory */
  1587. while (ptr < 0x400)
  1588. A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
  1589. seg = snd_enter_user();
  1590. icode->gpr_add_control_count = nctl;
  1591. icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
  1592. emu->support_tlv = 1; /* support TLV */
  1593. err = snd_emu10k1_icode_poke(emu, icode);
  1594. emu->support_tlv = 0; /* clear again */
  1595. snd_leave_user(seg);
  1596. __err:
  1597. kfree(controls);
  1598. if (icode != NULL) {
  1599. kfree((void __force *)icode->gpr_map);
  1600. kfree(icode);
  1601. }
  1602. return err;
  1603. }
  1604. /*
  1605. * initial DSP configuration for Emu10k1
  1606. */
  1607. /* when volume = max, then copy only to avoid volume modification */
  1608. /* with iMAC0 (negative values) */
  1609. static void __devinit _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1610. {
  1611. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1612. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1613. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001);
  1614. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1615. }
  1616. static void __devinit _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1617. {
  1618. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1619. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1620. OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001);
  1621. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1622. OP(icode, ptr, iMAC0, dst, dst, src, vol);
  1623. }
  1624. static void __devinit _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1625. {
  1626. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1627. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1628. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1629. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1630. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1631. }
  1632. #define VOLUME(icode, ptr, dst, src, vol) \
  1633. _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1634. #define VOLUME_IN(icode, ptr, dst, src, vol) \
  1635. _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1636. #define VOLUME_ADD(icode, ptr, dst, src, vol) \
  1637. _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1638. #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
  1639. _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1640. #define VOLUME_OUT(icode, ptr, dst, src, vol) \
  1641. _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
  1642. #define _SWITCH(icode, ptr, dst, src, sw) \
  1643. OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
  1644. #define SWITCH(icode, ptr, dst, src, sw) \
  1645. _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
  1646. #define SWITCH_IN(icode, ptr, dst, src, sw) \
  1647. _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
  1648. #define _SWITCH_NEG(icode, ptr, dst, src) \
  1649. OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
  1650. #define SWITCH_NEG(icode, ptr, dst, src) \
  1651. _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
  1652. static int __devinit _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  1653. {
  1654. int err, i, z, gpr, tmp, playback, capture;
  1655. u32 ptr;
  1656. struct snd_emu10k1_fx8010_code *icode;
  1657. struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
  1658. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1659. u32 *gpr_map;
  1660. mm_segment_t seg;
  1661. if ((icode = kzalloc(sizeof(*icode), GFP_KERNEL)) == NULL)
  1662. return -ENOMEM;
  1663. if ((icode->gpr_map = (u_int32_t __user *)
  1664. kcalloc(256 + 160 + 160 + 2 * 512, sizeof(u_int32_t),
  1665. GFP_KERNEL)) == NULL ||
  1666. (controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1667. sizeof(struct snd_emu10k1_fx8010_control_gpr),
  1668. GFP_KERNEL)) == NULL ||
  1669. (ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL)) == NULL) {
  1670. err = -ENOMEM;
  1671. goto __err;
  1672. }
  1673. gpr_map = (u32 __force *)icode->gpr_map;
  1674. icode->tram_data_map = icode->gpr_map + 256;
  1675. icode->tram_addr_map = icode->tram_data_map + 160;
  1676. icode->code = icode->tram_addr_map + 160;
  1677. /* clear free GPRs */
  1678. for (i = 0; i < 256; i++)
  1679. set_bit(i, icode->gpr_valid);
  1680. /* clear TRAM data & address lines */
  1681. for (i = 0; i < 160; i++)
  1682. set_bit(i, icode->tram_valid);
  1683. strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
  1684. ptr = 0; i = 0;
  1685. /* we have 12 inputs */
  1686. playback = SND_EMU10K1_INPUTS;
  1687. /* we have 6 playback channels and tone control doubles */
  1688. capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);
  1689. gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
  1690. tmp = 0x88; /* we need 4 temporary GPR */
  1691. /* from 0x8c to 0xff is the area for tone control */
  1692. /* stop FX processor */
  1693. snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);
  1694. /*
  1695. * Process FX Buses
  1696. */
  1697. OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);
  1698. OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);
  1699. OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);
  1700. OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);
  1701. OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);
  1702. OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);
  1703. OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);
  1704. OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);
  1705. OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
  1706. OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
  1707. OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);
  1708. OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);
  1709. /* Raw S/PDIF PCM */
  1710. ipcm->substream = 0;
  1711. ipcm->channels = 2;
  1712. ipcm->tram_start = 0;
  1713. ipcm->buffer_size = (64 * 1024) / 2;
  1714. ipcm->gpr_size = gpr++;
  1715. ipcm->gpr_ptr = gpr++;
  1716. ipcm->gpr_count = gpr++;
  1717. ipcm->gpr_tmpcount = gpr++;
  1718. ipcm->gpr_trigger = gpr++;
  1719. ipcm->gpr_running = gpr++;
  1720. ipcm->etram[0] = 0;
  1721. ipcm->etram[1] = 1;
  1722. gpr_map[gpr + 0] = 0xfffff000;
  1723. gpr_map[gpr + 1] = 0xffff0000;
  1724. gpr_map[gpr + 2] = 0x70000000;
  1725. gpr_map[gpr + 3] = 0x00000007;
  1726. gpr_map[gpr + 4] = 0x001f << 11;
  1727. gpr_map[gpr + 5] = 0x001c << 11;
  1728. gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
  1729. gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
  1730. gpr_map[gpr + 8] = 0x2000000 + (2<<11);
  1731. gpr_map[gpr + 9] = 0x4000000 + (2<<11);
  1732. gpr_map[gpr + 10] = 1<<11;
  1733. gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
  1734. gpr_map[gpr + 12] = 0;
  1735. /* if the trigger flag is not set, skip */
  1736. /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
  1737. /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
  1738. /* if the running flag is set, we're running */
  1739. /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
  1740. /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
  1741. /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
  1742. /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
  1743. /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
  1744. /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
  1745. /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
  1746. /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
  1747. /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
  1748. /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
  1749. /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
  1750. /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
  1751. /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1752. /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1753. /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1754. /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
  1755. /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
  1756. /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1757. /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1758. /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1759. /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
  1760. /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
  1761. /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
  1762. /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
  1763. /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
  1764. /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
  1765. /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
  1766. /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1767. /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
  1768. /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
  1769. /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
  1770. /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
  1771. /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
  1772. /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
  1773. /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
  1774. /* 24: */
  1775. gpr += 13;
  1776. /* Wave Playback Volume */
  1777. for (z = 0; z < 2; z++)
  1778. VOLUME(icode, &ptr, playback + z, z, gpr + z);
  1779. snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
  1780. gpr += 2;
  1781. /* Wave Surround Playback Volume */
  1782. for (z = 0; z < 2; z++)
  1783. VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
  1784. snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
  1785. gpr += 2;
  1786. /* Wave Center/LFE Playback Volume */
  1787. OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
  1788. OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);
  1789. VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
  1790. snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
  1791. VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
  1792. snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
  1793. /* Wave Capture Volume + Switch */
  1794. for (z = 0; z < 2; z++) {
  1795. SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
  1796. VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1797. }
  1798. snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
  1799. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
  1800. gpr += 4;
  1801. /* Synth Playback Volume */
  1802. for (z = 0; z < 2; z++)
  1803. VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
  1804. snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
  1805. gpr += 2;
  1806. /* Synth Capture Volume + Switch */
  1807. for (z = 0; z < 2; z++) {
  1808. SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
  1809. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1810. }
  1811. snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
  1812. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
  1813. gpr += 4;
  1814. /* Surround Digital Playback Volume (renamed later without Digital) */
  1815. for (z = 0; z < 2; z++)
  1816. VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
  1817. snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
  1818. gpr += 2;
  1819. /* Surround Capture Volume + Switch */
  1820. for (z = 0; z < 2; z++) {
  1821. SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
  1822. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1823. }
  1824. snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
  1825. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
  1826. gpr += 4;
  1827. /* Center Playback Volume (renamed later without Digital) */
  1828. VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
  1829. snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
  1830. /* LFE Playback Volume + Switch (renamed later without Digital) */
  1831. VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
  1832. snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
  1833. /* Front Playback Volume */
  1834. for (z = 0; z < 2; z++)
  1835. VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
  1836. snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
  1837. gpr += 2;
  1838. /* Front Capture Volume + Switch */
  1839. for (z = 0; z < 2; z++) {
  1840. SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
  1841. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1842. }
  1843. snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
  1844. snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
  1845. gpr += 3;
  1846. /*
  1847. * Process inputs
  1848. */
  1849. if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
  1850. /* AC'97 Playback Volume */
  1851. VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
  1852. VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
  1853. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
  1854. /* AC'97 Capture Volume */
  1855. VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
  1856. VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
  1857. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
  1858. }
  1859. if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
  1860. /* IEC958 TTL Playback Volume */
  1861. for (z = 0; z < 2; z++)
  1862. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
  1863. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
  1864. gpr += 2;
  1865. /* IEC958 TTL Capture Volume + Switch */
  1866. for (z = 0; z < 2; z++) {
  1867. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
  1868. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1869. }
  1870. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
  1871. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
  1872. gpr += 4;
  1873. }
  1874. if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
  1875. /* Zoom Video Playback Volume */
  1876. for (z = 0; z < 2; z++)
  1877. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
  1878. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
  1879. gpr += 2;
  1880. /* Zoom Video Capture Volume + Switch */
  1881. for (z = 0; z < 2; z++) {
  1882. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
  1883. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1884. }
  1885. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
  1886. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
  1887. gpr += 4;
  1888. }
  1889. if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
  1890. /* IEC958 Optical Playback Volume */
  1891. for (z = 0; z < 2; z++)
  1892. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
  1893. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
  1894. gpr += 2;
  1895. /* IEC958 Optical Capture Volume */
  1896. for (z = 0; z < 2; z++) {
  1897. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
  1898. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1899. }
  1900. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
  1901. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
  1902. gpr += 4;
  1903. }
  1904. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
  1905. /* Line LiveDrive Playback Volume */
  1906. for (z = 0; z < 2; z++)
  1907. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
  1908. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
  1909. gpr += 2;
  1910. /* Line LiveDrive Capture Volume + Switch */
  1911. for (z = 0; z < 2; z++) {
  1912. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
  1913. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1914. }
  1915. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
  1916. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
  1917. gpr += 4;
  1918. }
  1919. if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
  1920. /* IEC958 Coax Playback Volume */
  1921. for (z = 0; z < 2; z++)
  1922. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
  1923. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
  1924. gpr += 2;
  1925. /* IEC958 Coax Capture Volume + Switch */
  1926. for (z = 0; z < 2; z++) {
  1927. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
  1928. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1929. }
  1930. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
  1931. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
  1932. gpr += 4;
  1933. }
  1934. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
  1935. /* Line LiveDrive Playback Volume */
  1936. for (z = 0; z < 2; z++)
  1937. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
  1938. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
  1939. controls[i-1].id.index = 1;
  1940. gpr += 2;
  1941. /* Line LiveDrive Capture Volume */
  1942. for (z = 0; z < 2; z++) {
  1943. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
  1944. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1945. }
  1946. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
  1947. controls[i-1].id.index = 1;
  1948. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
  1949. controls[i-1].id.index = 1;
  1950. gpr += 4;
  1951. }
  1952. /*
  1953. * Process tone control
  1954. */
  1955. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */
  1956. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */
  1957. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */
  1958. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */
  1959. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */
  1960. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */
  1961. ctl = &controls[i + 0];
  1962. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1963. strcpy(ctl->id.name, "Tone Control - Bass");
  1964. ctl->vcount = 2;
  1965. ctl->count = 10;
  1966. ctl->min = 0;
  1967. ctl->max = 40;
  1968. ctl->value[0] = ctl->value[1] = 20;
  1969. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1970. ctl = &controls[i + 1];
  1971. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1972. strcpy(ctl->id.name, "Tone Control - Treble");
  1973. ctl->vcount = 2;
  1974. ctl->count = 10;
  1975. ctl->min = 0;
  1976. ctl->max = 40;
  1977. ctl->value[0] = ctl->value[1] = 20;
  1978. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1979. #define BASS_GPR 0x8c
  1980. #define TREBLE_GPR 0x96
  1981. for (z = 0; z < 5; z++) {
  1982. int j;
  1983. for (j = 0; j < 2; j++) {
  1984. controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1985. controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1986. }
  1987. }
  1988. for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
  1989. int j, k, l, d;
  1990. for (j = 0; j < 2; j++) { /* left/right */
  1991. k = 0xa0 + (z * 8) + (j * 4);
  1992. l = 0xd0 + (z * 8) + (j * 4);
  1993. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  1994. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
  1995. OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
  1996. OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
  1997. OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
  1998. OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
  1999. OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
  2000. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
  2001. OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
  2002. OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
  2003. OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
  2004. OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
  2005. OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
  2006. OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
  2007. if (z == 2) /* center */
  2008. break;
  2009. }
  2010. }
  2011. i += 2;
  2012. #undef BASS_GPR
  2013. #undef TREBLE_GPR
  2014. for (z = 0; z < 6; z++) {
  2015. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  2016. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  2017. SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  2018. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2019. }
  2020. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
  2021. gpr += 2;
  2022. /*
  2023. * Process outputs
  2024. */
  2025. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
  2026. /* AC'97 Playback Volume */
  2027. for (z = 0; z < 2; z++)
  2028. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);
  2029. }
  2030. if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
  2031. /* IEC958 Optical Raw Playback Switch */
  2032. for (z = 0; z < 2; z++) {
  2033. SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
  2034. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  2035. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  2036. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2037. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  2038. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2039. #endif
  2040. }
  2041. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  2042. gpr += 2;
  2043. }
  2044. if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
  2045. /* Headphone Playback Volume */
  2046. for (z = 0; z < 2; z++) {
  2047. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);
  2048. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
  2049. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  2050. OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2051. VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
  2052. }
  2053. snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
  2054. controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
  2055. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
  2056. controls[i-1].id.index = 1;
  2057. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
  2058. controls[i-1].id.index = 1;
  2059. gpr += 4;
  2060. }
  2061. if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
  2062. for (z = 0; z < 2; z++)
  2063. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2064. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
  2065. for (z = 0; z < 2; z++)
  2066. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2067. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
  2068. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2069. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2070. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2071. #else
  2072. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2073. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2074. #endif
  2075. }
  2076. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
  2077. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2078. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2079. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2080. #else
  2081. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2082. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2083. #endif
  2084. }
  2085. #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
  2086. for (z = 0; z < 2; z++)
  2087. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
  2088. #endif
  2089. if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
  2090. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
  2091. /* EFX capture - capture the 16 EXTINS */
  2092. if (emu->card_capabilities->sblive51) {
  2093. /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER
  2094. * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
  2095. *
  2096. * Since only 14 of the 16 EXTINs are used, this is not a big problem.
  2097. * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture
  2098. * 0 and 3, then the rest of the EXTINs to the corresponding FX capture
  2099. * channel. Multitrack recorders will still see the center/lfe output signal
  2100. * on the second and third channels.
  2101. */
  2102. OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));
  2103. OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));
  2104. OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));
  2105. OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));
  2106. for (z = 4; z < 14; z++)
  2107. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2108. } else {
  2109. for (z = 0; z < 16; z++)
  2110. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2111. }
  2112. if (gpr > tmp) {
  2113. snd_BUG();
  2114. err = -EIO;
  2115. goto __err;
  2116. }
  2117. if (i > SND_EMU10K1_GPR_CONTROLS) {
  2118. snd_BUG();
  2119. err = -EIO;
  2120. goto __err;
  2121. }
  2122. /* clear remaining instruction memory */
  2123. while (ptr < 0x200)
  2124. OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
  2125. if ((err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size)) < 0)
  2126. goto __err;
  2127. seg = snd_enter_user();
  2128. icode->gpr_add_control_count = i;
  2129. icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
  2130. emu->support_tlv = 1; /* support TLV */
  2131. err = snd_emu10k1_icode_poke(emu, icode);
  2132. emu->support_tlv = 0; /* clear again */
  2133. snd_leave_user(seg);
  2134. if (err >= 0)
  2135. err = snd_emu10k1_ipcm_poke(emu, ipcm);
  2136. __err:
  2137. kfree(ipcm);
  2138. kfree(controls);
  2139. if (icode != NULL) {
  2140. kfree((void __force *)icode->gpr_map);
  2141. kfree(icode);
  2142. }
  2143. return err;
  2144. }
  2145. int __devinit snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  2146. {
  2147. spin_lock_init(&emu->fx8010.irq_lock);
  2148. INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
  2149. if (emu->audigy)
  2150. return _snd_emu10k1_audigy_init_efx(emu);
  2151. else
  2152. return _snd_emu10k1_init_efx(emu);
  2153. }
  2154. void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
  2155. {
  2156. /* stop processor */
  2157. if (emu->audigy)
  2158. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
  2159. else
  2160. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
  2161. }
  2162. #if 0 /* FIXME: who use them? */
  2163. int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
  2164. {
  2165. if (output < 0 || output >= 6)
  2166. return -EINVAL;
  2167. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
  2168. return 0;
  2169. }
  2170. int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
  2171. {
  2172. if (output < 0 || output >= 6)
  2173. return -EINVAL;
  2174. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
  2175. return 0;
  2176. }
  2177. #endif
  2178. int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
  2179. {
  2180. u8 size_reg = 0;
  2181. /* size is in samples */
  2182. if (size != 0) {
  2183. size = (size - 1) >> 13;
  2184. while (size) {
  2185. size >>= 1;
  2186. size_reg++;
  2187. }
  2188. size = 0x2000 << size_reg;
  2189. }
  2190. if ((emu->fx8010.etram_pages.bytes / 2) == size)
  2191. return 0;
  2192. spin_lock_irq(&emu->emu_lock);
  2193. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2194. spin_unlock_irq(&emu->emu_lock);
  2195. snd_emu10k1_ptr_write(emu, TCB, 0, 0);
  2196. snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
  2197. if (emu->fx8010.etram_pages.area != NULL) {
  2198. snd_dma_free_pages(&emu->fx8010.etram_pages);
  2199. emu->fx8010.etram_pages.area = NULL;
  2200. emu->fx8010.etram_pages.bytes = 0;
  2201. }
  2202. if (size > 0) {
  2203. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(emu->pci),
  2204. size * 2, &emu->fx8010.etram_pages) < 0)
  2205. return -ENOMEM;
  2206. memset(emu->fx8010.etram_pages.area, 0, size * 2);
  2207. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2208. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2209. spin_lock_irq(&emu->emu_lock);
  2210. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2211. spin_unlock_irq(&emu->emu_lock);
  2212. }
  2213. return 0;
  2214. }
  2215. static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
  2216. {
  2217. return 0;
  2218. }
  2219. static void copy_string(char *dst, char *src, char *null, int idx)
  2220. {
  2221. if (src == NULL)
  2222. sprintf(dst, "%s %02X", null, idx);
  2223. else
  2224. strcpy(dst, src);
  2225. }
  2226. static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
  2227. struct snd_emu10k1_fx8010_info *info)
  2228. {
  2229. char **fxbus, **extin, **extout;
  2230. unsigned short fxbus_mask, extin_mask, extout_mask;
  2231. int res;
  2232. info->internal_tram_size = emu->fx8010.itram_size;
  2233. info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
  2234. fxbus = fxbuses;
  2235. extin = emu->audigy ? audigy_ins : creative_ins;
  2236. extout = emu->audigy ? audigy_outs : creative_outs;
  2237. fxbus_mask = emu->fx8010.fxbus_mask;
  2238. extin_mask = emu->fx8010.extin_mask;
  2239. extout_mask = emu->fx8010.extout_mask;
  2240. for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
  2241. copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);
  2242. copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
  2243. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2244. }
  2245. for (res = 16; res < 32; res++, extout++)
  2246. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2247. info->gpr_controls = emu->fx8010.gpr_count;
  2248. }
  2249. static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
  2250. {
  2251. struct snd_emu10k1 *emu = hw->private_data;
  2252. struct snd_emu10k1_fx8010_info *info;
  2253. struct snd_emu10k1_fx8010_code *icode;
  2254. struct snd_emu10k1_fx8010_pcm_rec *ipcm;
  2255. unsigned int addr;
  2256. void __user *argp = (void __user *)arg;
  2257. int res;
  2258. switch (cmd) {
  2259. case SNDRV_EMU10K1_IOCTL_PVERSION:
  2260. emu->support_tlv = 1;
  2261. return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
  2262. case SNDRV_EMU10K1_IOCTL_INFO:
  2263. info = kmalloc(sizeof(*info), GFP_KERNEL);
  2264. if (!info)
  2265. return -ENOMEM;
  2266. snd_emu10k1_fx8010_info(emu, info);
  2267. if (copy_to_user(argp, info, sizeof(*info))) {
  2268. kfree(info);
  2269. return -EFAULT;
  2270. }
  2271. kfree(info);
  2272. return 0;
  2273. case SNDRV_EMU10K1_IOCTL_CODE_POKE:
  2274. if (!capable(CAP_SYS_ADMIN))
  2275. return -EPERM;
  2276. icode = memdup_user(argp, sizeof(*icode));
  2277. if (IS_ERR(icode))
  2278. return PTR_ERR(icode);
  2279. res = snd_emu10k1_icode_poke(emu, icode);
  2280. kfree(icode);
  2281. return res;
  2282. case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
  2283. icode = memdup_user(argp, sizeof(*icode));
  2284. if (IS_ERR(icode))
  2285. return PTR_ERR(icode);
  2286. res = snd_emu10k1_icode_peek(emu, icode);
  2287. if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
  2288. kfree(icode);
  2289. return -EFAULT;
  2290. }
  2291. kfree(icode);
  2292. return res;
  2293. case SNDRV_EMU10K1_IOCTL_PCM_POKE:
  2294. ipcm = memdup_user(argp, sizeof(*ipcm));
  2295. if (IS_ERR(ipcm))
  2296. return PTR_ERR(ipcm);
  2297. res = snd_emu10k1_ipcm_poke(emu, ipcm);
  2298. kfree(ipcm);
  2299. return res;
  2300. case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
  2301. ipcm = memdup_user(argp, sizeof(*ipcm));
  2302. if (IS_ERR(ipcm))
  2303. return PTR_ERR(ipcm);
  2304. res = snd_emu10k1_ipcm_peek(emu, ipcm);
  2305. if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
  2306. kfree(ipcm);
  2307. return -EFAULT;
  2308. }
  2309. kfree(ipcm);
  2310. return res;
  2311. case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
  2312. if (!capable(CAP_SYS_ADMIN))
  2313. return -EPERM;
  2314. if (get_user(addr, (unsigned int __user *)argp))
  2315. return -EFAULT;
  2316. mutex_lock(&emu->fx8010.lock);
  2317. res = snd_emu10k1_fx8010_tram_setup(emu, addr);
  2318. mutex_unlock(&emu->fx8010.lock);
  2319. return res;
  2320. case SNDRV_EMU10K1_IOCTL_STOP:
  2321. if (!capable(CAP_SYS_ADMIN))
  2322. return -EPERM;
  2323. if (emu->audigy)
  2324. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
  2325. else
  2326. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
  2327. return 0;
  2328. case SNDRV_EMU10K1_IOCTL_CONTINUE:
  2329. if (!capable(CAP_SYS_ADMIN))
  2330. return -EPERM;
  2331. if (emu->audigy)
  2332. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
  2333. else
  2334. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
  2335. return 0;
  2336. case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
  2337. if (!capable(CAP_SYS_ADMIN))
  2338. return -EPERM;
  2339. if (emu->audigy)
  2340. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
  2341. else
  2342. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
  2343. udelay(10);
  2344. if (emu->audigy)
  2345. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2346. else
  2347. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2348. return 0;
  2349. case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
  2350. if (!capable(CAP_SYS_ADMIN))
  2351. return -EPERM;
  2352. if (get_user(addr, (unsigned int __user *)argp))
  2353. return -EFAULT;
  2354. if (addr > 0x1ff)
  2355. return -EINVAL;
  2356. if (emu->audigy)
  2357. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr);
  2358. else
  2359. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr);
  2360. udelay(10);
  2361. if (emu->audigy)
  2362. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr);
  2363. else
  2364. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr);
  2365. return 0;
  2366. case SNDRV_EMU10K1_IOCTL_DBG_READ:
  2367. if (emu->audigy)
  2368. addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
  2369. else
  2370. addr = snd_emu10k1_ptr_read(emu, DBG, 0);
  2371. if (put_user(addr, (unsigned int __user *)argp))
  2372. return -EFAULT;
  2373. return 0;
  2374. }
  2375. return -ENOTTY;
  2376. }
  2377. static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
  2378. {
  2379. return 0;
  2380. }
  2381. int __devinit snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep)
  2382. {
  2383. struct snd_hwdep *hw;
  2384. int err;
  2385. if (rhwdep)
  2386. *rhwdep = NULL;
  2387. if ((err = snd_hwdep_new(emu->card, "FX8010", device, &hw)) < 0)
  2388. return err;
  2389. strcpy(hw->name, "EMU10K1 (FX8010)");
  2390. hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
  2391. hw->ops.open = snd_emu10k1_fx8010_open;
  2392. hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
  2393. hw->ops.release = snd_emu10k1_fx8010_release;
  2394. hw->private_data = emu;
  2395. if (rhwdep)
  2396. *rhwdep = hw;
  2397. return 0;
  2398. }
  2399. #ifdef CONFIG_PM
  2400. int __devinit snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
  2401. {
  2402. int len;
  2403. len = emu->audigy ? 0x200 : 0x100;
  2404. emu->saved_gpr = kmalloc(len * 4, GFP_KERNEL);
  2405. if (! emu->saved_gpr)
  2406. return -ENOMEM;
  2407. len = emu->audigy ? 0x100 : 0xa0;
  2408. emu->tram_val_saved = kmalloc(len * 4, GFP_KERNEL);
  2409. emu->tram_addr_saved = kmalloc(len * 4, GFP_KERNEL);
  2410. if (! emu->tram_val_saved || ! emu->tram_addr_saved)
  2411. return -ENOMEM;
  2412. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2413. emu->saved_icode = vmalloc(len * 4);
  2414. if (! emu->saved_icode)
  2415. return -ENOMEM;
  2416. return 0;
  2417. }
  2418. void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
  2419. {
  2420. kfree(emu->saved_gpr);
  2421. kfree(emu->tram_val_saved);
  2422. kfree(emu->tram_addr_saved);
  2423. vfree(emu->saved_icode);
  2424. }
  2425. /*
  2426. * save/restore GPR, TRAM and codes
  2427. */
  2428. void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
  2429. {
  2430. int i, len;
  2431. len = emu->audigy ? 0x200 : 0x100;
  2432. for (i = 0; i < len; i++)
  2433. emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
  2434. len = emu->audigy ? 0x100 : 0xa0;
  2435. for (i = 0; i < len; i++) {
  2436. emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
  2437. emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
  2438. if (emu->audigy) {
  2439. emu->tram_addr_saved[i] >>= 12;
  2440. emu->tram_addr_saved[i] |=
  2441. snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
  2442. }
  2443. }
  2444. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2445. for (i = 0; i < len; i++)
  2446. emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
  2447. }
  2448. void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
  2449. {
  2450. int i, len;
  2451. /* set up TRAM */
  2452. if (emu->fx8010.etram_pages.bytes > 0) {
  2453. unsigned size, size_reg = 0;
  2454. size = emu->fx8010.etram_pages.bytes / 2;
  2455. size = (size - 1) >> 13;
  2456. while (size) {
  2457. size >>= 1;
  2458. size_reg++;
  2459. }
  2460. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2461. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2462. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2463. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2464. }
  2465. if (emu->audigy)
  2466. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  2467. else
  2468. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  2469. len = emu->audigy ? 0x200 : 0x100;
  2470. for (i = 0; i < len; i++)
  2471. snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
  2472. len = emu->audigy ? 0x100 : 0xa0;
  2473. for (i = 0; i < len; i++) {
  2474. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
  2475. emu->tram_val_saved[i]);
  2476. if (! emu->audigy)
  2477. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2478. emu->tram_addr_saved[i]);
  2479. else {
  2480. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2481. emu->tram_addr_saved[i] << 12);
  2482. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2483. emu->tram_addr_saved[i] >> 20);
  2484. }
  2485. }
  2486. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2487. for (i = 0; i < len; i++)
  2488. snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
  2489. /* start FX processor when the DSP code is updated */
  2490. if (emu->audigy)
  2491. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2492. else
  2493. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2494. }
  2495. #endif