dsp_spos.c 55 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License as published by
  4. * the Free Software Foundation; either version 2 of the License, or
  5. * (at your option) any later version.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  15. *
  16. */
  17. /*
  18. * 2002-07 Benny Sjostrand benny@hostmobility.com
  19. */
  20. #include <asm/io.h>
  21. #include <linux/delay.h>
  22. #include <linux/pm.h>
  23. #include <linux/init.h>
  24. #include <linux/slab.h>
  25. #include <linux/vmalloc.h>
  26. #include <linux/mutex.h>
  27. #include <sound/core.h>
  28. #include <sound/control.h>
  29. #include <sound/info.h>
  30. #include <sound/asoundef.h>
  31. #include <sound/cs46xx.h>
  32. #include "cs46xx_lib.h"
  33. #include "dsp_spos.h"
  34. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  35. struct dsp_scb_descriptor * fg_entry);
  36. static enum wide_opcode wide_opcodes[] = {
  37. WIDE_FOR_BEGIN_LOOP,
  38. WIDE_FOR_BEGIN_LOOP2,
  39. WIDE_COND_GOTO_ADDR,
  40. WIDE_COND_GOTO_CALL,
  41. WIDE_TBEQ_COND_GOTO_ADDR,
  42. WIDE_TBEQ_COND_CALL_ADDR,
  43. WIDE_TBEQ_NCOND_GOTO_ADDR,
  44. WIDE_TBEQ_NCOND_CALL_ADDR,
  45. WIDE_TBEQ_COND_GOTO1_ADDR,
  46. WIDE_TBEQ_COND_CALL1_ADDR,
  47. WIDE_TBEQ_NCOND_GOTOI_ADDR,
  48. WIDE_TBEQ_NCOND_CALL1_ADDR
  49. };
  50. static int shadow_and_reallocate_code (struct snd_cs46xx * chip, u32 * data, u32 size,
  51. u32 overlay_begin_address)
  52. {
  53. unsigned int i = 0, j, nreallocated = 0;
  54. u32 hival,loval,address;
  55. u32 mop_operands,mop_type,wide_op;
  56. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  57. if (snd_BUG_ON(size %2))
  58. return -EINVAL;
  59. while (i < size) {
  60. loval = data[i++];
  61. hival = data[i++];
  62. if (ins->code.offset > 0) {
  63. mop_operands = (hival >> 6) & 0x03fff;
  64. mop_type = mop_operands >> 10;
  65. /* check for wide type instruction */
  66. if (mop_type == 0 &&
  67. (mop_operands & WIDE_LADD_INSTR_MASK) == 0 &&
  68. (mop_operands & WIDE_INSTR_MASK) != 0) {
  69. wide_op = loval & 0x7f;
  70. for (j = 0;j < ARRAY_SIZE(wide_opcodes); ++j) {
  71. if (wide_opcodes[j] == wide_op) {
  72. /* need to reallocate instruction */
  73. address = (hival & 0x00FFF) << 5;
  74. address |= loval >> 15;
  75. snd_printdd("handle_wideop[1]: %05x:%05x addr %04x\n",hival,loval,address);
  76. if ( !(address & 0x8000) ) {
  77. address += (ins->code.offset / 2) - overlay_begin_address;
  78. } else {
  79. snd_printdd("handle_wideop[1]: ROM symbol not reallocated\n");
  80. }
  81. hival &= 0xFF000;
  82. loval &= 0x07FFF;
  83. hival |= ( (address >> 5) & 0x00FFF);
  84. loval |= ( (address << 15) & 0xF8000);
  85. address = (hival & 0x00FFF) << 5;
  86. address |= loval >> 15;
  87. snd_printdd("handle_wideop:[2] %05x:%05x addr %04x\n",hival,loval,address);
  88. nreallocated ++;
  89. } /* wide_opcodes[j] == wide_op */
  90. } /* for */
  91. } /* mod_type == 0 ... */
  92. } /* ins->code.offset > 0 */
  93. ins->code.data[ins->code.size++] = loval;
  94. ins->code.data[ins->code.size++] = hival;
  95. }
  96. snd_printdd("dsp_spos: %d instructions reallocated\n",nreallocated);
  97. return nreallocated;
  98. }
  99. static struct dsp_segment_desc * get_segment_desc (struct dsp_module_desc * module, int seg_type)
  100. {
  101. int i;
  102. for (i = 0;i < module->nsegments; ++i) {
  103. if (module->segments[i].segment_type == seg_type) {
  104. return (module->segments + i);
  105. }
  106. }
  107. return NULL;
  108. };
  109. static int find_free_symbol_index (struct dsp_spos_instance * ins)
  110. {
  111. int index = ins->symbol_table.nsymbols,i;
  112. for (i = ins->symbol_table.highest_frag_index; i < ins->symbol_table.nsymbols; ++i) {
  113. if (ins->symbol_table.symbols[i].deleted) {
  114. index = i;
  115. break;
  116. }
  117. }
  118. return index;
  119. }
  120. static int add_symbols (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  121. {
  122. int i;
  123. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  124. if (module->symbol_table.nsymbols > 0) {
  125. if (!strcmp(module->symbol_table.symbols[0].symbol_name, "OVERLAYBEGINADDRESS") &&
  126. module->symbol_table.symbols[0].symbol_type == SYMBOL_CONSTANT ) {
  127. module->overlay_begin_address = module->symbol_table.symbols[0].address;
  128. }
  129. }
  130. for (i = 0;i < module->symbol_table.nsymbols; ++i) {
  131. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  132. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  133. return -ENOMEM;
  134. }
  135. if (cs46xx_dsp_lookup_symbol(chip,
  136. module->symbol_table.symbols[i].symbol_name,
  137. module->symbol_table.symbols[i].symbol_type) == NULL) {
  138. ins->symbol_table.symbols[ins->symbol_table.nsymbols] = module->symbol_table.symbols[i];
  139. ins->symbol_table.symbols[ins->symbol_table.nsymbols].address += ((ins->code.offset / 2) - module->overlay_begin_address);
  140. ins->symbol_table.symbols[ins->symbol_table.nsymbols].module = module;
  141. ins->symbol_table.symbols[ins->symbol_table.nsymbols].deleted = 0;
  142. if (ins->symbol_table.nsymbols > ins->symbol_table.highest_frag_index)
  143. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  144. ins->symbol_table.nsymbols++;
  145. } else {
  146. /* if (0) printk ("dsp_spos: symbol <%s> duplicated, probably nothing wrong with that (Cirrus?)\n",
  147. module->symbol_table.symbols[i].symbol_name); */
  148. }
  149. }
  150. return 0;
  151. }
  152. static struct dsp_symbol_entry *
  153. add_symbol (struct snd_cs46xx * chip, char * symbol_name, u32 address, int type)
  154. {
  155. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  156. struct dsp_symbol_entry * symbol = NULL;
  157. int index;
  158. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  159. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  160. return NULL;
  161. }
  162. if (cs46xx_dsp_lookup_symbol(chip,
  163. symbol_name,
  164. type) != NULL) {
  165. snd_printk(KERN_ERR "dsp_spos: symbol <%s> duplicated\n", symbol_name);
  166. return NULL;
  167. }
  168. index = find_free_symbol_index (ins);
  169. strcpy (ins->symbol_table.symbols[index].symbol_name, symbol_name);
  170. ins->symbol_table.symbols[index].address = address;
  171. ins->symbol_table.symbols[index].symbol_type = type;
  172. ins->symbol_table.symbols[index].module = NULL;
  173. ins->symbol_table.symbols[index].deleted = 0;
  174. symbol = (ins->symbol_table.symbols + index);
  175. if (index > ins->symbol_table.highest_frag_index)
  176. ins->symbol_table.highest_frag_index = index;
  177. if (index == ins->symbol_table.nsymbols)
  178. ins->symbol_table.nsymbols++; /* no frag. in list */
  179. return symbol;
  180. }
  181. struct dsp_spos_instance *cs46xx_dsp_spos_create (struct snd_cs46xx * chip)
  182. {
  183. struct dsp_spos_instance * ins = kzalloc(sizeof(struct dsp_spos_instance), GFP_KERNEL);
  184. if (ins == NULL)
  185. return NULL;
  186. /* better to use vmalloc for this big table */
  187. ins->symbol_table.nsymbols = 0;
  188. ins->symbol_table.symbols = vmalloc(sizeof(struct dsp_symbol_entry) *
  189. DSP_MAX_SYMBOLS);
  190. ins->symbol_table.highest_frag_index = 0;
  191. if (ins->symbol_table.symbols == NULL) {
  192. cs46xx_dsp_spos_destroy(chip);
  193. goto error;
  194. }
  195. ins->code.offset = 0;
  196. ins->code.size = 0;
  197. ins->code.data = kmalloc(DSP_CODE_BYTE_SIZE, GFP_KERNEL);
  198. if (ins->code.data == NULL) {
  199. cs46xx_dsp_spos_destroy(chip);
  200. goto error;
  201. }
  202. ins->nscb = 0;
  203. ins->ntask = 0;
  204. ins->nmodules = 0;
  205. ins->modules = kmalloc(sizeof(struct dsp_module_desc) * DSP_MAX_MODULES, GFP_KERNEL);
  206. if (ins->modules == NULL) {
  207. cs46xx_dsp_spos_destroy(chip);
  208. goto error;
  209. }
  210. /* default SPDIF input sample rate
  211. to 48000 khz */
  212. ins->spdif_in_sample_rate = 48000;
  213. /* maximize volume */
  214. ins->dac_volume_right = 0x8000;
  215. ins->dac_volume_left = 0x8000;
  216. ins->spdif_input_volume_right = 0x8000;
  217. ins->spdif_input_volume_left = 0x8000;
  218. /* set left and right validity bits and
  219. default channel status */
  220. ins->spdif_csuv_default =
  221. ins->spdif_csuv_stream =
  222. /* byte 0 */ ((unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF & 0xff)) << 24) |
  223. /* byte 1 */ ((unsigned int)_wrap_all_bits( ((SNDRV_PCM_DEFAULT_CON_SPDIF >> 8) & 0xff)) << 16) |
  224. /* byte 3 */ (unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF >> 24) & 0xff) |
  225. /* left and right validity bits */ (1 << 13) | (1 << 12);
  226. return ins;
  227. error:
  228. kfree(ins);
  229. return NULL;
  230. }
  231. void cs46xx_dsp_spos_destroy (struct snd_cs46xx * chip)
  232. {
  233. int i;
  234. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  235. if (snd_BUG_ON(!ins))
  236. return;
  237. mutex_lock(&chip->spos_mutex);
  238. for (i = 0; i < ins->nscb; ++i) {
  239. if (ins->scbs[i].deleted) continue;
  240. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  241. #ifdef CONFIG_PM
  242. kfree(ins->scbs[i].data);
  243. #endif
  244. }
  245. kfree(ins->code.data);
  246. vfree(ins->symbol_table.symbols);
  247. kfree(ins->modules);
  248. kfree(ins);
  249. mutex_unlock(&chip->spos_mutex);
  250. }
  251. static int dsp_load_parameter(struct snd_cs46xx *chip,
  252. struct dsp_segment_desc *parameter)
  253. {
  254. u32 doffset, dsize;
  255. if (!parameter) {
  256. snd_printdd("dsp_spos: module got no parameter segment\n");
  257. return 0;
  258. }
  259. doffset = (parameter->offset * 4 + DSP_PARAMETER_BYTE_OFFSET);
  260. dsize = parameter->size * 4;
  261. snd_printdd("dsp_spos: "
  262. "downloading parameter data to chip (%08x-%08x)\n",
  263. doffset,doffset + dsize);
  264. if (snd_cs46xx_download (chip, parameter->data, doffset, dsize)) {
  265. snd_printk(KERN_ERR "dsp_spos: "
  266. "failed to download parameter data to DSP\n");
  267. return -EINVAL;
  268. }
  269. return 0;
  270. }
  271. static int dsp_load_sample(struct snd_cs46xx *chip,
  272. struct dsp_segment_desc *sample)
  273. {
  274. u32 doffset, dsize;
  275. if (!sample) {
  276. snd_printdd("dsp_spos: module got no sample segment\n");
  277. return 0;
  278. }
  279. doffset = (sample->offset * 4 + DSP_SAMPLE_BYTE_OFFSET);
  280. dsize = sample->size * 4;
  281. snd_printdd("dsp_spos: downloading sample data to chip (%08x-%08x)\n",
  282. doffset,doffset + dsize);
  283. if (snd_cs46xx_download (chip,sample->data,doffset,dsize)) {
  284. snd_printk(KERN_ERR "dsp_spos: failed to sample data to DSP\n");
  285. return -EINVAL;
  286. }
  287. return 0;
  288. }
  289. int cs46xx_dsp_load_module (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  290. {
  291. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  292. struct dsp_segment_desc * code = get_segment_desc (module,SEGTYPE_SP_PROGRAM);
  293. u32 doffset, dsize;
  294. int err;
  295. if (ins->nmodules == DSP_MAX_MODULES - 1) {
  296. snd_printk(KERN_ERR "dsp_spos: to many modules loaded into DSP\n");
  297. return -ENOMEM;
  298. }
  299. snd_printdd("dsp_spos: loading module %s into DSP\n", module->module_name);
  300. if (ins->nmodules == 0) {
  301. snd_printdd("dsp_spos: clearing parameter area\n");
  302. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET, DSP_PARAMETER_BYTE_SIZE);
  303. }
  304. err = dsp_load_parameter(chip, get_segment_desc(module,
  305. SEGTYPE_SP_PARAMETER));
  306. if (err < 0)
  307. return err;
  308. if (ins->nmodules == 0) {
  309. snd_printdd("dsp_spos: clearing sample area\n");
  310. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET, DSP_SAMPLE_BYTE_SIZE);
  311. }
  312. err = dsp_load_sample(chip, get_segment_desc(module,
  313. SEGTYPE_SP_SAMPLE));
  314. if (err < 0)
  315. return err;
  316. if (ins->nmodules == 0) {
  317. snd_printdd("dsp_spos: clearing code area\n");
  318. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  319. }
  320. if (code == NULL) {
  321. snd_printdd("dsp_spos: module got no code segment\n");
  322. } else {
  323. if (ins->code.offset + code->size > DSP_CODE_BYTE_SIZE) {
  324. snd_printk(KERN_ERR "dsp_spos: no space available in DSP\n");
  325. return -ENOMEM;
  326. }
  327. module->load_address = ins->code.offset;
  328. module->overlay_begin_address = 0x000;
  329. /* if module has a code segment it must have
  330. symbol table */
  331. if (snd_BUG_ON(!module->symbol_table.symbols))
  332. return -ENOMEM;
  333. if (add_symbols(chip,module)) {
  334. snd_printk(KERN_ERR "dsp_spos: failed to load symbol table\n");
  335. return -ENOMEM;
  336. }
  337. doffset = (code->offset * 4 + ins->code.offset * 4 + DSP_CODE_BYTE_OFFSET);
  338. dsize = code->size * 4;
  339. snd_printdd("dsp_spos: downloading code to chip (%08x-%08x)\n",
  340. doffset,doffset + dsize);
  341. module->nfixups = shadow_and_reallocate_code(chip,code->data,code->size,module->overlay_begin_address);
  342. if (snd_cs46xx_download (chip,(ins->code.data + ins->code.offset),doffset,dsize)) {
  343. snd_printk(KERN_ERR "dsp_spos: failed to download code to DSP\n");
  344. return -EINVAL;
  345. }
  346. ins->code.offset += code->size;
  347. }
  348. /* NOTE: module segments and symbol table must be
  349. statically allocated. Case that module data is
  350. not generated by the ospparser */
  351. ins->modules[ins->nmodules] = *module;
  352. ins->nmodules++;
  353. return 0;
  354. }
  355. struct dsp_symbol_entry *
  356. cs46xx_dsp_lookup_symbol (struct snd_cs46xx * chip, char * symbol_name, int symbol_type)
  357. {
  358. int i;
  359. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  360. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  361. if (ins->symbol_table.symbols[i].deleted)
  362. continue;
  363. if (!strcmp(ins->symbol_table.symbols[i].symbol_name,symbol_name) &&
  364. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  365. return (ins->symbol_table.symbols + i);
  366. }
  367. }
  368. #if 0
  369. printk ("dsp_spos: symbol <%s> type %02x not found\n",
  370. symbol_name,symbol_type);
  371. #endif
  372. return NULL;
  373. }
  374. #ifdef CONFIG_PROC_FS
  375. static struct dsp_symbol_entry *
  376. cs46xx_dsp_lookup_symbol_addr (struct snd_cs46xx * chip, u32 address, int symbol_type)
  377. {
  378. int i;
  379. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  380. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  381. if (ins->symbol_table.symbols[i].deleted)
  382. continue;
  383. if (ins->symbol_table.symbols[i].address == address &&
  384. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  385. return (ins->symbol_table.symbols + i);
  386. }
  387. }
  388. return NULL;
  389. }
  390. static void cs46xx_dsp_proc_symbol_table_read (struct snd_info_entry *entry,
  391. struct snd_info_buffer *buffer)
  392. {
  393. struct snd_cs46xx *chip = entry->private_data;
  394. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  395. int i;
  396. snd_iprintf(buffer, "SYMBOLS:\n");
  397. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  398. char *module_str = "system";
  399. if (ins->symbol_table.symbols[i].deleted)
  400. continue;
  401. if (ins->symbol_table.symbols[i].module != NULL) {
  402. module_str = ins->symbol_table.symbols[i].module->module_name;
  403. }
  404. snd_iprintf(buffer, "%04X <%02X> %s [%s]\n",
  405. ins->symbol_table.symbols[i].address,
  406. ins->symbol_table.symbols[i].symbol_type,
  407. ins->symbol_table.symbols[i].symbol_name,
  408. module_str);
  409. }
  410. }
  411. static void cs46xx_dsp_proc_modules_read (struct snd_info_entry *entry,
  412. struct snd_info_buffer *buffer)
  413. {
  414. struct snd_cs46xx *chip = entry->private_data;
  415. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  416. int i,j;
  417. mutex_lock(&chip->spos_mutex);
  418. snd_iprintf(buffer, "MODULES:\n");
  419. for ( i = 0; i < ins->nmodules; ++i ) {
  420. snd_iprintf(buffer, "\n%s:\n", ins->modules[i].module_name);
  421. snd_iprintf(buffer, " %d symbols\n", ins->modules[i].symbol_table.nsymbols);
  422. snd_iprintf(buffer, " %d fixups\n", ins->modules[i].nfixups);
  423. for (j = 0; j < ins->modules[i].nsegments; ++ j) {
  424. struct dsp_segment_desc * desc = (ins->modules[i].segments + j);
  425. snd_iprintf(buffer, " segment %02x offset %08x size %08x\n",
  426. desc->segment_type,desc->offset, desc->size);
  427. }
  428. }
  429. mutex_unlock(&chip->spos_mutex);
  430. }
  431. static void cs46xx_dsp_proc_task_tree_read (struct snd_info_entry *entry,
  432. struct snd_info_buffer *buffer)
  433. {
  434. struct snd_cs46xx *chip = entry->private_data;
  435. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  436. int i, j, col;
  437. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  438. mutex_lock(&chip->spos_mutex);
  439. snd_iprintf(buffer, "TASK TREES:\n");
  440. for ( i = 0; i < ins->ntask; ++i) {
  441. snd_iprintf(buffer,"\n%04x %s:\n",ins->tasks[i].address,ins->tasks[i].task_name);
  442. for (col = 0,j = 0;j < ins->tasks[i].size; j++,col++) {
  443. u32 val;
  444. if (col == 4) {
  445. snd_iprintf(buffer,"\n");
  446. col = 0;
  447. }
  448. val = readl(dst + (ins->tasks[i].address + j) * sizeof(u32));
  449. snd_iprintf(buffer,"%08x ",val);
  450. }
  451. }
  452. snd_iprintf(buffer,"\n");
  453. mutex_unlock(&chip->spos_mutex);
  454. }
  455. static void cs46xx_dsp_proc_scb_read (struct snd_info_entry *entry,
  456. struct snd_info_buffer *buffer)
  457. {
  458. struct snd_cs46xx *chip = entry->private_data;
  459. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  460. int i;
  461. mutex_lock(&chip->spos_mutex);
  462. snd_iprintf(buffer, "SCB's:\n");
  463. for ( i = 0; i < ins->nscb; ++i) {
  464. if (ins->scbs[i].deleted)
  465. continue;
  466. snd_iprintf(buffer,"\n%04x %s:\n\n",ins->scbs[i].address,ins->scbs[i].scb_name);
  467. if (ins->scbs[i].parent_scb_ptr != NULL) {
  468. snd_iprintf(buffer,"parent [%s:%04x] ",
  469. ins->scbs[i].parent_scb_ptr->scb_name,
  470. ins->scbs[i].parent_scb_ptr->address);
  471. } else snd_iprintf(buffer,"parent [none] ");
  472. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  473. ins->scbs[i].sub_list_ptr->scb_name,
  474. ins->scbs[i].sub_list_ptr->address,
  475. ins->scbs[i].next_scb_ptr->scb_name,
  476. ins->scbs[i].next_scb_ptr->address,
  477. ins->scbs[i].task_entry->symbol_name,
  478. ins->scbs[i].task_entry->address);
  479. }
  480. snd_iprintf(buffer,"\n");
  481. mutex_unlock(&chip->spos_mutex);
  482. }
  483. static void cs46xx_dsp_proc_parameter_dump_read (struct snd_info_entry *entry,
  484. struct snd_info_buffer *buffer)
  485. {
  486. struct snd_cs46xx *chip = entry->private_data;
  487. /*struct dsp_spos_instance * ins = chip->dsp_spos_instance; */
  488. unsigned int i, col = 0;
  489. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  490. struct dsp_symbol_entry * symbol;
  491. for (i = 0;i < DSP_PARAMETER_BYTE_SIZE; i += sizeof(u32),col ++) {
  492. if (col == 4) {
  493. snd_iprintf(buffer,"\n");
  494. col = 0;
  495. }
  496. if ( (symbol = cs46xx_dsp_lookup_symbol_addr (chip,i / sizeof(u32), SYMBOL_PARAMETER)) != NULL) {
  497. col = 0;
  498. snd_iprintf (buffer,"\n%s:\n",symbol->symbol_name);
  499. }
  500. if (col == 0) {
  501. snd_iprintf(buffer, "%04X ", i / (unsigned int)sizeof(u32));
  502. }
  503. snd_iprintf(buffer,"%08X ",readl(dst + i));
  504. }
  505. }
  506. static void cs46xx_dsp_proc_sample_dump_read (struct snd_info_entry *entry,
  507. struct snd_info_buffer *buffer)
  508. {
  509. struct snd_cs46xx *chip = entry->private_data;
  510. int i,col = 0;
  511. void __iomem *dst = chip->region.idx[2].remap_addr;
  512. snd_iprintf(buffer,"PCMREADER:\n");
  513. for (i = PCM_READER_BUF1;i < PCM_READER_BUF1 + 0x30; i += sizeof(u32),col ++) {
  514. if (col == 4) {
  515. snd_iprintf(buffer,"\n");
  516. col = 0;
  517. }
  518. if (col == 0) {
  519. snd_iprintf(buffer, "%04X ",i);
  520. }
  521. snd_iprintf(buffer,"%08X ",readl(dst + i));
  522. }
  523. snd_iprintf(buffer,"\nMIX_SAMPLE_BUF1:\n");
  524. col = 0;
  525. for (i = MIX_SAMPLE_BUF1;i < MIX_SAMPLE_BUF1 + 0x40; i += sizeof(u32),col ++) {
  526. if (col == 4) {
  527. snd_iprintf(buffer,"\n");
  528. col = 0;
  529. }
  530. if (col == 0) {
  531. snd_iprintf(buffer, "%04X ",i);
  532. }
  533. snd_iprintf(buffer,"%08X ",readl(dst + i));
  534. }
  535. snd_iprintf(buffer,"\nSRC_TASK_SCB1:\n");
  536. col = 0;
  537. for (i = 0x2480 ; i < 0x2480 + 0x40 ; i += sizeof(u32),col ++) {
  538. if (col == 4) {
  539. snd_iprintf(buffer,"\n");
  540. col = 0;
  541. }
  542. if (col == 0) {
  543. snd_iprintf(buffer, "%04X ",i);
  544. }
  545. snd_iprintf(buffer,"%08X ",readl(dst + i));
  546. }
  547. snd_iprintf(buffer,"\nSPDIFO_BUFFER:\n");
  548. col = 0;
  549. for (i = SPDIFO_IP_OUTPUT_BUFFER1;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x30; i += sizeof(u32),col ++) {
  550. if (col == 4) {
  551. snd_iprintf(buffer,"\n");
  552. col = 0;
  553. }
  554. if (col == 0) {
  555. snd_iprintf(buffer, "%04X ",i);
  556. }
  557. snd_iprintf(buffer,"%08X ",readl(dst + i));
  558. }
  559. snd_iprintf(buffer,"\n...\n");
  560. col = 0;
  561. for (i = SPDIFO_IP_OUTPUT_BUFFER1+0xD0;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x110; i += sizeof(u32),col ++) {
  562. if (col == 4) {
  563. snd_iprintf(buffer,"\n");
  564. col = 0;
  565. }
  566. if (col == 0) {
  567. snd_iprintf(buffer, "%04X ",i);
  568. }
  569. snd_iprintf(buffer,"%08X ",readl(dst + i));
  570. }
  571. snd_iprintf(buffer,"\nOUTPUT_SNOOP:\n");
  572. col = 0;
  573. for (i = OUTPUT_SNOOP_BUFFER;i < OUTPUT_SNOOP_BUFFER + 0x40; i += sizeof(u32),col ++) {
  574. if (col == 4) {
  575. snd_iprintf(buffer,"\n");
  576. col = 0;
  577. }
  578. if (col == 0) {
  579. snd_iprintf(buffer, "%04X ",i);
  580. }
  581. snd_iprintf(buffer,"%08X ",readl(dst + i));
  582. }
  583. snd_iprintf(buffer,"\nCODEC_INPUT_BUF1: \n");
  584. col = 0;
  585. for (i = CODEC_INPUT_BUF1;i < CODEC_INPUT_BUF1 + 0x40; i += sizeof(u32),col ++) {
  586. if (col == 4) {
  587. snd_iprintf(buffer,"\n");
  588. col = 0;
  589. }
  590. if (col == 0) {
  591. snd_iprintf(buffer, "%04X ",i);
  592. }
  593. snd_iprintf(buffer,"%08X ",readl(dst + i));
  594. }
  595. #if 0
  596. snd_iprintf(buffer,"\nWRITE_BACK_BUF1: \n");
  597. col = 0;
  598. for (i = WRITE_BACK_BUF1;i < WRITE_BACK_BUF1 + 0x40; i += sizeof(u32),col ++) {
  599. if (col == 4) {
  600. snd_iprintf(buffer,"\n");
  601. col = 0;
  602. }
  603. if (col == 0) {
  604. snd_iprintf(buffer, "%04X ",i);
  605. }
  606. snd_iprintf(buffer,"%08X ",readl(dst + i));
  607. }
  608. #endif
  609. snd_iprintf(buffer,"\nSPDIFI_IP_OUTPUT_BUFFER1: \n");
  610. col = 0;
  611. for (i = SPDIFI_IP_OUTPUT_BUFFER1;i < SPDIFI_IP_OUTPUT_BUFFER1 + 0x80; i += sizeof(u32),col ++) {
  612. if (col == 4) {
  613. snd_iprintf(buffer,"\n");
  614. col = 0;
  615. }
  616. if (col == 0) {
  617. snd_iprintf(buffer, "%04X ",i);
  618. }
  619. snd_iprintf(buffer,"%08X ",readl(dst + i));
  620. }
  621. snd_iprintf(buffer,"\n");
  622. }
  623. int cs46xx_dsp_proc_init (struct snd_card *card, struct snd_cs46xx *chip)
  624. {
  625. struct snd_info_entry *entry;
  626. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  627. int i;
  628. ins->snd_card = card;
  629. if ((entry = snd_info_create_card_entry(card, "dsp", card->proc_root)) != NULL) {
  630. entry->content = SNDRV_INFO_CONTENT_TEXT;
  631. entry->mode = S_IFDIR | S_IRUGO | S_IXUGO;
  632. if (snd_info_register(entry) < 0) {
  633. snd_info_free_entry(entry);
  634. entry = NULL;
  635. }
  636. }
  637. ins->proc_dsp_dir = entry;
  638. if (!ins->proc_dsp_dir)
  639. return -ENOMEM;
  640. if ((entry = snd_info_create_card_entry(card, "spos_symbols", ins->proc_dsp_dir)) != NULL) {
  641. entry->content = SNDRV_INFO_CONTENT_TEXT;
  642. entry->private_data = chip;
  643. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  644. entry->c.text.read = cs46xx_dsp_proc_symbol_table_read;
  645. if (snd_info_register(entry) < 0) {
  646. snd_info_free_entry(entry);
  647. entry = NULL;
  648. }
  649. }
  650. ins->proc_sym_info_entry = entry;
  651. if ((entry = snd_info_create_card_entry(card, "spos_modules", ins->proc_dsp_dir)) != NULL) {
  652. entry->content = SNDRV_INFO_CONTENT_TEXT;
  653. entry->private_data = chip;
  654. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  655. entry->c.text.read = cs46xx_dsp_proc_modules_read;
  656. if (snd_info_register(entry) < 0) {
  657. snd_info_free_entry(entry);
  658. entry = NULL;
  659. }
  660. }
  661. ins->proc_modules_info_entry = entry;
  662. if ((entry = snd_info_create_card_entry(card, "parameter", ins->proc_dsp_dir)) != NULL) {
  663. entry->content = SNDRV_INFO_CONTENT_TEXT;
  664. entry->private_data = chip;
  665. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  666. entry->c.text.read = cs46xx_dsp_proc_parameter_dump_read;
  667. if (snd_info_register(entry) < 0) {
  668. snd_info_free_entry(entry);
  669. entry = NULL;
  670. }
  671. }
  672. ins->proc_parameter_dump_info_entry = entry;
  673. if ((entry = snd_info_create_card_entry(card, "sample", ins->proc_dsp_dir)) != NULL) {
  674. entry->content = SNDRV_INFO_CONTENT_TEXT;
  675. entry->private_data = chip;
  676. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  677. entry->c.text.read = cs46xx_dsp_proc_sample_dump_read;
  678. if (snd_info_register(entry) < 0) {
  679. snd_info_free_entry(entry);
  680. entry = NULL;
  681. }
  682. }
  683. ins->proc_sample_dump_info_entry = entry;
  684. if ((entry = snd_info_create_card_entry(card, "task_tree", ins->proc_dsp_dir)) != NULL) {
  685. entry->content = SNDRV_INFO_CONTENT_TEXT;
  686. entry->private_data = chip;
  687. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  688. entry->c.text.read = cs46xx_dsp_proc_task_tree_read;
  689. if (snd_info_register(entry) < 0) {
  690. snd_info_free_entry(entry);
  691. entry = NULL;
  692. }
  693. }
  694. ins->proc_task_info_entry = entry;
  695. if ((entry = snd_info_create_card_entry(card, "scb_info", ins->proc_dsp_dir)) != NULL) {
  696. entry->content = SNDRV_INFO_CONTENT_TEXT;
  697. entry->private_data = chip;
  698. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  699. entry->c.text.read = cs46xx_dsp_proc_scb_read;
  700. if (snd_info_register(entry) < 0) {
  701. snd_info_free_entry(entry);
  702. entry = NULL;
  703. }
  704. }
  705. ins->proc_scb_info_entry = entry;
  706. mutex_lock(&chip->spos_mutex);
  707. /* register/update SCB's entries on proc */
  708. for (i = 0; i < ins->nscb; ++i) {
  709. if (ins->scbs[i].deleted) continue;
  710. cs46xx_dsp_proc_register_scb_desc (chip, (ins->scbs + i));
  711. }
  712. mutex_unlock(&chip->spos_mutex);
  713. return 0;
  714. }
  715. int cs46xx_dsp_proc_done (struct snd_cs46xx *chip)
  716. {
  717. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  718. int i;
  719. snd_info_free_entry(ins->proc_sym_info_entry);
  720. ins->proc_sym_info_entry = NULL;
  721. snd_info_free_entry(ins->proc_modules_info_entry);
  722. ins->proc_modules_info_entry = NULL;
  723. snd_info_free_entry(ins->proc_parameter_dump_info_entry);
  724. ins->proc_parameter_dump_info_entry = NULL;
  725. snd_info_free_entry(ins->proc_sample_dump_info_entry);
  726. ins->proc_sample_dump_info_entry = NULL;
  727. snd_info_free_entry(ins->proc_scb_info_entry);
  728. ins->proc_scb_info_entry = NULL;
  729. snd_info_free_entry(ins->proc_task_info_entry);
  730. ins->proc_task_info_entry = NULL;
  731. mutex_lock(&chip->spos_mutex);
  732. for (i = 0; i < ins->nscb; ++i) {
  733. if (ins->scbs[i].deleted) continue;
  734. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  735. }
  736. mutex_unlock(&chip->spos_mutex);
  737. snd_info_free_entry(ins->proc_dsp_dir);
  738. ins->proc_dsp_dir = NULL;
  739. return 0;
  740. }
  741. #endif /* CONFIG_PROC_FS */
  742. static int debug_tree;
  743. static void _dsp_create_task_tree (struct snd_cs46xx *chip, u32 * task_data,
  744. u32 dest, int size)
  745. {
  746. void __iomem *spdst = chip->region.idx[1].remap_addr +
  747. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  748. int i;
  749. for (i = 0; i < size; ++i) {
  750. if (debug_tree) printk ("addr %p, val %08x\n",spdst,task_data[i]);
  751. writel(task_data[i],spdst);
  752. spdst += sizeof(u32);
  753. }
  754. }
  755. static int debug_scb;
  756. static void _dsp_create_scb (struct snd_cs46xx *chip, u32 * scb_data, u32 dest)
  757. {
  758. void __iomem *spdst = chip->region.idx[1].remap_addr +
  759. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  760. int i;
  761. for (i = 0; i < 0x10; ++i) {
  762. if (debug_scb) printk ("addr %p, val %08x\n",spdst,scb_data[i]);
  763. writel(scb_data[i],spdst);
  764. spdst += sizeof(u32);
  765. }
  766. }
  767. static int find_free_scb_index (struct dsp_spos_instance * ins)
  768. {
  769. int index = ins->nscb, i;
  770. for (i = ins->scb_highest_frag_index; i < ins->nscb; ++i) {
  771. if (ins->scbs[i].deleted) {
  772. index = i;
  773. break;
  774. }
  775. }
  776. return index;
  777. }
  778. static struct dsp_scb_descriptor * _map_scb (struct snd_cs46xx *chip, char * name, u32 dest)
  779. {
  780. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  781. struct dsp_scb_descriptor * desc = NULL;
  782. int index;
  783. if (ins->nscb == DSP_MAX_SCB_DESC - 1) {
  784. snd_printk(KERN_ERR "dsp_spos: got no place for other SCB\n");
  785. return NULL;
  786. }
  787. index = find_free_scb_index (ins);
  788. memset(&ins->scbs[index], 0, sizeof(ins->scbs[index]));
  789. strcpy(ins->scbs[index].scb_name, name);
  790. ins->scbs[index].address = dest;
  791. ins->scbs[index].index = index;
  792. ins->scbs[index].ref_count = 1;
  793. desc = (ins->scbs + index);
  794. ins->scbs[index].scb_symbol = add_symbol (chip, name, dest, SYMBOL_PARAMETER);
  795. if (index > ins->scb_highest_frag_index)
  796. ins->scb_highest_frag_index = index;
  797. if (index == ins->nscb)
  798. ins->nscb++;
  799. return desc;
  800. }
  801. static struct dsp_task_descriptor *
  802. _map_task_tree (struct snd_cs46xx *chip, char * name, u32 dest, u32 size)
  803. {
  804. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  805. struct dsp_task_descriptor * desc = NULL;
  806. if (ins->ntask == DSP_MAX_TASK_DESC - 1) {
  807. snd_printk(KERN_ERR "dsp_spos: got no place for other TASK\n");
  808. return NULL;
  809. }
  810. if (name)
  811. strcpy(ins->tasks[ins->ntask].task_name, name);
  812. else
  813. strcpy(ins->tasks[ins->ntask].task_name, "(NULL)");
  814. ins->tasks[ins->ntask].address = dest;
  815. ins->tasks[ins->ntask].size = size;
  816. /* quick find in list */
  817. ins->tasks[ins->ntask].index = ins->ntask;
  818. desc = (ins->tasks + ins->ntask);
  819. ins->ntask++;
  820. if (name)
  821. add_symbol (chip,name,dest,SYMBOL_PARAMETER);
  822. return desc;
  823. }
  824. #define SCB_BYTES (0x10 * 4)
  825. struct dsp_scb_descriptor *
  826. cs46xx_dsp_create_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest)
  827. {
  828. struct dsp_scb_descriptor * desc;
  829. #ifdef CONFIG_PM
  830. /* copy the data for resume */
  831. scb_data = kmemdup(scb_data, SCB_BYTES, GFP_KERNEL);
  832. if (!scb_data)
  833. return NULL;
  834. #endif
  835. desc = _map_scb (chip,name,dest);
  836. if (desc) {
  837. desc->data = scb_data;
  838. _dsp_create_scb(chip,scb_data,dest);
  839. } else {
  840. snd_printk(KERN_ERR "dsp_spos: failed to map SCB\n");
  841. #ifdef CONFIG_PM
  842. kfree(scb_data);
  843. #endif
  844. }
  845. return desc;
  846. }
  847. static struct dsp_task_descriptor *
  848. cs46xx_dsp_create_task_tree (struct snd_cs46xx *chip, char * name, u32 * task_data,
  849. u32 dest, int size)
  850. {
  851. struct dsp_task_descriptor * desc;
  852. desc = _map_task_tree (chip,name,dest,size);
  853. if (desc) {
  854. desc->data = task_data;
  855. _dsp_create_task_tree(chip,task_data,dest,size);
  856. } else {
  857. snd_printk(KERN_ERR "dsp_spos: failed to map TASK\n");
  858. }
  859. return desc;
  860. }
  861. int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip)
  862. {
  863. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  864. struct dsp_symbol_entry * fg_task_tree_header_code;
  865. struct dsp_symbol_entry * task_tree_header_code;
  866. struct dsp_symbol_entry * task_tree_thread;
  867. struct dsp_symbol_entry * null_algorithm;
  868. struct dsp_symbol_entry * magic_snoop_task;
  869. struct dsp_scb_descriptor * timing_master_scb;
  870. struct dsp_scb_descriptor * codec_out_scb;
  871. struct dsp_scb_descriptor * codec_in_scb;
  872. struct dsp_scb_descriptor * src_task_scb;
  873. struct dsp_scb_descriptor * master_mix_scb;
  874. struct dsp_scb_descriptor * rear_mix_scb;
  875. struct dsp_scb_descriptor * record_mix_scb;
  876. struct dsp_scb_descriptor * write_back_scb;
  877. struct dsp_scb_descriptor * vari_decimate_scb;
  878. struct dsp_scb_descriptor * rear_codec_out_scb;
  879. struct dsp_scb_descriptor * clfe_codec_out_scb;
  880. struct dsp_scb_descriptor * magic_snoop_scb;
  881. int fifo_addr, fifo_span, valid_slots;
  882. static struct dsp_spos_control_block sposcb = {
  883. /* 0 */ HFG_TREE_SCB,HFG_STACK,
  884. /* 1 */ SPOSCB_ADDR,BG_TREE_SCB_ADDR,
  885. /* 2 */ DSP_SPOS_DC,0,
  886. /* 3 */ DSP_SPOS_DC,DSP_SPOS_DC,
  887. /* 4 */ 0,0,
  888. /* 5 */ DSP_SPOS_UU,0,
  889. /* 6 */ FG_TASK_HEADER_ADDR,0,
  890. /* 7 */ 0,0,
  891. /* 8 */ DSP_SPOS_UU,DSP_SPOS_DC,
  892. /* 9 */ 0,
  893. /* A */ 0,HFG_FIRST_EXECUTE_MODE,
  894. /* B */ DSP_SPOS_UU,DSP_SPOS_UU,
  895. /* C */ DSP_SPOS_DC_DC,
  896. /* D */ DSP_SPOS_DC_DC,
  897. /* E */ DSP_SPOS_DC_DC,
  898. /* F */ DSP_SPOS_DC_DC
  899. };
  900. cs46xx_dsp_create_task_tree(chip, "sposCB", (u32 *)&sposcb, SPOSCB_ADDR, 0x10);
  901. null_algorithm = cs46xx_dsp_lookup_symbol(chip, "NULLALGORITHM", SYMBOL_CODE);
  902. if (null_algorithm == NULL) {
  903. snd_printk(KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  904. return -EIO;
  905. }
  906. fg_task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "FGTASKTREEHEADERCODE", SYMBOL_CODE);
  907. if (fg_task_tree_header_code == NULL) {
  908. snd_printk(KERN_ERR "dsp_spos: symbol FGTASKTREEHEADERCODE not found\n");
  909. return -EIO;
  910. }
  911. task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "TASKTREEHEADERCODE", SYMBOL_CODE);
  912. if (task_tree_header_code == NULL) {
  913. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREEHEADERCODE not found\n");
  914. return -EIO;
  915. }
  916. task_tree_thread = cs46xx_dsp_lookup_symbol(chip, "TASKTREETHREAD", SYMBOL_CODE);
  917. if (task_tree_thread == NULL) {
  918. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREETHREAD not found\n");
  919. return -EIO;
  920. }
  921. magic_snoop_task = cs46xx_dsp_lookup_symbol(chip, "MAGICSNOOPTASK", SYMBOL_CODE);
  922. if (magic_snoop_task == NULL) {
  923. snd_printk(KERN_ERR "dsp_spos: symbol MAGICSNOOPTASK not found\n");
  924. return -EIO;
  925. }
  926. {
  927. /* create the null SCB */
  928. static struct dsp_generic_scb null_scb = {
  929. { 0, 0, 0, 0 },
  930. { 0, 0, 0, 0, 0 },
  931. NULL_SCB_ADDR, NULL_SCB_ADDR,
  932. 0, 0, 0, 0, 0,
  933. {
  934. 0,0,
  935. 0,0,
  936. }
  937. };
  938. null_scb.entry_point = null_algorithm->address;
  939. ins->the_null_scb = cs46xx_dsp_create_scb(chip, "nullSCB", (u32 *)&null_scb, NULL_SCB_ADDR);
  940. ins->the_null_scb->task_entry = null_algorithm;
  941. ins->the_null_scb->sub_list_ptr = ins->the_null_scb;
  942. ins->the_null_scb->next_scb_ptr = ins->the_null_scb;
  943. ins->the_null_scb->parent_scb_ptr = NULL;
  944. cs46xx_dsp_proc_register_scb_desc (chip,ins->the_null_scb);
  945. }
  946. {
  947. /* setup foreground task tree */
  948. static struct dsp_task_tree_control_block fg_task_tree_hdr = {
  949. { FG_TASK_HEADER_ADDR | (DSP_SPOS_DC << 0x10),
  950. DSP_SPOS_DC_DC,
  951. DSP_SPOS_DC_DC,
  952. 0x0000,DSP_SPOS_DC,
  953. DSP_SPOS_DC, DSP_SPOS_DC,
  954. DSP_SPOS_DC_DC,
  955. DSP_SPOS_DC_DC,
  956. DSP_SPOS_DC_DC,
  957. DSP_SPOS_DC,DSP_SPOS_DC },
  958. {
  959. BG_TREE_SCB_ADDR,TIMINGMASTER_SCB_ADDR,
  960. 0,
  961. FG_TASK_HEADER_ADDR + TCBData,
  962. },
  963. {
  964. 4,0,
  965. 1,0,
  966. 2,SPOSCB_ADDR + HFGFlags,
  967. 0,0,
  968. FG_TASK_HEADER_ADDR + TCBContextBlk,FG_STACK
  969. },
  970. {
  971. DSP_SPOS_DC,0,
  972. DSP_SPOS_DC,DSP_SPOS_DC,
  973. DSP_SPOS_DC,DSP_SPOS_DC,
  974. DSP_SPOS_DC,DSP_SPOS_DC,
  975. DSP_SPOS_DC,DSP_SPOS_DC,
  976. DSP_SPOS_DCDC,
  977. DSP_SPOS_UU,1,
  978. DSP_SPOS_DCDC,
  979. DSP_SPOS_DCDC,
  980. DSP_SPOS_DCDC,
  981. DSP_SPOS_DCDC,
  982. DSP_SPOS_DCDC,
  983. DSP_SPOS_DCDC,
  984. DSP_SPOS_DCDC,
  985. DSP_SPOS_DCDC,
  986. DSP_SPOS_DCDC,
  987. DSP_SPOS_DCDC,
  988. DSP_SPOS_DCDC,
  989. DSP_SPOS_DCDC,
  990. DSP_SPOS_DCDC,
  991. DSP_SPOS_DCDC,
  992. DSP_SPOS_DCDC,
  993. DSP_SPOS_DCDC,
  994. DSP_SPOS_DCDC,
  995. DSP_SPOS_DCDC,
  996. DSP_SPOS_DCDC,
  997. DSP_SPOS_DCDC,
  998. DSP_SPOS_DCDC,
  999. DSP_SPOS_DCDC,
  1000. DSP_SPOS_DCDC,
  1001. DSP_SPOS_DCDC,
  1002. DSP_SPOS_DCDC,
  1003. DSP_SPOS_DCDC,
  1004. DSP_SPOS_DCDC,
  1005. DSP_SPOS_DCDC
  1006. },
  1007. {
  1008. FG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  1009. 0,0
  1010. }
  1011. };
  1012. fg_task_tree_hdr.links.entry_point = fg_task_tree_header_code->address;
  1013. fg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1014. cs46xx_dsp_create_task_tree(chip,"FGtaskTreeHdr",(u32 *)&fg_task_tree_hdr,FG_TASK_HEADER_ADDR,0x35);
  1015. }
  1016. {
  1017. /* setup foreground task tree */
  1018. static struct dsp_task_tree_control_block bg_task_tree_hdr = {
  1019. { DSP_SPOS_DC_DC,
  1020. DSP_SPOS_DC_DC,
  1021. DSP_SPOS_DC_DC,
  1022. DSP_SPOS_DC, DSP_SPOS_DC,
  1023. DSP_SPOS_DC, DSP_SPOS_DC,
  1024. DSP_SPOS_DC_DC,
  1025. DSP_SPOS_DC_DC,
  1026. DSP_SPOS_DC_DC,
  1027. DSP_SPOS_DC,DSP_SPOS_DC },
  1028. {
  1029. NULL_SCB_ADDR,NULL_SCB_ADDR, /* Set up the background to do nothing */
  1030. 0,
  1031. BG_TREE_SCB_ADDR + TCBData,
  1032. },
  1033. {
  1034. 9999,0,
  1035. 0,1,
  1036. 0,SPOSCB_ADDR + HFGFlags,
  1037. 0,0,
  1038. BG_TREE_SCB_ADDR + TCBContextBlk,BG_STACK
  1039. },
  1040. {
  1041. DSP_SPOS_DC,0,
  1042. DSP_SPOS_DC,DSP_SPOS_DC,
  1043. DSP_SPOS_DC,DSP_SPOS_DC,
  1044. DSP_SPOS_DC,DSP_SPOS_DC,
  1045. DSP_SPOS_DC,DSP_SPOS_DC,
  1046. DSP_SPOS_DCDC,
  1047. DSP_SPOS_UU,1,
  1048. DSP_SPOS_DCDC,
  1049. DSP_SPOS_DCDC,
  1050. DSP_SPOS_DCDC,
  1051. DSP_SPOS_DCDC,
  1052. DSP_SPOS_DCDC,
  1053. DSP_SPOS_DCDC,
  1054. DSP_SPOS_DCDC,
  1055. DSP_SPOS_DCDC,
  1056. DSP_SPOS_DCDC,
  1057. DSP_SPOS_DCDC,
  1058. DSP_SPOS_DCDC,
  1059. DSP_SPOS_DCDC,
  1060. DSP_SPOS_DCDC,
  1061. DSP_SPOS_DCDC,
  1062. DSP_SPOS_DCDC,
  1063. DSP_SPOS_DCDC,
  1064. DSP_SPOS_DCDC,
  1065. DSP_SPOS_DCDC,
  1066. DSP_SPOS_DCDC,
  1067. DSP_SPOS_DCDC,
  1068. DSP_SPOS_DCDC,
  1069. DSP_SPOS_DCDC,
  1070. DSP_SPOS_DCDC,
  1071. DSP_SPOS_DCDC,
  1072. DSP_SPOS_DCDC,
  1073. DSP_SPOS_DCDC,
  1074. DSP_SPOS_DCDC,
  1075. DSP_SPOS_DCDC
  1076. },
  1077. {
  1078. BG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  1079. 0,0
  1080. }
  1081. };
  1082. bg_task_tree_hdr.links.entry_point = task_tree_header_code->address;
  1083. bg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1084. cs46xx_dsp_create_task_tree(chip,"BGtaskTreeHdr",(u32 *)&bg_task_tree_hdr,BG_TREE_SCB_ADDR,0x35);
  1085. }
  1086. /* create timing master SCB */
  1087. timing_master_scb = cs46xx_dsp_create_timing_master_scb(chip);
  1088. /* create the CODEC output task */
  1089. codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_I",0x0010,0x0000,
  1090. MASTERMIX_SCB_ADDR,
  1091. CODECOUT_SCB_ADDR,timing_master_scb,
  1092. SCB_ON_PARENT_SUBLIST_SCB);
  1093. if (!codec_out_scb) goto _fail_end;
  1094. /* create the master mix SCB */
  1095. master_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"MasterMixSCB",
  1096. MIX_SAMPLE_BUF1,MASTERMIX_SCB_ADDR,
  1097. codec_out_scb,
  1098. SCB_ON_PARENT_SUBLIST_SCB);
  1099. ins->master_mix_scb = master_mix_scb;
  1100. if (!master_mix_scb) goto _fail_end;
  1101. /* create codec in */
  1102. codec_in_scb = cs46xx_dsp_create_codec_in_scb(chip,"CodecInSCB",0x0010,0x00A0,
  1103. CODEC_INPUT_BUF1,
  1104. CODECIN_SCB_ADDR,codec_out_scb,
  1105. SCB_ON_PARENT_NEXT_SCB);
  1106. if (!codec_in_scb) goto _fail_end;
  1107. ins->codec_in_scb = codec_in_scb;
  1108. /* create write back scb */
  1109. write_back_scb = cs46xx_dsp_create_mix_to_ostream_scb(chip,"WriteBackSCB",
  1110. WRITE_BACK_BUF1,WRITE_BACK_SPB,
  1111. WRITEBACK_SCB_ADDR,
  1112. timing_master_scb,
  1113. SCB_ON_PARENT_NEXT_SCB);
  1114. if (!write_back_scb) goto _fail_end;
  1115. {
  1116. static struct dsp_mix2_ostream_spb mix2_ostream_spb = {
  1117. 0x00020000,
  1118. 0x0000ffff
  1119. };
  1120. if (!cs46xx_dsp_create_task_tree(chip, NULL,
  1121. (u32 *)&mix2_ostream_spb,
  1122. WRITE_BACK_SPB, 2))
  1123. goto _fail_end;
  1124. }
  1125. /* input sample converter */
  1126. vari_decimate_scb = cs46xx_dsp_create_vari_decimate_scb(chip,"VariDecimateSCB",
  1127. VARI_DECIMATE_BUF0,
  1128. VARI_DECIMATE_BUF1,
  1129. VARIDECIMATE_SCB_ADDR,
  1130. write_back_scb,
  1131. SCB_ON_PARENT_SUBLIST_SCB);
  1132. if (!vari_decimate_scb) goto _fail_end;
  1133. /* create the record mixer SCB */
  1134. record_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RecordMixerSCB",
  1135. MIX_SAMPLE_BUF2,
  1136. RECORD_MIXER_SCB_ADDR,
  1137. vari_decimate_scb,
  1138. SCB_ON_PARENT_SUBLIST_SCB);
  1139. ins->record_mixer_scb = record_mix_scb;
  1140. if (!record_mix_scb) goto _fail_end;
  1141. valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
  1142. if (snd_BUG_ON(chip->nr_ac97_codecs != 1 && chip->nr_ac97_codecs != 2))
  1143. goto _fail_end;
  1144. if (chip->nr_ac97_codecs == 1) {
  1145. /* output on slot 5 and 11
  1146. on primary CODEC */
  1147. fifo_addr = 0x20;
  1148. fifo_span = 0x60;
  1149. /* enable slot 5 and 11 */
  1150. valid_slots |= ACOSV_SLV5 | ACOSV_SLV11;
  1151. } else {
  1152. /* output on slot 7 and 8
  1153. on secondary CODEC */
  1154. fifo_addr = 0x40;
  1155. fifo_span = 0x10;
  1156. /* enable slot 7 and 8 */
  1157. valid_slots |= ACOSV_SLV7 | ACOSV_SLV8;
  1158. }
  1159. /* create CODEC tasklet for rear speakers output*/
  1160. rear_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_Rear",fifo_span,fifo_addr,
  1161. REAR_MIXER_SCB_ADDR,
  1162. REAR_CODECOUT_SCB_ADDR,codec_in_scb,
  1163. SCB_ON_PARENT_NEXT_SCB);
  1164. if (!rear_codec_out_scb) goto _fail_end;
  1165. /* create the rear PCM channel mixer SCB */
  1166. rear_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RearMixerSCB",
  1167. MIX_SAMPLE_BUF3,
  1168. REAR_MIXER_SCB_ADDR,
  1169. rear_codec_out_scb,
  1170. SCB_ON_PARENT_SUBLIST_SCB);
  1171. ins->rear_mix_scb = rear_mix_scb;
  1172. if (!rear_mix_scb) goto _fail_end;
  1173. if (chip->nr_ac97_codecs == 2) {
  1174. /* create CODEC tasklet for rear Center/LFE output
  1175. slot 6 and 9 on seconadry CODEC */
  1176. clfe_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_CLFE",0x0030,0x0030,
  1177. CLFE_MIXER_SCB_ADDR,
  1178. CLFE_CODEC_SCB_ADDR,
  1179. rear_codec_out_scb,
  1180. SCB_ON_PARENT_NEXT_SCB);
  1181. if (!clfe_codec_out_scb) goto _fail_end;
  1182. /* create the rear PCM channel mixer SCB */
  1183. ins->center_lfe_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"CLFEMixerSCB",
  1184. MIX_SAMPLE_BUF4,
  1185. CLFE_MIXER_SCB_ADDR,
  1186. clfe_codec_out_scb,
  1187. SCB_ON_PARENT_SUBLIST_SCB);
  1188. if (!ins->center_lfe_mix_scb) goto _fail_end;
  1189. /* enable slot 6 and 9 */
  1190. valid_slots |= ACOSV_SLV6 | ACOSV_SLV9;
  1191. } else {
  1192. clfe_codec_out_scb = rear_codec_out_scb;
  1193. ins->center_lfe_mix_scb = rear_mix_scb;
  1194. }
  1195. /* enable slots depending on CODEC configuration */
  1196. snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
  1197. /* the magic snooper */
  1198. magic_snoop_scb = cs46xx_dsp_create_magic_snoop_scb (chip,"MagicSnoopSCB_I",OUTPUTSNOOP_SCB_ADDR,
  1199. OUTPUT_SNOOP_BUFFER,
  1200. codec_out_scb,
  1201. clfe_codec_out_scb,
  1202. SCB_ON_PARENT_NEXT_SCB);
  1203. if (!magic_snoop_scb) goto _fail_end;
  1204. ins->ref_snoop_scb = magic_snoop_scb;
  1205. /* SP IO access */
  1206. if (!cs46xx_dsp_create_spio_write_scb(chip,"SPIOWriteSCB",SPIOWRITE_SCB_ADDR,
  1207. magic_snoop_scb,
  1208. SCB_ON_PARENT_NEXT_SCB))
  1209. goto _fail_end;
  1210. /* SPDIF input sampel rate converter */
  1211. src_task_scb = cs46xx_dsp_create_src_task_scb(chip,"SrcTaskSCB_SPDIFI",
  1212. ins->spdif_in_sample_rate,
  1213. SRC_OUTPUT_BUF1,
  1214. SRC_DELAY_BUF1,SRCTASK_SCB_ADDR,
  1215. master_mix_scb,
  1216. SCB_ON_PARENT_SUBLIST_SCB,1);
  1217. if (!src_task_scb) goto _fail_end;
  1218. cs46xx_src_unlink(chip,src_task_scb);
  1219. /* NOTE: when we now how to detect the SPDIF input
  1220. sample rate we will use this SRC to adjust it */
  1221. ins->spdif_in_src = src_task_scb;
  1222. cs46xx_dsp_async_init(chip,timing_master_scb);
  1223. return 0;
  1224. _fail_end:
  1225. snd_printk(KERN_ERR "dsp_spos: failed to setup SCB's in DSP\n");
  1226. return -EINVAL;
  1227. }
  1228. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  1229. struct dsp_scb_descriptor * fg_entry)
  1230. {
  1231. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1232. struct dsp_symbol_entry * s16_async_codec_input_task;
  1233. struct dsp_symbol_entry * spdifo_task;
  1234. struct dsp_symbol_entry * spdifi_task;
  1235. struct dsp_scb_descriptor * spdifi_scb_desc, * spdifo_scb_desc, * async_codec_scb_desc;
  1236. s16_async_codec_input_task = cs46xx_dsp_lookup_symbol(chip, "S16_ASYNCCODECINPUTTASK", SYMBOL_CODE);
  1237. if (s16_async_codec_input_task == NULL) {
  1238. snd_printk(KERN_ERR "dsp_spos: symbol S16_ASYNCCODECINPUTTASK not found\n");
  1239. return -EIO;
  1240. }
  1241. spdifo_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFOTASK", SYMBOL_CODE);
  1242. if (spdifo_task == NULL) {
  1243. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFOTASK not found\n");
  1244. return -EIO;
  1245. }
  1246. spdifi_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFITASK", SYMBOL_CODE);
  1247. if (spdifi_task == NULL) {
  1248. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFITASK not found\n");
  1249. return -EIO;
  1250. }
  1251. {
  1252. /* 0xBC0 */
  1253. struct dsp_spdifoscb spdifo_scb = {
  1254. /* 0 */ DSP_SPOS_UUUU,
  1255. {
  1256. /* 1 */ 0xb0,
  1257. /* 2 */ 0,
  1258. /* 3 */ 0,
  1259. /* 4 */ 0,
  1260. },
  1261. /* NOTE: the SPDIF output task read samples in mono
  1262. format, the AsynchFGTxSCB task writes to buffer
  1263. in stereo format
  1264. */
  1265. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_256,
  1266. /* 6 */ ( SPDIFO_IP_OUTPUT_BUFFER1 << 0x10 ) | 0xFFFC,
  1267. /* 7 */ 0,0,
  1268. /* 8 */ 0,
  1269. /* 9 */ FG_TASK_HEADER_ADDR, NULL_SCB_ADDR,
  1270. /* A */ spdifo_task->address,
  1271. SPDIFO_SCB_INST + SPDIFOFIFOPointer,
  1272. {
  1273. /* B */ 0x0040, /*DSP_SPOS_UUUU,*/
  1274. /* C */ 0x20ff, /*DSP_SPOS_UUUU,*/
  1275. },
  1276. /* D */ 0x804c,0, /* SPDIFOFIFOPointer:SPDIFOStatRegAddr; */
  1277. /* E */ 0x0108,0x0001, /* SPDIFOStMoFormat:SPDIFOFIFOBaseAddr; */
  1278. /* F */ DSP_SPOS_UUUU /* SPDIFOFree; */
  1279. };
  1280. /* 0xBB0 */
  1281. struct dsp_spdifiscb spdifi_scb = {
  1282. /* 0 */ DSP_SPOS_UULO,DSP_SPOS_UUHI,
  1283. /* 1 */ 0,
  1284. /* 2 */ 0,
  1285. /* 3 */ 1,4000, /* SPDIFICountLimit SPDIFICount */
  1286. /* 4 */ DSP_SPOS_UUUU, /* SPDIFIStatusData */
  1287. /* 5 */ 0,DSP_SPOS_UUHI, /* StatusData, Free4 */
  1288. /* 6 */ DSP_SPOS_UUUU, /* Free3 */
  1289. /* 7 */ DSP_SPOS_UU,DSP_SPOS_DC, /* Free2 BitCount*/
  1290. /* 8 */ DSP_SPOS_UUUU, /* TempStatus */
  1291. /* 9 */ SPDIFO_SCB_INST, NULL_SCB_ADDR,
  1292. /* A */ spdifi_task->address,
  1293. SPDIFI_SCB_INST + SPDIFIFIFOPointer,
  1294. /* NOTE: The SPDIF input task write the sample in mono
  1295. format from the HW FIFO, the AsynchFGRxSCB task reads
  1296. them in stereo
  1297. */
  1298. /* B */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_128,
  1299. /* C */ (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1300. /* D */ 0x8048,0,
  1301. /* E */ 0x01f0,0x0001,
  1302. /* F */ DSP_SPOS_UUUU /* SPDIN_STATUS monitor */
  1303. };
  1304. /* 0xBA0 */
  1305. struct dsp_async_codec_input_scb async_codec_input_scb = {
  1306. /* 0 */ DSP_SPOS_UUUU,
  1307. /* 1 */ 0,
  1308. /* 2 */ 0,
  1309. /* 3 */ 1,4000,
  1310. /* 4 */ 0x0118,0x0001,
  1311. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_64,
  1312. /* 6 */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1313. /* 7 */ DSP_SPOS_UU,0x3,
  1314. /* 8 */ DSP_SPOS_UUUU,
  1315. /* 9 */ SPDIFI_SCB_INST,NULL_SCB_ADDR,
  1316. /* A */ s16_async_codec_input_task->address,
  1317. HFG_TREE_SCB + AsyncCIOFIFOPointer,
  1318. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  1319. /* C */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10), /*(ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,*/
  1320. #ifdef UseASER1Input
  1321. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1322. Init. 0000:8042: for ASER1
  1323. 0000:8044: for ASER2 */
  1324. /* D */ 0x8042,0,
  1325. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1326. Init 1 stero:8050 ASER1
  1327. Init 0 mono:8070 ASER2
  1328. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1329. /* E */ 0x0100,0x0001,
  1330. #endif
  1331. #ifdef UseASER2Input
  1332. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1333. Init. 0000:8042: for ASER1
  1334. 0000:8044: for ASER2 */
  1335. /* D */ 0x8044,0,
  1336. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1337. Init 1 stero:8050 ASER1
  1338. Init 0 mono:8070 ASER2
  1339. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1340. /* E */ 0x0110,0x0001,
  1341. #endif
  1342. /* short AsyncCIOutputBufModulo:AsyncCIFree;
  1343. AsyncCIOutputBufModulo: The modulo size for
  1344. the output buffer of this task */
  1345. /* F */ 0, /* DSP_SPOS_UUUU */
  1346. };
  1347. spdifo_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFOSCB",(u32 *)&spdifo_scb,SPDIFO_SCB_INST);
  1348. if (snd_BUG_ON(!spdifo_scb_desc))
  1349. return -EIO;
  1350. spdifi_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFISCB",(u32 *)&spdifi_scb,SPDIFI_SCB_INST);
  1351. if (snd_BUG_ON(!spdifi_scb_desc))
  1352. return -EIO;
  1353. async_codec_scb_desc = cs46xx_dsp_create_scb(chip,"AsynCodecInputSCB",(u32 *)&async_codec_input_scb, HFG_TREE_SCB);
  1354. if (snd_BUG_ON(!async_codec_scb_desc))
  1355. return -EIO;
  1356. async_codec_scb_desc->parent_scb_ptr = NULL;
  1357. async_codec_scb_desc->next_scb_ptr = spdifi_scb_desc;
  1358. async_codec_scb_desc->sub_list_ptr = ins->the_null_scb;
  1359. async_codec_scb_desc->task_entry = s16_async_codec_input_task;
  1360. spdifi_scb_desc->parent_scb_ptr = async_codec_scb_desc;
  1361. spdifi_scb_desc->next_scb_ptr = spdifo_scb_desc;
  1362. spdifi_scb_desc->sub_list_ptr = ins->the_null_scb;
  1363. spdifi_scb_desc->task_entry = spdifi_task;
  1364. spdifo_scb_desc->parent_scb_ptr = spdifi_scb_desc;
  1365. spdifo_scb_desc->next_scb_ptr = fg_entry;
  1366. spdifo_scb_desc->sub_list_ptr = ins->the_null_scb;
  1367. spdifo_scb_desc->task_entry = spdifo_task;
  1368. /* this one is faked, as the parnet of SPDIFO task
  1369. is the FG task tree */
  1370. fg_entry->parent_scb_ptr = spdifo_scb_desc;
  1371. /* for proc fs */
  1372. cs46xx_dsp_proc_register_scb_desc (chip,spdifo_scb_desc);
  1373. cs46xx_dsp_proc_register_scb_desc (chip,spdifi_scb_desc);
  1374. cs46xx_dsp_proc_register_scb_desc (chip,async_codec_scb_desc);
  1375. /* Async MASTER ENABLE, affects both SPDIF input and output */
  1376. snd_cs46xx_pokeBA0(chip, BA0_ASER_MASTER, 0x1 );
  1377. }
  1378. return 0;
  1379. }
  1380. static void cs46xx_dsp_disable_spdif_hw (struct snd_cs46xx *chip)
  1381. {
  1382. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1383. /* set SPDIF output FIFO slot */
  1384. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, 0);
  1385. /* SPDIF output MASTER ENABLE */
  1386. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0);
  1387. /* right and left validate bit */
  1388. /*cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);*/
  1389. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, 0x0);
  1390. /* clear fifo pointer */
  1391. cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);
  1392. /* monitor state */
  1393. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_HW_ENABLED;
  1394. }
  1395. int cs46xx_dsp_enable_spdif_hw (struct snd_cs46xx *chip)
  1396. {
  1397. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1398. /* if hw-ctrl already enabled, turn off to reset logic ... */
  1399. cs46xx_dsp_disable_spdif_hw (chip);
  1400. udelay(50);
  1401. /* set SPDIF output FIFO slot */
  1402. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, ( 0x8000 | ((SP_SPDOUT_FIFO >> 4) << 4) ));
  1403. /* SPDIF output MASTER ENABLE */
  1404. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0x80000000);
  1405. /* right and left validate bit */
  1406. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1407. /* monitor state */
  1408. ins->spdif_status_out |= DSP_SPDIF_STATUS_HW_ENABLED;
  1409. return 0;
  1410. }
  1411. int cs46xx_dsp_enable_spdif_in (struct snd_cs46xx *chip)
  1412. {
  1413. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1414. /* turn on amplifier */
  1415. chip->active_ctrl(chip, 1);
  1416. chip->amplifier_ctrl(chip, 1);
  1417. if (snd_BUG_ON(ins->asynch_rx_scb))
  1418. return -EINVAL;
  1419. if (snd_BUG_ON(!ins->spdif_in_src))
  1420. return -EINVAL;
  1421. mutex_lock(&chip->spos_mutex);
  1422. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED) ) {
  1423. /* time countdown enable */
  1424. cs46xx_poke_via_dsp (chip,SP_ASER_COUNTDOWN, 0x80000005);
  1425. /* NOTE: 80000005 value is just magic. With all values
  1426. that I've tested this one seem to give the best result.
  1427. Got no explication why. (Benny) */
  1428. /* SPDIF input MASTER ENABLE */
  1429. cs46xx_poke_via_dsp (chip,SP_SPDIN_CONTROL, 0x800003ff);
  1430. ins->spdif_status_out |= DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED;
  1431. }
  1432. /* create and start the asynchronous receiver SCB */
  1433. ins->asynch_rx_scb = cs46xx_dsp_create_asynch_fg_rx_scb(chip,"AsynchFGRxSCB",
  1434. ASYNCRX_SCB_ADDR,
  1435. SPDIFI_SCB_INST,
  1436. SPDIFI_IP_OUTPUT_BUFFER1,
  1437. ins->spdif_in_src,
  1438. SCB_ON_PARENT_SUBLIST_SCB);
  1439. spin_lock_irq(&chip->reg_lock);
  1440. /* reset SPDIF input sample buffer pointer */
  1441. /*snd_cs46xx_poke (chip, (SPDIFI_SCB_INST + 0x0c) << 2,
  1442. (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC);*/
  1443. /* reset FIFO ptr */
  1444. /*cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);*/
  1445. cs46xx_src_link(chip,ins->spdif_in_src);
  1446. /* unmute SRC volume */
  1447. cs46xx_dsp_scb_set_volume (chip,ins->spdif_in_src,0x7fff,0x7fff);
  1448. spin_unlock_irq(&chip->reg_lock);
  1449. /* set SPDIF input sample rate and unmute
  1450. NOTE: only 48khz support for SPDIF input this time */
  1451. /* cs46xx_dsp_set_src_sample_rate(chip,ins->spdif_in_src,48000); */
  1452. /* monitor state */
  1453. ins->spdif_status_in = 1;
  1454. mutex_unlock(&chip->spos_mutex);
  1455. return 0;
  1456. }
  1457. int cs46xx_dsp_disable_spdif_in (struct snd_cs46xx *chip)
  1458. {
  1459. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1460. if (snd_BUG_ON(!ins->asynch_rx_scb))
  1461. return -EINVAL;
  1462. if (snd_BUG_ON(!ins->spdif_in_src))
  1463. return -EINVAL;
  1464. mutex_lock(&chip->spos_mutex);
  1465. /* Remove the asynchronous receiver SCB */
  1466. cs46xx_dsp_remove_scb (chip,ins->asynch_rx_scb);
  1467. ins->asynch_rx_scb = NULL;
  1468. cs46xx_src_unlink(chip,ins->spdif_in_src);
  1469. /* monitor state */
  1470. ins->spdif_status_in = 0;
  1471. mutex_unlock(&chip->spos_mutex);
  1472. /* restore amplifier */
  1473. chip->active_ctrl(chip, -1);
  1474. chip->amplifier_ctrl(chip, -1);
  1475. return 0;
  1476. }
  1477. int cs46xx_dsp_enable_pcm_capture (struct snd_cs46xx *chip)
  1478. {
  1479. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1480. if (snd_BUG_ON(ins->pcm_input))
  1481. return -EINVAL;
  1482. if (snd_BUG_ON(!ins->ref_snoop_scb))
  1483. return -EINVAL;
  1484. mutex_lock(&chip->spos_mutex);
  1485. ins->pcm_input = cs46xx_add_record_source(chip,ins->ref_snoop_scb,PCMSERIALIN_PCM_SCB_ADDR,
  1486. "PCMSerialInput_Wave");
  1487. mutex_unlock(&chip->spos_mutex);
  1488. return 0;
  1489. }
  1490. int cs46xx_dsp_disable_pcm_capture (struct snd_cs46xx *chip)
  1491. {
  1492. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1493. if (snd_BUG_ON(!ins->pcm_input))
  1494. return -EINVAL;
  1495. mutex_lock(&chip->spos_mutex);
  1496. cs46xx_dsp_remove_scb (chip,ins->pcm_input);
  1497. ins->pcm_input = NULL;
  1498. mutex_unlock(&chip->spos_mutex);
  1499. return 0;
  1500. }
  1501. int cs46xx_dsp_enable_adc_capture (struct snd_cs46xx *chip)
  1502. {
  1503. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1504. if (snd_BUG_ON(ins->adc_input))
  1505. return -EINVAL;
  1506. if (snd_BUG_ON(!ins->codec_in_scb))
  1507. return -EINVAL;
  1508. mutex_lock(&chip->spos_mutex);
  1509. ins->adc_input = cs46xx_add_record_source(chip,ins->codec_in_scb,PCMSERIALIN_SCB_ADDR,
  1510. "PCMSerialInput_ADC");
  1511. mutex_unlock(&chip->spos_mutex);
  1512. return 0;
  1513. }
  1514. int cs46xx_dsp_disable_adc_capture (struct snd_cs46xx *chip)
  1515. {
  1516. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1517. if (snd_BUG_ON(!ins->adc_input))
  1518. return -EINVAL;
  1519. mutex_lock(&chip->spos_mutex);
  1520. cs46xx_dsp_remove_scb (chip,ins->adc_input);
  1521. ins->adc_input = NULL;
  1522. mutex_unlock(&chip->spos_mutex);
  1523. return 0;
  1524. }
  1525. int cs46xx_poke_via_dsp (struct snd_cs46xx *chip, u32 address, u32 data)
  1526. {
  1527. u32 temp;
  1528. int i;
  1529. /* santiy check the parameters. (These numbers are not 100% correct. They are
  1530. a rough guess from looking at the controller spec.) */
  1531. if (address < 0x8000 || address >= 0x9000)
  1532. return -EINVAL;
  1533. /* initialize the SP_IO_WRITE SCB with the data. */
  1534. temp = ( address << 16 ) | ( address & 0x0000FFFF); /* offset 0 <-- address2 : address1 */
  1535. snd_cs46xx_poke(chip,( SPIOWRITE_SCB_ADDR << 2), temp);
  1536. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 1) << 2), data); /* offset 1 <-- data1 */
  1537. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 2) << 2), data); /* offset 1 <-- data2 */
  1538. /* Poke this location to tell the task to start */
  1539. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 6) << 2), SPIOWRITE_SCB_ADDR << 0x10);
  1540. /* Verify that the task ran */
  1541. for (i=0; i<25; i++) {
  1542. udelay(125);
  1543. temp = snd_cs46xx_peek(chip,((SPIOWRITE_SCB_ADDR + 6) << 2));
  1544. if (temp == 0x00000000)
  1545. break;
  1546. }
  1547. if (i == 25) {
  1548. snd_printk(KERN_ERR "dsp_spos: SPIOWriteTask not responding\n");
  1549. return -EBUSY;
  1550. }
  1551. return 0;
  1552. }
  1553. int cs46xx_dsp_set_dac_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1554. {
  1555. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1556. struct dsp_scb_descriptor * scb;
  1557. mutex_lock(&chip->spos_mutex);
  1558. /* main output */
  1559. scb = ins->master_mix_scb->sub_list_ptr;
  1560. while (scb != ins->the_null_scb) {
  1561. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1562. scb = scb->next_scb_ptr;
  1563. }
  1564. /* rear output */
  1565. scb = ins->rear_mix_scb->sub_list_ptr;
  1566. while (scb != ins->the_null_scb) {
  1567. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1568. scb = scb->next_scb_ptr;
  1569. }
  1570. ins->dac_volume_left = left;
  1571. ins->dac_volume_right = right;
  1572. mutex_unlock(&chip->spos_mutex);
  1573. return 0;
  1574. }
  1575. int cs46xx_dsp_set_iec958_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1576. {
  1577. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1578. mutex_lock(&chip->spos_mutex);
  1579. if (ins->asynch_rx_scb != NULL)
  1580. cs46xx_dsp_scb_set_volume (chip,ins->asynch_rx_scb,
  1581. left,right);
  1582. ins->spdif_input_volume_left = left;
  1583. ins->spdif_input_volume_right = right;
  1584. mutex_unlock(&chip->spos_mutex);
  1585. return 0;
  1586. }
  1587. #ifdef CONFIG_PM
  1588. int cs46xx_dsp_resume(struct snd_cs46xx * chip)
  1589. {
  1590. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1591. int i, err;
  1592. /* clear parameter, sample and code areas */
  1593. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET,
  1594. DSP_PARAMETER_BYTE_SIZE);
  1595. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET,
  1596. DSP_SAMPLE_BYTE_SIZE);
  1597. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  1598. for (i = 0; i < ins->nmodules; i++) {
  1599. struct dsp_module_desc *module = &ins->modules[i];
  1600. struct dsp_segment_desc *seg;
  1601. u32 doffset, dsize;
  1602. seg = get_segment_desc(module, SEGTYPE_SP_PARAMETER);
  1603. err = dsp_load_parameter(chip, seg);
  1604. if (err < 0)
  1605. return err;
  1606. seg = get_segment_desc(module, SEGTYPE_SP_SAMPLE);
  1607. err = dsp_load_sample(chip, seg);
  1608. if (err < 0)
  1609. return err;
  1610. seg = get_segment_desc(module, SEGTYPE_SP_PROGRAM);
  1611. if (!seg)
  1612. continue;
  1613. doffset = seg->offset * 4 + module->load_address * 4
  1614. + DSP_CODE_BYTE_OFFSET;
  1615. dsize = seg->size * 4;
  1616. err = snd_cs46xx_download(chip,
  1617. ins->code.data + module->load_address,
  1618. doffset, dsize);
  1619. if (err < 0)
  1620. return err;
  1621. }
  1622. for (i = 0; i < ins->ntask; i++) {
  1623. struct dsp_task_descriptor *t = &ins->tasks[i];
  1624. _dsp_create_task_tree(chip, t->data, t->address, t->size);
  1625. }
  1626. for (i = 0; i < ins->nscb; i++) {
  1627. struct dsp_scb_descriptor *s = &ins->scbs[i];
  1628. if (s->deleted)
  1629. continue;
  1630. _dsp_create_scb(chip, s->data, s->address);
  1631. }
  1632. for (i = 0; i < ins->nscb; i++) {
  1633. struct dsp_scb_descriptor *s = &ins->scbs[i];
  1634. if (s->deleted)
  1635. continue;
  1636. if (s->updated)
  1637. cs46xx_dsp_spos_update_scb(chip, s);
  1638. if (s->volume_set)
  1639. cs46xx_dsp_scb_set_volume(chip, s,
  1640. s->volume[0], s->volume[1]);
  1641. }
  1642. if (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) {
  1643. cs46xx_dsp_enable_spdif_hw(chip);
  1644. snd_cs46xx_poke(chip, (ins->ref_snoop_scb->address + 2) << 2,
  1645. (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10);
  1646. if (ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN)
  1647. cs46xx_poke_via_dsp(chip, SP_SPDOUT_CSUV,
  1648. ins->spdif_csuv_stream);
  1649. }
  1650. if (chip->dsp_spos_instance->spdif_status_in) {
  1651. cs46xx_poke_via_dsp(chip, SP_ASER_COUNTDOWN, 0x80000005);
  1652. cs46xx_poke_via_dsp(chip, SP_SPDIN_CONTROL, 0x800003ff);
  1653. }
  1654. return 0;
  1655. }
  1656. #endif