i915_drm.h 24 KB

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  1. /*
  2. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial portions
  15. * of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #ifndef _I915_DRM_H_
  27. #define _I915_DRM_H_
  28. #include "drm.h"
  29. /* Please note that modifications to all structs defined here are
  30. * subject to backwards-compatibility constraints.
  31. */
  32. #ifdef __KERNEL__
  33. /* For use by IPS driver */
  34. extern unsigned long i915_read_mch_val(void);
  35. extern bool i915_gpu_raise(void);
  36. extern bool i915_gpu_lower(void);
  37. extern bool i915_gpu_busy(void);
  38. extern bool i915_gpu_turbo_disable(void);
  39. #endif
  40. /* Each region is a minimum of 16k, and there are at most 255 of them.
  41. */
  42. #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  43. * of chars for next/prev indices */
  44. #define I915_LOG_MIN_TEX_REGION_SIZE 14
  45. typedef struct _drm_i915_init {
  46. enum {
  47. I915_INIT_DMA = 0x01,
  48. I915_CLEANUP_DMA = 0x02,
  49. I915_RESUME_DMA = 0x03
  50. } func;
  51. unsigned int mmio_offset;
  52. int sarea_priv_offset;
  53. unsigned int ring_start;
  54. unsigned int ring_end;
  55. unsigned int ring_size;
  56. unsigned int front_offset;
  57. unsigned int back_offset;
  58. unsigned int depth_offset;
  59. unsigned int w;
  60. unsigned int h;
  61. unsigned int pitch;
  62. unsigned int pitch_bits;
  63. unsigned int back_pitch;
  64. unsigned int depth_pitch;
  65. unsigned int cpp;
  66. unsigned int chipset;
  67. } drm_i915_init_t;
  68. typedef struct _drm_i915_sarea {
  69. struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  70. int last_upload; /* last time texture was uploaded */
  71. int last_enqueue; /* last time a buffer was enqueued */
  72. int last_dispatch; /* age of the most recently dispatched buffer */
  73. int ctxOwner; /* last context to upload state */
  74. int texAge;
  75. int pf_enabled; /* is pageflipping allowed? */
  76. int pf_active;
  77. int pf_current_page; /* which buffer is being displayed? */
  78. int perf_boxes; /* performance boxes to be displayed */
  79. int width, height; /* screen size in pixels */
  80. drm_handle_t front_handle;
  81. int front_offset;
  82. int front_size;
  83. drm_handle_t back_handle;
  84. int back_offset;
  85. int back_size;
  86. drm_handle_t depth_handle;
  87. int depth_offset;
  88. int depth_size;
  89. drm_handle_t tex_handle;
  90. int tex_offset;
  91. int tex_size;
  92. int log_tex_granularity;
  93. int pitch;
  94. int rotation; /* 0, 90, 180 or 270 */
  95. int rotated_offset;
  96. int rotated_size;
  97. int rotated_pitch;
  98. int virtualX, virtualY;
  99. unsigned int front_tiled;
  100. unsigned int back_tiled;
  101. unsigned int depth_tiled;
  102. unsigned int rotated_tiled;
  103. unsigned int rotated2_tiled;
  104. int pipeA_x;
  105. int pipeA_y;
  106. int pipeA_w;
  107. int pipeA_h;
  108. int pipeB_x;
  109. int pipeB_y;
  110. int pipeB_w;
  111. int pipeB_h;
  112. /* fill out some space for old userspace triple buffer */
  113. drm_handle_t unused_handle;
  114. __u32 unused1, unused2, unused3;
  115. /* buffer object handles for static buffers. May change
  116. * over the lifetime of the client.
  117. */
  118. __u32 front_bo_handle;
  119. __u32 back_bo_handle;
  120. __u32 unused_bo_handle;
  121. __u32 depth_bo_handle;
  122. } drm_i915_sarea_t;
  123. /* due to userspace building against these headers we need some compat here */
  124. #define planeA_x pipeA_x
  125. #define planeA_y pipeA_y
  126. #define planeA_w pipeA_w
  127. #define planeA_h pipeA_h
  128. #define planeB_x pipeB_x
  129. #define planeB_y pipeB_y
  130. #define planeB_w pipeB_w
  131. #define planeB_h pipeB_h
  132. /* Flags for perf_boxes
  133. */
  134. #define I915_BOX_RING_EMPTY 0x1
  135. #define I915_BOX_FLIP 0x2
  136. #define I915_BOX_WAIT 0x4
  137. #define I915_BOX_TEXTURE_LOAD 0x8
  138. #define I915_BOX_LOST_CONTEXT 0x10
  139. /* I915 specific ioctls
  140. * The device specific ioctl range is 0x40 to 0x79.
  141. */
  142. #define DRM_I915_INIT 0x00
  143. #define DRM_I915_FLUSH 0x01
  144. #define DRM_I915_FLIP 0x02
  145. #define DRM_I915_BATCHBUFFER 0x03
  146. #define DRM_I915_IRQ_EMIT 0x04
  147. #define DRM_I915_IRQ_WAIT 0x05
  148. #define DRM_I915_GETPARAM 0x06
  149. #define DRM_I915_SETPARAM 0x07
  150. #define DRM_I915_ALLOC 0x08
  151. #define DRM_I915_FREE 0x09
  152. #define DRM_I915_INIT_HEAP 0x0a
  153. #define DRM_I915_CMDBUFFER 0x0b
  154. #define DRM_I915_DESTROY_HEAP 0x0c
  155. #define DRM_I915_SET_VBLANK_PIPE 0x0d
  156. #define DRM_I915_GET_VBLANK_PIPE 0x0e
  157. #define DRM_I915_VBLANK_SWAP 0x0f
  158. #define DRM_I915_HWS_ADDR 0x11
  159. #define DRM_I915_GEM_INIT 0x13
  160. #define DRM_I915_GEM_EXECBUFFER 0x14
  161. #define DRM_I915_GEM_PIN 0x15
  162. #define DRM_I915_GEM_UNPIN 0x16
  163. #define DRM_I915_GEM_BUSY 0x17
  164. #define DRM_I915_GEM_THROTTLE 0x18
  165. #define DRM_I915_GEM_ENTERVT 0x19
  166. #define DRM_I915_GEM_LEAVEVT 0x1a
  167. #define DRM_I915_GEM_CREATE 0x1b
  168. #define DRM_I915_GEM_PREAD 0x1c
  169. #define DRM_I915_GEM_PWRITE 0x1d
  170. #define DRM_I915_GEM_MMAP 0x1e
  171. #define DRM_I915_GEM_SET_DOMAIN 0x1f
  172. #define DRM_I915_GEM_SW_FINISH 0x20
  173. #define DRM_I915_GEM_SET_TILING 0x21
  174. #define DRM_I915_GEM_GET_TILING 0x22
  175. #define DRM_I915_GEM_GET_APERTURE 0x23
  176. #define DRM_I915_GEM_MMAP_GTT 0x24
  177. #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
  178. #define DRM_I915_GEM_MADVISE 0x26
  179. #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
  180. #define DRM_I915_OVERLAY_ATTRS 0x28
  181. #define DRM_I915_GEM_EXECBUFFER2 0x29
  182. #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
  183. #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
  184. #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
  185. #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
  186. #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
  187. #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
  188. #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
  189. #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
  190. #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
  191. #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
  192. #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
  193. #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
  194. #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
  195. #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
  196. #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
  197. #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
  198. #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
  199. #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
  200. #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
  201. #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
  202. #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
  203. #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
  204. #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
  205. #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
  206. #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
  207. #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
  208. #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
  209. #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
  210. #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
  211. #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
  212. #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
  213. #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
  214. #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
  215. #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
  216. #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
  217. #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
  218. #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
  219. #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
  220. #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
  221. #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
  222. /* Allow drivers to submit batchbuffers directly to hardware, relying
  223. * on the security mechanisms provided by hardware.
  224. */
  225. typedef struct drm_i915_batchbuffer {
  226. int start; /* agp offset */
  227. int used; /* nr bytes in use */
  228. int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
  229. int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
  230. int num_cliprects; /* mulitpass with multiple cliprects? */
  231. struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
  232. } drm_i915_batchbuffer_t;
  233. /* As above, but pass a pointer to userspace buffer which can be
  234. * validated by the kernel prior to sending to hardware.
  235. */
  236. typedef struct _drm_i915_cmdbuffer {
  237. char __user *buf; /* pointer to userspace command buffer */
  238. int sz; /* nr bytes in buf */
  239. int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
  240. int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
  241. int num_cliprects; /* mulitpass with multiple cliprects? */
  242. struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
  243. } drm_i915_cmdbuffer_t;
  244. /* Userspace can request & wait on irq's:
  245. */
  246. typedef struct drm_i915_irq_emit {
  247. int __user *irq_seq;
  248. } drm_i915_irq_emit_t;
  249. typedef struct drm_i915_irq_wait {
  250. int irq_seq;
  251. } drm_i915_irq_wait_t;
  252. /* Ioctl to query kernel params:
  253. */
  254. #define I915_PARAM_IRQ_ACTIVE 1
  255. #define I915_PARAM_ALLOW_BATCHBUFFER 2
  256. #define I915_PARAM_LAST_DISPATCH 3
  257. #define I915_PARAM_CHIPSET_ID 4
  258. #define I915_PARAM_HAS_GEM 5
  259. #define I915_PARAM_NUM_FENCES_AVAIL 6
  260. #define I915_PARAM_HAS_OVERLAY 7
  261. #define I915_PARAM_HAS_PAGEFLIPPING 8
  262. #define I915_PARAM_HAS_EXECBUF2 9
  263. #define I915_PARAM_HAS_BSD 10
  264. typedef struct drm_i915_getparam {
  265. int param;
  266. int __user *value;
  267. } drm_i915_getparam_t;
  268. /* Ioctl to set kernel params:
  269. */
  270. #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
  271. #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
  272. #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
  273. #define I915_SETPARAM_NUM_USED_FENCES 4
  274. typedef struct drm_i915_setparam {
  275. int param;
  276. int value;
  277. } drm_i915_setparam_t;
  278. /* A memory manager for regions of shared memory:
  279. */
  280. #define I915_MEM_REGION_AGP 1
  281. typedef struct drm_i915_mem_alloc {
  282. int region;
  283. int alignment;
  284. int size;
  285. int __user *region_offset; /* offset from start of fb or agp */
  286. } drm_i915_mem_alloc_t;
  287. typedef struct drm_i915_mem_free {
  288. int region;
  289. int region_offset;
  290. } drm_i915_mem_free_t;
  291. typedef struct drm_i915_mem_init_heap {
  292. int region;
  293. int size;
  294. int start;
  295. } drm_i915_mem_init_heap_t;
  296. /* Allow memory manager to be torn down and re-initialized (eg on
  297. * rotate):
  298. */
  299. typedef struct drm_i915_mem_destroy_heap {
  300. int region;
  301. } drm_i915_mem_destroy_heap_t;
  302. /* Allow X server to configure which pipes to monitor for vblank signals
  303. */
  304. #define DRM_I915_VBLANK_PIPE_A 1
  305. #define DRM_I915_VBLANK_PIPE_B 2
  306. typedef struct drm_i915_vblank_pipe {
  307. int pipe;
  308. } drm_i915_vblank_pipe_t;
  309. /* Schedule buffer swap at given vertical blank:
  310. */
  311. typedef struct drm_i915_vblank_swap {
  312. drm_drawable_t drawable;
  313. enum drm_vblank_seq_type seqtype;
  314. unsigned int sequence;
  315. } drm_i915_vblank_swap_t;
  316. typedef struct drm_i915_hws_addr {
  317. __u64 addr;
  318. } drm_i915_hws_addr_t;
  319. struct drm_i915_gem_init {
  320. /**
  321. * Beginning offset in the GTT to be managed by the DRM memory
  322. * manager.
  323. */
  324. __u64 gtt_start;
  325. /**
  326. * Ending offset in the GTT to be managed by the DRM memory
  327. * manager.
  328. */
  329. __u64 gtt_end;
  330. };
  331. struct drm_i915_gem_create {
  332. /**
  333. * Requested size for the object.
  334. *
  335. * The (page-aligned) allocated size for the object will be returned.
  336. */
  337. __u64 size;
  338. /**
  339. * Returned handle for the object.
  340. *
  341. * Object handles are nonzero.
  342. */
  343. __u32 handle;
  344. __u32 pad;
  345. };
  346. struct drm_i915_gem_pread {
  347. /** Handle for the object being read. */
  348. __u32 handle;
  349. __u32 pad;
  350. /** Offset into the object to read from */
  351. __u64 offset;
  352. /** Length of data to read */
  353. __u64 size;
  354. /**
  355. * Pointer to write the data into.
  356. *
  357. * This is a fixed-size type for 32/64 compatibility.
  358. */
  359. __u64 data_ptr;
  360. };
  361. struct drm_i915_gem_pwrite {
  362. /** Handle for the object being written to. */
  363. __u32 handle;
  364. __u32 pad;
  365. /** Offset into the object to write to */
  366. __u64 offset;
  367. /** Length of data to write */
  368. __u64 size;
  369. /**
  370. * Pointer to read the data from.
  371. *
  372. * This is a fixed-size type for 32/64 compatibility.
  373. */
  374. __u64 data_ptr;
  375. };
  376. struct drm_i915_gem_mmap {
  377. /** Handle for the object being mapped. */
  378. __u32 handle;
  379. __u32 pad;
  380. /** Offset in the object to map. */
  381. __u64 offset;
  382. /**
  383. * Length of data to map.
  384. *
  385. * The value will be page-aligned.
  386. */
  387. __u64 size;
  388. /**
  389. * Returned pointer the data was mapped at.
  390. *
  391. * This is a fixed-size type for 32/64 compatibility.
  392. */
  393. __u64 addr_ptr;
  394. };
  395. struct drm_i915_gem_mmap_gtt {
  396. /** Handle for the object being mapped. */
  397. __u32 handle;
  398. __u32 pad;
  399. /**
  400. * Fake offset to use for subsequent mmap call
  401. *
  402. * This is a fixed-size type for 32/64 compatibility.
  403. */
  404. __u64 offset;
  405. };
  406. struct drm_i915_gem_set_domain {
  407. /** Handle for the object */
  408. __u32 handle;
  409. /** New read domains */
  410. __u32 read_domains;
  411. /** New write domain */
  412. __u32 write_domain;
  413. };
  414. struct drm_i915_gem_sw_finish {
  415. /** Handle for the object */
  416. __u32 handle;
  417. };
  418. struct drm_i915_gem_relocation_entry {
  419. /**
  420. * Handle of the buffer being pointed to by this relocation entry.
  421. *
  422. * It's appealing to make this be an index into the mm_validate_entry
  423. * list to refer to the buffer, but this allows the driver to create
  424. * a relocation list for state buffers and not re-write it per
  425. * exec using the buffer.
  426. */
  427. __u32 target_handle;
  428. /**
  429. * Value to be added to the offset of the target buffer to make up
  430. * the relocation entry.
  431. */
  432. __u32 delta;
  433. /** Offset in the buffer the relocation entry will be written into */
  434. __u64 offset;
  435. /**
  436. * Offset value of the target buffer that the relocation entry was last
  437. * written as.
  438. *
  439. * If the buffer has the same offset as last time, we can skip syncing
  440. * and writing the relocation. This value is written back out by
  441. * the execbuffer ioctl when the relocation is written.
  442. */
  443. __u64 presumed_offset;
  444. /**
  445. * Target memory domains read by this operation.
  446. */
  447. __u32 read_domains;
  448. /**
  449. * Target memory domains written by this operation.
  450. *
  451. * Note that only one domain may be written by the whole
  452. * execbuffer operation, so that where there are conflicts,
  453. * the application will get -EINVAL back.
  454. */
  455. __u32 write_domain;
  456. };
  457. /** @{
  458. * Intel memory domains
  459. *
  460. * Most of these just align with the various caches in
  461. * the system and are used to flush and invalidate as
  462. * objects end up cached in different domains.
  463. */
  464. /** CPU cache */
  465. #define I915_GEM_DOMAIN_CPU 0x00000001
  466. /** Render cache, used by 2D and 3D drawing */
  467. #define I915_GEM_DOMAIN_RENDER 0x00000002
  468. /** Sampler cache, used by texture engine */
  469. #define I915_GEM_DOMAIN_SAMPLER 0x00000004
  470. /** Command queue, used to load batch buffers */
  471. #define I915_GEM_DOMAIN_COMMAND 0x00000008
  472. /** Instruction cache, used by shader programs */
  473. #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
  474. /** Vertex address cache */
  475. #define I915_GEM_DOMAIN_VERTEX 0x00000020
  476. /** GTT domain - aperture and scanout */
  477. #define I915_GEM_DOMAIN_GTT 0x00000040
  478. /** @} */
  479. struct drm_i915_gem_exec_object {
  480. /**
  481. * User's handle for a buffer to be bound into the GTT for this
  482. * operation.
  483. */
  484. __u32 handle;
  485. /** Number of relocations to be performed on this buffer */
  486. __u32 relocation_count;
  487. /**
  488. * Pointer to array of struct drm_i915_gem_relocation_entry containing
  489. * the relocations to be performed in this buffer.
  490. */
  491. __u64 relocs_ptr;
  492. /** Required alignment in graphics aperture */
  493. __u64 alignment;
  494. /**
  495. * Returned value of the updated offset of the object, for future
  496. * presumed_offset writes.
  497. */
  498. __u64 offset;
  499. };
  500. struct drm_i915_gem_execbuffer {
  501. /**
  502. * List of buffers to be validated with their relocations to be
  503. * performend on them.
  504. *
  505. * This is a pointer to an array of struct drm_i915_gem_validate_entry.
  506. *
  507. * These buffers must be listed in an order such that all relocations
  508. * a buffer is performing refer to buffers that have already appeared
  509. * in the validate list.
  510. */
  511. __u64 buffers_ptr;
  512. __u32 buffer_count;
  513. /** Offset in the batchbuffer to start execution from. */
  514. __u32 batch_start_offset;
  515. /** Bytes used in batchbuffer from batch_start_offset */
  516. __u32 batch_len;
  517. __u32 DR1;
  518. __u32 DR4;
  519. __u32 num_cliprects;
  520. /** This is a struct drm_clip_rect *cliprects */
  521. __u64 cliprects_ptr;
  522. };
  523. struct drm_i915_gem_exec_object2 {
  524. /**
  525. * User's handle for a buffer to be bound into the GTT for this
  526. * operation.
  527. */
  528. __u32 handle;
  529. /** Number of relocations to be performed on this buffer */
  530. __u32 relocation_count;
  531. /**
  532. * Pointer to array of struct drm_i915_gem_relocation_entry containing
  533. * the relocations to be performed in this buffer.
  534. */
  535. __u64 relocs_ptr;
  536. /** Required alignment in graphics aperture */
  537. __u64 alignment;
  538. /**
  539. * Returned value of the updated offset of the object, for future
  540. * presumed_offset writes.
  541. */
  542. __u64 offset;
  543. #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
  544. __u64 flags;
  545. __u64 rsvd1;
  546. __u64 rsvd2;
  547. };
  548. struct drm_i915_gem_execbuffer2 {
  549. /**
  550. * List of gem_exec_object2 structs
  551. */
  552. __u64 buffers_ptr;
  553. __u32 buffer_count;
  554. /** Offset in the batchbuffer to start execution from. */
  555. __u32 batch_start_offset;
  556. /** Bytes used in batchbuffer from batch_start_offset */
  557. __u32 batch_len;
  558. __u32 DR1;
  559. __u32 DR4;
  560. __u32 num_cliprects;
  561. /** This is a struct drm_clip_rect *cliprects */
  562. __u64 cliprects_ptr;
  563. #define I915_EXEC_RENDER (1<<0)
  564. #define I915_EXEC_BSD (1<<1)
  565. __u64 flags;
  566. __u64 rsvd1;
  567. __u64 rsvd2;
  568. };
  569. struct drm_i915_gem_pin {
  570. /** Handle of the buffer to be pinned. */
  571. __u32 handle;
  572. __u32 pad;
  573. /** alignment required within the aperture */
  574. __u64 alignment;
  575. /** Returned GTT offset of the buffer. */
  576. __u64 offset;
  577. };
  578. struct drm_i915_gem_unpin {
  579. /** Handle of the buffer to be unpinned. */
  580. __u32 handle;
  581. __u32 pad;
  582. };
  583. struct drm_i915_gem_busy {
  584. /** Handle of the buffer to check for busy */
  585. __u32 handle;
  586. /** Return busy status (1 if busy, 0 if idle) */
  587. __u32 busy;
  588. };
  589. #define I915_TILING_NONE 0
  590. #define I915_TILING_X 1
  591. #define I915_TILING_Y 2
  592. #define I915_BIT_6_SWIZZLE_NONE 0
  593. #define I915_BIT_6_SWIZZLE_9 1
  594. #define I915_BIT_6_SWIZZLE_9_10 2
  595. #define I915_BIT_6_SWIZZLE_9_11 3
  596. #define I915_BIT_6_SWIZZLE_9_10_11 4
  597. /* Not seen by userland */
  598. #define I915_BIT_6_SWIZZLE_UNKNOWN 5
  599. /* Seen by userland. */
  600. #define I915_BIT_6_SWIZZLE_9_17 6
  601. #define I915_BIT_6_SWIZZLE_9_10_17 7
  602. struct drm_i915_gem_set_tiling {
  603. /** Handle of the buffer to have its tiling state updated */
  604. __u32 handle;
  605. /**
  606. * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
  607. * I915_TILING_Y).
  608. *
  609. * This value is to be set on request, and will be updated by the
  610. * kernel on successful return with the actual chosen tiling layout.
  611. *
  612. * The tiling mode may be demoted to I915_TILING_NONE when the system
  613. * has bit 6 swizzling that can't be managed correctly by GEM.
  614. *
  615. * Buffer contents become undefined when changing tiling_mode.
  616. */
  617. __u32 tiling_mode;
  618. /**
  619. * Stride in bytes for the object when in I915_TILING_X or
  620. * I915_TILING_Y.
  621. */
  622. __u32 stride;
  623. /**
  624. * Returned address bit 6 swizzling required for CPU access through
  625. * mmap mapping.
  626. */
  627. __u32 swizzle_mode;
  628. };
  629. struct drm_i915_gem_get_tiling {
  630. /** Handle of the buffer to get tiling state for. */
  631. __u32 handle;
  632. /**
  633. * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
  634. * I915_TILING_Y).
  635. */
  636. __u32 tiling_mode;
  637. /**
  638. * Returned address bit 6 swizzling required for CPU access through
  639. * mmap mapping.
  640. */
  641. __u32 swizzle_mode;
  642. };
  643. struct drm_i915_gem_get_aperture {
  644. /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
  645. __u64 aper_size;
  646. /**
  647. * Available space in the aperture used by i915_gem_execbuffer, in
  648. * bytes
  649. */
  650. __u64 aper_available_size;
  651. };
  652. struct drm_i915_get_pipe_from_crtc_id {
  653. /** ID of CRTC being requested **/
  654. __u32 crtc_id;
  655. /** pipe of requested CRTC **/
  656. __u32 pipe;
  657. };
  658. #define I915_MADV_WILLNEED 0
  659. #define I915_MADV_DONTNEED 1
  660. #define __I915_MADV_PURGED 2 /* internal state */
  661. struct drm_i915_gem_madvise {
  662. /** Handle of the buffer to change the backing store advice */
  663. __u32 handle;
  664. /* Advice: either the buffer will be needed again in the near future,
  665. * or wont be and could be discarded under memory pressure.
  666. */
  667. __u32 madv;
  668. /** Whether the backing store still exists. */
  669. __u32 retained;
  670. };
  671. /* flags */
  672. #define I915_OVERLAY_TYPE_MASK 0xff
  673. #define I915_OVERLAY_YUV_PLANAR 0x01
  674. #define I915_OVERLAY_YUV_PACKED 0x02
  675. #define I915_OVERLAY_RGB 0x03
  676. #define I915_OVERLAY_DEPTH_MASK 0xff00
  677. #define I915_OVERLAY_RGB24 0x1000
  678. #define I915_OVERLAY_RGB16 0x2000
  679. #define I915_OVERLAY_RGB15 0x3000
  680. #define I915_OVERLAY_YUV422 0x0100
  681. #define I915_OVERLAY_YUV411 0x0200
  682. #define I915_OVERLAY_YUV420 0x0300
  683. #define I915_OVERLAY_YUV410 0x0400
  684. #define I915_OVERLAY_SWAP_MASK 0xff0000
  685. #define I915_OVERLAY_NO_SWAP 0x000000
  686. #define I915_OVERLAY_UV_SWAP 0x010000
  687. #define I915_OVERLAY_Y_SWAP 0x020000
  688. #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
  689. #define I915_OVERLAY_FLAGS_MASK 0xff000000
  690. #define I915_OVERLAY_ENABLE 0x01000000
  691. struct drm_intel_overlay_put_image {
  692. /* various flags and src format description */
  693. __u32 flags;
  694. /* source picture description */
  695. __u32 bo_handle;
  696. /* stride values and offsets are in bytes, buffer relative */
  697. __u16 stride_Y; /* stride for packed formats */
  698. __u16 stride_UV;
  699. __u32 offset_Y; /* offset for packet formats */
  700. __u32 offset_U;
  701. __u32 offset_V;
  702. /* in pixels */
  703. __u16 src_width;
  704. __u16 src_height;
  705. /* to compensate the scaling factors for partially covered surfaces */
  706. __u16 src_scan_width;
  707. __u16 src_scan_height;
  708. /* output crtc description */
  709. __u32 crtc_id;
  710. __u16 dst_x;
  711. __u16 dst_y;
  712. __u16 dst_width;
  713. __u16 dst_height;
  714. };
  715. /* flags */
  716. #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
  717. #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
  718. struct drm_intel_overlay_attrs {
  719. __u32 flags;
  720. __u32 color_key;
  721. __s32 brightness;
  722. __u32 contrast;
  723. __u32 saturation;
  724. __u32 gamma0;
  725. __u32 gamma1;
  726. __u32 gamma2;
  727. __u32 gamma3;
  728. __u32 gamma4;
  729. __u32 gamma5;
  730. };
  731. #endif /* _I915_DRM_H_ */