m66592-udc.c 42 KB

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  1. /*
  2. * M66592 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/slab.h>
  28. #include <linux/err.h>
  29. #include <linux/usb/ch9.h>
  30. #include <linux/usb/gadget.h>
  31. #include "m66592-udc.h"
  32. MODULE_DESCRIPTION("M66592 USB gadget driver");
  33. MODULE_LICENSE("GPL");
  34. MODULE_AUTHOR("Yoshihiro Shimoda");
  35. MODULE_ALIAS("platform:m66592_udc");
  36. #define DRIVER_VERSION "21 July 2009"
  37. static const char udc_name[] = "m66592_udc";
  38. static const char *m66592_ep_name[] = {
  39. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
  40. };
  41. static void disable_controller(struct m66592 *m66592);
  42. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
  43. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
  44. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  45. gfp_t gfp_flags);
  46. static void transfer_complete(struct m66592_ep *ep,
  47. struct m66592_request *req, int status);
  48. /*-------------------------------------------------------------------------*/
  49. static inline u16 get_usb_speed(struct m66592 *m66592)
  50. {
  51. return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
  52. }
  53. static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  54. unsigned long reg)
  55. {
  56. u16 tmp;
  57. tmp = m66592_read(m66592, M66592_INTENB0);
  58. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  59. M66592_INTENB0);
  60. m66592_bset(m66592, (1 << pipenum), reg);
  61. m66592_write(m66592, tmp, M66592_INTENB0);
  62. }
  63. static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  64. unsigned long reg)
  65. {
  66. u16 tmp;
  67. tmp = m66592_read(m66592, M66592_INTENB0);
  68. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  69. M66592_INTENB0);
  70. m66592_bclr(m66592, (1 << pipenum), reg);
  71. m66592_write(m66592, tmp, M66592_INTENB0);
  72. }
  73. static void m66592_usb_connect(struct m66592 *m66592)
  74. {
  75. m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
  76. m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  77. M66592_INTENB0);
  78. m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  79. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  80. }
  81. static void m66592_usb_disconnect(struct m66592 *m66592)
  82. __releases(m66592->lock)
  83. __acquires(m66592->lock)
  84. {
  85. m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
  86. m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  87. M66592_INTENB0);
  88. m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  89. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  90. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  91. spin_unlock(&m66592->lock);
  92. m66592->driver->disconnect(&m66592->gadget);
  93. spin_lock(&m66592->lock);
  94. disable_controller(m66592);
  95. INIT_LIST_HEAD(&m66592->ep[0].queue);
  96. }
  97. static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
  98. {
  99. u16 pid = 0;
  100. unsigned long offset;
  101. if (pipenum == 0)
  102. pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
  103. else if (pipenum < M66592_MAX_NUM_PIPE) {
  104. offset = get_pipectr_addr(pipenum);
  105. pid = m66592_read(m66592, offset) & M66592_PID;
  106. } else
  107. pr_err("unexpect pipe num (%d)\n", pipenum);
  108. return pid;
  109. }
  110. static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
  111. u16 pid)
  112. {
  113. unsigned long offset;
  114. if (pipenum == 0)
  115. m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
  116. else if (pipenum < M66592_MAX_NUM_PIPE) {
  117. offset = get_pipectr_addr(pipenum);
  118. m66592_mdfy(m66592, pid, M66592_PID, offset);
  119. } else
  120. pr_err("unexpect pipe num (%d)\n", pipenum);
  121. }
  122. static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
  123. {
  124. control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
  125. }
  126. static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
  127. {
  128. control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
  129. }
  130. static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
  131. {
  132. control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
  133. }
  134. static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
  135. {
  136. u16 ret = 0;
  137. unsigned long offset;
  138. if (pipenum == 0)
  139. ret = m66592_read(m66592, M66592_DCPCTR);
  140. else if (pipenum < M66592_MAX_NUM_PIPE) {
  141. offset = get_pipectr_addr(pipenum);
  142. ret = m66592_read(m66592, offset);
  143. } else
  144. pr_err("unexpect pipe num (%d)\n", pipenum);
  145. return ret;
  146. }
  147. static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
  148. {
  149. unsigned long offset;
  150. pipe_stop(m66592, pipenum);
  151. if (pipenum == 0)
  152. m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
  153. else if (pipenum < M66592_MAX_NUM_PIPE) {
  154. offset = get_pipectr_addr(pipenum);
  155. m66592_bset(m66592, M66592_SQCLR, offset);
  156. } else
  157. pr_err("unexpect pipe num(%d)\n", pipenum);
  158. }
  159. static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
  160. {
  161. u16 tmp;
  162. int size;
  163. if (pipenum == 0) {
  164. tmp = m66592_read(m66592, M66592_DCPCFG);
  165. if ((tmp & M66592_CNTMD) != 0)
  166. size = 256;
  167. else {
  168. tmp = m66592_read(m66592, M66592_DCPMAXP);
  169. size = tmp & M66592_MAXP;
  170. }
  171. } else {
  172. m66592_write(m66592, pipenum, M66592_PIPESEL);
  173. tmp = m66592_read(m66592, M66592_PIPECFG);
  174. if ((tmp & M66592_CNTMD) != 0) {
  175. tmp = m66592_read(m66592, M66592_PIPEBUF);
  176. size = ((tmp >> 10) + 1) * 64;
  177. } else {
  178. tmp = m66592_read(m66592, M66592_PIPEMAXP);
  179. size = tmp & M66592_MXPS;
  180. }
  181. }
  182. return size;
  183. }
  184. static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
  185. {
  186. struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
  187. unsigned short mbw;
  188. if (ep->use_dma)
  189. return;
  190. m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
  191. ndelay(450);
  192. if (m66592->pdata->on_chip)
  193. mbw = M66592_MBW_32;
  194. else
  195. mbw = M66592_MBW_16;
  196. m66592_bset(m66592, mbw, ep->fifosel);
  197. }
  198. static int pipe_buffer_setting(struct m66592 *m66592,
  199. struct m66592_pipe_info *info)
  200. {
  201. u16 bufnum = 0, buf_bsize = 0;
  202. u16 pipecfg = 0;
  203. if (info->pipe == 0)
  204. return -EINVAL;
  205. m66592_write(m66592, info->pipe, M66592_PIPESEL);
  206. if (info->dir_in)
  207. pipecfg |= M66592_DIR;
  208. pipecfg |= info->type;
  209. pipecfg |= info->epnum;
  210. switch (info->type) {
  211. case M66592_INT:
  212. bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
  213. buf_bsize = 0;
  214. break;
  215. case M66592_BULK:
  216. /* isochronous pipes may be used as bulk pipes */
  217. if (info->pipe > M66592_BASE_PIPENUM_BULK)
  218. bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
  219. else
  220. bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
  221. bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
  222. buf_bsize = 7;
  223. pipecfg |= M66592_DBLB;
  224. if (!info->dir_in)
  225. pipecfg |= M66592_SHTNAK;
  226. break;
  227. case M66592_ISO:
  228. bufnum = M66592_BASE_BUFNUM +
  229. (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
  230. buf_bsize = 7;
  231. break;
  232. }
  233. if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
  234. pr_err("m66592 pipe memory is insufficient\n");
  235. return -ENOMEM;
  236. }
  237. m66592_write(m66592, pipecfg, M66592_PIPECFG);
  238. m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
  239. m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
  240. if (info->interval)
  241. info->interval--;
  242. m66592_write(m66592, info->interval, M66592_PIPEPERI);
  243. return 0;
  244. }
  245. static void pipe_buffer_release(struct m66592 *m66592,
  246. struct m66592_pipe_info *info)
  247. {
  248. if (info->pipe == 0)
  249. return;
  250. if (is_bulk_pipe(info->pipe)) {
  251. m66592->bulk--;
  252. } else if (is_interrupt_pipe(info->pipe))
  253. m66592->interrupt--;
  254. else if (is_isoc_pipe(info->pipe)) {
  255. m66592->isochronous--;
  256. if (info->type == M66592_BULK)
  257. m66592->bulk--;
  258. } else
  259. pr_err("ep_release: unexpect pipenum (%d)\n",
  260. info->pipe);
  261. }
  262. static void pipe_initialize(struct m66592_ep *ep)
  263. {
  264. struct m66592 *m66592 = ep->m66592;
  265. unsigned short mbw;
  266. m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
  267. m66592_write(m66592, M66592_ACLRM, ep->pipectr);
  268. m66592_write(m66592, 0, ep->pipectr);
  269. m66592_write(m66592, M66592_SQCLR, ep->pipectr);
  270. if (ep->use_dma) {
  271. m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
  272. ndelay(450);
  273. if (m66592->pdata->on_chip)
  274. mbw = M66592_MBW_32;
  275. else
  276. mbw = M66592_MBW_16;
  277. m66592_bset(m66592, mbw, ep->fifosel);
  278. }
  279. }
  280. static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
  281. const struct usb_endpoint_descriptor *desc,
  282. u16 pipenum, int dma)
  283. {
  284. if ((pipenum != 0) && dma) {
  285. if (m66592->num_dma == 0) {
  286. m66592->num_dma++;
  287. ep->use_dma = 1;
  288. ep->fifoaddr = M66592_D0FIFO;
  289. ep->fifosel = M66592_D0FIFOSEL;
  290. ep->fifoctr = M66592_D0FIFOCTR;
  291. ep->fifotrn = M66592_D0FIFOTRN;
  292. } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
  293. m66592->num_dma++;
  294. ep->use_dma = 1;
  295. ep->fifoaddr = M66592_D1FIFO;
  296. ep->fifosel = M66592_D1FIFOSEL;
  297. ep->fifoctr = M66592_D1FIFOCTR;
  298. ep->fifotrn = M66592_D1FIFOTRN;
  299. } else {
  300. ep->use_dma = 0;
  301. ep->fifoaddr = M66592_CFIFO;
  302. ep->fifosel = M66592_CFIFOSEL;
  303. ep->fifoctr = M66592_CFIFOCTR;
  304. ep->fifotrn = 0;
  305. }
  306. } else {
  307. ep->use_dma = 0;
  308. ep->fifoaddr = M66592_CFIFO;
  309. ep->fifosel = M66592_CFIFOSEL;
  310. ep->fifoctr = M66592_CFIFOCTR;
  311. ep->fifotrn = 0;
  312. }
  313. ep->pipectr = get_pipectr_addr(pipenum);
  314. ep->pipenum = pipenum;
  315. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  316. m66592->pipenum2ep[pipenum] = ep;
  317. m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
  318. INIT_LIST_HEAD(&ep->queue);
  319. }
  320. static void m66592_ep_release(struct m66592_ep *ep)
  321. {
  322. struct m66592 *m66592 = ep->m66592;
  323. u16 pipenum = ep->pipenum;
  324. if (pipenum == 0)
  325. return;
  326. if (ep->use_dma)
  327. m66592->num_dma--;
  328. ep->pipenum = 0;
  329. ep->busy = 0;
  330. ep->use_dma = 0;
  331. }
  332. static int alloc_pipe_config(struct m66592_ep *ep,
  333. const struct usb_endpoint_descriptor *desc)
  334. {
  335. struct m66592 *m66592 = ep->m66592;
  336. struct m66592_pipe_info info;
  337. int dma = 0;
  338. int *counter;
  339. int ret;
  340. ep->desc = desc;
  341. BUG_ON(ep->pipenum);
  342. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  343. case USB_ENDPOINT_XFER_BULK:
  344. if (m66592->bulk >= M66592_MAX_NUM_BULK) {
  345. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  346. pr_err("bulk pipe is insufficient\n");
  347. return -ENODEV;
  348. } else {
  349. info.pipe = M66592_BASE_PIPENUM_ISOC
  350. + m66592->isochronous;
  351. counter = &m66592->isochronous;
  352. }
  353. } else {
  354. info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
  355. counter = &m66592->bulk;
  356. }
  357. info.type = M66592_BULK;
  358. dma = 1;
  359. break;
  360. case USB_ENDPOINT_XFER_INT:
  361. if (m66592->interrupt >= M66592_MAX_NUM_INT) {
  362. pr_err("interrupt pipe is insufficient\n");
  363. return -ENODEV;
  364. }
  365. info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
  366. info.type = M66592_INT;
  367. counter = &m66592->interrupt;
  368. break;
  369. case USB_ENDPOINT_XFER_ISOC:
  370. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  371. pr_err("isochronous pipe is insufficient\n");
  372. return -ENODEV;
  373. }
  374. info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
  375. info.type = M66592_ISO;
  376. counter = &m66592->isochronous;
  377. break;
  378. default:
  379. pr_err("unexpect xfer type\n");
  380. return -EINVAL;
  381. }
  382. ep->type = info.type;
  383. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  384. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  385. info.interval = desc->bInterval;
  386. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  387. info.dir_in = 1;
  388. else
  389. info.dir_in = 0;
  390. ret = pipe_buffer_setting(m66592, &info);
  391. if (ret < 0) {
  392. pr_err("pipe_buffer_setting fail\n");
  393. return ret;
  394. }
  395. (*counter)++;
  396. if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
  397. m66592->bulk++;
  398. m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
  399. pipe_initialize(ep);
  400. return 0;
  401. }
  402. static int free_pipe_config(struct m66592_ep *ep)
  403. {
  404. struct m66592 *m66592 = ep->m66592;
  405. struct m66592_pipe_info info;
  406. info.pipe = ep->pipenum;
  407. info.type = ep->type;
  408. pipe_buffer_release(m66592, &info);
  409. m66592_ep_release(ep);
  410. return 0;
  411. }
  412. /*-------------------------------------------------------------------------*/
  413. static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
  414. {
  415. enable_irq_ready(m66592, pipenum);
  416. enable_irq_nrdy(m66592, pipenum);
  417. }
  418. static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
  419. {
  420. disable_irq_ready(m66592, pipenum);
  421. disable_irq_nrdy(m66592, pipenum);
  422. }
  423. /* if complete is true, gadget driver complete function is not call */
  424. static void control_end(struct m66592 *m66592, unsigned ccpl)
  425. {
  426. m66592->ep[0].internal_ccpl = ccpl;
  427. pipe_start(m66592, 0);
  428. m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
  429. }
  430. static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  431. {
  432. struct m66592 *m66592 = ep->m66592;
  433. pipe_change(m66592, ep->pipenum);
  434. m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
  435. (M66592_ISEL | M66592_CURPIPE),
  436. M66592_CFIFOSEL);
  437. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  438. if (req->req.length == 0) {
  439. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  440. pipe_start(m66592, 0);
  441. transfer_complete(ep, req, 0);
  442. } else {
  443. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  444. irq_ep0_write(ep, req);
  445. }
  446. }
  447. static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  448. {
  449. struct m66592 *m66592 = ep->m66592;
  450. u16 tmp;
  451. pipe_change(m66592, ep->pipenum);
  452. disable_irq_empty(m66592, ep->pipenum);
  453. pipe_start(m66592, ep->pipenum);
  454. tmp = m66592_read(m66592, ep->fifoctr);
  455. if (unlikely((tmp & M66592_FRDY) == 0))
  456. pipe_irq_enable(m66592, ep->pipenum);
  457. else
  458. irq_packet_write(ep, req);
  459. }
  460. static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  461. {
  462. struct m66592 *m66592 = ep->m66592;
  463. u16 pipenum = ep->pipenum;
  464. if (ep->pipenum == 0) {
  465. m66592_mdfy(m66592, M66592_PIPE0,
  466. (M66592_ISEL | M66592_CURPIPE),
  467. M66592_CFIFOSEL);
  468. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  469. pipe_start(m66592, pipenum);
  470. pipe_irq_enable(m66592, pipenum);
  471. } else {
  472. if (ep->use_dma) {
  473. m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
  474. pipe_change(m66592, pipenum);
  475. m66592_bset(m66592, M66592_TRENB, ep->fifosel);
  476. m66592_write(m66592,
  477. (req->req.length + ep->ep.maxpacket - 1)
  478. / ep->ep.maxpacket,
  479. ep->fifotrn);
  480. }
  481. pipe_start(m66592, pipenum); /* trigger once */
  482. pipe_irq_enable(m66592, pipenum);
  483. }
  484. }
  485. static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
  486. {
  487. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  488. start_packet_write(ep, req);
  489. else
  490. start_packet_read(ep, req);
  491. }
  492. static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
  493. {
  494. u16 ctsq;
  495. ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
  496. switch (ctsq) {
  497. case M66592_CS_RDDS:
  498. start_ep0_write(ep, req);
  499. break;
  500. case M66592_CS_WRDS:
  501. start_packet_read(ep, req);
  502. break;
  503. case M66592_CS_WRND:
  504. control_end(ep->m66592, 0);
  505. break;
  506. default:
  507. pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
  508. break;
  509. }
  510. }
  511. static void init_controller(struct m66592 *m66592)
  512. {
  513. unsigned int endian;
  514. if (m66592->pdata->on_chip) {
  515. if (m66592->pdata->endian)
  516. endian = 0; /* big endian */
  517. else
  518. endian = M66592_LITTLE; /* little endian */
  519. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  520. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  521. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  522. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  523. /* This is a workaound for SH7722 2nd cut */
  524. m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
  525. m66592_bset(m66592, 0x1000, M66592_TESTMODE);
  526. m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
  527. m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
  528. m66592_write(m66592, 0, M66592_CFBCFG);
  529. m66592_write(m66592, 0, M66592_D0FBCFG);
  530. m66592_bset(m66592, endian, M66592_CFBCFG);
  531. m66592_bset(m66592, endian, M66592_D0FBCFG);
  532. } else {
  533. unsigned int clock, vif, irq_sense;
  534. if (m66592->pdata->endian)
  535. endian = M66592_BIGEND; /* big endian */
  536. else
  537. endian = 0; /* little endian */
  538. if (m66592->pdata->vif)
  539. vif = M66592_LDRV; /* 3.3v */
  540. else
  541. vif = 0; /* 1.5v */
  542. switch (m66592->pdata->xtal) {
  543. case M66592_PLATDATA_XTAL_12MHZ:
  544. clock = M66592_XTAL12;
  545. break;
  546. case M66592_PLATDATA_XTAL_24MHZ:
  547. clock = M66592_XTAL24;
  548. break;
  549. case M66592_PLATDATA_XTAL_48MHZ:
  550. clock = M66592_XTAL48;
  551. break;
  552. default:
  553. pr_warning("m66592-udc: xtal configuration error\n");
  554. clock = 0;
  555. }
  556. switch (m66592->irq_trigger) {
  557. case IRQF_TRIGGER_LOW:
  558. irq_sense = M66592_INTL;
  559. break;
  560. case IRQF_TRIGGER_FALLING:
  561. irq_sense = 0;
  562. break;
  563. default:
  564. pr_warning("m66592-udc: irq trigger config error\n");
  565. irq_sense = 0;
  566. }
  567. m66592_bset(m66592,
  568. (vif & M66592_LDRV) | (endian & M66592_BIGEND),
  569. M66592_PINCFG);
  570. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  571. m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
  572. M66592_SYSCFG);
  573. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  574. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  575. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  576. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  577. msleep(3);
  578. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  579. msleep(1);
  580. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  581. m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
  582. m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
  583. M66592_DMA0CFG);
  584. }
  585. }
  586. static void disable_controller(struct m66592 *m66592)
  587. {
  588. if (!m66592->pdata->on_chip) {
  589. m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
  590. udelay(1);
  591. m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
  592. udelay(1);
  593. m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
  594. udelay(1);
  595. m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
  596. }
  597. }
  598. static void m66592_start_xclock(struct m66592 *m66592)
  599. {
  600. u16 tmp;
  601. if (!m66592->pdata->on_chip) {
  602. tmp = m66592_read(m66592, M66592_SYSCFG);
  603. if (!(tmp & M66592_XCKE))
  604. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  605. }
  606. }
  607. /*-------------------------------------------------------------------------*/
  608. static void transfer_complete(struct m66592_ep *ep,
  609. struct m66592_request *req, int status)
  610. __releases(m66592->lock)
  611. __acquires(m66592->lock)
  612. {
  613. int restart = 0;
  614. if (unlikely(ep->pipenum == 0)) {
  615. if (ep->internal_ccpl) {
  616. ep->internal_ccpl = 0;
  617. return;
  618. }
  619. }
  620. list_del_init(&req->queue);
  621. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  622. req->req.status = -ESHUTDOWN;
  623. else
  624. req->req.status = status;
  625. if (!list_empty(&ep->queue))
  626. restart = 1;
  627. spin_unlock(&ep->m66592->lock);
  628. req->req.complete(&ep->ep, &req->req);
  629. spin_lock(&ep->m66592->lock);
  630. if (restart) {
  631. req = list_entry(ep->queue.next, struct m66592_request, queue);
  632. if (ep->desc)
  633. start_packet(ep, req);
  634. }
  635. }
  636. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  637. {
  638. int i;
  639. u16 tmp;
  640. unsigned bufsize;
  641. size_t size;
  642. void *buf;
  643. u16 pipenum = ep->pipenum;
  644. struct m66592 *m66592 = ep->m66592;
  645. pipe_change(m66592, pipenum);
  646. m66592_bset(m66592, M66592_ISEL, ep->fifosel);
  647. i = 0;
  648. do {
  649. tmp = m66592_read(m66592, ep->fifoctr);
  650. if (i++ > 100000) {
  651. pr_err("pipe0 is busy. maybe cpu i/o bus "
  652. "conflict. please power off this controller.");
  653. return;
  654. }
  655. ndelay(1);
  656. } while ((tmp & M66592_FRDY) == 0);
  657. /* prepare parameters */
  658. bufsize = get_buffer_size(m66592, pipenum);
  659. buf = req->req.buf + req->req.actual;
  660. size = min(bufsize, req->req.length - req->req.actual);
  661. /* write fifo */
  662. if (req->req.buf) {
  663. if (size > 0)
  664. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  665. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  666. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  667. }
  668. /* update parameters */
  669. req->req.actual += size;
  670. /* check transfer finish */
  671. if ((!req->req.zero && (req->req.actual == req->req.length))
  672. || (size % ep->ep.maxpacket)
  673. || (size == 0)) {
  674. disable_irq_ready(m66592, pipenum);
  675. disable_irq_empty(m66592, pipenum);
  676. } else {
  677. disable_irq_ready(m66592, pipenum);
  678. enable_irq_empty(m66592, pipenum);
  679. }
  680. pipe_start(m66592, pipenum);
  681. }
  682. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  683. {
  684. u16 tmp;
  685. unsigned bufsize;
  686. size_t size;
  687. void *buf;
  688. u16 pipenum = ep->pipenum;
  689. struct m66592 *m66592 = ep->m66592;
  690. pipe_change(m66592, pipenum);
  691. tmp = m66592_read(m66592, ep->fifoctr);
  692. if (unlikely((tmp & M66592_FRDY) == 0)) {
  693. pipe_stop(m66592, pipenum);
  694. pipe_irq_disable(m66592, pipenum);
  695. pr_err("write fifo not ready. pipnum=%d\n", pipenum);
  696. return;
  697. }
  698. /* prepare parameters */
  699. bufsize = get_buffer_size(m66592, pipenum);
  700. buf = req->req.buf + req->req.actual;
  701. size = min(bufsize, req->req.length - req->req.actual);
  702. /* write fifo */
  703. if (req->req.buf) {
  704. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  705. if ((size == 0)
  706. || ((size % ep->ep.maxpacket) != 0)
  707. || ((bufsize != ep->ep.maxpacket)
  708. && (bufsize > size)))
  709. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  710. }
  711. /* update parameters */
  712. req->req.actual += size;
  713. /* check transfer finish */
  714. if ((!req->req.zero && (req->req.actual == req->req.length))
  715. || (size % ep->ep.maxpacket)
  716. || (size == 0)) {
  717. disable_irq_ready(m66592, pipenum);
  718. enable_irq_empty(m66592, pipenum);
  719. } else {
  720. disable_irq_empty(m66592, pipenum);
  721. pipe_irq_enable(m66592, pipenum);
  722. }
  723. }
  724. static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  725. {
  726. u16 tmp;
  727. int rcv_len, bufsize, req_len;
  728. int size;
  729. void *buf;
  730. u16 pipenum = ep->pipenum;
  731. struct m66592 *m66592 = ep->m66592;
  732. int finish = 0;
  733. pipe_change(m66592, pipenum);
  734. tmp = m66592_read(m66592, ep->fifoctr);
  735. if (unlikely((tmp & M66592_FRDY) == 0)) {
  736. req->req.status = -EPIPE;
  737. pipe_stop(m66592, pipenum);
  738. pipe_irq_disable(m66592, pipenum);
  739. pr_err("read fifo not ready");
  740. return;
  741. }
  742. /* prepare parameters */
  743. rcv_len = tmp & M66592_DTLN;
  744. bufsize = get_buffer_size(m66592, pipenum);
  745. buf = req->req.buf + req->req.actual;
  746. req_len = req->req.length - req->req.actual;
  747. if (rcv_len < bufsize)
  748. size = min(rcv_len, req_len);
  749. else
  750. size = min(bufsize, req_len);
  751. /* update parameters */
  752. req->req.actual += size;
  753. /* check transfer finish */
  754. if ((!req->req.zero && (req->req.actual == req->req.length))
  755. || (size % ep->ep.maxpacket)
  756. || (size == 0)) {
  757. pipe_stop(m66592, pipenum);
  758. pipe_irq_disable(m66592, pipenum);
  759. finish = 1;
  760. }
  761. /* read fifo */
  762. if (req->req.buf) {
  763. if (size == 0)
  764. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  765. else
  766. m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
  767. }
  768. if ((ep->pipenum != 0) && finish)
  769. transfer_complete(ep, req, 0);
  770. }
  771. static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
  772. {
  773. u16 check;
  774. u16 pipenum;
  775. struct m66592_ep *ep;
  776. struct m66592_request *req;
  777. if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
  778. m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
  779. m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
  780. M66592_CFIFOSEL);
  781. ep = &m66592->ep[0];
  782. req = list_entry(ep->queue.next, struct m66592_request, queue);
  783. irq_packet_read(ep, req);
  784. } else {
  785. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  786. check = 1 << pipenum;
  787. if ((status & check) && (enb & check)) {
  788. m66592_write(m66592, ~check, M66592_BRDYSTS);
  789. ep = m66592->pipenum2ep[pipenum];
  790. req = list_entry(ep->queue.next,
  791. struct m66592_request, queue);
  792. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  793. irq_packet_write(ep, req);
  794. else
  795. irq_packet_read(ep, req);
  796. }
  797. }
  798. }
  799. }
  800. static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
  801. {
  802. u16 tmp;
  803. u16 check;
  804. u16 pipenum;
  805. struct m66592_ep *ep;
  806. struct m66592_request *req;
  807. if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
  808. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  809. ep = &m66592->ep[0];
  810. req = list_entry(ep->queue.next, struct m66592_request, queue);
  811. irq_ep0_write(ep, req);
  812. } else {
  813. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  814. check = 1 << pipenum;
  815. if ((status & check) && (enb & check)) {
  816. m66592_write(m66592, ~check, M66592_BEMPSTS);
  817. tmp = control_reg_get(m66592, pipenum);
  818. if ((tmp & M66592_INBUFM) == 0) {
  819. disable_irq_empty(m66592, pipenum);
  820. pipe_irq_disable(m66592, pipenum);
  821. pipe_stop(m66592, pipenum);
  822. ep = m66592->pipenum2ep[pipenum];
  823. req = list_entry(ep->queue.next,
  824. struct m66592_request,
  825. queue);
  826. if (!list_empty(&ep->queue))
  827. transfer_complete(ep, req, 0);
  828. }
  829. }
  830. }
  831. }
  832. }
  833. static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  834. __releases(m66592->lock)
  835. __acquires(m66592->lock)
  836. {
  837. struct m66592_ep *ep;
  838. u16 pid;
  839. u16 status = 0;
  840. u16 w_index = le16_to_cpu(ctrl->wIndex);
  841. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  842. case USB_RECIP_DEVICE:
  843. status = 1 << USB_DEVICE_SELF_POWERED;
  844. break;
  845. case USB_RECIP_INTERFACE:
  846. status = 0;
  847. break;
  848. case USB_RECIP_ENDPOINT:
  849. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  850. pid = control_reg_get_pid(m66592, ep->pipenum);
  851. if (pid == M66592_PID_STALL)
  852. status = 1 << USB_ENDPOINT_HALT;
  853. else
  854. status = 0;
  855. break;
  856. default:
  857. pipe_stall(m66592, 0);
  858. return; /* exit */
  859. }
  860. m66592->ep0_data = cpu_to_le16(status);
  861. m66592->ep0_req->buf = &m66592->ep0_data;
  862. m66592->ep0_req->length = 2;
  863. /* AV: what happens if we get called again before that gets through? */
  864. spin_unlock(&m66592->lock);
  865. m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
  866. spin_lock(&m66592->lock);
  867. }
  868. static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  869. {
  870. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  871. case USB_RECIP_DEVICE:
  872. control_end(m66592, 1);
  873. break;
  874. case USB_RECIP_INTERFACE:
  875. control_end(m66592, 1);
  876. break;
  877. case USB_RECIP_ENDPOINT: {
  878. struct m66592_ep *ep;
  879. struct m66592_request *req;
  880. u16 w_index = le16_to_cpu(ctrl->wIndex);
  881. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  882. pipe_stop(m66592, ep->pipenum);
  883. control_reg_sqclr(m66592, ep->pipenum);
  884. control_end(m66592, 1);
  885. req = list_entry(ep->queue.next,
  886. struct m66592_request, queue);
  887. if (ep->busy) {
  888. ep->busy = 0;
  889. if (list_empty(&ep->queue))
  890. break;
  891. start_packet(ep, req);
  892. } else if (!list_empty(&ep->queue))
  893. pipe_start(m66592, ep->pipenum);
  894. }
  895. break;
  896. default:
  897. pipe_stall(m66592, 0);
  898. break;
  899. }
  900. }
  901. static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  902. {
  903. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  904. case USB_RECIP_DEVICE:
  905. control_end(m66592, 1);
  906. break;
  907. case USB_RECIP_INTERFACE:
  908. control_end(m66592, 1);
  909. break;
  910. case USB_RECIP_ENDPOINT: {
  911. struct m66592_ep *ep;
  912. u16 w_index = le16_to_cpu(ctrl->wIndex);
  913. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  914. pipe_stall(m66592, ep->pipenum);
  915. control_end(m66592, 1);
  916. }
  917. break;
  918. default:
  919. pipe_stall(m66592, 0);
  920. break;
  921. }
  922. }
  923. /* if return value is true, call class driver's setup() */
  924. static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  925. {
  926. u16 *p = (u16 *)ctrl;
  927. unsigned long offset = M66592_USBREQ;
  928. int i, ret = 0;
  929. /* read fifo */
  930. m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
  931. for (i = 0; i < 4; i++)
  932. p[i] = m66592_read(m66592, offset + i*2);
  933. /* check request */
  934. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  935. switch (ctrl->bRequest) {
  936. case USB_REQ_GET_STATUS:
  937. get_status(m66592, ctrl);
  938. break;
  939. case USB_REQ_CLEAR_FEATURE:
  940. clear_feature(m66592, ctrl);
  941. break;
  942. case USB_REQ_SET_FEATURE:
  943. set_feature(m66592, ctrl);
  944. break;
  945. default:
  946. ret = 1;
  947. break;
  948. }
  949. } else
  950. ret = 1;
  951. return ret;
  952. }
  953. static void m66592_update_usb_speed(struct m66592 *m66592)
  954. {
  955. u16 speed = get_usb_speed(m66592);
  956. switch (speed) {
  957. case M66592_HSMODE:
  958. m66592->gadget.speed = USB_SPEED_HIGH;
  959. break;
  960. case M66592_FSMODE:
  961. m66592->gadget.speed = USB_SPEED_FULL;
  962. break;
  963. default:
  964. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  965. pr_err("USB speed unknown\n");
  966. }
  967. }
  968. static void irq_device_state(struct m66592 *m66592)
  969. {
  970. u16 dvsq;
  971. dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
  972. m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
  973. if (dvsq == M66592_DS_DFLT) { /* bus reset */
  974. m66592->driver->disconnect(&m66592->gadget);
  975. m66592_update_usb_speed(m66592);
  976. }
  977. if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
  978. m66592_update_usb_speed(m66592);
  979. if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
  980. && m66592->gadget.speed == USB_SPEED_UNKNOWN)
  981. m66592_update_usb_speed(m66592);
  982. m66592->old_dvsq = dvsq;
  983. }
  984. static void irq_control_stage(struct m66592 *m66592)
  985. __releases(m66592->lock)
  986. __acquires(m66592->lock)
  987. {
  988. struct usb_ctrlrequest ctrl;
  989. u16 ctsq;
  990. ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
  991. m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
  992. switch (ctsq) {
  993. case M66592_CS_IDST: {
  994. struct m66592_ep *ep;
  995. struct m66592_request *req;
  996. ep = &m66592->ep[0];
  997. req = list_entry(ep->queue.next, struct m66592_request, queue);
  998. transfer_complete(ep, req, 0);
  999. }
  1000. break;
  1001. case M66592_CS_RDDS:
  1002. case M66592_CS_WRDS:
  1003. case M66592_CS_WRND:
  1004. if (setup_packet(m66592, &ctrl)) {
  1005. spin_unlock(&m66592->lock);
  1006. if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
  1007. pipe_stall(m66592, 0);
  1008. spin_lock(&m66592->lock);
  1009. }
  1010. break;
  1011. case M66592_CS_RDSS:
  1012. case M66592_CS_WRSS:
  1013. control_end(m66592, 0);
  1014. break;
  1015. default:
  1016. pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  1017. break;
  1018. }
  1019. }
  1020. static irqreturn_t m66592_irq(int irq, void *_m66592)
  1021. {
  1022. struct m66592 *m66592 = _m66592;
  1023. u16 intsts0;
  1024. u16 intenb0;
  1025. u16 brdysts, nrdysts, bempsts;
  1026. u16 brdyenb, nrdyenb, bempenb;
  1027. u16 savepipe;
  1028. u16 mask0;
  1029. spin_lock(&m66592->lock);
  1030. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1031. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1032. if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
  1033. /*
  1034. * When USB clock stops, it cannot read register. Even if a
  1035. * clock stops, the interrupt occurs. So this driver turn on
  1036. * a clock by this timing and do re-reading of register.
  1037. */
  1038. m66592_start_xclock(m66592);
  1039. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1040. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1041. }
  1042. savepipe = m66592_read(m66592, M66592_CFIFOSEL);
  1043. mask0 = intsts0 & intenb0;
  1044. if (mask0) {
  1045. brdysts = m66592_read(m66592, M66592_BRDYSTS);
  1046. nrdysts = m66592_read(m66592, M66592_NRDYSTS);
  1047. bempsts = m66592_read(m66592, M66592_BEMPSTS);
  1048. brdyenb = m66592_read(m66592, M66592_BRDYENB);
  1049. nrdyenb = m66592_read(m66592, M66592_NRDYENB);
  1050. bempenb = m66592_read(m66592, M66592_BEMPENB);
  1051. if (mask0 & M66592_VBINT) {
  1052. m66592_write(m66592, 0xffff & ~M66592_VBINT,
  1053. M66592_INTSTS0);
  1054. m66592_start_xclock(m66592);
  1055. /* start vbus sampling */
  1056. m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
  1057. & M66592_VBSTS;
  1058. m66592->scount = M66592_MAX_SAMPLING;
  1059. mod_timer(&m66592->timer,
  1060. jiffies + msecs_to_jiffies(50));
  1061. }
  1062. if (intsts0 & M66592_DVSQ)
  1063. irq_device_state(m66592);
  1064. if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
  1065. && (brdysts & brdyenb)) {
  1066. irq_pipe_ready(m66592, brdysts, brdyenb);
  1067. }
  1068. if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
  1069. && (bempsts & bempenb)) {
  1070. irq_pipe_empty(m66592, bempsts, bempenb);
  1071. }
  1072. if (intsts0 & M66592_CTRT)
  1073. irq_control_stage(m66592);
  1074. }
  1075. m66592_write(m66592, savepipe, M66592_CFIFOSEL);
  1076. spin_unlock(&m66592->lock);
  1077. return IRQ_HANDLED;
  1078. }
  1079. static void m66592_timer(unsigned long _m66592)
  1080. {
  1081. struct m66592 *m66592 = (struct m66592 *)_m66592;
  1082. unsigned long flags;
  1083. u16 tmp;
  1084. spin_lock_irqsave(&m66592->lock, flags);
  1085. tmp = m66592_read(m66592, M66592_SYSCFG);
  1086. if (!(tmp & M66592_RCKE)) {
  1087. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  1088. udelay(10);
  1089. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  1090. }
  1091. if (m66592->scount > 0) {
  1092. tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
  1093. if (tmp == m66592->old_vbus) {
  1094. m66592->scount--;
  1095. if (m66592->scount == 0) {
  1096. if (tmp == M66592_VBSTS)
  1097. m66592_usb_connect(m66592);
  1098. else
  1099. m66592_usb_disconnect(m66592);
  1100. } else {
  1101. mod_timer(&m66592->timer,
  1102. jiffies + msecs_to_jiffies(50));
  1103. }
  1104. } else {
  1105. m66592->scount = M66592_MAX_SAMPLING;
  1106. m66592->old_vbus = tmp;
  1107. mod_timer(&m66592->timer,
  1108. jiffies + msecs_to_jiffies(50));
  1109. }
  1110. }
  1111. spin_unlock_irqrestore(&m66592->lock, flags);
  1112. }
  1113. /*-------------------------------------------------------------------------*/
  1114. static int m66592_enable(struct usb_ep *_ep,
  1115. const struct usb_endpoint_descriptor *desc)
  1116. {
  1117. struct m66592_ep *ep;
  1118. ep = container_of(_ep, struct m66592_ep, ep);
  1119. return alloc_pipe_config(ep, desc);
  1120. }
  1121. static int m66592_disable(struct usb_ep *_ep)
  1122. {
  1123. struct m66592_ep *ep;
  1124. struct m66592_request *req;
  1125. unsigned long flags;
  1126. ep = container_of(_ep, struct m66592_ep, ep);
  1127. BUG_ON(!ep);
  1128. while (!list_empty(&ep->queue)) {
  1129. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1130. spin_lock_irqsave(&ep->m66592->lock, flags);
  1131. transfer_complete(ep, req, -ECONNRESET);
  1132. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1133. }
  1134. pipe_irq_disable(ep->m66592, ep->pipenum);
  1135. return free_pipe_config(ep);
  1136. }
  1137. static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
  1138. gfp_t gfp_flags)
  1139. {
  1140. struct m66592_request *req;
  1141. req = kzalloc(sizeof(struct m66592_request), gfp_flags);
  1142. if (!req)
  1143. return NULL;
  1144. INIT_LIST_HEAD(&req->queue);
  1145. return &req->req;
  1146. }
  1147. static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1148. {
  1149. struct m66592_request *req;
  1150. req = container_of(_req, struct m66592_request, req);
  1151. kfree(req);
  1152. }
  1153. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  1154. gfp_t gfp_flags)
  1155. {
  1156. struct m66592_ep *ep;
  1157. struct m66592_request *req;
  1158. unsigned long flags;
  1159. int request = 0;
  1160. ep = container_of(_ep, struct m66592_ep, ep);
  1161. req = container_of(_req, struct m66592_request, req);
  1162. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1163. return -ESHUTDOWN;
  1164. spin_lock_irqsave(&ep->m66592->lock, flags);
  1165. if (list_empty(&ep->queue))
  1166. request = 1;
  1167. list_add_tail(&req->queue, &ep->queue);
  1168. req->req.actual = 0;
  1169. req->req.status = -EINPROGRESS;
  1170. if (ep->desc == NULL) /* control */
  1171. start_ep0(ep, req);
  1172. else {
  1173. if (request && !ep->busy)
  1174. start_packet(ep, req);
  1175. }
  1176. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1177. return 0;
  1178. }
  1179. static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1180. {
  1181. struct m66592_ep *ep;
  1182. struct m66592_request *req;
  1183. unsigned long flags;
  1184. ep = container_of(_ep, struct m66592_ep, ep);
  1185. req = container_of(_req, struct m66592_request, req);
  1186. spin_lock_irqsave(&ep->m66592->lock, flags);
  1187. if (!list_empty(&ep->queue))
  1188. transfer_complete(ep, req, -ECONNRESET);
  1189. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1190. return 0;
  1191. }
  1192. static int m66592_set_halt(struct usb_ep *_ep, int value)
  1193. {
  1194. struct m66592_ep *ep;
  1195. struct m66592_request *req;
  1196. unsigned long flags;
  1197. int ret = 0;
  1198. ep = container_of(_ep, struct m66592_ep, ep);
  1199. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1200. spin_lock_irqsave(&ep->m66592->lock, flags);
  1201. if (!list_empty(&ep->queue)) {
  1202. ret = -EAGAIN;
  1203. goto out;
  1204. }
  1205. if (value) {
  1206. ep->busy = 1;
  1207. pipe_stall(ep->m66592, ep->pipenum);
  1208. } else {
  1209. ep->busy = 0;
  1210. pipe_stop(ep->m66592, ep->pipenum);
  1211. }
  1212. out:
  1213. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1214. return ret;
  1215. }
  1216. static void m66592_fifo_flush(struct usb_ep *_ep)
  1217. {
  1218. struct m66592_ep *ep;
  1219. unsigned long flags;
  1220. ep = container_of(_ep, struct m66592_ep, ep);
  1221. spin_lock_irqsave(&ep->m66592->lock, flags);
  1222. if (list_empty(&ep->queue) && !ep->busy) {
  1223. pipe_stop(ep->m66592, ep->pipenum);
  1224. m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
  1225. }
  1226. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1227. }
  1228. static struct usb_ep_ops m66592_ep_ops = {
  1229. .enable = m66592_enable,
  1230. .disable = m66592_disable,
  1231. .alloc_request = m66592_alloc_request,
  1232. .free_request = m66592_free_request,
  1233. .queue = m66592_queue,
  1234. .dequeue = m66592_dequeue,
  1235. .set_halt = m66592_set_halt,
  1236. .fifo_flush = m66592_fifo_flush,
  1237. };
  1238. /*-------------------------------------------------------------------------*/
  1239. static struct m66592 *the_controller;
  1240. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1241. {
  1242. struct m66592 *m66592 = the_controller;
  1243. int retval;
  1244. if (!driver
  1245. || driver->speed != USB_SPEED_HIGH
  1246. || !driver->bind
  1247. || !driver->setup)
  1248. return -EINVAL;
  1249. if (!m66592)
  1250. return -ENODEV;
  1251. if (m66592->driver)
  1252. return -EBUSY;
  1253. /* hook up the driver */
  1254. driver->driver.bus = NULL;
  1255. m66592->driver = driver;
  1256. m66592->gadget.dev.driver = &driver->driver;
  1257. retval = device_add(&m66592->gadget.dev);
  1258. if (retval) {
  1259. pr_err("device_add error (%d)\n", retval);
  1260. goto error;
  1261. }
  1262. retval = driver->bind (&m66592->gadget);
  1263. if (retval) {
  1264. pr_err("bind to driver error (%d)\n", retval);
  1265. device_del(&m66592->gadget.dev);
  1266. goto error;
  1267. }
  1268. m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1269. if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
  1270. m66592_start_xclock(m66592);
  1271. /* start vbus sampling */
  1272. m66592->old_vbus = m66592_read(m66592,
  1273. M66592_INTSTS0) & M66592_VBSTS;
  1274. m66592->scount = M66592_MAX_SAMPLING;
  1275. mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
  1276. }
  1277. return 0;
  1278. error:
  1279. m66592->driver = NULL;
  1280. m66592->gadget.dev.driver = NULL;
  1281. return retval;
  1282. }
  1283. EXPORT_SYMBOL(usb_gadget_register_driver);
  1284. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1285. {
  1286. struct m66592 *m66592 = the_controller;
  1287. unsigned long flags;
  1288. if (driver != m66592->driver || !driver->unbind)
  1289. return -EINVAL;
  1290. spin_lock_irqsave(&m66592->lock, flags);
  1291. if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
  1292. m66592_usb_disconnect(m66592);
  1293. spin_unlock_irqrestore(&m66592->lock, flags);
  1294. m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1295. driver->unbind(&m66592->gadget);
  1296. m66592->gadget.dev.driver = NULL;
  1297. init_controller(m66592);
  1298. disable_controller(m66592);
  1299. device_del(&m66592->gadget.dev);
  1300. m66592->driver = NULL;
  1301. return 0;
  1302. }
  1303. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1304. /*-------------------------------------------------------------------------*/
  1305. static int m66592_get_frame(struct usb_gadget *_gadget)
  1306. {
  1307. struct m66592 *m66592 = gadget_to_m66592(_gadget);
  1308. return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
  1309. }
  1310. static struct usb_gadget_ops m66592_gadget_ops = {
  1311. .get_frame = m66592_get_frame,
  1312. };
  1313. static int __exit m66592_remove(struct platform_device *pdev)
  1314. {
  1315. struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
  1316. del_timer_sync(&m66592->timer);
  1317. iounmap(m66592->reg);
  1318. free_irq(platform_get_irq(pdev, 0), m66592);
  1319. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1320. #ifdef CONFIG_HAVE_CLK
  1321. if (m66592->pdata->on_chip) {
  1322. clk_disable(m66592->clk);
  1323. clk_put(m66592->clk);
  1324. }
  1325. #endif
  1326. kfree(m66592);
  1327. return 0;
  1328. }
  1329. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1330. {
  1331. }
  1332. static int __init m66592_probe(struct platform_device *pdev)
  1333. {
  1334. struct resource *res, *ires;
  1335. void __iomem *reg = NULL;
  1336. struct m66592 *m66592 = NULL;
  1337. #ifdef CONFIG_HAVE_CLK
  1338. char clk_name[8];
  1339. #endif
  1340. int ret = 0;
  1341. int i;
  1342. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1343. if (!res) {
  1344. ret = -ENODEV;
  1345. pr_err("platform_get_resource error.\n");
  1346. goto clean_up;
  1347. }
  1348. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1349. if (!ires) {
  1350. ret = -ENODEV;
  1351. dev_err(&pdev->dev,
  1352. "platform_get_resource IORESOURCE_IRQ error.\n");
  1353. goto clean_up;
  1354. }
  1355. reg = ioremap(res->start, resource_size(res));
  1356. if (reg == NULL) {
  1357. ret = -ENOMEM;
  1358. pr_err("ioremap error.\n");
  1359. goto clean_up;
  1360. }
  1361. if (pdev->dev.platform_data == NULL) {
  1362. dev_err(&pdev->dev, "no platform data\n");
  1363. ret = -ENODEV;
  1364. goto clean_up;
  1365. }
  1366. /* initialize ucd */
  1367. m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
  1368. if (m66592 == NULL) {
  1369. ret = -ENOMEM;
  1370. pr_err("kzalloc error\n");
  1371. goto clean_up;
  1372. }
  1373. m66592->pdata = pdev->dev.platform_data;
  1374. m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1375. spin_lock_init(&m66592->lock);
  1376. dev_set_drvdata(&pdev->dev, m66592);
  1377. m66592->gadget.ops = &m66592_gadget_ops;
  1378. device_initialize(&m66592->gadget.dev);
  1379. dev_set_name(&m66592->gadget.dev, "gadget");
  1380. m66592->gadget.is_dualspeed = 1;
  1381. m66592->gadget.dev.parent = &pdev->dev;
  1382. m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1383. m66592->gadget.dev.release = pdev->dev.release;
  1384. m66592->gadget.name = udc_name;
  1385. init_timer(&m66592->timer);
  1386. m66592->timer.function = m66592_timer;
  1387. m66592->timer.data = (unsigned long)m66592;
  1388. m66592->reg = reg;
  1389. ret = request_irq(ires->start, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
  1390. udc_name, m66592);
  1391. if (ret < 0) {
  1392. pr_err("request_irq error (%d)\n", ret);
  1393. goto clean_up;
  1394. }
  1395. #ifdef CONFIG_HAVE_CLK
  1396. if (m66592->pdata->on_chip) {
  1397. snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
  1398. m66592->clk = clk_get(&pdev->dev, clk_name);
  1399. if (IS_ERR(m66592->clk)) {
  1400. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1401. clk_name);
  1402. ret = PTR_ERR(m66592->clk);
  1403. goto clean_up2;
  1404. }
  1405. clk_enable(m66592->clk);
  1406. }
  1407. #endif
  1408. INIT_LIST_HEAD(&m66592->gadget.ep_list);
  1409. m66592->gadget.ep0 = &m66592->ep[0].ep;
  1410. INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
  1411. for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
  1412. struct m66592_ep *ep = &m66592->ep[i];
  1413. if (i != 0) {
  1414. INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
  1415. list_add_tail(&m66592->ep[i].ep.ep_list,
  1416. &m66592->gadget.ep_list);
  1417. }
  1418. ep->m66592 = m66592;
  1419. INIT_LIST_HEAD(&ep->queue);
  1420. ep->ep.name = m66592_ep_name[i];
  1421. ep->ep.ops = &m66592_ep_ops;
  1422. ep->ep.maxpacket = 512;
  1423. }
  1424. m66592->ep[0].ep.maxpacket = 64;
  1425. m66592->ep[0].pipenum = 0;
  1426. m66592->ep[0].fifoaddr = M66592_CFIFO;
  1427. m66592->ep[0].fifosel = M66592_CFIFOSEL;
  1428. m66592->ep[0].fifoctr = M66592_CFIFOCTR;
  1429. m66592->ep[0].fifotrn = 0;
  1430. m66592->ep[0].pipectr = get_pipectr_addr(0);
  1431. m66592->pipenum2ep[0] = &m66592->ep[0];
  1432. m66592->epaddr2ep[0] = &m66592->ep[0];
  1433. the_controller = m66592;
  1434. m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
  1435. if (m66592->ep0_req == NULL)
  1436. goto clean_up3;
  1437. m66592->ep0_req->complete = nop_completion;
  1438. init_controller(m66592);
  1439. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1440. return 0;
  1441. clean_up3:
  1442. #ifdef CONFIG_HAVE_CLK
  1443. if (m66592->pdata->on_chip) {
  1444. clk_disable(m66592->clk);
  1445. clk_put(m66592->clk);
  1446. }
  1447. clean_up2:
  1448. #endif
  1449. free_irq(ires->start, m66592);
  1450. clean_up:
  1451. if (m66592) {
  1452. if (m66592->ep0_req)
  1453. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1454. kfree(m66592);
  1455. }
  1456. if (reg)
  1457. iounmap(reg);
  1458. return ret;
  1459. }
  1460. /*-------------------------------------------------------------------------*/
  1461. static struct platform_driver m66592_driver = {
  1462. .remove = __exit_p(m66592_remove),
  1463. .driver = {
  1464. .name = (char *) udc_name,
  1465. .owner = THIS_MODULE,
  1466. },
  1467. };
  1468. static int __init m66592_udc_init(void)
  1469. {
  1470. return platform_driver_probe(&m66592_driver, m66592_probe);
  1471. }
  1472. module_init(m66592_udc_init);
  1473. static void __exit m66592_udc_cleanup(void)
  1474. {
  1475. platform_driver_unregister(&m66592_driver);
  1476. }
  1477. module_exit(m66592_udc_cleanup);