main.c 31 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Subsystem core
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/ssb/ssb.h>
  14. #include <linux/ssb/ssb_regs.h>
  15. #include <linux/ssb/ssb_driver_gige.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/pci.h>
  18. #include <linux/mmc/sdio_func.h>
  19. #include <linux/slab.h>
  20. #include <pcmcia/cs.h>
  21. #include <pcmcia/cistpl.h>
  22. #include <pcmcia/ds.h>
  23. MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
  24. MODULE_LICENSE("GPL");
  25. /* Temporary list of yet-to-be-attached buses */
  26. static LIST_HEAD(attach_queue);
  27. /* List if running buses */
  28. static LIST_HEAD(buses);
  29. /* Software ID counter */
  30. static unsigned int next_busnumber;
  31. /* buses_mutes locks the two buslists and the next_busnumber.
  32. * Don't lock this directly, but use ssb_buses_[un]lock() below. */
  33. static DEFINE_MUTEX(buses_mutex);
  34. /* There are differences in the codeflow, if the bus is
  35. * initialized from early boot, as various needed services
  36. * are not available early. This is a mechanism to delay
  37. * these initializations to after early boot has finished.
  38. * It's also used to avoid mutex locking, as that's not
  39. * available and needed early. */
  40. static bool ssb_is_early_boot = 1;
  41. static void ssb_buses_lock(void);
  42. static void ssb_buses_unlock(void);
  43. #ifdef CONFIG_SSB_PCIHOST
  44. struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
  45. {
  46. struct ssb_bus *bus;
  47. ssb_buses_lock();
  48. list_for_each_entry(bus, &buses, list) {
  49. if (bus->bustype == SSB_BUSTYPE_PCI &&
  50. bus->host_pci == pdev)
  51. goto found;
  52. }
  53. bus = NULL;
  54. found:
  55. ssb_buses_unlock();
  56. return bus;
  57. }
  58. #endif /* CONFIG_SSB_PCIHOST */
  59. #ifdef CONFIG_SSB_PCMCIAHOST
  60. struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
  61. {
  62. struct ssb_bus *bus;
  63. ssb_buses_lock();
  64. list_for_each_entry(bus, &buses, list) {
  65. if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
  66. bus->host_pcmcia == pdev)
  67. goto found;
  68. }
  69. bus = NULL;
  70. found:
  71. ssb_buses_unlock();
  72. return bus;
  73. }
  74. #endif /* CONFIG_SSB_PCMCIAHOST */
  75. #ifdef CONFIG_SSB_SDIOHOST
  76. struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
  77. {
  78. struct ssb_bus *bus;
  79. ssb_buses_lock();
  80. list_for_each_entry(bus, &buses, list) {
  81. if (bus->bustype == SSB_BUSTYPE_SDIO &&
  82. bus->host_sdio == func)
  83. goto found;
  84. }
  85. bus = NULL;
  86. found:
  87. ssb_buses_unlock();
  88. return bus;
  89. }
  90. #endif /* CONFIG_SSB_SDIOHOST */
  91. int ssb_for_each_bus_call(unsigned long data,
  92. int (*func)(struct ssb_bus *bus, unsigned long data))
  93. {
  94. struct ssb_bus *bus;
  95. int res;
  96. ssb_buses_lock();
  97. list_for_each_entry(bus, &buses, list) {
  98. res = func(bus, data);
  99. if (res >= 0) {
  100. ssb_buses_unlock();
  101. return res;
  102. }
  103. }
  104. ssb_buses_unlock();
  105. return -ENODEV;
  106. }
  107. static struct ssb_device *ssb_device_get(struct ssb_device *dev)
  108. {
  109. if (dev)
  110. get_device(dev->dev);
  111. return dev;
  112. }
  113. static void ssb_device_put(struct ssb_device *dev)
  114. {
  115. if (dev)
  116. put_device(dev->dev);
  117. }
  118. static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
  119. {
  120. if (drv)
  121. get_driver(&drv->drv);
  122. return drv;
  123. }
  124. static inline void ssb_driver_put(struct ssb_driver *drv)
  125. {
  126. if (drv)
  127. put_driver(&drv->drv);
  128. }
  129. static int ssb_device_resume(struct device *dev)
  130. {
  131. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  132. struct ssb_driver *ssb_drv;
  133. int err = 0;
  134. if (dev->driver) {
  135. ssb_drv = drv_to_ssb_drv(dev->driver);
  136. if (ssb_drv && ssb_drv->resume)
  137. err = ssb_drv->resume(ssb_dev);
  138. if (err)
  139. goto out;
  140. }
  141. out:
  142. return err;
  143. }
  144. static int ssb_device_suspend(struct device *dev, pm_message_t state)
  145. {
  146. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  147. struct ssb_driver *ssb_drv;
  148. int err = 0;
  149. if (dev->driver) {
  150. ssb_drv = drv_to_ssb_drv(dev->driver);
  151. if (ssb_drv && ssb_drv->suspend)
  152. err = ssb_drv->suspend(ssb_dev, state);
  153. if (err)
  154. goto out;
  155. }
  156. out:
  157. return err;
  158. }
  159. int ssb_bus_resume(struct ssb_bus *bus)
  160. {
  161. int err;
  162. /* Reset HW state information in memory, so that HW is
  163. * completely reinitialized. */
  164. bus->mapped_device = NULL;
  165. #ifdef CONFIG_SSB_DRIVER_PCICORE
  166. bus->pcicore.setup_done = 0;
  167. #endif
  168. err = ssb_bus_powerup(bus, 0);
  169. if (err)
  170. return err;
  171. err = ssb_pcmcia_hardware_setup(bus);
  172. if (err) {
  173. ssb_bus_may_powerdown(bus);
  174. return err;
  175. }
  176. ssb_chipco_resume(&bus->chipco);
  177. ssb_bus_may_powerdown(bus);
  178. return 0;
  179. }
  180. EXPORT_SYMBOL(ssb_bus_resume);
  181. int ssb_bus_suspend(struct ssb_bus *bus)
  182. {
  183. ssb_chipco_suspend(&bus->chipco);
  184. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  185. return 0;
  186. }
  187. EXPORT_SYMBOL(ssb_bus_suspend);
  188. #ifdef CONFIG_SSB_SPROM
  189. /** ssb_devices_freeze - Freeze all devices on the bus.
  190. *
  191. * After freezing no device driver will be handling a device
  192. * on this bus anymore. ssb_devices_thaw() must be called after
  193. * a successful freeze to reactivate the devices.
  194. *
  195. * @bus: The bus.
  196. * @ctx: Context structure. Pass this to ssb_devices_thaw().
  197. */
  198. int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
  199. {
  200. struct ssb_device *sdev;
  201. struct ssb_driver *sdrv;
  202. unsigned int i;
  203. memset(ctx, 0, sizeof(*ctx));
  204. ctx->bus = bus;
  205. SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
  206. for (i = 0; i < bus->nr_devices; i++) {
  207. sdev = ssb_device_get(&bus->devices[i]);
  208. if (!sdev->dev || !sdev->dev->driver ||
  209. !device_is_registered(sdev->dev)) {
  210. ssb_device_put(sdev);
  211. continue;
  212. }
  213. sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
  214. if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
  215. ssb_device_put(sdev);
  216. continue;
  217. }
  218. sdrv->remove(sdev);
  219. ctx->device_frozen[i] = 1;
  220. }
  221. return 0;
  222. }
  223. /** ssb_devices_thaw - Unfreeze all devices on the bus.
  224. *
  225. * This will re-attach the device drivers and re-init the devices.
  226. *
  227. * @ctx: The context structure from ssb_devices_freeze()
  228. */
  229. int ssb_devices_thaw(struct ssb_freeze_context *ctx)
  230. {
  231. struct ssb_bus *bus = ctx->bus;
  232. struct ssb_device *sdev;
  233. struct ssb_driver *sdrv;
  234. unsigned int i;
  235. int err, result = 0;
  236. for (i = 0; i < bus->nr_devices; i++) {
  237. if (!ctx->device_frozen[i])
  238. continue;
  239. sdev = &bus->devices[i];
  240. if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
  241. continue;
  242. sdrv = drv_to_ssb_drv(sdev->dev->driver);
  243. if (SSB_WARN_ON(!sdrv || !sdrv->probe))
  244. continue;
  245. err = sdrv->probe(sdev, &sdev->id);
  246. if (err) {
  247. ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
  248. dev_name(sdev->dev));
  249. result = err;
  250. }
  251. ssb_driver_put(sdrv);
  252. ssb_device_put(sdev);
  253. }
  254. return result;
  255. }
  256. #endif /* CONFIG_SSB_SPROM */
  257. static void ssb_device_shutdown(struct device *dev)
  258. {
  259. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  260. struct ssb_driver *ssb_drv;
  261. if (!dev->driver)
  262. return;
  263. ssb_drv = drv_to_ssb_drv(dev->driver);
  264. if (ssb_drv && ssb_drv->shutdown)
  265. ssb_drv->shutdown(ssb_dev);
  266. }
  267. static int ssb_device_remove(struct device *dev)
  268. {
  269. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  270. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  271. if (ssb_drv && ssb_drv->remove)
  272. ssb_drv->remove(ssb_dev);
  273. ssb_device_put(ssb_dev);
  274. return 0;
  275. }
  276. static int ssb_device_probe(struct device *dev)
  277. {
  278. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  279. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  280. int err = 0;
  281. ssb_device_get(ssb_dev);
  282. if (ssb_drv && ssb_drv->probe)
  283. err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
  284. if (err)
  285. ssb_device_put(ssb_dev);
  286. return err;
  287. }
  288. static int ssb_match_devid(const struct ssb_device_id *tabid,
  289. const struct ssb_device_id *devid)
  290. {
  291. if ((tabid->vendor != devid->vendor) &&
  292. tabid->vendor != SSB_ANY_VENDOR)
  293. return 0;
  294. if ((tabid->coreid != devid->coreid) &&
  295. tabid->coreid != SSB_ANY_ID)
  296. return 0;
  297. if ((tabid->revision != devid->revision) &&
  298. tabid->revision != SSB_ANY_REV)
  299. return 0;
  300. return 1;
  301. }
  302. static int ssb_bus_match(struct device *dev, struct device_driver *drv)
  303. {
  304. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  305. struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
  306. const struct ssb_device_id *id;
  307. for (id = ssb_drv->id_table;
  308. id->vendor || id->coreid || id->revision;
  309. id++) {
  310. if (ssb_match_devid(id, &ssb_dev->id))
  311. return 1; /* found */
  312. }
  313. return 0;
  314. }
  315. static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
  316. {
  317. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  318. if (!dev)
  319. return -ENODEV;
  320. return add_uevent_var(env,
  321. "MODALIAS=ssb:v%04Xid%04Xrev%02X",
  322. ssb_dev->id.vendor, ssb_dev->id.coreid,
  323. ssb_dev->id.revision);
  324. }
  325. static struct bus_type ssb_bustype = {
  326. .name = "ssb",
  327. .match = ssb_bus_match,
  328. .probe = ssb_device_probe,
  329. .remove = ssb_device_remove,
  330. .shutdown = ssb_device_shutdown,
  331. .suspend = ssb_device_suspend,
  332. .resume = ssb_device_resume,
  333. .uevent = ssb_device_uevent,
  334. };
  335. static void ssb_buses_lock(void)
  336. {
  337. /* See the comment at the ssb_is_early_boot definition */
  338. if (!ssb_is_early_boot)
  339. mutex_lock(&buses_mutex);
  340. }
  341. static void ssb_buses_unlock(void)
  342. {
  343. /* See the comment at the ssb_is_early_boot definition */
  344. if (!ssb_is_early_boot)
  345. mutex_unlock(&buses_mutex);
  346. }
  347. static void ssb_devices_unregister(struct ssb_bus *bus)
  348. {
  349. struct ssb_device *sdev;
  350. int i;
  351. for (i = bus->nr_devices - 1; i >= 0; i--) {
  352. sdev = &(bus->devices[i]);
  353. if (sdev->dev)
  354. device_unregister(sdev->dev);
  355. }
  356. }
  357. void ssb_bus_unregister(struct ssb_bus *bus)
  358. {
  359. ssb_buses_lock();
  360. ssb_devices_unregister(bus);
  361. list_del(&bus->list);
  362. ssb_buses_unlock();
  363. ssb_pcmcia_exit(bus);
  364. ssb_pci_exit(bus);
  365. ssb_iounmap(bus);
  366. }
  367. EXPORT_SYMBOL(ssb_bus_unregister);
  368. static void ssb_release_dev(struct device *dev)
  369. {
  370. struct __ssb_dev_wrapper *devwrap;
  371. devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  372. kfree(devwrap);
  373. }
  374. static int ssb_devices_register(struct ssb_bus *bus)
  375. {
  376. struct ssb_device *sdev;
  377. struct device *dev;
  378. struct __ssb_dev_wrapper *devwrap;
  379. int i, err = 0;
  380. int dev_idx = 0;
  381. for (i = 0; i < bus->nr_devices; i++) {
  382. sdev = &(bus->devices[i]);
  383. /* We don't register SSB-system devices to the kernel,
  384. * as the drivers for them are built into SSB. */
  385. switch (sdev->id.coreid) {
  386. case SSB_DEV_CHIPCOMMON:
  387. case SSB_DEV_PCI:
  388. case SSB_DEV_PCIE:
  389. case SSB_DEV_PCMCIA:
  390. case SSB_DEV_MIPS:
  391. case SSB_DEV_MIPS_3302:
  392. case SSB_DEV_EXTIF:
  393. continue;
  394. }
  395. devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
  396. if (!devwrap) {
  397. ssb_printk(KERN_ERR PFX
  398. "Could not allocate device\n");
  399. err = -ENOMEM;
  400. goto error;
  401. }
  402. dev = &devwrap->dev;
  403. devwrap->sdev = sdev;
  404. dev->release = ssb_release_dev;
  405. dev->bus = &ssb_bustype;
  406. dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
  407. switch (bus->bustype) {
  408. case SSB_BUSTYPE_PCI:
  409. #ifdef CONFIG_SSB_PCIHOST
  410. sdev->irq = bus->host_pci->irq;
  411. dev->parent = &bus->host_pci->dev;
  412. sdev->dma_dev = dev->parent;
  413. #endif
  414. break;
  415. case SSB_BUSTYPE_PCMCIA:
  416. #ifdef CONFIG_SSB_PCMCIAHOST
  417. sdev->irq = bus->host_pcmcia->irq;
  418. dev->parent = &bus->host_pcmcia->dev;
  419. #endif
  420. break;
  421. case SSB_BUSTYPE_SDIO:
  422. #ifdef CONFIG_SSB_SDIOHOST
  423. dev->parent = &bus->host_sdio->dev;
  424. #endif
  425. break;
  426. case SSB_BUSTYPE_SSB:
  427. dev->dma_mask = &dev->coherent_dma_mask;
  428. sdev->dma_dev = dev;
  429. break;
  430. }
  431. sdev->dev = dev;
  432. err = device_register(dev);
  433. if (err) {
  434. ssb_printk(KERN_ERR PFX
  435. "Could not register %s\n",
  436. dev_name(dev));
  437. /* Set dev to NULL to not unregister
  438. * dev on error unwinding. */
  439. sdev->dev = NULL;
  440. kfree(devwrap);
  441. goto error;
  442. }
  443. dev_idx++;
  444. }
  445. return 0;
  446. error:
  447. /* Unwind the already registered devices. */
  448. ssb_devices_unregister(bus);
  449. return err;
  450. }
  451. /* Needs ssb_buses_lock() */
  452. static int ssb_attach_queued_buses(void)
  453. {
  454. struct ssb_bus *bus, *n;
  455. int err = 0;
  456. int drop_them_all = 0;
  457. list_for_each_entry_safe(bus, n, &attach_queue, list) {
  458. if (drop_them_all) {
  459. list_del(&bus->list);
  460. continue;
  461. }
  462. /* Can't init the PCIcore in ssb_bus_register(), as that
  463. * is too early in boot for embedded systems
  464. * (no udelay() available). So do it here in attach stage.
  465. */
  466. err = ssb_bus_powerup(bus, 0);
  467. if (err)
  468. goto error;
  469. ssb_pcicore_init(&bus->pcicore);
  470. ssb_bus_may_powerdown(bus);
  471. err = ssb_devices_register(bus);
  472. error:
  473. if (err) {
  474. drop_them_all = 1;
  475. list_del(&bus->list);
  476. continue;
  477. }
  478. list_move_tail(&bus->list, &buses);
  479. }
  480. return err;
  481. }
  482. static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
  483. {
  484. struct ssb_bus *bus = dev->bus;
  485. offset += dev->core_index * SSB_CORE_SIZE;
  486. return readb(bus->mmio + offset);
  487. }
  488. static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
  489. {
  490. struct ssb_bus *bus = dev->bus;
  491. offset += dev->core_index * SSB_CORE_SIZE;
  492. return readw(bus->mmio + offset);
  493. }
  494. static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
  495. {
  496. struct ssb_bus *bus = dev->bus;
  497. offset += dev->core_index * SSB_CORE_SIZE;
  498. return readl(bus->mmio + offset);
  499. }
  500. #ifdef CONFIG_SSB_BLOCKIO
  501. static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
  502. size_t count, u16 offset, u8 reg_width)
  503. {
  504. struct ssb_bus *bus = dev->bus;
  505. void __iomem *addr;
  506. offset += dev->core_index * SSB_CORE_SIZE;
  507. addr = bus->mmio + offset;
  508. switch (reg_width) {
  509. case sizeof(u8): {
  510. u8 *buf = buffer;
  511. while (count) {
  512. *buf = __raw_readb(addr);
  513. buf++;
  514. count--;
  515. }
  516. break;
  517. }
  518. case sizeof(u16): {
  519. __le16 *buf = buffer;
  520. SSB_WARN_ON(count & 1);
  521. while (count) {
  522. *buf = (__force __le16)__raw_readw(addr);
  523. buf++;
  524. count -= 2;
  525. }
  526. break;
  527. }
  528. case sizeof(u32): {
  529. __le32 *buf = buffer;
  530. SSB_WARN_ON(count & 3);
  531. while (count) {
  532. *buf = (__force __le32)__raw_readl(addr);
  533. buf++;
  534. count -= 4;
  535. }
  536. break;
  537. }
  538. default:
  539. SSB_WARN_ON(1);
  540. }
  541. }
  542. #endif /* CONFIG_SSB_BLOCKIO */
  543. static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
  544. {
  545. struct ssb_bus *bus = dev->bus;
  546. offset += dev->core_index * SSB_CORE_SIZE;
  547. writeb(value, bus->mmio + offset);
  548. }
  549. static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
  550. {
  551. struct ssb_bus *bus = dev->bus;
  552. offset += dev->core_index * SSB_CORE_SIZE;
  553. writew(value, bus->mmio + offset);
  554. }
  555. static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
  556. {
  557. struct ssb_bus *bus = dev->bus;
  558. offset += dev->core_index * SSB_CORE_SIZE;
  559. writel(value, bus->mmio + offset);
  560. }
  561. #ifdef CONFIG_SSB_BLOCKIO
  562. static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
  563. size_t count, u16 offset, u8 reg_width)
  564. {
  565. struct ssb_bus *bus = dev->bus;
  566. void __iomem *addr;
  567. offset += dev->core_index * SSB_CORE_SIZE;
  568. addr = bus->mmio + offset;
  569. switch (reg_width) {
  570. case sizeof(u8): {
  571. const u8 *buf = buffer;
  572. while (count) {
  573. __raw_writeb(*buf, addr);
  574. buf++;
  575. count--;
  576. }
  577. break;
  578. }
  579. case sizeof(u16): {
  580. const __le16 *buf = buffer;
  581. SSB_WARN_ON(count & 1);
  582. while (count) {
  583. __raw_writew((__force u16)(*buf), addr);
  584. buf++;
  585. count -= 2;
  586. }
  587. break;
  588. }
  589. case sizeof(u32): {
  590. const __le32 *buf = buffer;
  591. SSB_WARN_ON(count & 3);
  592. while (count) {
  593. __raw_writel((__force u32)(*buf), addr);
  594. buf++;
  595. count -= 4;
  596. }
  597. break;
  598. }
  599. default:
  600. SSB_WARN_ON(1);
  601. }
  602. }
  603. #endif /* CONFIG_SSB_BLOCKIO */
  604. /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
  605. static const struct ssb_bus_ops ssb_ssb_ops = {
  606. .read8 = ssb_ssb_read8,
  607. .read16 = ssb_ssb_read16,
  608. .read32 = ssb_ssb_read32,
  609. .write8 = ssb_ssb_write8,
  610. .write16 = ssb_ssb_write16,
  611. .write32 = ssb_ssb_write32,
  612. #ifdef CONFIG_SSB_BLOCKIO
  613. .block_read = ssb_ssb_block_read,
  614. .block_write = ssb_ssb_block_write,
  615. #endif
  616. };
  617. static int ssb_fetch_invariants(struct ssb_bus *bus,
  618. ssb_invariants_func_t get_invariants)
  619. {
  620. struct ssb_init_invariants iv;
  621. int err;
  622. memset(&iv, 0, sizeof(iv));
  623. err = get_invariants(bus, &iv);
  624. if (err)
  625. goto out;
  626. memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  627. memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  628. bus->has_cardbus_slot = iv.has_cardbus_slot;
  629. out:
  630. return err;
  631. }
  632. static int ssb_bus_register(struct ssb_bus *bus,
  633. ssb_invariants_func_t get_invariants,
  634. unsigned long baseaddr)
  635. {
  636. int err;
  637. spin_lock_init(&bus->bar_lock);
  638. INIT_LIST_HEAD(&bus->list);
  639. #ifdef CONFIG_SSB_EMBEDDED
  640. spin_lock_init(&bus->gpio_lock);
  641. #endif
  642. /* Powerup the bus */
  643. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  644. if (err)
  645. goto out;
  646. /* Init SDIO-host device (if any), before the scan */
  647. err = ssb_sdio_init(bus);
  648. if (err)
  649. goto err_disable_xtal;
  650. ssb_buses_lock();
  651. bus->busnumber = next_busnumber;
  652. /* Scan for devices (cores) */
  653. err = ssb_bus_scan(bus, baseaddr);
  654. if (err)
  655. goto err_sdio_exit;
  656. /* Init PCI-host device (if any) */
  657. err = ssb_pci_init(bus);
  658. if (err)
  659. goto err_unmap;
  660. /* Init PCMCIA-host device (if any) */
  661. err = ssb_pcmcia_init(bus);
  662. if (err)
  663. goto err_pci_exit;
  664. /* Initialize basic system devices (if available) */
  665. err = ssb_bus_powerup(bus, 0);
  666. if (err)
  667. goto err_pcmcia_exit;
  668. ssb_chipcommon_init(&bus->chipco);
  669. ssb_mipscore_init(&bus->mipscore);
  670. err = ssb_fetch_invariants(bus, get_invariants);
  671. if (err) {
  672. ssb_bus_may_powerdown(bus);
  673. goto err_pcmcia_exit;
  674. }
  675. ssb_bus_may_powerdown(bus);
  676. /* Queue it for attach.
  677. * See the comment at the ssb_is_early_boot definition. */
  678. list_add_tail(&bus->list, &attach_queue);
  679. if (!ssb_is_early_boot) {
  680. /* This is not early boot, so we must attach the bus now */
  681. err = ssb_attach_queued_buses();
  682. if (err)
  683. goto err_dequeue;
  684. }
  685. next_busnumber++;
  686. ssb_buses_unlock();
  687. out:
  688. return err;
  689. err_dequeue:
  690. list_del(&bus->list);
  691. err_pcmcia_exit:
  692. ssb_pcmcia_exit(bus);
  693. err_pci_exit:
  694. ssb_pci_exit(bus);
  695. err_unmap:
  696. ssb_iounmap(bus);
  697. err_sdio_exit:
  698. ssb_sdio_exit(bus);
  699. err_disable_xtal:
  700. ssb_buses_unlock();
  701. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  702. return err;
  703. }
  704. #ifdef CONFIG_SSB_PCIHOST
  705. int ssb_bus_pcibus_register(struct ssb_bus *bus,
  706. struct pci_dev *host_pci)
  707. {
  708. int err;
  709. bus->bustype = SSB_BUSTYPE_PCI;
  710. bus->host_pci = host_pci;
  711. bus->ops = &ssb_pci_ops;
  712. err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
  713. if (!err) {
  714. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  715. "PCI device %s\n", dev_name(&host_pci->dev));
  716. } else {
  717. ssb_printk(KERN_ERR PFX "Failed to register PCI version"
  718. " of SSB with error %d\n", err);
  719. }
  720. return err;
  721. }
  722. EXPORT_SYMBOL(ssb_bus_pcibus_register);
  723. #endif /* CONFIG_SSB_PCIHOST */
  724. #ifdef CONFIG_SSB_PCMCIAHOST
  725. int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  726. struct pcmcia_device *pcmcia_dev,
  727. unsigned long baseaddr)
  728. {
  729. int err;
  730. bus->bustype = SSB_BUSTYPE_PCMCIA;
  731. bus->host_pcmcia = pcmcia_dev;
  732. bus->ops = &ssb_pcmcia_ops;
  733. err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
  734. if (!err) {
  735. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  736. "PCMCIA device %s\n", pcmcia_dev->devname);
  737. }
  738. return err;
  739. }
  740. EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
  741. #endif /* CONFIG_SSB_PCMCIAHOST */
  742. #ifdef CONFIG_SSB_SDIOHOST
  743. int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
  744. unsigned int quirks)
  745. {
  746. int err;
  747. bus->bustype = SSB_BUSTYPE_SDIO;
  748. bus->host_sdio = func;
  749. bus->ops = &ssb_sdio_ops;
  750. bus->quirks = quirks;
  751. err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
  752. if (!err) {
  753. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  754. "SDIO device %s\n", sdio_func_id(func));
  755. }
  756. return err;
  757. }
  758. EXPORT_SYMBOL(ssb_bus_sdiobus_register);
  759. #endif /* CONFIG_SSB_PCMCIAHOST */
  760. int ssb_bus_ssbbus_register(struct ssb_bus *bus,
  761. unsigned long baseaddr,
  762. ssb_invariants_func_t get_invariants)
  763. {
  764. int err;
  765. bus->bustype = SSB_BUSTYPE_SSB;
  766. bus->ops = &ssb_ssb_ops;
  767. err = ssb_bus_register(bus, get_invariants, baseaddr);
  768. if (!err) {
  769. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
  770. "address 0x%08lX\n", baseaddr);
  771. }
  772. return err;
  773. }
  774. int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
  775. {
  776. drv->drv.name = drv->name;
  777. drv->drv.bus = &ssb_bustype;
  778. drv->drv.owner = owner;
  779. return driver_register(&drv->drv);
  780. }
  781. EXPORT_SYMBOL(__ssb_driver_register);
  782. void ssb_driver_unregister(struct ssb_driver *drv)
  783. {
  784. driver_unregister(&drv->drv);
  785. }
  786. EXPORT_SYMBOL(ssb_driver_unregister);
  787. void ssb_set_devtypedata(struct ssb_device *dev, void *data)
  788. {
  789. struct ssb_bus *bus = dev->bus;
  790. struct ssb_device *ent;
  791. int i;
  792. for (i = 0; i < bus->nr_devices; i++) {
  793. ent = &(bus->devices[i]);
  794. if (ent->id.vendor != dev->id.vendor)
  795. continue;
  796. if (ent->id.coreid != dev->id.coreid)
  797. continue;
  798. ent->devtypedata = data;
  799. }
  800. }
  801. EXPORT_SYMBOL(ssb_set_devtypedata);
  802. static u32 clkfactor_f6_resolve(u32 v)
  803. {
  804. /* map the magic values */
  805. switch (v) {
  806. case SSB_CHIPCO_CLK_F6_2:
  807. return 2;
  808. case SSB_CHIPCO_CLK_F6_3:
  809. return 3;
  810. case SSB_CHIPCO_CLK_F6_4:
  811. return 4;
  812. case SSB_CHIPCO_CLK_F6_5:
  813. return 5;
  814. case SSB_CHIPCO_CLK_F6_6:
  815. return 6;
  816. case SSB_CHIPCO_CLK_F6_7:
  817. return 7;
  818. }
  819. return 0;
  820. }
  821. /* Calculate the speed the backplane would run at a given set of clockcontrol values */
  822. u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
  823. {
  824. u32 n1, n2, clock, m1, m2, m3, mc;
  825. n1 = (n & SSB_CHIPCO_CLK_N1);
  826. n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
  827. switch (plltype) {
  828. case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
  829. if (m & SSB_CHIPCO_CLK_T6_MMASK)
  830. return SSB_CHIPCO_CLK_T6_M0;
  831. return SSB_CHIPCO_CLK_T6_M1;
  832. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  833. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  834. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  835. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  836. n1 = clkfactor_f6_resolve(n1);
  837. n2 += SSB_CHIPCO_CLK_F5_BIAS;
  838. break;
  839. case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
  840. n1 += SSB_CHIPCO_CLK_T2_BIAS;
  841. n2 += SSB_CHIPCO_CLK_T2_BIAS;
  842. SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
  843. SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
  844. break;
  845. case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
  846. return 100000000;
  847. default:
  848. SSB_WARN_ON(1);
  849. }
  850. switch (plltype) {
  851. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  852. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  853. clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
  854. break;
  855. default:
  856. clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
  857. }
  858. if (!clock)
  859. return 0;
  860. m1 = (m & SSB_CHIPCO_CLK_M1);
  861. m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
  862. m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
  863. mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
  864. switch (plltype) {
  865. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  866. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  867. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  868. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  869. m1 = clkfactor_f6_resolve(m1);
  870. if ((plltype == SSB_PLLTYPE_1) ||
  871. (plltype == SSB_PLLTYPE_3))
  872. m2 += SSB_CHIPCO_CLK_F5_BIAS;
  873. else
  874. m2 = clkfactor_f6_resolve(m2);
  875. m3 = clkfactor_f6_resolve(m3);
  876. switch (mc) {
  877. case SSB_CHIPCO_CLK_MC_BYPASS:
  878. return clock;
  879. case SSB_CHIPCO_CLK_MC_M1:
  880. return (clock / m1);
  881. case SSB_CHIPCO_CLK_MC_M1M2:
  882. return (clock / (m1 * m2));
  883. case SSB_CHIPCO_CLK_MC_M1M2M3:
  884. return (clock / (m1 * m2 * m3));
  885. case SSB_CHIPCO_CLK_MC_M1M3:
  886. return (clock / (m1 * m3));
  887. }
  888. return 0;
  889. case SSB_PLLTYPE_2:
  890. m1 += SSB_CHIPCO_CLK_T2_BIAS;
  891. m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
  892. m3 += SSB_CHIPCO_CLK_T2_BIAS;
  893. SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
  894. SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
  895. SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
  896. if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
  897. clock /= m1;
  898. if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
  899. clock /= m2;
  900. if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
  901. clock /= m3;
  902. return clock;
  903. default:
  904. SSB_WARN_ON(1);
  905. }
  906. return 0;
  907. }
  908. /* Get the current speed the backplane is running at */
  909. u32 ssb_clockspeed(struct ssb_bus *bus)
  910. {
  911. u32 rate;
  912. u32 plltype;
  913. u32 clkctl_n, clkctl_m;
  914. if (ssb_extif_available(&bus->extif))
  915. ssb_extif_get_clockcontrol(&bus->extif, &plltype,
  916. &clkctl_n, &clkctl_m);
  917. else if (bus->chipco.dev)
  918. ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
  919. &clkctl_n, &clkctl_m);
  920. else
  921. return 0;
  922. if (bus->chip_id == 0x5365) {
  923. rate = 100000000;
  924. } else {
  925. rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  926. if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
  927. rate /= 2;
  928. }
  929. return rate;
  930. }
  931. EXPORT_SYMBOL(ssb_clockspeed);
  932. static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
  933. {
  934. u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
  935. /* The REJECT bit changed position in TMSLOW between
  936. * Backplane revisions. */
  937. switch (rev) {
  938. case SSB_IDLOW_SSBREV_22:
  939. return SSB_TMSLOW_REJECT_22;
  940. case SSB_IDLOW_SSBREV_23:
  941. return SSB_TMSLOW_REJECT_23;
  942. case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
  943. case SSB_IDLOW_SSBREV_25: /* same here */
  944. case SSB_IDLOW_SSBREV_26: /* same here */
  945. case SSB_IDLOW_SSBREV_27: /* same here */
  946. return SSB_TMSLOW_REJECT_23; /* this is a guess */
  947. default:
  948. printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
  949. WARN_ON(1);
  950. }
  951. return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
  952. }
  953. int ssb_device_is_enabled(struct ssb_device *dev)
  954. {
  955. u32 val;
  956. u32 reject;
  957. reject = ssb_tmslow_reject_bitmask(dev);
  958. val = ssb_read32(dev, SSB_TMSLOW);
  959. val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
  960. return (val == SSB_TMSLOW_CLOCK);
  961. }
  962. EXPORT_SYMBOL(ssb_device_is_enabled);
  963. static void ssb_flush_tmslow(struct ssb_device *dev)
  964. {
  965. /* Make _really_ sure the device has finished the TMSLOW
  966. * register write transaction, as we risk running into
  967. * a machine check exception otherwise.
  968. * Do this by reading the register back to commit the
  969. * PCI write and delay an additional usec for the device
  970. * to react to the change. */
  971. ssb_read32(dev, SSB_TMSLOW);
  972. udelay(1);
  973. }
  974. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
  975. {
  976. u32 val;
  977. ssb_device_disable(dev, core_specific_flags);
  978. ssb_write32(dev, SSB_TMSLOW,
  979. SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
  980. SSB_TMSLOW_FGC | core_specific_flags);
  981. ssb_flush_tmslow(dev);
  982. /* Clear SERR if set. This is a hw bug workaround. */
  983. if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
  984. ssb_write32(dev, SSB_TMSHIGH, 0);
  985. val = ssb_read32(dev, SSB_IMSTATE);
  986. if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
  987. val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
  988. ssb_write32(dev, SSB_IMSTATE, val);
  989. }
  990. ssb_write32(dev, SSB_TMSLOW,
  991. SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
  992. core_specific_flags);
  993. ssb_flush_tmslow(dev);
  994. ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
  995. core_specific_flags);
  996. ssb_flush_tmslow(dev);
  997. }
  998. EXPORT_SYMBOL(ssb_device_enable);
  999. /* Wait for a bit in a register to get set or unset.
  1000. * timeout is in units of ten-microseconds */
  1001. static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
  1002. int timeout, int set)
  1003. {
  1004. int i;
  1005. u32 val;
  1006. for (i = 0; i < timeout; i++) {
  1007. val = ssb_read32(dev, reg);
  1008. if (set) {
  1009. if (val & bitmask)
  1010. return 0;
  1011. } else {
  1012. if (!(val & bitmask))
  1013. return 0;
  1014. }
  1015. udelay(10);
  1016. }
  1017. printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
  1018. "register %04X to %s.\n",
  1019. bitmask, reg, (set ? "set" : "clear"));
  1020. return -ETIMEDOUT;
  1021. }
  1022. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
  1023. {
  1024. u32 reject;
  1025. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
  1026. return;
  1027. reject = ssb_tmslow_reject_bitmask(dev);
  1028. ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
  1029. ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
  1030. ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
  1031. ssb_write32(dev, SSB_TMSLOW,
  1032. SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
  1033. reject | SSB_TMSLOW_RESET |
  1034. core_specific_flags);
  1035. ssb_flush_tmslow(dev);
  1036. ssb_write32(dev, SSB_TMSLOW,
  1037. reject | SSB_TMSLOW_RESET |
  1038. core_specific_flags);
  1039. ssb_flush_tmslow(dev);
  1040. }
  1041. EXPORT_SYMBOL(ssb_device_disable);
  1042. u32 ssb_dma_translation(struct ssb_device *dev)
  1043. {
  1044. switch (dev->bus->bustype) {
  1045. case SSB_BUSTYPE_SSB:
  1046. return 0;
  1047. case SSB_BUSTYPE_PCI:
  1048. return SSB_PCI_DMA;
  1049. default:
  1050. __ssb_dma_not_implemented(dev);
  1051. }
  1052. return 0;
  1053. }
  1054. EXPORT_SYMBOL(ssb_dma_translation);
  1055. int ssb_bus_may_powerdown(struct ssb_bus *bus)
  1056. {
  1057. struct ssb_chipcommon *cc;
  1058. int err = 0;
  1059. /* On buses where more than one core may be working
  1060. * at a time, we must not powerdown stuff if there are
  1061. * still cores that may want to run. */
  1062. if (bus->bustype == SSB_BUSTYPE_SSB)
  1063. goto out;
  1064. cc = &bus->chipco;
  1065. if (!cc->dev)
  1066. goto out;
  1067. if (cc->dev->id.revision < 5)
  1068. goto out;
  1069. ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
  1070. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  1071. if (err)
  1072. goto error;
  1073. out:
  1074. #ifdef CONFIG_SSB_DEBUG
  1075. bus->powered_up = 0;
  1076. #endif
  1077. return err;
  1078. error:
  1079. ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
  1080. goto out;
  1081. }
  1082. EXPORT_SYMBOL(ssb_bus_may_powerdown);
  1083. int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
  1084. {
  1085. struct ssb_chipcommon *cc;
  1086. int err;
  1087. enum ssb_clkmode mode;
  1088. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  1089. if (err)
  1090. goto error;
  1091. cc = &bus->chipco;
  1092. mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
  1093. ssb_chipco_set_clockmode(cc, mode);
  1094. #ifdef CONFIG_SSB_DEBUG
  1095. bus->powered_up = 1;
  1096. #endif
  1097. return 0;
  1098. error:
  1099. ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
  1100. return err;
  1101. }
  1102. EXPORT_SYMBOL(ssb_bus_powerup);
  1103. u32 ssb_admatch_base(u32 adm)
  1104. {
  1105. u32 base = 0;
  1106. switch (adm & SSB_ADM_TYPE) {
  1107. case SSB_ADM_TYPE0:
  1108. base = (adm & SSB_ADM_BASE0);
  1109. break;
  1110. case SSB_ADM_TYPE1:
  1111. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1112. base = (adm & SSB_ADM_BASE1);
  1113. break;
  1114. case SSB_ADM_TYPE2:
  1115. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1116. base = (adm & SSB_ADM_BASE2);
  1117. break;
  1118. default:
  1119. SSB_WARN_ON(1);
  1120. }
  1121. return base;
  1122. }
  1123. EXPORT_SYMBOL(ssb_admatch_base);
  1124. u32 ssb_admatch_size(u32 adm)
  1125. {
  1126. u32 size = 0;
  1127. switch (adm & SSB_ADM_TYPE) {
  1128. case SSB_ADM_TYPE0:
  1129. size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
  1130. break;
  1131. case SSB_ADM_TYPE1:
  1132. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1133. size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
  1134. break;
  1135. case SSB_ADM_TYPE2:
  1136. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1137. size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
  1138. break;
  1139. default:
  1140. SSB_WARN_ON(1);
  1141. }
  1142. size = (1 << (size + 1));
  1143. return size;
  1144. }
  1145. EXPORT_SYMBOL(ssb_admatch_size);
  1146. static int __init ssb_modinit(void)
  1147. {
  1148. int err;
  1149. /* See the comment at the ssb_is_early_boot definition */
  1150. ssb_is_early_boot = 0;
  1151. err = bus_register(&ssb_bustype);
  1152. if (err)
  1153. return err;
  1154. /* Maybe we already registered some buses at early boot.
  1155. * Check for this and attach them
  1156. */
  1157. ssb_buses_lock();
  1158. err = ssb_attach_queued_buses();
  1159. ssb_buses_unlock();
  1160. if (err) {
  1161. bus_unregister(&ssb_bustype);
  1162. goto out;
  1163. }
  1164. err = b43_pci_ssb_bridge_init();
  1165. if (err) {
  1166. ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
  1167. "initialization failed\n");
  1168. /* don't fail SSB init because of this */
  1169. err = 0;
  1170. }
  1171. err = ssb_gige_init();
  1172. if (err) {
  1173. ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
  1174. "driver initialization failed\n");
  1175. /* don't fail SSB init because of this */
  1176. err = 0;
  1177. }
  1178. out:
  1179. return err;
  1180. }
  1181. /* ssb must be initialized after PCI but before the ssb drivers.
  1182. * That means we must use some initcall between subsys_initcall
  1183. * and device_initcall. */
  1184. fs_initcall(ssb_modinit);
  1185. static void __exit ssb_modexit(void)
  1186. {
  1187. ssb_gige_exit();
  1188. b43_pci_ssb_bridge_exit();
  1189. bus_unregister(&ssb_bustype);
  1190. }
  1191. module_exit(ssb_modexit)