rtc-s3c.c 15 KB

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  1. /* drivers/rtc/rtc-s3c.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * Copyright (c) 2004,2006 Simtec Electronics
  7. * Ben Dooks, <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * S3C2410/S3C2440/S3C24XX Internal RTC Driver
  15. */
  16. #include <linux/module.h>
  17. #include <linux/fs.h>
  18. #include <linux/string.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/rtc.h>
  23. #include <linux/bcd.h>
  24. #include <linux/clk.h>
  25. #include <linux/log2.h>
  26. #include <linux/slab.h>
  27. #include <mach/hardware.h>
  28. #include <asm/uaccess.h>
  29. #include <asm/io.h>
  30. #include <asm/irq.h>
  31. #include <plat/regs-rtc.h>
  32. enum s3c_cpu_type {
  33. TYPE_S3C2410,
  34. TYPE_S3C64XX,
  35. };
  36. /* I have yet to find an S3C implementation with more than one
  37. * of these rtc blocks in */
  38. static struct resource *s3c_rtc_mem;
  39. static struct clk *rtc_clk;
  40. static void __iomem *s3c_rtc_base;
  41. static int s3c_rtc_alarmno = NO_IRQ;
  42. static int s3c_rtc_tickno = NO_IRQ;
  43. static enum s3c_cpu_type s3c_rtc_cpu_type;
  44. static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
  45. /* IRQ Handlers */
  46. static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
  47. {
  48. struct rtc_device *rdev = id;
  49. rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
  50. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  51. writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
  52. return IRQ_HANDLED;
  53. }
  54. static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
  55. {
  56. struct rtc_device *rdev = id;
  57. rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
  58. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  59. writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
  60. return IRQ_HANDLED;
  61. }
  62. /* Update control registers */
  63. static void s3c_rtc_setaie(int to)
  64. {
  65. unsigned int tmp;
  66. pr_debug("%s: aie=%d\n", __func__, to);
  67. tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
  68. if (to)
  69. tmp |= S3C2410_RTCALM_ALMEN;
  70. writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
  71. }
  72. static int s3c_rtc_setpie(struct device *dev, int enabled)
  73. {
  74. unsigned int tmp;
  75. pr_debug("%s: pie=%d\n", __func__, enabled);
  76. spin_lock_irq(&s3c_rtc_pie_lock);
  77. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  78. tmp = readb(s3c_rtc_base + S3C2410_RTCCON);
  79. tmp &= ~S3C64XX_RTCCON_TICEN;
  80. if (enabled)
  81. tmp |= S3C64XX_RTCCON_TICEN;
  82. writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
  83. } else {
  84. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  85. tmp &= ~S3C2410_TICNT_ENABLE;
  86. if (enabled)
  87. tmp |= S3C2410_TICNT_ENABLE;
  88. writeb(tmp, s3c_rtc_base + S3C2410_TICNT);
  89. }
  90. spin_unlock_irq(&s3c_rtc_pie_lock);
  91. return 0;
  92. }
  93. static int s3c_rtc_setfreq(struct device *dev, int freq)
  94. {
  95. struct platform_device *pdev = to_platform_device(dev);
  96. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  97. unsigned int tmp = 0;
  98. if (!is_power_of_2(freq))
  99. return -EINVAL;
  100. spin_lock_irq(&s3c_rtc_pie_lock);
  101. if (s3c_rtc_cpu_type == TYPE_S3C2410) {
  102. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  103. tmp &= S3C2410_TICNT_ENABLE;
  104. }
  105. tmp |= (rtc_dev->max_user_freq / freq)-1;
  106. writel(tmp, s3c_rtc_base + S3C2410_TICNT);
  107. spin_unlock_irq(&s3c_rtc_pie_lock);
  108. return 0;
  109. }
  110. /* Time read/write */
  111. static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  112. {
  113. unsigned int have_retried = 0;
  114. void __iomem *base = s3c_rtc_base;
  115. retry_get_time:
  116. rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
  117. rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
  118. rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
  119. rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
  120. rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
  121. rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
  122. /* the only way to work out wether the system was mid-update
  123. * when we read it is to check the second counter, and if it
  124. * is zero, then we re-try the entire read
  125. */
  126. if (rtc_tm->tm_sec == 0 && !have_retried) {
  127. have_retried = 1;
  128. goto retry_get_time;
  129. }
  130. pr_debug("read time %02x.%02x.%02x %02x/%02x/%02x\n",
  131. rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
  132. rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
  133. rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
  134. rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
  135. rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
  136. rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
  137. rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
  138. rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
  139. rtc_tm->tm_year += 100;
  140. rtc_tm->tm_mon -= 1;
  141. return 0;
  142. }
  143. static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
  144. {
  145. void __iomem *base = s3c_rtc_base;
  146. int year = tm->tm_year - 100;
  147. pr_debug("set time %02d.%02d.%02d %02d/%02d/%02d\n",
  148. tm->tm_year, tm->tm_mon, tm->tm_mday,
  149. tm->tm_hour, tm->tm_min, tm->tm_sec);
  150. /* we get around y2k by simply not supporting it */
  151. if (year < 0 || year >= 100) {
  152. dev_err(dev, "rtc only supports 100 years\n");
  153. return -EINVAL;
  154. }
  155. writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
  156. writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
  157. writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
  158. writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
  159. writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
  160. writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
  161. return 0;
  162. }
  163. static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
  164. {
  165. struct rtc_time *alm_tm = &alrm->time;
  166. void __iomem *base = s3c_rtc_base;
  167. unsigned int alm_en;
  168. alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
  169. alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
  170. alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
  171. alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
  172. alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
  173. alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
  174. alm_en = readb(base + S3C2410_RTCALM);
  175. alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
  176. pr_debug("read alarm %02x %02x.%02x.%02x %02x/%02x/%02x\n",
  177. alm_en,
  178. alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
  179. alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
  180. /* decode the alarm enable field */
  181. if (alm_en & S3C2410_RTCALM_SECEN)
  182. alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
  183. else
  184. alm_tm->tm_sec = 0xff;
  185. if (alm_en & S3C2410_RTCALM_MINEN)
  186. alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
  187. else
  188. alm_tm->tm_min = 0xff;
  189. if (alm_en & S3C2410_RTCALM_HOUREN)
  190. alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
  191. else
  192. alm_tm->tm_hour = 0xff;
  193. if (alm_en & S3C2410_RTCALM_DAYEN)
  194. alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
  195. else
  196. alm_tm->tm_mday = 0xff;
  197. if (alm_en & S3C2410_RTCALM_MONEN) {
  198. alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
  199. alm_tm->tm_mon -= 1;
  200. } else {
  201. alm_tm->tm_mon = 0xff;
  202. }
  203. if (alm_en & S3C2410_RTCALM_YEAREN)
  204. alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
  205. else
  206. alm_tm->tm_year = 0xffff;
  207. return 0;
  208. }
  209. static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  210. {
  211. struct rtc_time *tm = &alrm->time;
  212. void __iomem *base = s3c_rtc_base;
  213. unsigned int alrm_en;
  214. pr_debug("s3c_rtc_setalarm: %d, %02x/%02x/%02x %02x.%02x.%02x\n",
  215. alrm->enabled,
  216. tm->tm_mday & 0xff, tm->tm_mon & 0xff, tm->tm_year & 0xff,
  217. tm->tm_hour & 0xff, tm->tm_min & 0xff, tm->tm_sec);
  218. alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
  219. writeb(0x00, base + S3C2410_RTCALM);
  220. if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
  221. alrm_en |= S3C2410_RTCALM_SECEN;
  222. writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
  223. }
  224. if (tm->tm_min < 60 && tm->tm_min >= 0) {
  225. alrm_en |= S3C2410_RTCALM_MINEN;
  226. writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
  227. }
  228. if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
  229. alrm_en |= S3C2410_RTCALM_HOUREN;
  230. writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
  231. }
  232. pr_debug("setting S3C2410_RTCALM to %08x\n", alrm_en);
  233. writeb(alrm_en, base + S3C2410_RTCALM);
  234. s3c_rtc_setaie(alrm->enabled);
  235. if (alrm->enabled)
  236. enable_irq_wake(s3c_rtc_alarmno);
  237. else
  238. disable_irq_wake(s3c_rtc_alarmno);
  239. return 0;
  240. }
  241. static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
  242. {
  243. unsigned int ticnt;
  244. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  245. ticnt = readb(s3c_rtc_base + S3C2410_RTCCON);
  246. ticnt &= S3C64XX_RTCCON_TICEN;
  247. } else {
  248. ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
  249. ticnt &= S3C2410_TICNT_ENABLE;
  250. }
  251. seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
  252. return 0;
  253. }
  254. static int s3c_rtc_open(struct device *dev)
  255. {
  256. struct platform_device *pdev = to_platform_device(dev);
  257. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  258. int ret;
  259. ret = request_irq(s3c_rtc_alarmno, s3c_rtc_alarmirq,
  260. IRQF_DISABLED, "s3c2410-rtc alarm", rtc_dev);
  261. if (ret) {
  262. dev_err(dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
  263. return ret;
  264. }
  265. ret = request_irq(s3c_rtc_tickno, s3c_rtc_tickirq,
  266. IRQF_DISABLED, "s3c2410-rtc tick", rtc_dev);
  267. if (ret) {
  268. dev_err(dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
  269. goto tick_err;
  270. }
  271. return ret;
  272. tick_err:
  273. free_irq(s3c_rtc_alarmno, rtc_dev);
  274. return ret;
  275. }
  276. static void s3c_rtc_release(struct device *dev)
  277. {
  278. struct platform_device *pdev = to_platform_device(dev);
  279. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  280. /* do not clear AIE here, it may be needed for wake */
  281. s3c_rtc_setpie(dev, 0);
  282. free_irq(s3c_rtc_alarmno, rtc_dev);
  283. free_irq(s3c_rtc_tickno, rtc_dev);
  284. }
  285. static const struct rtc_class_ops s3c_rtcops = {
  286. .open = s3c_rtc_open,
  287. .release = s3c_rtc_release,
  288. .read_time = s3c_rtc_gettime,
  289. .set_time = s3c_rtc_settime,
  290. .read_alarm = s3c_rtc_getalarm,
  291. .set_alarm = s3c_rtc_setalarm,
  292. .irq_set_freq = s3c_rtc_setfreq,
  293. .irq_set_state = s3c_rtc_setpie,
  294. .proc = s3c_rtc_proc,
  295. };
  296. static void s3c_rtc_enable(struct platform_device *pdev, int en)
  297. {
  298. void __iomem *base = s3c_rtc_base;
  299. unsigned int tmp;
  300. if (s3c_rtc_base == NULL)
  301. return;
  302. if (!en) {
  303. tmp = readb(base + S3C2410_RTCCON);
  304. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  305. tmp &= ~S3C64XX_RTCCON_TICEN;
  306. tmp &= ~S3C2410_RTCCON_RTCEN;
  307. writeb(tmp, base + S3C2410_RTCCON);
  308. if (s3c_rtc_cpu_type == TYPE_S3C2410) {
  309. tmp = readb(base + S3C2410_TICNT);
  310. tmp &= ~S3C2410_TICNT_ENABLE;
  311. writeb(tmp, base + S3C2410_TICNT);
  312. }
  313. } else {
  314. /* re-enable the device, and check it is ok */
  315. if ((readb(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){
  316. dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
  317. tmp = readb(base + S3C2410_RTCCON);
  318. writeb(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON);
  319. }
  320. if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){
  321. dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
  322. tmp = readb(base + S3C2410_RTCCON);
  323. writeb(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON);
  324. }
  325. if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){
  326. dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
  327. tmp = readb(base + S3C2410_RTCCON);
  328. writeb(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON);
  329. }
  330. }
  331. }
  332. static int __devexit s3c_rtc_remove(struct platform_device *dev)
  333. {
  334. struct rtc_device *rtc = platform_get_drvdata(dev);
  335. platform_set_drvdata(dev, NULL);
  336. rtc_device_unregister(rtc);
  337. s3c_rtc_setpie(&dev->dev, 0);
  338. s3c_rtc_setaie(0);
  339. clk_disable(rtc_clk);
  340. clk_put(rtc_clk);
  341. rtc_clk = NULL;
  342. iounmap(s3c_rtc_base);
  343. release_resource(s3c_rtc_mem);
  344. kfree(s3c_rtc_mem);
  345. return 0;
  346. }
  347. static int __devinit s3c_rtc_probe(struct platform_device *pdev)
  348. {
  349. struct rtc_device *rtc;
  350. struct resource *res;
  351. unsigned int tmp, i;
  352. int ret;
  353. pr_debug("%s: probe=%p\n", __func__, pdev);
  354. /* find the IRQs */
  355. s3c_rtc_tickno = platform_get_irq(pdev, 1);
  356. if (s3c_rtc_tickno < 0) {
  357. dev_err(&pdev->dev, "no irq for rtc tick\n");
  358. return -ENOENT;
  359. }
  360. s3c_rtc_alarmno = platform_get_irq(pdev, 0);
  361. if (s3c_rtc_alarmno < 0) {
  362. dev_err(&pdev->dev, "no irq for alarm\n");
  363. return -ENOENT;
  364. }
  365. pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n",
  366. s3c_rtc_tickno, s3c_rtc_alarmno);
  367. /* get the memory region */
  368. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  369. if (res == NULL) {
  370. dev_err(&pdev->dev, "failed to get memory region resource\n");
  371. return -ENOENT;
  372. }
  373. s3c_rtc_mem = request_mem_region(res->start,
  374. res->end-res->start+1,
  375. pdev->name);
  376. if (s3c_rtc_mem == NULL) {
  377. dev_err(&pdev->dev, "failed to reserve memory region\n");
  378. ret = -ENOENT;
  379. goto err_nores;
  380. }
  381. s3c_rtc_base = ioremap(res->start, res->end - res->start + 1);
  382. if (s3c_rtc_base == NULL) {
  383. dev_err(&pdev->dev, "failed ioremap()\n");
  384. ret = -EINVAL;
  385. goto err_nomap;
  386. }
  387. rtc_clk = clk_get(&pdev->dev, "rtc");
  388. if (IS_ERR(rtc_clk)) {
  389. dev_err(&pdev->dev, "failed to find rtc clock source\n");
  390. ret = PTR_ERR(rtc_clk);
  391. rtc_clk = NULL;
  392. goto err_clk;
  393. }
  394. clk_enable(rtc_clk);
  395. /* check to see if everything is setup correctly */
  396. s3c_rtc_enable(pdev, 1);
  397. pr_debug("s3c2410_rtc: RTCCON=%02x\n",
  398. readb(s3c_rtc_base + S3C2410_RTCCON));
  399. device_init_wakeup(&pdev->dev, 1);
  400. /* register RTC and exit */
  401. rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops,
  402. THIS_MODULE);
  403. if (IS_ERR(rtc)) {
  404. dev_err(&pdev->dev, "cannot attach rtc\n");
  405. ret = PTR_ERR(rtc);
  406. goto err_nortc;
  407. }
  408. s3c_rtc_cpu_type = platform_get_device_id(pdev)->driver_data;
  409. /* Check RTC Time */
  410. for (i = S3C2410_RTCSEC; i <= S3C2410_RTCYEAR; i += 0x4) {
  411. tmp = readb(s3c_rtc_base + i);
  412. if ((tmp & 0xf) > 0x9 || ((tmp >> 4) & 0xf) > 0x9)
  413. writeb(0, s3c_rtc_base + i);
  414. }
  415. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  416. rtc->max_user_freq = 32768;
  417. else
  418. rtc->max_user_freq = 128;
  419. platform_set_drvdata(pdev, rtc);
  420. s3c_rtc_setfreq(&pdev->dev, 1);
  421. return 0;
  422. err_nortc:
  423. s3c_rtc_enable(pdev, 0);
  424. clk_disable(rtc_clk);
  425. clk_put(rtc_clk);
  426. err_clk:
  427. iounmap(s3c_rtc_base);
  428. err_nomap:
  429. release_resource(s3c_rtc_mem);
  430. err_nores:
  431. return ret;
  432. }
  433. #ifdef CONFIG_PM
  434. /* RTC Power management control */
  435. static int ticnt_save, ticnt_en_save;
  436. static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
  437. {
  438. /* save TICNT for anyone using periodic interrupts */
  439. ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
  440. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  441. ticnt_en_save = readb(s3c_rtc_base + S3C2410_RTCCON);
  442. ticnt_en_save &= S3C64XX_RTCCON_TICEN;
  443. }
  444. s3c_rtc_enable(pdev, 0);
  445. return 0;
  446. }
  447. static int s3c_rtc_resume(struct platform_device *pdev)
  448. {
  449. unsigned int tmp;
  450. s3c_rtc_enable(pdev, 1);
  451. writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
  452. if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
  453. tmp = readb(s3c_rtc_base + S3C2410_RTCCON);
  454. writeb(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
  455. }
  456. return 0;
  457. }
  458. #else
  459. #define s3c_rtc_suspend NULL
  460. #define s3c_rtc_resume NULL
  461. #endif
  462. static struct platform_device_id s3c_rtc_driver_ids[] = {
  463. {
  464. .name = "s3c2410-rtc",
  465. .driver_data = TYPE_S3C2410,
  466. }, {
  467. .name = "s3c64xx-rtc",
  468. .driver_data = TYPE_S3C64XX,
  469. },
  470. { }
  471. };
  472. MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
  473. static struct platform_driver s3c_rtc_driver = {
  474. .probe = s3c_rtc_probe,
  475. .remove = __devexit_p(s3c_rtc_remove),
  476. .suspend = s3c_rtc_suspend,
  477. .resume = s3c_rtc_resume,
  478. .id_table = s3c_rtc_driver_ids,
  479. .driver = {
  480. .name = "s3c-rtc",
  481. .owner = THIS_MODULE,
  482. },
  483. };
  484. static char __initdata banner[] = "S3C24XX RTC, (c) 2004,2006 Simtec Electronics\n";
  485. static int __init s3c_rtc_init(void)
  486. {
  487. printk(banner);
  488. return platform_driver_register(&s3c_rtc_driver);
  489. }
  490. static void __exit s3c_rtc_exit(void)
  491. {
  492. platform_driver_unregister(&s3c_rtc_driver);
  493. }
  494. module_init(s3c_rtc_init);
  495. module_exit(s3c_rtc_exit);
  496. MODULE_DESCRIPTION("Samsung S3C RTC Driver");
  497. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  498. MODULE_LICENSE("GPL");
  499. MODULE_ALIAS("platform:s3c2410-rtc");