rtc-jz4740.c 8.1 KB

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  1. /*
  2. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3. * JZ4740 SoC RTC driver
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * You should have received a copy of the GNU General Public License along
  11. * with this program; if not, write to the Free Software Foundation, Inc.,
  12. * 675 Mass Ave, Cambridge, MA 02139, USA.
  13. *
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/rtc.h>
  19. #include <linux/slab.h>
  20. #include <linux/spinlock.h>
  21. #define JZ_REG_RTC_CTRL 0x00
  22. #define JZ_REG_RTC_SEC 0x04
  23. #define JZ_REG_RTC_SEC_ALARM 0x08
  24. #define JZ_REG_RTC_REGULATOR 0x0C
  25. #define JZ_REG_RTC_HIBERNATE 0x20
  26. #define JZ_REG_RTC_SCRATCHPAD 0x34
  27. #define JZ_RTC_CTRL_WRDY BIT(7)
  28. #define JZ_RTC_CTRL_1HZ BIT(6)
  29. #define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
  30. #define JZ_RTC_CTRL_AF BIT(4)
  31. #define JZ_RTC_CTRL_AF_IRQ BIT(3)
  32. #define JZ_RTC_CTRL_AE BIT(2)
  33. #define JZ_RTC_CTRL_ENABLE BIT(0)
  34. struct jz4740_rtc {
  35. struct resource *mem;
  36. void __iomem *base;
  37. struct rtc_device *rtc;
  38. unsigned int irq;
  39. spinlock_t lock;
  40. };
  41. static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
  42. {
  43. return readl(rtc->base + reg);
  44. }
  45. static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
  46. {
  47. uint32_t ctrl;
  48. int timeout = 1000;
  49. do {
  50. ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  51. } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
  52. return timeout ? 0 : -EIO;
  53. }
  54. static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
  55. uint32_t val)
  56. {
  57. int ret;
  58. ret = jz4740_rtc_wait_write_ready(rtc);
  59. if (ret == 0)
  60. writel(val, rtc->base + reg);
  61. return ret;
  62. }
  63. static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
  64. bool set)
  65. {
  66. int ret;
  67. unsigned long flags;
  68. uint32_t ctrl;
  69. spin_lock_irqsave(&rtc->lock, flags);
  70. ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  71. /* Don't clear interrupt flags by accident */
  72. ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
  73. if (set)
  74. ctrl |= mask;
  75. else
  76. ctrl &= ~mask;
  77. ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
  78. spin_unlock_irqrestore(&rtc->lock, flags);
  79. return ret;
  80. }
  81. static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
  82. {
  83. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  84. uint32_t secs, secs2;
  85. int timeout = 5;
  86. /* If the seconds register is read while it is updated, it can contain a
  87. * bogus value. This can be avoided by making sure that two consecutive
  88. * reads have the same value.
  89. */
  90. secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
  91. secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
  92. while (secs != secs2 && --timeout) {
  93. secs = secs2;
  94. secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
  95. }
  96. if (timeout == 0)
  97. return -EIO;
  98. rtc_time_to_tm(secs, time);
  99. return rtc_valid_tm(time);
  100. }
  101. static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
  102. {
  103. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  104. return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
  105. }
  106. static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  107. {
  108. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  109. uint32_t secs;
  110. uint32_t ctrl;
  111. secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
  112. ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  113. alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
  114. alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
  115. rtc_time_to_tm(secs, &alrm->time);
  116. return rtc_valid_tm(&alrm->time);
  117. }
  118. static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  119. {
  120. int ret;
  121. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  122. unsigned long secs;
  123. rtc_tm_to_time(&alrm->time, &secs);
  124. ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
  125. if (!ret)
  126. ret = jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AE, alrm->enabled);
  127. return ret;
  128. }
  129. static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
  130. {
  131. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  132. return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ, enable);
  133. }
  134. static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
  135. {
  136. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  137. return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
  138. }
  139. static struct rtc_class_ops jz4740_rtc_ops = {
  140. .read_time = jz4740_rtc_read_time,
  141. .set_mmss = jz4740_rtc_set_mmss,
  142. .read_alarm = jz4740_rtc_read_alarm,
  143. .set_alarm = jz4740_rtc_set_alarm,
  144. .update_irq_enable = jz4740_rtc_update_irq_enable,
  145. .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
  146. };
  147. static irqreturn_t jz4740_rtc_irq(int irq, void *data)
  148. {
  149. struct jz4740_rtc *rtc = data;
  150. uint32_t ctrl;
  151. unsigned long events = 0;
  152. ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  153. if (ctrl & JZ_RTC_CTRL_1HZ)
  154. events |= (RTC_UF | RTC_IRQF);
  155. if (ctrl & JZ_RTC_CTRL_AF)
  156. events |= (RTC_AF | RTC_IRQF);
  157. rtc_update_irq(rtc->rtc, 1, events);
  158. jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
  159. return IRQ_HANDLED;
  160. }
  161. void jz4740_rtc_poweroff(struct device *dev)
  162. {
  163. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  164. jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
  165. }
  166. EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
  167. static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
  168. {
  169. int ret;
  170. struct jz4740_rtc *rtc;
  171. uint32_t scratchpad;
  172. rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
  173. if (!rtc)
  174. return -ENOMEM;
  175. rtc->irq = platform_get_irq(pdev, 0);
  176. if (rtc->irq < 0) {
  177. ret = -ENOENT;
  178. dev_err(&pdev->dev, "Failed to get platform irq\n");
  179. goto err_free;
  180. }
  181. rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  182. if (!rtc->mem) {
  183. ret = -ENOENT;
  184. dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
  185. goto err_free;
  186. }
  187. rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
  188. pdev->name);
  189. if (!rtc->mem) {
  190. ret = -EBUSY;
  191. dev_err(&pdev->dev, "Failed to request mmio memory region\n");
  192. goto err_free;
  193. }
  194. rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
  195. if (!rtc->base) {
  196. ret = -EBUSY;
  197. dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
  198. goto err_release_mem_region;
  199. }
  200. spin_lock_init(&rtc->lock);
  201. platform_set_drvdata(pdev, rtc);
  202. rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
  203. THIS_MODULE);
  204. if (IS_ERR(rtc->rtc)) {
  205. ret = PTR_ERR(rtc->rtc);
  206. dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
  207. goto err_iounmap;
  208. }
  209. ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
  210. pdev->name, rtc);
  211. if (ret) {
  212. dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
  213. goto err_unregister_rtc;
  214. }
  215. scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
  216. if (scratchpad != 0x12345678) {
  217. ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
  218. ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
  219. if (ret) {
  220. dev_err(&pdev->dev, "Could not write write to RTC registers\n");
  221. goto err_free_irq;
  222. }
  223. }
  224. return 0;
  225. err_free_irq:
  226. free_irq(rtc->irq, rtc);
  227. err_unregister_rtc:
  228. rtc_device_unregister(rtc->rtc);
  229. err_iounmap:
  230. platform_set_drvdata(pdev, NULL);
  231. iounmap(rtc->base);
  232. err_release_mem_region:
  233. release_mem_region(rtc->mem->start, resource_size(rtc->mem));
  234. err_free:
  235. kfree(rtc);
  236. return ret;
  237. }
  238. static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
  239. {
  240. struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
  241. free_irq(rtc->irq, rtc);
  242. rtc_device_unregister(rtc->rtc);
  243. iounmap(rtc->base);
  244. release_mem_region(rtc->mem->start, resource_size(rtc->mem));
  245. kfree(rtc);
  246. platform_set_drvdata(pdev, NULL);
  247. return 0;
  248. }
  249. struct platform_driver jz4740_rtc_driver = {
  250. .probe = jz4740_rtc_probe,
  251. .remove = __devexit_p(jz4740_rtc_remove),
  252. .driver = {
  253. .name = "jz4740-rtc",
  254. .owner = THIS_MODULE,
  255. },
  256. };
  257. static int __init jz4740_rtc_init(void)
  258. {
  259. return platform_driver_register(&jz4740_rtc_driver);
  260. }
  261. module_init(jz4740_rtc_init);
  262. static void __exit jz4740_rtc_exit(void)
  263. {
  264. platform_driver_unregister(&jz4740_rtc_driver);
  265. }
  266. module_exit(jz4740_rtc_exit);
  267. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  268. MODULE_LICENSE("GPL");
  269. MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
  270. MODULE_ALIAS("platform:jz4740-rtc");