sdhci-s3c.c 13 KB

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  1. /* linux/drivers/mmc/host/sdhci-s3c.c
  2. *
  3. * Copyright 2008 Openmoko Inc.
  4. * Copyright 2008 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. * http://armlinux.simtec.co.uk/
  7. *
  8. * SDHCI (HSMMC) support for Samsung SoC
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/clk.h>
  19. #include <linux/io.h>
  20. #include <linux/gpio.h>
  21. #include <linux/mmc/host.h>
  22. #include <plat/sdhci.h>
  23. #include <plat/regs-sdhci.h>
  24. #include "sdhci.h"
  25. #define MAX_BUS_CLK (4)
  26. /**
  27. * struct sdhci_s3c - S3C SDHCI instance
  28. * @host: The SDHCI host created
  29. * @pdev: The platform device we where created from.
  30. * @ioarea: The resource created when we claimed the IO area.
  31. * @pdata: The platform data for this controller.
  32. * @cur_clk: The index of the current bus clock.
  33. * @clk_io: The clock for the internal bus interface.
  34. * @clk_bus: The clocks that are available for the SD/MMC bus clock.
  35. */
  36. struct sdhci_s3c {
  37. struct sdhci_host *host;
  38. struct platform_device *pdev;
  39. struct resource *ioarea;
  40. struct s3c_sdhci_platdata *pdata;
  41. unsigned int cur_clk;
  42. int ext_cd_irq;
  43. int ext_cd_gpio;
  44. struct clk *clk_io;
  45. struct clk *clk_bus[MAX_BUS_CLK];
  46. };
  47. static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
  48. {
  49. return sdhci_priv(host);
  50. }
  51. /**
  52. * get_curclk - convert ctrl2 register to clock source number
  53. * @ctrl2: Control2 register value.
  54. */
  55. static u32 get_curclk(u32 ctrl2)
  56. {
  57. ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
  58. ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
  59. return ctrl2;
  60. }
  61. static void sdhci_s3c_check_sclk(struct sdhci_host *host)
  62. {
  63. struct sdhci_s3c *ourhost = to_s3c(host);
  64. u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
  65. if (get_curclk(tmp) != ourhost->cur_clk) {
  66. dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
  67. tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
  68. tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
  69. writel(tmp, host->ioaddr + 0x80);
  70. }
  71. }
  72. /**
  73. * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
  74. * @host: The SDHCI host instance.
  75. *
  76. * Callback to return the maximum clock rate acheivable by the controller.
  77. */
  78. static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
  79. {
  80. struct sdhci_s3c *ourhost = to_s3c(host);
  81. struct clk *busclk;
  82. unsigned int rate, max;
  83. int clk;
  84. /* note, a reset will reset the clock source */
  85. sdhci_s3c_check_sclk(host);
  86. for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
  87. busclk = ourhost->clk_bus[clk];
  88. if (!busclk)
  89. continue;
  90. rate = clk_get_rate(busclk);
  91. if (rate > max)
  92. max = rate;
  93. }
  94. return max;
  95. }
  96. /**
  97. * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
  98. * @ourhost: Our SDHCI instance.
  99. * @src: The source clock index.
  100. * @wanted: The clock frequency wanted.
  101. */
  102. static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
  103. unsigned int src,
  104. unsigned int wanted)
  105. {
  106. unsigned long rate;
  107. struct clk *clksrc = ourhost->clk_bus[src];
  108. int div;
  109. if (!clksrc)
  110. return UINT_MAX;
  111. rate = clk_get_rate(clksrc);
  112. for (div = 1; div < 256; div *= 2) {
  113. if ((rate / div) <= wanted)
  114. break;
  115. }
  116. dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
  117. src, rate, wanted, rate / div);
  118. return (wanted - (rate / div));
  119. }
  120. /**
  121. * sdhci_s3c_set_clock - callback on clock change
  122. * @host: The SDHCI host being changed
  123. * @clock: The clock rate being requested.
  124. *
  125. * When the card's clock is going to be changed, look at the new frequency
  126. * and find the best clock source to go with it.
  127. */
  128. static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
  129. {
  130. struct sdhci_s3c *ourhost = to_s3c(host);
  131. unsigned int best = UINT_MAX;
  132. unsigned int delta;
  133. int best_src = 0;
  134. int src;
  135. u32 ctrl;
  136. /* don't bother if the clock is going off. */
  137. if (clock == 0)
  138. return;
  139. for (src = 0; src < MAX_BUS_CLK; src++) {
  140. delta = sdhci_s3c_consider_clock(ourhost, src, clock);
  141. if (delta < best) {
  142. best = delta;
  143. best_src = src;
  144. }
  145. }
  146. dev_dbg(&ourhost->pdev->dev,
  147. "selected source %d, clock %d, delta %d\n",
  148. best_src, clock, best);
  149. /* select the new clock source */
  150. if (ourhost->cur_clk != best_src) {
  151. struct clk *clk = ourhost->clk_bus[best_src];
  152. /* turn clock off to card before changing clock source */
  153. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  154. ourhost->cur_clk = best_src;
  155. host->max_clk = clk_get_rate(clk);
  156. ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
  157. ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
  158. ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
  159. writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
  160. }
  161. /* reconfigure the hardware for new clock rate */
  162. {
  163. struct mmc_ios ios;
  164. ios.clock = clock;
  165. if (ourhost->pdata->cfg_card)
  166. (ourhost->pdata->cfg_card)(ourhost->pdev, host->ioaddr,
  167. &ios, NULL);
  168. }
  169. }
  170. /**
  171. * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
  172. * @host: The SDHCI host being queried
  173. *
  174. * To init mmc host properly a minimal clock value is needed. For high system
  175. * bus clock's values the standard formula gives values out of allowed range.
  176. * The clock still can be set to lower values, if clock source other then
  177. * system bus is selected.
  178. */
  179. static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
  180. {
  181. struct sdhci_s3c *ourhost = to_s3c(host);
  182. unsigned int delta, min = UINT_MAX;
  183. int src;
  184. for (src = 0; src < MAX_BUS_CLK; src++) {
  185. delta = sdhci_s3c_consider_clock(ourhost, src, 0);
  186. if (delta == UINT_MAX)
  187. continue;
  188. /* delta is a negative value in this case */
  189. if (-delta < min)
  190. min = -delta;
  191. }
  192. return min;
  193. }
  194. static struct sdhci_ops sdhci_s3c_ops = {
  195. .get_max_clock = sdhci_s3c_get_max_clk,
  196. .set_clock = sdhci_s3c_set_clock,
  197. .get_min_clock = sdhci_s3c_get_min_clock,
  198. };
  199. static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
  200. {
  201. struct sdhci_host *host = platform_get_drvdata(dev);
  202. if (host) {
  203. spin_lock(&host->lock);
  204. if (state) {
  205. dev_dbg(&dev->dev, "card inserted.\n");
  206. host->flags &= ~SDHCI_DEVICE_DEAD;
  207. host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  208. } else {
  209. dev_dbg(&dev->dev, "card removed.\n");
  210. host->flags |= SDHCI_DEVICE_DEAD;
  211. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  212. }
  213. tasklet_schedule(&host->card_tasklet);
  214. spin_unlock(&host->lock);
  215. }
  216. }
  217. static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id)
  218. {
  219. struct sdhci_s3c *sc = dev_id;
  220. int status = gpio_get_value(sc->ext_cd_gpio);
  221. if (sc->pdata->ext_cd_gpio_invert)
  222. status = !status;
  223. sdhci_s3c_notify_change(sc->pdev, status);
  224. return IRQ_HANDLED;
  225. }
  226. static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
  227. {
  228. struct s3c_sdhci_platdata *pdata = sc->pdata;
  229. struct device *dev = &sc->pdev->dev;
  230. if (gpio_request(pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) {
  231. sc->ext_cd_gpio = pdata->ext_cd_gpio;
  232. sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio);
  233. if (sc->ext_cd_irq &&
  234. request_threaded_irq(sc->ext_cd_irq, NULL,
  235. sdhci_s3c_gpio_card_detect_thread,
  236. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
  237. dev_name(dev), sc) == 0) {
  238. int status = gpio_get_value(sc->ext_cd_gpio);
  239. if (pdata->ext_cd_gpio_invert)
  240. status = !status;
  241. sdhci_s3c_notify_change(sc->pdev, status);
  242. } else {
  243. dev_warn(dev, "cannot request irq for card detect\n");
  244. sc->ext_cd_irq = 0;
  245. }
  246. } else {
  247. dev_err(dev, "cannot request gpio for card detect\n");
  248. }
  249. }
  250. static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
  251. {
  252. struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
  253. struct device *dev = &pdev->dev;
  254. struct sdhci_host *host;
  255. struct sdhci_s3c *sc;
  256. struct resource *res;
  257. int ret, irq, ptr, clks;
  258. if (!pdata) {
  259. dev_err(dev, "no device data specified\n");
  260. return -ENOENT;
  261. }
  262. irq = platform_get_irq(pdev, 0);
  263. if (irq < 0) {
  264. dev_err(dev, "no irq specified\n");
  265. return irq;
  266. }
  267. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  268. if (!res) {
  269. dev_err(dev, "no memory specified\n");
  270. return -ENOENT;
  271. }
  272. host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
  273. if (IS_ERR(host)) {
  274. dev_err(dev, "sdhci_alloc_host() failed\n");
  275. return PTR_ERR(host);
  276. }
  277. sc = sdhci_priv(host);
  278. sc->host = host;
  279. sc->pdev = pdev;
  280. sc->pdata = pdata;
  281. sc->ext_cd_gpio = -1; /* invalid gpio number */
  282. platform_set_drvdata(pdev, host);
  283. sc->clk_io = clk_get(dev, "hsmmc");
  284. if (IS_ERR(sc->clk_io)) {
  285. dev_err(dev, "failed to get io clock\n");
  286. ret = PTR_ERR(sc->clk_io);
  287. goto err_io_clk;
  288. }
  289. /* enable the local io clock and keep it running for the moment. */
  290. clk_enable(sc->clk_io);
  291. for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
  292. struct clk *clk;
  293. char *name = pdata->clocks[ptr];
  294. if (name == NULL)
  295. continue;
  296. clk = clk_get(dev, name);
  297. if (IS_ERR(clk)) {
  298. dev_err(dev, "failed to get clock %s\n", name);
  299. continue;
  300. }
  301. clks++;
  302. sc->clk_bus[ptr] = clk;
  303. clk_enable(clk);
  304. dev_info(dev, "clock source %d: %s (%ld Hz)\n",
  305. ptr, name, clk_get_rate(clk));
  306. }
  307. if (clks == 0) {
  308. dev_err(dev, "failed to find any bus clocks\n");
  309. ret = -ENOENT;
  310. goto err_no_busclks;
  311. }
  312. sc->ioarea = request_mem_region(res->start, resource_size(res),
  313. mmc_hostname(host->mmc));
  314. if (!sc->ioarea) {
  315. dev_err(dev, "failed to reserve register area\n");
  316. ret = -ENXIO;
  317. goto err_req_regs;
  318. }
  319. host->ioaddr = ioremap_nocache(res->start, resource_size(res));
  320. if (!host->ioaddr) {
  321. dev_err(dev, "failed to map registers\n");
  322. ret = -ENXIO;
  323. goto err_req_regs;
  324. }
  325. /* Ensure we have minimal gpio selected CMD/CLK/Detect */
  326. if (pdata->cfg_gpio)
  327. pdata->cfg_gpio(pdev, pdata->max_width);
  328. host->hw_name = "samsung-hsmmc";
  329. host->ops = &sdhci_s3c_ops;
  330. host->quirks = 0;
  331. host->irq = irq;
  332. /* Setup quirks for the controller */
  333. host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
  334. host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
  335. #ifndef CONFIG_MMC_SDHCI_S3C_DMA
  336. /* we currently see overruns on errors, so disable the SDMA
  337. * support as well. */
  338. host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
  339. #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
  340. /* It seems we do not get an DATA transfer complete on non-busy
  341. * transfers, not sure if this is a problem with this specific
  342. * SDHCI block, or a missing configuration that needs to be set. */
  343. host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
  344. if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
  345. pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
  346. host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  347. if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
  348. host->mmc->caps = MMC_CAP_NONREMOVABLE;
  349. host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
  350. SDHCI_QUIRK_32BIT_DMA_SIZE);
  351. /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
  352. host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
  353. ret = sdhci_add_host(host);
  354. if (ret) {
  355. dev_err(dev, "sdhci_add_host() failed\n");
  356. goto err_add_host;
  357. }
  358. /* The following two methods of card detection might call
  359. sdhci_s3c_notify_change() immediately, so they can be called
  360. only after sdhci_add_host(). Setup errors are ignored. */
  361. if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
  362. pdata->ext_cd_init(&sdhci_s3c_notify_change);
  363. if (pdata->cd_type == S3C_SDHCI_CD_GPIO &&
  364. gpio_is_valid(pdata->ext_cd_gpio))
  365. sdhci_s3c_setup_card_detect_gpio(sc);
  366. return 0;
  367. err_add_host:
  368. release_resource(sc->ioarea);
  369. kfree(sc->ioarea);
  370. err_req_regs:
  371. for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
  372. clk_disable(sc->clk_bus[ptr]);
  373. clk_put(sc->clk_bus[ptr]);
  374. }
  375. err_no_busclks:
  376. clk_disable(sc->clk_io);
  377. clk_put(sc->clk_io);
  378. err_io_clk:
  379. sdhci_free_host(host);
  380. return ret;
  381. }
  382. static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
  383. {
  384. struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
  385. struct sdhci_host *host = platform_get_drvdata(pdev);
  386. struct sdhci_s3c *sc = sdhci_priv(host);
  387. int ptr;
  388. if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
  389. pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
  390. if (sc->ext_cd_irq)
  391. free_irq(sc->ext_cd_irq, sc);
  392. if (gpio_is_valid(sc->ext_cd_gpio))
  393. gpio_free(sc->ext_cd_gpio);
  394. sdhci_remove_host(host, 1);
  395. for (ptr = 0; ptr < 3; ptr++) {
  396. clk_disable(sc->clk_bus[ptr]);
  397. clk_put(sc->clk_bus[ptr]);
  398. }
  399. clk_disable(sc->clk_io);
  400. clk_put(sc->clk_io);
  401. iounmap(host->ioaddr);
  402. release_resource(sc->ioarea);
  403. kfree(sc->ioarea);
  404. sdhci_free_host(host);
  405. platform_set_drvdata(pdev, NULL);
  406. return 0;
  407. }
  408. #ifdef CONFIG_PM
  409. static int sdhci_s3c_suspend(struct platform_device *dev, pm_message_t pm)
  410. {
  411. struct sdhci_host *host = platform_get_drvdata(dev);
  412. sdhci_suspend_host(host, pm);
  413. return 0;
  414. }
  415. static int sdhci_s3c_resume(struct platform_device *dev)
  416. {
  417. struct sdhci_host *host = platform_get_drvdata(dev);
  418. sdhci_resume_host(host);
  419. return 0;
  420. }
  421. #else
  422. #define sdhci_s3c_suspend NULL
  423. #define sdhci_s3c_resume NULL
  424. #endif
  425. static struct platform_driver sdhci_s3c_driver = {
  426. .probe = sdhci_s3c_probe,
  427. .remove = __devexit_p(sdhci_s3c_remove),
  428. .suspend = sdhci_s3c_suspend,
  429. .resume = sdhci_s3c_resume,
  430. .driver = {
  431. .owner = THIS_MODULE,
  432. .name = "s3c-sdhci",
  433. },
  434. };
  435. static int __init sdhci_s3c_init(void)
  436. {
  437. return platform_driver_register(&sdhci_s3c_driver);
  438. }
  439. static void __exit sdhci_s3c_exit(void)
  440. {
  441. platform_driver_unregister(&sdhci_s3c_driver);
  442. }
  443. module_init(sdhci_s3c_init);
  444. module_exit(sdhci_s3c_exit);
  445. MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
  446. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  447. MODULE_LICENSE("GPL v2");
  448. MODULE_ALIAS("platform:s3c-sdhci");