ene_ir.c 26 KB

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  1. /*
  2. * driver for ENE KB3926 B/C/D CIR (pnp id: ENE0XXX)
  3. *
  4. * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of the
  9. * License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  19. * USA
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/pnp.h>
  24. #include <linux/io.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/sched.h>
  27. #include <linux/slab.h>
  28. #include <linux/input.h>
  29. #include <media/ir-core.h>
  30. #include <media/ir-common.h>
  31. #include "ene_ir.h"
  32. static int sample_period = -1;
  33. static int enable_idle = 1;
  34. static int input = 1;
  35. static int debug;
  36. static int txsim;
  37. static int ene_irq_status(struct ene_device *dev);
  38. /* read a hardware register */
  39. static u8 ene_hw_read_reg(struct ene_device *dev, u16 reg)
  40. {
  41. u8 retval;
  42. outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
  43. outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
  44. retval = inb(dev->hw_io + ENE_IO);
  45. ene_dbg_verbose("reg %04x == %02x", reg, retval);
  46. return retval;
  47. }
  48. /* write a hardware register */
  49. static void ene_hw_write_reg(struct ene_device *dev, u16 reg, u8 value)
  50. {
  51. outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
  52. outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
  53. outb(value, dev->hw_io + ENE_IO);
  54. ene_dbg_verbose("reg %04x <- %02x", reg, value);
  55. }
  56. /* change specific bits in hardware register */
  57. static void ene_hw_write_reg_mask(struct ene_device *dev,
  58. u16 reg, u8 value, u8 mask)
  59. {
  60. u8 regvalue;
  61. outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
  62. outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
  63. regvalue = inb(dev->hw_io + ENE_IO) & ~mask;
  64. regvalue |= (value & mask);
  65. outb(regvalue, dev->hw_io + ENE_IO);
  66. ene_dbg_verbose("reg %04x <- %02x (mask=%02x)", reg, value, mask);
  67. }
  68. /* detect hardware features */
  69. static int ene_hw_detect(struct ene_device *dev)
  70. {
  71. u8 chip_major, chip_minor;
  72. u8 hw_revision, old_ver;
  73. u8 tmp;
  74. u8 fw_capabilities;
  75. int pll_freq;
  76. tmp = ene_hw_read_reg(dev, ENE_HW_UNK);
  77. ene_hw_write_reg(dev, ENE_HW_UNK, tmp & ~ENE_HW_UNK_CLR);
  78. chip_major = ene_hw_read_reg(dev, ENE_HW_VER_MAJOR);
  79. chip_minor = ene_hw_read_reg(dev, ENE_HW_VER_MINOR);
  80. ene_hw_write_reg(dev, ENE_HW_UNK, tmp);
  81. hw_revision = ene_hw_read_reg(dev, ENE_HW_VERSION);
  82. old_ver = ene_hw_read_reg(dev, ENE_HW_VER_OLD);
  83. pll_freq = (ene_hw_read_reg(dev, ENE_PLLFRH) << 4) +
  84. (ene_hw_read_reg(dev, ENE_PLLFRL) >> 4);
  85. if (pll_freq != 1000)
  86. dev->rx_period_adjust = 4;
  87. else
  88. dev->rx_period_adjust = 2;
  89. ene_printk(KERN_NOTICE, "PLL freq = %d\n", pll_freq);
  90. if (hw_revision == 0xFF) {
  91. ene_printk(KERN_WARNING, "device seems to be disabled\n");
  92. ene_printk(KERN_WARNING,
  93. "send a mail to lirc-list@lists.sourceforge.net\n");
  94. ene_printk(KERN_WARNING, "please attach output of acpidump\n");
  95. return -ENODEV;
  96. }
  97. if (chip_major == 0x33) {
  98. ene_printk(KERN_WARNING, "chips 0x33xx aren't supported\n");
  99. return -ENODEV;
  100. }
  101. if (chip_major == 0x39 && chip_minor == 0x26 && hw_revision == 0xC0) {
  102. dev->hw_revision = ENE_HW_C;
  103. } else if (old_ver == 0x24 && hw_revision == 0xC0) {
  104. dev->hw_revision = ENE_HW_B;
  105. ene_printk(KERN_NOTICE, "KB3926B detected\n");
  106. } else {
  107. dev->hw_revision = ENE_HW_D;
  108. ene_printk(KERN_WARNING,
  109. "unknown ENE chip detected, assuming KB3926D\n");
  110. ene_printk(KERN_WARNING,
  111. "driver support might be not complete");
  112. }
  113. ene_printk(KERN_DEBUG,
  114. "chip is 0x%02x%02x - kbver = 0x%02x, rev = 0x%02x\n",
  115. chip_major, chip_minor, old_ver, hw_revision);
  116. /* detect features hardware supports */
  117. if (dev->hw_revision < ENE_HW_C)
  118. return 0;
  119. fw_capabilities = ene_hw_read_reg(dev, ENE_FW2);
  120. ene_dbg("Firmware capabilities: %02x", fw_capabilities);
  121. dev->hw_gpio40_learning = fw_capabilities & ENE_FW2_GP40_AS_LEARN;
  122. dev->hw_learning_and_tx_capable = fw_capabilities & ENE_FW2_LEARNING;
  123. dev->hw_fan_as_normal_input = dev->hw_learning_and_tx_capable &&
  124. (fw_capabilities & ENE_FW2_FAN_AS_NRML_IN);
  125. ene_printk(KERN_NOTICE, "hardware features:\n");
  126. ene_printk(KERN_NOTICE,
  127. "learning and transmit %s, gpio40_learn %s, fan_in %s\n",
  128. dev->hw_learning_and_tx_capable ? "on" : "off",
  129. dev->hw_gpio40_learning ? "on" : "off",
  130. dev->hw_fan_as_normal_input ? "on" : "off");
  131. if (dev->hw_learning_and_tx_capable) {
  132. ene_printk(KERN_WARNING,
  133. "Device supports transmitting, but that support is\n");
  134. ene_printk(KERN_WARNING,
  135. "lightly tested. Please test it and mail\n");
  136. ene_printk(KERN_WARNING,
  137. "lirc-list@lists.sourceforge.net\n");
  138. }
  139. return 0;
  140. }
  141. /* this enables/disables IR input via gpio40*/
  142. static void ene_enable_gpio40_receive(struct ene_device *dev, int enable)
  143. {
  144. ene_hw_write_reg_mask(dev, ENE_CIR_CONF2, enable ?
  145. 0 : ENE_CIR_CONF2_GPIO40DIS,
  146. ENE_CIR_CONF2_GPIO40DIS);
  147. }
  148. /* this enables/disables IR via standard input */
  149. static void ene_enable_normal_receive(struct ene_device *dev, int enable)
  150. {
  151. ene_hw_write_reg(dev, ENE_CIR_CONF1, enable ? ENE_CIR_CONF1_RX_ON : 0);
  152. }
  153. /* this enables/disables IR input via unused fan tachtometer input */
  154. static void ene_enable_fan_receive(struct ene_device *dev, int enable)
  155. {
  156. if (!enable)
  157. ene_hw_write_reg(dev, ENE_FAN_AS_IN1, 0);
  158. else {
  159. ene_hw_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
  160. ene_hw_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
  161. }
  162. dev->rx_fan_input_inuse = enable;
  163. }
  164. /* Sense current received carrier */
  165. static int ene_rx_sense_carrier(struct ene_device *dev)
  166. {
  167. int period = ene_hw_read_reg(dev, ENE_RX_CARRIER);
  168. int carrier;
  169. ene_dbg("RX: hardware carrier period = %02x", period);
  170. if (!(period & ENE_RX_CARRIER_VALID))
  171. return 0;
  172. period &= ~ENE_RX_CARRIER_VALID;
  173. if (!period)
  174. return 0;
  175. carrier = 2000000 / period;
  176. ene_dbg("RX: sensed carrier = %d Hz", carrier);
  177. return carrier;
  178. }
  179. /* determine which input to use*/
  180. static void ene_rx_set_inputs(struct ene_device *dev)
  181. {
  182. int learning_mode = dev->learning_enabled;
  183. ene_dbg("RX: setup receiver, learning mode = %d", learning_mode);
  184. ene_enable_normal_receive(dev, 1);
  185. /* old hardware doesn't support learning mode for sure */
  186. if (dev->hw_revision <= ENE_HW_B)
  187. return;
  188. /* receiver not learning capable, still set gpio40 correctly */
  189. if (!dev->hw_learning_and_tx_capable) {
  190. ene_enable_gpio40_receive(dev, !dev->hw_gpio40_learning);
  191. return;
  192. }
  193. /* enable learning mode */
  194. if (learning_mode) {
  195. ene_enable_gpio40_receive(dev, dev->hw_gpio40_learning);
  196. /* fan input is not used for learning */
  197. if (dev->hw_fan_as_normal_input)
  198. ene_enable_fan_receive(dev, 0);
  199. /* disable learning mode */
  200. } else {
  201. if (dev->hw_fan_as_normal_input) {
  202. ene_enable_fan_receive(dev, 1);
  203. ene_enable_normal_receive(dev, 0);
  204. } else
  205. ene_enable_gpio40_receive(dev,
  206. !dev->hw_gpio40_learning);
  207. }
  208. /* set few additional settings for this mode */
  209. ene_hw_write_reg_mask(dev, ENE_CIR_CONF1, learning_mode ?
  210. ENE_CIR_CONF1_LEARN1 : 0, ENE_CIR_CONF1_LEARN1);
  211. ene_hw_write_reg_mask(dev, ENE_CIR_CONF2, learning_mode ?
  212. ENE_CIR_CONF2_LEARN2 : 0, ENE_CIR_CONF2_LEARN2);
  213. if (dev->rx_fan_input_inuse) {
  214. dev->props->rx_resolution = ENE_SAMPLE_PERIOD_FAN * 1000;
  215. dev->props->timeout =
  216. ENE_FAN_VALUE_MASK * ENE_SAMPLE_PERIOD_FAN * 1000;
  217. } else {
  218. dev->props->rx_resolution = sample_period * 1000;
  219. dev->props->timeout = ENE_MAXGAP * 1000;
  220. }
  221. }
  222. /* Enable the device for receive */
  223. static void ene_rx_enable(struct ene_device *dev)
  224. {
  225. u8 reg_value;
  226. if (dev->hw_revision < ENE_HW_C) {
  227. ene_hw_write_reg(dev, ENEB_IRQ, dev->irq << 1);
  228. ene_hw_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
  229. } else {
  230. reg_value = ene_hw_read_reg(dev, ENEC_IRQ) & 0xF0;
  231. reg_value |= ENEC_IRQ_UNK_EN;
  232. reg_value &= ~ENEC_IRQ_STATUS;
  233. reg_value |= (dev->irq & ENEC_IRQ_MASK);
  234. ene_hw_write_reg(dev, ENEC_IRQ, reg_value);
  235. ene_hw_write_reg(dev, ENE_TX_UNK1, 0x63);
  236. }
  237. ene_hw_write_reg(dev, ENE_CIR_CONF2, 0x00);
  238. ene_rx_set_inputs(dev);
  239. /* set sampling period */
  240. ene_hw_write_reg(dev, ENE_CIR_SAMPLE_PERIOD, sample_period);
  241. /* ack any pending irqs - just in case */
  242. ene_irq_status(dev);
  243. /* enable firmware bits */
  244. ene_hw_write_reg_mask(dev, ENE_FW1,
  245. ENE_FW1_ENABLE | ENE_FW1_IRQ,
  246. ENE_FW1_ENABLE | ENE_FW1_IRQ);
  247. /* enter idle mode */
  248. ir_raw_event_set_idle(dev->idev, 1);
  249. ir_raw_event_reset(dev->idev);
  250. }
  251. /* Disable the device receiver */
  252. static void ene_rx_disable(struct ene_device *dev)
  253. {
  254. /* disable inputs */
  255. ene_enable_normal_receive(dev, 0);
  256. if (dev->hw_fan_as_normal_input)
  257. ene_enable_fan_receive(dev, 0);
  258. /* disable hardware IRQ and firmware flag */
  259. ene_hw_write_reg_mask(dev, ENE_FW1, 0, ENE_FW1_ENABLE | ENE_FW1_IRQ);
  260. ir_raw_event_set_idle(dev->idev, 1);
  261. ir_raw_event_reset(dev->idev);
  262. }
  263. /* prepare transmission */
  264. static void ene_tx_prepare(struct ene_device *dev)
  265. {
  266. u8 conf1;
  267. conf1 = ene_hw_read_reg(dev, ENE_CIR_CONF1);
  268. dev->saved_conf1 = conf1;
  269. if (dev->hw_revision == ENE_HW_C)
  270. conf1 &= ~ENE_CIR_CONF1_TX_CLEAR;
  271. /* Enable TX engine */
  272. conf1 |= ENE_CIR_CONF1_TX_ON;
  273. /* Set carrier */
  274. if (dev->tx_period) {
  275. /* NOTE: duty cycle handling is just a guess, it might
  276. not be aviable. Default values were tested */
  277. int tx_period_in500ns = dev->tx_period * 2;
  278. int tx_pulse_width_in_500ns =
  279. tx_period_in500ns / (100 / dev->tx_duty_cycle);
  280. if (!tx_pulse_width_in_500ns)
  281. tx_pulse_width_in_500ns = 1;
  282. ene_dbg("TX: pulse distance = %d * 500 ns", tx_period_in500ns);
  283. ene_dbg("TX: pulse width = %d * 500 ns",
  284. tx_pulse_width_in_500ns);
  285. ene_hw_write_reg(dev, ENE_TX_PERIOD, ENE_TX_PERIOD_UNKBIT |
  286. tx_period_in500ns);
  287. ene_hw_write_reg(dev, ENE_TX_PERIOD_PULSE,
  288. tx_pulse_width_in_500ns);
  289. conf1 |= ENE_CIR_CONF1_TX_CARR;
  290. } else
  291. conf1 &= ~ENE_CIR_CONF1_TX_CARR;
  292. ene_hw_write_reg(dev, ENE_CIR_CONF1, conf1);
  293. }
  294. /* end transmission */
  295. static void ene_tx_complete(struct ene_device *dev)
  296. {
  297. ene_hw_write_reg(dev, ENE_CIR_CONF1, dev->saved_conf1);
  298. dev->tx_buffer = NULL;
  299. }
  300. /* set transmit mask */
  301. static void ene_tx_hw_set_transmiter_mask(struct ene_device *dev)
  302. {
  303. u8 txport1 = ene_hw_read_reg(dev, ENE_TX_PORT1) & ~ENE_TX_PORT1_EN;
  304. u8 txport2 = ene_hw_read_reg(dev, ENE_TX_PORT2) & ~ENE_TX_PORT2_EN;
  305. if (dev->transmitter_mask & 0x01)
  306. txport1 |= ENE_TX_PORT1_EN;
  307. if (dev->transmitter_mask & 0x02)
  308. txport2 |= ENE_TX_PORT2_EN;
  309. ene_hw_write_reg(dev, ENE_TX_PORT1, txport1);
  310. ene_hw_write_reg(dev, ENE_TX_PORT2, txport2);
  311. }
  312. /* TX one sample - must be called with dev->hw_lock*/
  313. static void ene_tx_sample(struct ene_device *dev)
  314. {
  315. u8 raw_tx;
  316. u32 sample;
  317. if (!dev->tx_buffer) {
  318. ene_dbg("TX: attempt to transmit NULL buffer");
  319. return;
  320. }
  321. /* Grab next TX sample */
  322. if (!dev->tx_sample) {
  323. again:
  324. if (dev->tx_pos == dev->tx_len + 1) {
  325. if (!dev->tx_done) {
  326. ene_dbg("TX: no more data to send");
  327. dev->tx_done = 1;
  328. goto exit;
  329. } else {
  330. ene_dbg("TX: last sample sent by hardware");
  331. ene_tx_complete(dev);
  332. complete(&dev->tx_complete);
  333. return;
  334. }
  335. }
  336. sample = dev->tx_buffer[dev->tx_pos++];
  337. dev->tx_sample_pulse = !dev->tx_sample_pulse;
  338. ene_dbg("TX: sample %8d (%s)", sample, dev->tx_sample_pulse ?
  339. "pulse" : "space");
  340. dev->tx_sample = DIV_ROUND_CLOSEST(sample, ENE_TX_SMPL_PERIOD);
  341. /* guard against too short samples */
  342. if (!dev->tx_sample)
  343. goto again;
  344. }
  345. raw_tx = min(dev->tx_sample , (unsigned int)ENE_TX_SMLP_MASK);
  346. dev->tx_sample -= raw_tx;
  347. if (dev->tx_sample_pulse)
  348. raw_tx |= ENE_TX_PULSE_MASK;
  349. ene_hw_write_reg(dev, ENE_TX_INPUT1 + dev->tx_reg, raw_tx);
  350. dev->tx_reg = !dev->tx_reg;
  351. exit:
  352. /* simulate TX done interrupt */
  353. if (txsim)
  354. mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500);
  355. }
  356. /* timer to simulate tx done interrupt */
  357. static void ene_tx_irqsim(unsigned long data)
  358. {
  359. struct ene_device *dev = (struct ene_device *)data;
  360. unsigned long flags;
  361. spin_lock_irqsave(&dev->hw_lock, flags);
  362. ene_tx_sample(dev);
  363. spin_unlock_irqrestore(&dev->hw_lock, flags);
  364. }
  365. /* read irq status and ack it */
  366. static int ene_irq_status(struct ene_device *dev)
  367. {
  368. u8 irq_status;
  369. u8 fw_flags1, fw_flags2;
  370. int cur_rx_pointer;
  371. int retval = 0;
  372. fw_flags2 = ene_hw_read_reg(dev, ENE_FW2);
  373. cur_rx_pointer = !!(fw_flags2 & ENE_FW2_BUF_HIGH);
  374. if (dev->hw_revision < ENE_HW_C) {
  375. irq_status = ene_hw_read_reg(dev, ENEB_IRQ_STATUS);
  376. if (!(irq_status & ENEB_IRQ_STATUS_IR))
  377. return 0;
  378. ene_hw_write_reg(dev, ENEB_IRQ_STATUS,
  379. irq_status & ~ENEB_IRQ_STATUS_IR);
  380. dev->rx_pointer = cur_rx_pointer;
  381. return ENE_IRQ_RX;
  382. }
  383. irq_status = ene_hw_read_reg(dev, ENEC_IRQ);
  384. if (!(irq_status & ENEC_IRQ_STATUS))
  385. return 0;
  386. /* original driver does that twice - a workaround ? */
  387. ene_hw_write_reg(dev, ENEC_IRQ, irq_status & ~ENEC_IRQ_STATUS);
  388. ene_hw_write_reg(dev, ENEC_IRQ, irq_status & ~ENEC_IRQ_STATUS);
  389. /* clear unknown flag in F8F9 */
  390. if (fw_flags2 & ENE_FW2_IRQ_CLR)
  391. ene_hw_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_IRQ_CLR);
  392. /* check if this is a TX interrupt */
  393. fw_flags1 = ene_hw_read_reg(dev, ENE_FW1);
  394. if (fw_flags1 & ENE_FW1_TXIRQ) {
  395. ene_hw_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);
  396. retval |= ENE_IRQ_TX;
  397. }
  398. /* Check if this is RX interrupt */
  399. if (dev->rx_pointer != cur_rx_pointer) {
  400. retval |= ENE_IRQ_RX;
  401. dev->rx_pointer = cur_rx_pointer;
  402. } else if (!(retval & ENE_IRQ_TX)) {
  403. ene_dbg("RX: interrupt without change in RX pointer(%d)",
  404. dev->rx_pointer);
  405. retval |= ENE_IRQ_RX;
  406. }
  407. if ((retval & ENE_IRQ_RX) && (retval & ENE_IRQ_TX))
  408. ene_dbg("both RX and TX interrupt at same time");
  409. return retval;
  410. }
  411. /* interrupt handler */
  412. static irqreturn_t ene_isr(int irq, void *data)
  413. {
  414. u16 hw_value;
  415. int i, hw_sample;
  416. int pulse;
  417. int irq_status;
  418. unsigned long flags;
  419. int carrier = 0;
  420. irqreturn_t retval = IRQ_NONE;
  421. struct ene_device *dev = (struct ene_device *)data;
  422. struct ir_raw_event ev;
  423. spin_lock_irqsave(&dev->hw_lock, flags);
  424. irq_status = ene_irq_status(dev);
  425. if (!irq_status)
  426. goto unlock;
  427. retval = IRQ_HANDLED;
  428. if (irq_status & ENE_IRQ_TX) {
  429. if (!dev->hw_learning_and_tx_capable) {
  430. ene_dbg("TX interrupt on unsupported device!");
  431. goto unlock;
  432. }
  433. ene_tx_sample(dev);
  434. }
  435. if (!(irq_status & ENE_IRQ_RX))
  436. goto unlock;
  437. if (dev->carrier_detect_enabled || debug)
  438. carrier = ene_rx_sense_carrier(dev);
  439. #if 0
  440. /* TODO */
  441. if (dev->carrier_detect_enabled && carrier)
  442. ir_raw_event_report_frequency(dev->idev, carrier);
  443. #endif
  444. for (i = 0; i < ENE_SAMPLES_SIZE; i++) {
  445. hw_value = ene_hw_read_reg(dev,
  446. ENE_SAMPLE_BUFFER + dev->rx_pointer * 4 + i);
  447. if (dev->rx_fan_input_inuse) {
  448. /* read high part of the sample */
  449. hw_value |= ene_hw_read_reg(dev,
  450. ENE_SAMPLE_BUFFER_FAN +
  451. dev->rx_pointer * 4 + i) << 8;
  452. pulse = hw_value & ENE_FAN_SMPL_PULS_MSK;
  453. /* clear space bit, and other unused bits */
  454. hw_value &= ENE_FAN_VALUE_MASK;
  455. hw_sample = hw_value * ENE_SAMPLE_PERIOD_FAN;
  456. } else {
  457. pulse = !(hw_value & ENE_SAMPLE_SPC_MASK);
  458. hw_value &= ENE_SAMPLE_VALUE_MASK;
  459. hw_sample = hw_value * sample_period;
  460. if (dev->rx_period_adjust) {
  461. hw_sample *= (100 - dev->rx_period_adjust);
  462. hw_sample /= 100;
  463. }
  464. }
  465. /* no more data */
  466. if (!(hw_value))
  467. break;
  468. ene_dbg("RX: %d (%s)", hw_sample, pulse ? "pulse" : "space");
  469. ev.duration = hw_sample * 1000;
  470. ev.pulse = pulse;
  471. ir_raw_event_store_with_filter(dev->idev, &ev);
  472. }
  473. ir_raw_event_handle(dev->idev);
  474. unlock:
  475. spin_unlock_irqrestore(&dev->hw_lock, flags);
  476. return retval;
  477. }
  478. /* Initialize default settings */
  479. static void ene_setup_settings(struct ene_device *dev)
  480. {
  481. dev->tx_period = 32;
  482. dev->tx_duty_cycle = 25; /*%*/
  483. dev->transmitter_mask = 3;
  484. /* Force learning mode if (input == 2), otherwise
  485. let user set it with LIRC_SET_REC_CARRIER */
  486. dev->learning_enabled =
  487. (input == 2 && dev->hw_learning_and_tx_capable);
  488. dev->rx_pointer = -1;
  489. }
  490. /* outside interface: called on first open*/
  491. static int ene_open(void *data)
  492. {
  493. struct ene_device *dev = (struct ene_device *)data;
  494. unsigned long flags;
  495. spin_lock_irqsave(&dev->hw_lock, flags);
  496. dev->in_use = 1;
  497. ene_setup_settings(dev);
  498. ene_rx_enable(dev);
  499. spin_unlock_irqrestore(&dev->hw_lock, flags);
  500. return 0;
  501. }
  502. /* outside interface: called on device close*/
  503. static void ene_close(void *data)
  504. {
  505. struct ene_device *dev = (struct ene_device *)data;
  506. unsigned long flags;
  507. spin_lock_irqsave(&dev->hw_lock, flags);
  508. ene_rx_disable(dev);
  509. dev->in_use = 0;
  510. spin_unlock_irqrestore(&dev->hw_lock, flags);
  511. }
  512. /* outside interface: set transmitter mask */
  513. static int ene_set_tx_mask(void *data, u32 tx_mask)
  514. {
  515. struct ene_device *dev = (struct ene_device *)data;
  516. unsigned long flags;
  517. ene_dbg("TX: attempt to set transmitter mask %02x", tx_mask);
  518. /* invalid txmask */
  519. if (!tx_mask || tx_mask & ~0x3) {
  520. ene_dbg("TX: invalid mask");
  521. /* return count of transmitters */
  522. return 2;
  523. }
  524. spin_lock_irqsave(&dev->hw_lock, flags);
  525. dev->transmitter_mask = tx_mask;
  526. spin_unlock_irqrestore(&dev->hw_lock, flags);
  527. return 0;
  528. }
  529. /* outside interface : set tx carrier */
  530. static int ene_set_tx_carrier(void *data, u32 carrier)
  531. {
  532. struct ene_device *dev = (struct ene_device *)data;
  533. unsigned long flags;
  534. u32 period = 1000000 / carrier; /* (1 / freq) (* # usec in 1 sec) */
  535. ene_dbg("TX: attempt to set tx carrier to %d kHz", carrier);
  536. if (period && (period > ENE_TX_PERIOD_MAX ||
  537. period < ENE_TX_PERIOD_MIN)) {
  538. ene_dbg("TX: out of range %d-%d carrier, "
  539. "falling back to 32 kHz",
  540. 1000 / ENE_TX_PERIOD_MIN,
  541. 1000 / ENE_TX_PERIOD_MAX);
  542. period = 32; /* this is just a coincidence!!! */
  543. }
  544. ene_dbg("TX: set carrier to %d kHz", carrier);
  545. spin_lock_irqsave(&dev->hw_lock, flags);
  546. dev->tx_period = period;
  547. spin_unlock_irqrestore(&dev->hw_lock, flags);
  548. return 0;
  549. }
  550. /* outside interface: enable learning mode */
  551. static int ene_set_learning_mode(void *data, int enable)
  552. {
  553. struct ene_device *dev = (struct ene_device *)data;
  554. unsigned long flags;
  555. if (enable == dev->learning_enabled)
  556. return 0;
  557. spin_lock_irqsave(&dev->hw_lock, flags);
  558. dev->learning_enabled = enable;
  559. ene_rx_set_inputs(dev);
  560. spin_unlock_irqrestore(&dev->hw_lock, flags);
  561. return 0;
  562. }
  563. /* outside interface: set rec carrier */
  564. static int ene_set_rec_carrier(void *data, u32 min, u32 max)
  565. {
  566. struct ene_device *dev = (struct ene_device *)data;
  567. ene_set_learning_mode(dev,
  568. max > ENE_NORMAL_RX_HI || min < ENE_NORMAL_RX_LOW);
  569. return 0;
  570. }
  571. /* outside interface: enable or disable idle mode */
  572. static void ene_rx_set_idle(void *data, int idle)
  573. {
  574. struct ene_device *dev = (struct ene_device *)data;
  575. ene_dbg("%sabling idle mode", idle ? "en" : "dis");
  576. ene_hw_write_reg_mask(dev, ENE_CIR_SAMPLE_PERIOD,
  577. (enable_idle && idle) ? 0 : ENE_CIR_SAMPLE_OVERFLOW,
  578. ENE_CIR_SAMPLE_OVERFLOW);
  579. }
  580. /* outside interface: transmit */
  581. static int ene_transmit(void *data, int *buf, u32 n)
  582. {
  583. struct ene_device *dev = (struct ene_device *)data;
  584. unsigned long flags;
  585. dev->tx_buffer = buf;
  586. dev->tx_len = n / sizeof(int);
  587. dev->tx_pos = 0;
  588. dev->tx_reg = 0;
  589. dev->tx_done = 0;
  590. dev->tx_sample = 0;
  591. dev->tx_sample_pulse = 0;
  592. ene_dbg("TX: %d samples", dev->tx_len);
  593. spin_lock_irqsave(&dev->hw_lock, flags);
  594. ene_tx_hw_set_transmiter_mask(dev);
  595. ene_tx_prepare(dev);
  596. /* Transmit first two samples */
  597. ene_tx_sample(dev);
  598. ene_tx_sample(dev);
  599. spin_unlock_irqrestore(&dev->hw_lock, flags);
  600. if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) {
  601. ene_dbg("TX: timeout");
  602. spin_lock_irqsave(&dev->hw_lock, flags);
  603. ene_tx_complete(dev);
  604. spin_unlock_irqrestore(&dev->hw_lock, flags);
  605. } else
  606. ene_dbg("TX: done");
  607. return n;
  608. }
  609. /* probe entry */
  610. static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id)
  611. {
  612. int error = -ENOMEM;
  613. struct ir_dev_props *ir_props;
  614. struct input_dev *input_dev;
  615. struct ene_device *dev;
  616. /* allocate memory */
  617. input_dev = input_allocate_device();
  618. ir_props = kzalloc(sizeof(struct ir_dev_props), GFP_KERNEL);
  619. dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL);
  620. if (!input_dev || !ir_props || !dev)
  621. goto error;
  622. /* validate resources */
  623. error = -ENODEV;
  624. if (!pnp_port_valid(pnp_dev, 0) ||
  625. pnp_port_len(pnp_dev, 0) < ENE_MAX_IO)
  626. goto error;
  627. if (!pnp_irq_valid(pnp_dev, 0))
  628. goto error;
  629. dev->hw_io = pnp_port_start(pnp_dev, 0);
  630. dev->irq = pnp_irq(pnp_dev, 0);
  631. spin_lock_init(&dev->hw_lock);
  632. /* claim the resources */
  633. error = -EBUSY;
  634. if (!request_region(dev->hw_io, ENE_MAX_IO, ENE_DRIVER_NAME))
  635. goto error;
  636. if (request_irq(dev->irq, ene_isr,
  637. IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev))
  638. goto error;
  639. pnp_set_drvdata(pnp_dev, dev);
  640. dev->pnp_dev = pnp_dev;
  641. /* detect hardware version and features */
  642. error = ene_hw_detect(dev);
  643. if (error)
  644. goto error;
  645. ene_setup_settings(dev);
  646. if (!dev->hw_learning_and_tx_capable && txsim) {
  647. dev->hw_learning_and_tx_capable = 1;
  648. setup_timer(&dev->tx_sim_timer, ene_tx_irqsim,
  649. (long unsigned int)dev);
  650. ene_printk(KERN_WARNING,
  651. "Simulation of TX activated\n");
  652. }
  653. ir_props->driver_type = RC_DRIVER_IR_RAW;
  654. ir_props->allowed_protos = IR_TYPE_ALL;
  655. ir_props->priv = dev;
  656. ir_props->open = ene_open;
  657. ir_props->close = ene_close;
  658. ir_props->min_timeout = ENE_MINGAP * 1000;
  659. ir_props->max_timeout = ENE_MAXGAP * 1000;
  660. ir_props->timeout = ENE_MAXGAP * 1000;
  661. if (dev->hw_revision == ENE_HW_B)
  662. ir_props->s_idle = ene_rx_set_idle;
  663. dev->props = ir_props;
  664. dev->idev = input_dev;
  665. /* don't allow too short/long sample periods */
  666. if (sample_period < 5 || sample_period > 0x7F)
  667. sample_period = -1;
  668. /* choose default sample period */
  669. if (sample_period == -1) {
  670. sample_period = 50;
  671. /* on revB, hardware idle mode eats first sample
  672. if we set too low sample period */
  673. if (dev->hw_revision == ENE_HW_B && enable_idle)
  674. sample_period = 75;
  675. }
  676. ir_props->rx_resolution = sample_period * 1000;
  677. if (dev->hw_learning_and_tx_capable) {
  678. ir_props->s_learning_mode = ene_set_learning_mode;
  679. if (input == 0)
  680. ir_props->s_rx_carrier_range = ene_set_rec_carrier;
  681. init_completion(&dev->tx_complete);
  682. ir_props->tx_ir = ene_transmit;
  683. ir_props->s_tx_mask = ene_set_tx_mask;
  684. ir_props->s_tx_carrier = ene_set_tx_carrier;
  685. ir_props->tx_resolution = ENE_TX_SMPL_PERIOD * 1000;
  686. /* ir_props->s_carrier_report = ene_set_carrier_report; */
  687. }
  688. device_set_wakeup_capable(&pnp_dev->dev, 1);
  689. device_set_wakeup_enable(&pnp_dev->dev, 1);
  690. if (dev->hw_learning_and_tx_capable)
  691. input_dev->name = "ENE eHome Infrared Remote Transceiver";
  692. else
  693. input_dev->name = "ENE eHome Infrared Remote Receiver";
  694. error = -ENODEV;
  695. if (ir_input_register(input_dev, RC_MAP_RC6_MCE, ir_props,
  696. ENE_DRIVER_NAME))
  697. goto error;
  698. ene_printk(KERN_NOTICE, "driver has been succesfully loaded\n");
  699. return 0;
  700. error:
  701. if (dev->irq)
  702. free_irq(dev->irq, dev);
  703. if (dev->hw_io)
  704. release_region(dev->hw_io, ENE_MAX_IO);
  705. input_free_device(input_dev);
  706. kfree(ir_props);
  707. kfree(dev);
  708. return error;
  709. }
  710. /* main unload function */
  711. static void ene_remove(struct pnp_dev *pnp_dev)
  712. {
  713. struct ene_device *dev = pnp_get_drvdata(pnp_dev);
  714. unsigned long flags;
  715. spin_lock_irqsave(&dev->hw_lock, flags);
  716. ene_rx_disable(dev);
  717. spin_unlock_irqrestore(&dev->hw_lock, flags);
  718. free_irq(dev->irq, dev);
  719. release_region(dev->hw_io, ENE_MAX_IO);
  720. ir_input_unregister(dev->idev);
  721. kfree(dev->props);
  722. kfree(dev);
  723. }
  724. /* enable wake on IR (wakes on specific button on original remote) */
  725. static void ene_enable_wake(struct ene_device *dev, int enable)
  726. {
  727. enable = enable && device_may_wakeup(&dev->pnp_dev->dev);
  728. ene_dbg("wake on IR %s", enable ? "enabled" : "disabled");
  729. ene_hw_write_reg_mask(dev, ENE_FW1, enable ?
  730. ENE_FW1_WAKE : 0, ENE_FW1_WAKE);
  731. }
  732. #ifdef CONFIG_PM
  733. static int ene_suspend(struct pnp_dev *pnp_dev, pm_message_t state)
  734. {
  735. struct ene_device *dev = pnp_get_drvdata(pnp_dev);
  736. ene_enable_wake(dev, 1);
  737. return 0;
  738. }
  739. static int ene_resume(struct pnp_dev *pnp_dev)
  740. {
  741. struct ene_device *dev = pnp_get_drvdata(pnp_dev);
  742. if (dev->in_use)
  743. ene_rx_enable(dev);
  744. ene_enable_wake(dev, 0);
  745. return 0;
  746. }
  747. #endif
  748. static void ene_shutdown(struct pnp_dev *pnp_dev)
  749. {
  750. struct ene_device *dev = pnp_get_drvdata(pnp_dev);
  751. ene_enable_wake(dev, 1);
  752. }
  753. static const struct pnp_device_id ene_ids[] = {
  754. {.id = "ENE0100",},
  755. {.id = "ENE0200",},
  756. {.id = "ENE0201",},
  757. {.id = "ENE0202",},
  758. {},
  759. };
  760. static struct pnp_driver ene_driver = {
  761. .name = ENE_DRIVER_NAME,
  762. .id_table = ene_ids,
  763. .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
  764. .probe = ene_probe,
  765. .remove = __devexit_p(ene_remove),
  766. #ifdef CONFIG_PM
  767. .suspend = ene_suspend,
  768. .resume = ene_resume,
  769. #endif
  770. .shutdown = ene_shutdown,
  771. };
  772. static int __init ene_init(void)
  773. {
  774. return pnp_register_driver(&ene_driver);
  775. }
  776. static void ene_exit(void)
  777. {
  778. pnp_unregister_driver(&ene_driver);
  779. }
  780. module_param(sample_period, int, S_IRUGO);
  781. MODULE_PARM_DESC(sample_period, "Hardware sample period (50 us default)");
  782. module_param(enable_idle, bool, S_IRUGO | S_IWUSR);
  783. MODULE_PARM_DESC(enable_idle,
  784. "Enables turning off signal sampling after long inactivity time; "
  785. "if disabled might help detecting input signal (default: enabled)"
  786. " (KB3926B only)");
  787. module_param(input, bool, S_IRUGO);
  788. MODULE_PARM_DESC(input, "select which input to use "
  789. "0 - auto, 1 - standard, 2 - wideband(KB3926C+)");
  790. module_param(debug, int, S_IRUGO | S_IWUSR);
  791. MODULE_PARM_DESC(debug, "Enable debug (debug=2 verbose debug output)");
  792. module_param(txsim, bool, S_IRUGO);
  793. MODULE_PARM_DESC(txsim,
  794. "Simulate TX features on unsupported hardware (dangerous)");
  795. MODULE_DEVICE_TABLE(pnp, ene_ids);
  796. MODULE_DESCRIPTION
  797. ("Infrared input driver for KB3926B/KB3926C/KB3926D "
  798. "(aka ENE0100/ENE0200/ENE0201) CIR port");
  799. MODULE_AUTHOR("Maxim Levitsky");
  800. MODULE_LICENSE("GPL");
  801. module_init(ene_init);
  802. module_exit(ene_exit);