stmpe-gpio.c 9.6 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License, version 2
  5. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  6. */
  7. #include <linux/module.h>
  8. #include <linux/init.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/gpio.h>
  12. #include <linux/irq.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/mfd/stmpe.h>
  15. /*
  16. * These registers are modified under the irq bus lock and cached to avoid
  17. * unnecessary writes in bus_sync_unlock.
  18. */
  19. enum { REG_RE, REG_FE, REG_IE };
  20. #define CACHE_NR_REGS 3
  21. #define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
  22. struct stmpe_gpio {
  23. struct gpio_chip chip;
  24. struct stmpe *stmpe;
  25. struct device *dev;
  26. struct mutex irq_lock;
  27. int irq_base;
  28. /* Caches of interrupt control registers for bus_lock */
  29. u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  30. u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  31. };
  32. static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
  33. {
  34. return container_of(chip, struct stmpe_gpio, chip);
  35. }
  36. static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
  37. {
  38. struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  39. struct stmpe *stmpe = stmpe_gpio->stmpe;
  40. u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
  41. u8 mask = 1 << (offset % 8);
  42. int ret;
  43. ret = stmpe_reg_read(stmpe, reg);
  44. if (ret < 0)
  45. return ret;
  46. return ret & mask;
  47. }
  48. static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  49. {
  50. struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  51. struct stmpe *stmpe = stmpe_gpio->stmpe;
  52. int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
  53. u8 reg = stmpe->regs[which] - (offset / 8);
  54. u8 mask = 1 << (offset % 8);
  55. stmpe_reg_write(stmpe, reg, mask);
  56. }
  57. static int stmpe_gpio_direction_output(struct gpio_chip *chip,
  58. unsigned offset, int val)
  59. {
  60. struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  61. struct stmpe *stmpe = stmpe_gpio->stmpe;
  62. u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
  63. u8 mask = 1 << (offset % 8);
  64. stmpe_gpio_set(chip, offset, val);
  65. return stmpe_set_bits(stmpe, reg, mask, mask);
  66. }
  67. static int stmpe_gpio_direction_input(struct gpio_chip *chip,
  68. unsigned offset)
  69. {
  70. struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  71. struct stmpe *stmpe = stmpe_gpio->stmpe;
  72. u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
  73. u8 mask = 1 << (offset % 8);
  74. return stmpe_set_bits(stmpe, reg, mask, 0);
  75. }
  76. static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  77. {
  78. struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  79. return stmpe_gpio->irq_base + offset;
  80. }
  81. static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
  82. {
  83. struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
  84. struct stmpe *stmpe = stmpe_gpio->stmpe;
  85. return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
  86. }
  87. static struct gpio_chip template_chip = {
  88. .label = "stmpe",
  89. .owner = THIS_MODULE,
  90. .direction_input = stmpe_gpio_direction_input,
  91. .get = stmpe_gpio_get,
  92. .direction_output = stmpe_gpio_direction_output,
  93. .set = stmpe_gpio_set,
  94. .to_irq = stmpe_gpio_to_irq,
  95. .request = stmpe_gpio_request,
  96. .can_sleep = 1,
  97. };
  98. static int stmpe_gpio_irq_set_type(unsigned int irq, unsigned int type)
  99. {
  100. struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
  101. int offset = irq - stmpe_gpio->irq_base;
  102. int regoffset = offset / 8;
  103. int mask = 1 << (offset % 8);
  104. if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
  105. return -EINVAL;
  106. if (type == IRQ_TYPE_EDGE_RISING)
  107. stmpe_gpio->regs[REG_RE][regoffset] |= mask;
  108. else
  109. stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
  110. if (type == IRQ_TYPE_EDGE_FALLING)
  111. stmpe_gpio->regs[REG_FE][regoffset] |= mask;
  112. else
  113. stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
  114. return 0;
  115. }
  116. static void stmpe_gpio_irq_lock(unsigned int irq)
  117. {
  118. struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
  119. mutex_lock(&stmpe_gpio->irq_lock);
  120. }
  121. static void stmpe_gpio_irq_sync_unlock(unsigned int irq)
  122. {
  123. struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
  124. struct stmpe *stmpe = stmpe_gpio->stmpe;
  125. int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
  126. static const u8 regmap[] = {
  127. [REG_RE] = STMPE_IDX_GPRER_LSB,
  128. [REG_FE] = STMPE_IDX_GPFER_LSB,
  129. [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
  130. };
  131. int i, j;
  132. for (i = 0; i < CACHE_NR_REGS; i++) {
  133. for (j = 0; j < num_banks; j++) {
  134. u8 old = stmpe_gpio->oldregs[i][j];
  135. u8 new = stmpe_gpio->regs[i][j];
  136. if (new == old)
  137. continue;
  138. stmpe_gpio->oldregs[i][j] = new;
  139. stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
  140. }
  141. }
  142. mutex_unlock(&stmpe_gpio->irq_lock);
  143. }
  144. static void stmpe_gpio_irq_mask(unsigned int irq)
  145. {
  146. struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
  147. int offset = irq - stmpe_gpio->irq_base;
  148. int regoffset = offset / 8;
  149. int mask = 1 << (offset % 8);
  150. stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
  151. }
  152. static void stmpe_gpio_irq_unmask(unsigned int irq)
  153. {
  154. struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
  155. int offset = irq - stmpe_gpio->irq_base;
  156. int regoffset = offset / 8;
  157. int mask = 1 << (offset % 8);
  158. stmpe_gpio->regs[REG_IE][regoffset] |= mask;
  159. }
  160. static struct irq_chip stmpe_gpio_irq_chip = {
  161. .name = "stmpe-gpio",
  162. .bus_lock = stmpe_gpio_irq_lock,
  163. .bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
  164. .mask = stmpe_gpio_irq_mask,
  165. .unmask = stmpe_gpio_irq_unmask,
  166. .set_type = stmpe_gpio_irq_set_type,
  167. };
  168. static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
  169. {
  170. struct stmpe_gpio *stmpe_gpio = dev;
  171. struct stmpe *stmpe = stmpe_gpio->stmpe;
  172. u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
  173. int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
  174. u8 status[num_banks];
  175. int ret;
  176. int i;
  177. ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
  178. if (ret < 0)
  179. return IRQ_NONE;
  180. for (i = 0; i < num_banks; i++) {
  181. int bank = num_banks - i - 1;
  182. unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
  183. unsigned int stat = status[i];
  184. stat &= enabled;
  185. if (!stat)
  186. continue;
  187. while (stat) {
  188. int bit = __ffs(stat);
  189. int line = bank * 8 + bit;
  190. handle_nested_irq(stmpe_gpio->irq_base + line);
  191. stat &= ~(1 << bit);
  192. }
  193. stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
  194. stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
  195. status[i]);
  196. }
  197. return IRQ_HANDLED;
  198. }
  199. static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
  200. {
  201. int base = stmpe_gpio->irq_base;
  202. int irq;
  203. for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
  204. set_irq_chip_data(irq, stmpe_gpio);
  205. set_irq_chip_and_handler(irq, &stmpe_gpio_irq_chip,
  206. handle_simple_irq);
  207. set_irq_nested_thread(irq, 1);
  208. #ifdef CONFIG_ARM
  209. set_irq_flags(irq, IRQF_VALID);
  210. #else
  211. set_irq_noprobe(irq);
  212. #endif
  213. }
  214. return 0;
  215. }
  216. static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
  217. {
  218. int base = stmpe_gpio->irq_base;
  219. int irq;
  220. for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
  221. #ifdef CONFIG_ARM
  222. set_irq_flags(irq, 0);
  223. #endif
  224. set_irq_chip_and_handler(irq, NULL, NULL);
  225. set_irq_chip_data(irq, NULL);
  226. }
  227. }
  228. static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
  229. {
  230. struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
  231. struct stmpe_gpio_platform_data *pdata;
  232. struct stmpe_gpio *stmpe_gpio;
  233. int ret;
  234. int irq;
  235. pdata = stmpe->pdata->gpio;
  236. if (!pdata)
  237. return -ENODEV;
  238. irq = platform_get_irq(pdev, 0);
  239. if (irq < 0)
  240. return irq;
  241. stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
  242. if (!stmpe_gpio)
  243. return -ENOMEM;
  244. mutex_init(&stmpe_gpio->irq_lock);
  245. stmpe_gpio->dev = &pdev->dev;
  246. stmpe_gpio->stmpe = stmpe;
  247. stmpe_gpio->chip = template_chip;
  248. stmpe_gpio->chip.ngpio = stmpe->num_gpios;
  249. stmpe_gpio->chip.dev = &pdev->dev;
  250. stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
  251. stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
  252. ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
  253. if (ret)
  254. return ret;
  255. ret = stmpe_gpio_irq_init(stmpe_gpio);
  256. if (ret)
  257. goto out_free;
  258. ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
  259. "stmpe-gpio", stmpe_gpio);
  260. if (ret) {
  261. dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
  262. goto out_removeirq;
  263. }
  264. ret = gpiochip_add(&stmpe_gpio->chip);
  265. if (ret) {
  266. dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
  267. goto out_freeirq;
  268. }
  269. if (pdata && pdata->setup)
  270. pdata->setup(stmpe, stmpe_gpio->chip.base);
  271. platform_set_drvdata(pdev, stmpe_gpio);
  272. return 0;
  273. out_freeirq:
  274. free_irq(irq, stmpe_gpio);
  275. out_removeirq:
  276. stmpe_gpio_irq_remove(stmpe_gpio);
  277. out_free:
  278. kfree(stmpe_gpio);
  279. return ret;
  280. }
  281. static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
  282. {
  283. struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
  284. struct stmpe *stmpe = stmpe_gpio->stmpe;
  285. struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
  286. int irq = platform_get_irq(pdev, 0);
  287. int ret;
  288. if (pdata && pdata->remove)
  289. pdata->remove(stmpe, stmpe_gpio->chip.base);
  290. ret = gpiochip_remove(&stmpe_gpio->chip);
  291. if (ret < 0) {
  292. dev_err(stmpe_gpio->dev,
  293. "unable to remove gpiochip: %d\n", ret);
  294. return ret;
  295. }
  296. stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
  297. free_irq(irq, stmpe_gpio);
  298. stmpe_gpio_irq_remove(stmpe_gpio);
  299. platform_set_drvdata(pdev, NULL);
  300. kfree(stmpe_gpio);
  301. return 0;
  302. }
  303. static struct platform_driver stmpe_gpio_driver = {
  304. .driver.name = "stmpe-gpio",
  305. .driver.owner = THIS_MODULE,
  306. .probe = stmpe_gpio_probe,
  307. .remove = __devexit_p(stmpe_gpio_remove),
  308. };
  309. static int __init stmpe_gpio_init(void)
  310. {
  311. return platform_driver_register(&stmpe_gpio_driver);
  312. }
  313. subsys_initcall(stmpe_gpio_init);
  314. static void __exit stmpe_gpio_exit(void)
  315. {
  316. platform_driver_unregister(&stmpe_gpio_driver);
  317. }
  318. module_exit(stmpe_gpio_exit);
  319. MODULE_LICENSE("GPL v2");
  320. MODULE_DESCRIPTION("STMPExxxx GPIO driver");
  321. MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");