setup-sh7720.c 9.9 KB

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  1. /*
  2. * SH7720 Setup
  3. *
  4. * Copyright (C) 2007 Markus Brunner, Mark Jonas
  5. * Copyright (C) 2009 Paul Mundt
  6. *
  7. * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
  8. *
  9. * Copyright (C) 2006 Paul Mundt
  10. * Copyright (C) 2006 Jamie Lenehan
  11. *
  12. * This file is subject to the terms and conditions of the GNU General Public
  13. * License. See the file "COPYING" in the main directory of this archive
  14. * for more details.
  15. */
  16. #include <linux/platform_device.h>
  17. #include <linux/init.h>
  18. #include <linux/serial.h>
  19. #include <linux/io.h>
  20. #include <linux/serial_sci.h>
  21. #include <linux/sh_timer.h>
  22. #include <asm/rtc.h>
  23. static struct resource rtc_resources[] = {
  24. [0] = {
  25. .start = 0xa413fec0,
  26. .end = 0xa413fec0 + 0x28 - 1,
  27. .flags = IORESOURCE_IO,
  28. },
  29. [1] = {
  30. /* Shared Period/Carry/Alarm IRQ */
  31. .start = 20,
  32. .flags = IORESOURCE_IRQ,
  33. },
  34. };
  35. static struct sh_rtc_platform_info rtc_info = {
  36. .capabilities = RTC_CAP_4_DIGIT_YEAR,
  37. };
  38. static struct platform_device rtc_device = {
  39. .name = "sh-rtc",
  40. .id = -1,
  41. .num_resources = ARRAY_SIZE(rtc_resources),
  42. .resource = rtc_resources,
  43. .dev = {
  44. .platform_data = &rtc_info,
  45. },
  46. };
  47. static struct plat_sci_port scif0_platform_data = {
  48. .mapbase = 0xa4430000,
  49. .flags = UPF_BOOT_AUTOCONF,
  50. .type = PORT_SCIF,
  51. .irqs = { 80, 80, 80, 80 },
  52. };
  53. static struct platform_device scif0_device = {
  54. .name = "sh-sci",
  55. .id = 0,
  56. .dev = {
  57. .platform_data = &scif0_platform_data,
  58. },
  59. };
  60. static struct plat_sci_port scif1_platform_data = {
  61. .mapbase = 0xa4438000,
  62. .flags = UPF_BOOT_AUTOCONF,
  63. .type = PORT_SCIF,
  64. .irqs = { 81, 81, 81, 81 },
  65. };
  66. static struct platform_device scif1_device = {
  67. .name = "sh-sci",
  68. .id = 1,
  69. .dev = {
  70. .platform_data = &scif1_platform_data,
  71. },
  72. };
  73. static struct resource usb_ohci_resources[] = {
  74. [0] = {
  75. .start = 0xA4428000,
  76. .end = 0xA44280FF,
  77. .flags = IORESOURCE_MEM,
  78. },
  79. [1] = {
  80. .start = 67,
  81. .end = 67,
  82. .flags = IORESOURCE_IRQ,
  83. },
  84. };
  85. static u64 usb_ohci_dma_mask = 0xffffffffUL;
  86. static struct platform_device usb_ohci_device = {
  87. .name = "sh_ohci",
  88. .id = -1,
  89. .dev = {
  90. .dma_mask = &usb_ohci_dma_mask,
  91. .coherent_dma_mask = 0xffffffff,
  92. },
  93. .num_resources = ARRAY_SIZE(usb_ohci_resources),
  94. .resource = usb_ohci_resources,
  95. };
  96. static struct resource usbf_resources[] = {
  97. [0] = {
  98. .name = "sh_udc",
  99. .start = 0xA4420000,
  100. .end = 0xA44200FF,
  101. .flags = IORESOURCE_MEM,
  102. },
  103. [1] = {
  104. .name = "sh_udc",
  105. .start = 65,
  106. .end = 65,
  107. .flags = IORESOURCE_IRQ,
  108. },
  109. };
  110. static struct platform_device usbf_device = {
  111. .name = "sh_udc",
  112. .id = -1,
  113. .dev = {
  114. .dma_mask = NULL,
  115. .coherent_dma_mask = 0xffffffff,
  116. },
  117. .num_resources = ARRAY_SIZE(usbf_resources),
  118. .resource = usbf_resources,
  119. };
  120. static struct sh_timer_config cmt0_platform_data = {
  121. .channel_offset = 0x10,
  122. .timer_bit = 0,
  123. .clockevent_rating = 125,
  124. .clocksource_rating = 125,
  125. };
  126. static struct resource cmt0_resources[] = {
  127. [0] = {
  128. .start = 0x044a0010,
  129. .end = 0x044a001b,
  130. .flags = IORESOURCE_MEM,
  131. },
  132. [1] = {
  133. .start = 104,
  134. .flags = IORESOURCE_IRQ,
  135. },
  136. };
  137. static struct platform_device cmt0_device = {
  138. .name = "sh_cmt",
  139. .id = 0,
  140. .dev = {
  141. .platform_data = &cmt0_platform_data,
  142. },
  143. .resource = cmt0_resources,
  144. .num_resources = ARRAY_SIZE(cmt0_resources),
  145. };
  146. static struct sh_timer_config cmt1_platform_data = {
  147. .channel_offset = 0x20,
  148. .timer_bit = 1,
  149. };
  150. static struct resource cmt1_resources[] = {
  151. [0] = {
  152. .start = 0x044a0020,
  153. .end = 0x044a002b,
  154. .flags = IORESOURCE_MEM,
  155. },
  156. [1] = {
  157. .start = 104,
  158. .flags = IORESOURCE_IRQ,
  159. },
  160. };
  161. static struct platform_device cmt1_device = {
  162. .name = "sh_cmt",
  163. .id = 1,
  164. .dev = {
  165. .platform_data = &cmt1_platform_data,
  166. },
  167. .resource = cmt1_resources,
  168. .num_resources = ARRAY_SIZE(cmt1_resources),
  169. };
  170. static struct sh_timer_config cmt2_platform_data = {
  171. .channel_offset = 0x30,
  172. .timer_bit = 2,
  173. };
  174. static struct resource cmt2_resources[] = {
  175. [0] = {
  176. .start = 0x044a0030,
  177. .end = 0x044a003b,
  178. .flags = IORESOURCE_MEM,
  179. },
  180. [1] = {
  181. .start = 104,
  182. .flags = IORESOURCE_IRQ,
  183. },
  184. };
  185. static struct platform_device cmt2_device = {
  186. .name = "sh_cmt",
  187. .id = 2,
  188. .dev = {
  189. .platform_data = &cmt2_platform_data,
  190. },
  191. .resource = cmt2_resources,
  192. .num_resources = ARRAY_SIZE(cmt2_resources),
  193. };
  194. static struct sh_timer_config cmt3_platform_data = {
  195. .channel_offset = 0x40,
  196. .timer_bit = 3,
  197. };
  198. static struct resource cmt3_resources[] = {
  199. [0] = {
  200. .start = 0x044a0040,
  201. .end = 0x044a004b,
  202. .flags = IORESOURCE_MEM,
  203. },
  204. [1] = {
  205. .start = 104,
  206. .flags = IORESOURCE_IRQ,
  207. },
  208. };
  209. static struct platform_device cmt3_device = {
  210. .name = "sh_cmt",
  211. .id = 3,
  212. .dev = {
  213. .platform_data = &cmt3_platform_data,
  214. },
  215. .resource = cmt3_resources,
  216. .num_resources = ARRAY_SIZE(cmt3_resources),
  217. };
  218. static struct sh_timer_config cmt4_platform_data = {
  219. .channel_offset = 0x50,
  220. .timer_bit = 4,
  221. };
  222. static struct resource cmt4_resources[] = {
  223. [0] = {
  224. .start = 0x044a0050,
  225. .end = 0x044a005b,
  226. .flags = IORESOURCE_MEM,
  227. },
  228. [1] = {
  229. .start = 104,
  230. .flags = IORESOURCE_IRQ,
  231. },
  232. };
  233. static struct platform_device cmt4_device = {
  234. .name = "sh_cmt",
  235. .id = 4,
  236. .dev = {
  237. .platform_data = &cmt4_platform_data,
  238. },
  239. .resource = cmt4_resources,
  240. .num_resources = ARRAY_SIZE(cmt4_resources),
  241. };
  242. static struct sh_timer_config tmu0_platform_data = {
  243. .channel_offset = 0x02,
  244. .timer_bit = 0,
  245. .clockevent_rating = 200,
  246. };
  247. static struct resource tmu0_resources[] = {
  248. [0] = {
  249. .start = 0xa412fe94,
  250. .end = 0xa412fe9f,
  251. .flags = IORESOURCE_MEM,
  252. },
  253. [1] = {
  254. .start = 16,
  255. .flags = IORESOURCE_IRQ,
  256. },
  257. };
  258. static struct platform_device tmu0_device = {
  259. .name = "sh_tmu",
  260. .id = 0,
  261. .dev = {
  262. .platform_data = &tmu0_platform_data,
  263. },
  264. .resource = tmu0_resources,
  265. .num_resources = ARRAY_SIZE(tmu0_resources),
  266. };
  267. static struct sh_timer_config tmu1_platform_data = {
  268. .channel_offset = 0xe,
  269. .timer_bit = 1,
  270. .clocksource_rating = 200,
  271. };
  272. static struct resource tmu1_resources[] = {
  273. [0] = {
  274. .start = 0xa412fea0,
  275. .end = 0xa412feab,
  276. .flags = IORESOURCE_MEM,
  277. },
  278. [1] = {
  279. .start = 17,
  280. .flags = IORESOURCE_IRQ,
  281. },
  282. };
  283. static struct platform_device tmu1_device = {
  284. .name = "sh_tmu",
  285. .id = 1,
  286. .dev = {
  287. .platform_data = &tmu1_platform_data,
  288. },
  289. .resource = tmu1_resources,
  290. .num_resources = ARRAY_SIZE(tmu1_resources),
  291. };
  292. static struct sh_timer_config tmu2_platform_data = {
  293. .channel_offset = 0x1a,
  294. .timer_bit = 2,
  295. };
  296. static struct resource tmu2_resources[] = {
  297. [0] = {
  298. .start = 0xa412feac,
  299. .end = 0xa412feb5,
  300. .flags = IORESOURCE_MEM,
  301. },
  302. [1] = {
  303. .start = 18,
  304. .flags = IORESOURCE_IRQ,
  305. },
  306. };
  307. static struct platform_device tmu2_device = {
  308. .name = "sh_tmu",
  309. .id = 2,
  310. .dev = {
  311. .platform_data = &tmu2_platform_data,
  312. },
  313. .resource = tmu2_resources,
  314. .num_resources = ARRAY_SIZE(tmu2_resources),
  315. };
  316. static struct platform_device *sh7720_devices[] __initdata = {
  317. &scif0_device,
  318. &scif1_device,
  319. &cmt0_device,
  320. &cmt1_device,
  321. &cmt2_device,
  322. &cmt3_device,
  323. &cmt4_device,
  324. &tmu0_device,
  325. &tmu1_device,
  326. &tmu2_device,
  327. &rtc_device,
  328. &usb_ohci_device,
  329. &usbf_device,
  330. };
  331. static int __init sh7720_devices_setup(void)
  332. {
  333. return platform_add_devices(sh7720_devices,
  334. ARRAY_SIZE(sh7720_devices));
  335. }
  336. arch_initcall(sh7720_devices_setup);
  337. static struct platform_device *sh7720_early_devices[] __initdata = {
  338. &scif0_device,
  339. &scif1_device,
  340. &cmt0_device,
  341. &cmt1_device,
  342. &cmt2_device,
  343. &cmt3_device,
  344. &cmt4_device,
  345. &tmu0_device,
  346. &tmu1_device,
  347. &tmu2_device,
  348. };
  349. void __init plat_early_device_setup(void)
  350. {
  351. early_platform_add_devices(sh7720_early_devices,
  352. ARRAY_SIZE(sh7720_early_devices));
  353. }
  354. enum {
  355. UNUSED = 0,
  356. /* interrupt sources */
  357. TMU0, TMU1, TMU2, RTC,
  358. WDT, REF_RCMI, SIM,
  359. IRQ0, IRQ1, IRQ2, IRQ3,
  360. USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
  361. DMAC1, LCDC, SSL,
  362. ADC, DMAC2, USBFI, CMT,
  363. SCIF0, SCIF1,
  364. PINT07, PINT815, TPU, IIC,
  365. SIOF0, SIOF1, MMC, PCC,
  366. USBHI, AFEIF,
  367. H_UDI,
  368. };
  369. static struct intc_vect vectors[] __initdata = {
  370. /* IRQ0->5 are handled in setup-sh3.c */
  371. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  372. INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),
  373. INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0),
  374. INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500),
  375. INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540),
  376. INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
  377. /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
  378. INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800),
  379. INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840),
  380. INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
  381. #if defined(CONFIG_CPU_SUBTYPE_SH7720)
  382. INTC_VECT(SSL, 0x980),
  383. #endif
  384. INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40),
  385. INTC_VECT(USBHI, 0xa60),
  386. INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
  387. INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
  388. INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
  389. INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
  390. INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80),
  391. INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0),
  392. INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00),
  393. INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0),
  394. INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0),
  395. INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
  396. INTC_VECT(AFEIF, 0xfe0),
  397. };
  398. static struct intc_prio_reg prio_registers[] __initdata = {
  399. { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  400. { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
  401. { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
  402. { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
  403. { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
  404. { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
  405. { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
  406. { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
  407. { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
  408. { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
  409. };
  410. static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
  411. NULL, prio_registers, NULL);
  412. void __init plat_irq_setup(void)
  413. {
  414. register_intc_controller(&intc_desc);
  415. plat_irq_setup_sh3();
  416. }