board-sh7785lcr.c 8.3 KB

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  1. /*
  2. * Renesas Technology Corp. R0P7785LC0011RL Support.
  3. *
  4. * Copyright (C) 2008 Yoshihiro Shimoda
  5. * Copyright (C) 2009 Paul Mundt
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/sm501.h>
  14. #include <linux/sm501-regs.h>
  15. #include <linux/fb.h>
  16. #include <linux/mtd/physmap.h>
  17. #include <linux/delay.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/i2c.h>
  20. #include <linux/i2c-pca-platform.h>
  21. #include <linux/i2c-algo-pca.h>
  22. #include <linux/usb/r8a66597.h>
  23. #include <linux/irq.h>
  24. #include <linux/io.h>
  25. #include <linux/clk.h>
  26. #include <linux/errno.h>
  27. #include <mach/sh7785lcr.h>
  28. #include <cpu/sh7785.h>
  29. #include <asm/heartbeat.h>
  30. #include <asm/clock.h>
  31. /*
  32. * NOTE: This board has 2 physical memory maps.
  33. * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
  34. */
  35. static struct resource heartbeat_resource = {
  36. .start = PLD_LEDCR,
  37. .end = PLD_LEDCR,
  38. .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
  39. };
  40. static struct platform_device heartbeat_device = {
  41. .name = "heartbeat",
  42. .id = -1,
  43. .num_resources = 1,
  44. .resource = &heartbeat_resource,
  45. };
  46. static struct mtd_partition nor_flash_partitions[] = {
  47. {
  48. .name = "loader",
  49. .offset = 0x00000000,
  50. .size = 512 * 1024,
  51. },
  52. {
  53. .name = "bootenv",
  54. .offset = MTDPART_OFS_APPEND,
  55. .size = 512 * 1024,
  56. },
  57. {
  58. .name = "kernel",
  59. .offset = MTDPART_OFS_APPEND,
  60. .size = 4 * 1024 * 1024,
  61. },
  62. {
  63. .name = "data",
  64. .offset = MTDPART_OFS_APPEND,
  65. .size = MTDPART_SIZ_FULL,
  66. },
  67. };
  68. static struct physmap_flash_data nor_flash_data = {
  69. .width = 4,
  70. .parts = nor_flash_partitions,
  71. .nr_parts = ARRAY_SIZE(nor_flash_partitions),
  72. };
  73. static struct resource nor_flash_resources[] = {
  74. [0] = {
  75. .start = NOR_FLASH_ADDR,
  76. .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
  77. .flags = IORESOURCE_MEM,
  78. }
  79. };
  80. static struct platform_device nor_flash_device = {
  81. .name = "physmap-flash",
  82. .dev = {
  83. .platform_data = &nor_flash_data,
  84. },
  85. .num_resources = ARRAY_SIZE(nor_flash_resources),
  86. .resource = nor_flash_resources,
  87. };
  88. static struct r8a66597_platdata r8a66597_data = {
  89. .xtal = R8A66597_PLATDATA_XTAL_12MHZ,
  90. .vif = 1,
  91. };
  92. static struct resource r8a66597_usb_host_resources[] = {
  93. [0] = {
  94. .start = R8A66597_ADDR,
  95. .end = R8A66597_ADDR + R8A66597_SIZE - 1,
  96. .flags = IORESOURCE_MEM,
  97. },
  98. [1] = {
  99. .start = 2,
  100. .end = 2,
  101. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  102. },
  103. };
  104. static struct platform_device r8a66597_usb_host_device = {
  105. .name = "r8a66597_hcd",
  106. .id = -1,
  107. .dev = {
  108. .dma_mask = NULL,
  109. .coherent_dma_mask = 0xffffffff,
  110. .platform_data = &r8a66597_data,
  111. },
  112. .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
  113. .resource = r8a66597_usb_host_resources,
  114. };
  115. static struct resource sm501_resources[] = {
  116. [0] = {
  117. .start = SM107_MEM_ADDR,
  118. .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
  119. .flags = IORESOURCE_MEM,
  120. },
  121. [1] = {
  122. .start = SM107_REG_ADDR,
  123. .end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. [2] = {
  127. .start = 10,
  128. .flags = IORESOURCE_IRQ,
  129. },
  130. };
  131. static struct fb_videomode sm501_default_mode_crt = {
  132. .pixclock = 35714, /* 28MHz */
  133. .xres = 640,
  134. .yres = 480,
  135. .left_margin = 105,
  136. .right_margin = 16,
  137. .upper_margin = 33,
  138. .lower_margin = 10,
  139. .hsync_len = 39,
  140. .vsync_len = 2,
  141. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  142. };
  143. static struct fb_videomode sm501_default_mode_pnl = {
  144. .pixclock = 40000, /* 25MHz */
  145. .xres = 640,
  146. .yres = 480,
  147. .left_margin = 2,
  148. .right_margin = 16,
  149. .upper_margin = 33,
  150. .lower_margin = 10,
  151. .hsync_len = 39,
  152. .vsync_len = 2,
  153. .sync = 0,
  154. };
  155. static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
  156. .def_bpp = 16,
  157. .def_mode = &sm501_default_mode_pnl,
  158. .flags = SM501FB_FLAG_USE_INIT_MODE |
  159. SM501FB_FLAG_USE_HWCURSOR |
  160. SM501FB_FLAG_USE_HWACCEL |
  161. SM501FB_FLAG_DISABLE_AT_EXIT |
  162. SM501FB_FLAG_PANEL_NO_VBIASEN,
  163. };
  164. static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
  165. .def_bpp = 16,
  166. .def_mode = &sm501_default_mode_crt,
  167. .flags = SM501FB_FLAG_USE_INIT_MODE |
  168. SM501FB_FLAG_USE_HWCURSOR |
  169. SM501FB_FLAG_USE_HWACCEL |
  170. SM501FB_FLAG_DISABLE_AT_EXIT,
  171. };
  172. static struct sm501_platdata_fb sm501_fb_pdata = {
  173. .fb_route = SM501_FB_OWN,
  174. .fb_crt = &sm501_pdata_fbsub_crt,
  175. .fb_pnl = &sm501_pdata_fbsub_pnl,
  176. };
  177. static struct sm501_initdata sm501_initdata = {
  178. .gpio_high = {
  179. .set = 0x00001fe0,
  180. .mask = 0x0,
  181. },
  182. .devices = 0,
  183. .mclk = 84 * 1000000,
  184. .m1xclk = 112 * 1000000,
  185. };
  186. static struct sm501_platdata sm501_platform_data = {
  187. .init = &sm501_initdata,
  188. .fb = &sm501_fb_pdata,
  189. };
  190. static struct platform_device sm501_device = {
  191. .name = "sm501",
  192. .id = -1,
  193. .dev = {
  194. .platform_data = &sm501_platform_data,
  195. },
  196. .num_resources = ARRAY_SIZE(sm501_resources),
  197. .resource = sm501_resources,
  198. };
  199. static struct resource i2c_proto_resources[] = {
  200. [0] = {
  201. .start = PCA9564_PROTO_32BIT_ADDR,
  202. .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
  203. .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
  204. },
  205. [1] = {
  206. .start = 12,
  207. .end = 12,
  208. .flags = IORESOURCE_IRQ,
  209. },
  210. };
  211. static struct resource i2c_resources[] = {
  212. [0] = {
  213. .start = PCA9564_ADDR,
  214. .end = PCA9564_ADDR + PCA9564_SIZE - 1,
  215. .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
  216. },
  217. [1] = {
  218. .start = 12,
  219. .end = 12,
  220. .flags = IORESOURCE_IRQ,
  221. },
  222. };
  223. static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
  224. .gpio = 0,
  225. .i2c_clock_speed = I2C_PCA_CON_330kHz,
  226. .timeout = HZ,
  227. };
  228. static struct platform_device i2c_device = {
  229. .name = "i2c-pca-platform",
  230. .id = -1,
  231. .dev = {
  232. .platform_data = &i2c_platform_data,
  233. },
  234. .num_resources = ARRAY_SIZE(i2c_resources),
  235. .resource = i2c_resources,
  236. };
  237. static struct platform_device *sh7785lcr_devices[] __initdata = {
  238. &heartbeat_device,
  239. &nor_flash_device,
  240. &r8a66597_usb_host_device,
  241. &sm501_device,
  242. &i2c_device,
  243. };
  244. static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
  245. {
  246. I2C_BOARD_INFO("r2025sd", 0x32),
  247. },
  248. };
  249. static int __init sh7785lcr_devices_setup(void)
  250. {
  251. i2c_register_board_info(0, sh7785lcr_i2c_devices,
  252. ARRAY_SIZE(sh7785lcr_i2c_devices));
  253. if (mach_is_sh7785lcr_pt()) {
  254. i2c_device.resource = i2c_proto_resources;
  255. i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
  256. }
  257. return platform_add_devices(sh7785lcr_devices,
  258. ARRAY_SIZE(sh7785lcr_devices));
  259. }
  260. __initcall(sh7785lcr_devices_setup);
  261. /* Initialize IRQ setting */
  262. void __init init_sh7785lcr_IRQ(void)
  263. {
  264. plat_irq_setup_pins(IRQ_MODE_IRQ7654);
  265. plat_irq_setup_pins(IRQ_MODE_IRQ3210);
  266. }
  267. static int sh7785lcr_clk_init(void)
  268. {
  269. struct clk *clk;
  270. int ret;
  271. clk = clk_get(NULL, "extal");
  272. if (!clk || IS_ERR(clk))
  273. return PTR_ERR(clk);
  274. ret = clk_set_rate(clk, 33333333);
  275. clk_put(clk);
  276. return ret;
  277. }
  278. static void sh7785lcr_power_off(void)
  279. {
  280. unsigned char *p;
  281. p = ioremap(PLD_POFCR, PLD_POFCR + 1);
  282. if (!p) {
  283. printk(KERN_ERR "%s: ioremap error.\n", __func__);
  284. return;
  285. }
  286. *p = 0x01;
  287. iounmap(p);
  288. set_bl_bit();
  289. while (1)
  290. cpu_relax();
  291. }
  292. /* Initialize the board */
  293. static void __init sh7785lcr_setup(char **cmdline_p)
  294. {
  295. void __iomem *sm501_reg;
  296. printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
  297. pm_power_off = sh7785lcr_power_off;
  298. /* sm501 DRAM configuration */
  299. sm501_reg = ioremap_nocache(SM107_REG_ADDR, SM501_DRAM_CONTROL);
  300. if (!sm501_reg) {
  301. printk(KERN_ERR "%s: ioremap error.\n", __func__);
  302. return;
  303. }
  304. writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
  305. iounmap(sm501_reg);
  306. }
  307. /* Return the board specific boot mode pin configuration */
  308. static int sh7785lcr_mode_pins(void)
  309. {
  310. int value = 0;
  311. /* These are the factory default settings of S1 and S2.
  312. * If you change these dip switches then you will need to
  313. * adjust the values below as well.
  314. */
  315. value |= MODE_PIN4; /* Clock Mode 16 */
  316. value |= MODE_PIN5; /* 32-bit Area0 bus width */
  317. value |= MODE_PIN6; /* 32-bit Area0 bus width */
  318. value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
  319. value |= MODE_PIN8; /* Little Endian */
  320. value |= MODE_PIN9; /* Master Mode */
  321. value |= MODE_PIN14; /* No PLL step-up */
  322. return value;
  323. }
  324. /*
  325. * The Machine Vector
  326. */
  327. static struct sh_machine_vector mv_sh7785lcr __initmv = {
  328. .mv_name = "SH7785LCR",
  329. .mv_setup = sh7785lcr_setup,
  330. .mv_clk_init = sh7785lcr_clk_init,
  331. .mv_init_irq = init_sh7785lcr_IRQ,
  332. .mv_mode_pins = sh7785lcr_mode_pins,
  333. };