hlwd-pic.c 5.2 KB

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  1. /*
  2. * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
  3. *
  4. * Nintendo Wii "Hollywood" interrupt controller support.
  5. * Copyright (C) 2009 The GameCube Linux Team
  6. * Copyright (C) 2009 Albert Herranz
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. *
  13. */
  14. #define DRV_MODULE_NAME "hlwd-pic"
  15. #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/irq.h>
  19. #include <linux/of.h>
  20. #include <asm/io.h>
  21. #include "hlwd-pic.h"
  22. #define HLWD_NR_IRQS 32
  23. /*
  24. * Each interrupt has a corresponding bit in both
  25. * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
  26. *
  27. * Enabling/disabling an interrupt line involves asserting/clearing
  28. * the corresponding bit in IMR. ACK'ing a request simply involves
  29. * asserting the corresponding bit in ICR.
  30. */
  31. #define HW_BROADWAY_ICR 0x00
  32. #define HW_BROADWAY_IMR 0x04
  33. /*
  34. * IRQ chip hooks.
  35. *
  36. */
  37. static void hlwd_pic_mask_and_ack(unsigned int virq)
  38. {
  39. int irq = virq_to_hw(virq);
  40. void __iomem *io_base = get_irq_chip_data(virq);
  41. u32 mask = 1 << irq;
  42. clrbits32(io_base + HW_BROADWAY_IMR, mask);
  43. out_be32(io_base + HW_BROADWAY_ICR, mask);
  44. }
  45. static void hlwd_pic_ack(unsigned int virq)
  46. {
  47. int irq = virq_to_hw(virq);
  48. void __iomem *io_base = get_irq_chip_data(virq);
  49. out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
  50. }
  51. static void hlwd_pic_mask(unsigned int virq)
  52. {
  53. int irq = virq_to_hw(virq);
  54. void __iomem *io_base = get_irq_chip_data(virq);
  55. clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
  56. }
  57. static void hlwd_pic_unmask(unsigned int virq)
  58. {
  59. int irq = virq_to_hw(virq);
  60. void __iomem *io_base = get_irq_chip_data(virq);
  61. setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
  62. }
  63. static struct irq_chip hlwd_pic = {
  64. .name = "hlwd-pic",
  65. .ack = hlwd_pic_ack,
  66. .mask_ack = hlwd_pic_mask_and_ack,
  67. .mask = hlwd_pic_mask,
  68. .unmask = hlwd_pic_unmask,
  69. };
  70. /*
  71. * IRQ host hooks.
  72. *
  73. */
  74. static struct irq_host *hlwd_irq_host;
  75. static int hlwd_pic_map(struct irq_host *h, unsigned int virq,
  76. irq_hw_number_t hwirq)
  77. {
  78. set_irq_chip_data(virq, h->host_data);
  79. irq_to_desc(virq)->status |= IRQ_LEVEL;
  80. set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
  81. return 0;
  82. }
  83. static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq)
  84. {
  85. set_irq_chip_data(irq, NULL);
  86. set_irq_chip(irq, NULL);
  87. }
  88. static struct irq_host_ops hlwd_irq_host_ops = {
  89. .map = hlwd_pic_map,
  90. .unmap = hlwd_pic_unmap,
  91. };
  92. static unsigned int __hlwd_pic_get_irq(struct irq_host *h)
  93. {
  94. void __iomem *io_base = h->host_data;
  95. int irq;
  96. u32 irq_status;
  97. irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
  98. in_be32(io_base + HW_BROADWAY_IMR);
  99. if (irq_status == 0)
  100. return NO_IRQ; /* no more IRQs pending */
  101. irq = __ffs(irq_status);
  102. return irq_linear_revmap(h, irq);
  103. }
  104. static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
  105. struct irq_desc *desc)
  106. {
  107. struct irq_host *irq_host = get_irq_data(cascade_virq);
  108. unsigned int virq;
  109. raw_spin_lock(&desc->lock);
  110. desc->chip->mask(cascade_virq); /* IRQ_LEVEL */
  111. raw_spin_unlock(&desc->lock);
  112. virq = __hlwd_pic_get_irq(irq_host);
  113. if (virq != NO_IRQ)
  114. generic_handle_irq(virq);
  115. else
  116. pr_err("spurious interrupt!\n");
  117. raw_spin_lock(&desc->lock);
  118. desc->chip->ack(cascade_virq); /* IRQ_LEVEL */
  119. if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
  120. desc->chip->unmask(cascade_virq);
  121. raw_spin_unlock(&desc->lock);
  122. }
  123. /*
  124. * Platform hooks.
  125. *
  126. */
  127. static void __hlwd_quiesce(void __iomem *io_base)
  128. {
  129. /* mask and ack all IRQs */
  130. out_be32(io_base + HW_BROADWAY_IMR, 0);
  131. out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
  132. }
  133. struct irq_host *hlwd_pic_init(struct device_node *np)
  134. {
  135. struct irq_host *irq_host;
  136. struct resource res;
  137. void __iomem *io_base;
  138. int retval;
  139. retval = of_address_to_resource(np, 0, &res);
  140. if (retval) {
  141. pr_err("no io memory range found\n");
  142. return NULL;
  143. }
  144. io_base = ioremap(res.start, resource_size(&res));
  145. if (!io_base) {
  146. pr_err("ioremap failed\n");
  147. return NULL;
  148. }
  149. pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
  150. __hlwd_quiesce(io_base);
  151. irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, HLWD_NR_IRQS,
  152. &hlwd_irq_host_ops, -1);
  153. if (!irq_host) {
  154. pr_err("failed to allocate irq_host\n");
  155. return NULL;
  156. }
  157. irq_host->host_data = io_base;
  158. return irq_host;
  159. }
  160. unsigned int hlwd_pic_get_irq(void)
  161. {
  162. return __hlwd_pic_get_irq(hlwd_irq_host);
  163. }
  164. /*
  165. * Probe function.
  166. *
  167. */
  168. void hlwd_pic_probe(void)
  169. {
  170. struct irq_host *host;
  171. struct device_node *np;
  172. const u32 *interrupts;
  173. int cascade_virq;
  174. for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
  175. interrupts = of_get_property(np, "interrupts", NULL);
  176. if (interrupts) {
  177. host = hlwd_pic_init(np);
  178. BUG_ON(!host);
  179. cascade_virq = irq_of_parse_and_map(np, 0);
  180. set_irq_data(cascade_virq, host);
  181. set_irq_chained_handler(cascade_virq,
  182. hlwd_pic_irq_cascade);
  183. hlwd_irq_host = host;
  184. break;
  185. }
  186. }
  187. }
  188. /**
  189. * hlwd_quiesce() - quiesce hollywood irq controller
  190. *
  191. * Mask and ack all interrupt sources.
  192. *
  193. */
  194. void hlwd_quiesce(void)
  195. {
  196. void __iomem *io_base = hlwd_irq_host->host_data;
  197. __hlwd_quiesce(io_base);
  198. }