db1200.h 2.5 KB

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  1. /*
  2. * AMD Alchemy DBAu1200 Reference Board
  3. * Board register defines.
  4. *
  5. * ########################################################################
  6. *
  7. * This program is free software; you can distribute it and/or modify it
  8. * under the terms of the GNU General Public License (Version 2) as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14. * for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19. *
  20. * ########################################################################
  21. *
  22. *
  23. */
  24. #ifndef __ASM_DB1200_H
  25. #define __ASM_DB1200_H
  26. #include <linux/types.h>
  27. #include <asm/mach-au1x00/au1000.h>
  28. #include <asm/mach-au1x00/au1xxx_psc.h>
  29. /* Bit positions for the different interrupt sources */
  30. #define BCSR_INT_IDE 0x0001
  31. #define BCSR_INT_ETH 0x0002
  32. #define BCSR_INT_PC0 0x0004
  33. #define BCSR_INT_PC0STSCHG 0x0008
  34. #define BCSR_INT_PC1 0x0010
  35. #define BCSR_INT_PC1STSCHG 0x0020
  36. #define BCSR_INT_DC 0x0040
  37. #define BCSR_INT_FLASHBUSY 0x0080
  38. #define BCSR_INT_PC0INSERT 0x0100
  39. #define BCSR_INT_PC0EJECT 0x0200
  40. #define BCSR_INT_PC1INSERT 0x0400
  41. #define BCSR_INT_PC1EJECT 0x0800
  42. #define BCSR_INT_SD0INSERT 0x1000
  43. #define BCSR_INT_SD0EJECT 0x2000
  44. #define IDE_PHYS_ADDR 0x18800000
  45. #define IDE_REG_SHIFT 5
  46. #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
  47. #define IDE_RQSIZE 128
  48. #define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR
  49. #define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
  50. #define DB1200_ETH_PHYS_ADDR 0x19000300
  51. #define DB1200_NAND_PHYS_ADDR 0x20000000
  52. /*
  53. * External Interrupts for DBAu1200 as of 8/6/2004.
  54. * Bit positions in the CPLD registers can be calculated by taking
  55. * the interrupt define and subtracting the DB1200_INT_BEGIN value.
  56. *
  57. * Example: IDE bis pos is = 64 - 64
  58. * ETH bit pos is = 65 - 64
  59. */
  60. enum external_db1200_ints {
  61. DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
  62. DB1200_IDE_INT = DB1200_INT_BEGIN,
  63. DB1200_ETH_INT,
  64. DB1200_PC0_INT,
  65. DB1200_PC0_STSCHG_INT,
  66. DB1200_PC1_INT,
  67. DB1200_PC1_STSCHG_INT,
  68. DB1200_DC_INT,
  69. DB1200_FLASHBUSY_INT,
  70. DB1200_PC0_INSERT_INT,
  71. DB1200_PC0_EJECT_INT,
  72. DB1200_PC1_INSERT_INT,
  73. DB1200_PC1_EJECT_INT,
  74. DB1200_SD0_INSERT_INT,
  75. DB1200_SD0_EJECT_INT,
  76. DB1200_INT_END = DB1200_INT_BEGIN + 15,
  77. };
  78. #endif /* __ASM_DB1200_H */