display.h 16 KB

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  1. /*
  2. * linux/include/asm-arm/arch-omap/display.h
  3. *
  4. * Copyright (C) 2008 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef __ASM_ARCH_OMAP_DISPLAY_H
  20. #define __ASM_ARCH_OMAP_DISPLAY_H
  21. #include <linux/list.h>
  22. #include <linux/kobject.h>
  23. #include <linux/device.h>
  24. #include <asm/atomic.h>
  25. #define DISPC_IRQ_FRAMEDONE (1 << 0)
  26. #define DISPC_IRQ_VSYNC (1 << 1)
  27. #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
  28. #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
  29. #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
  30. #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
  31. #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
  32. #define DISPC_IRQ_GFX_END_WIN (1 << 7)
  33. #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
  34. #define DISPC_IRQ_OCP_ERR (1 << 9)
  35. #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
  36. #define DISPC_IRQ_VID1_END_WIN (1 << 11)
  37. #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
  38. #define DISPC_IRQ_VID2_END_WIN (1 << 13)
  39. #define DISPC_IRQ_SYNC_LOST (1 << 14)
  40. #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
  41. #define DISPC_IRQ_WAKEUP (1 << 16)
  42. struct omap_dss_device;
  43. struct omap_overlay_manager;
  44. enum omap_display_type {
  45. OMAP_DISPLAY_TYPE_NONE = 0,
  46. OMAP_DISPLAY_TYPE_DPI = 1 << 0,
  47. OMAP_DISPLAY_TYPE_DBI = 1 << 1,
  48. OMAP_DISPLAY_TYPE_SDI = 1 << 2,
  49. OMAP_DISPLAY_TYPE_DSI = 1 << 3,
  50. OMAP_DISPLAY_TYPE_VENC = 1 << 4,
  51. };
  52. enum omap_plane {
  53. OMAP_DSS_GFX = 0,
  54. OMAP_DSS_VIDEO1 = 1,
  55. OMAP_DSS_VIDEO2 = 2
  56. };
  57. enum omap_channel {
  58. OMAP_DSS_CHANNEL_LCD = 0,
  59. OMAP_DSS_CHANNEL_DIGIT = 1,
  60. };
  61. enum omap_color_mode {
  62. OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
  63. OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
  64. OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
  65. OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
  66. OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
  67. OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
  68. OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
  69. OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
  70. OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
  71. OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
  72. OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
  73. OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
  74. OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
  75. OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
  76. OMAP_DSS_COLOR_GFX_OMAP2 =
  77. OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  78. OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  79. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
  80. OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
  81. OMAP_DSS_COLOR_VID_OMAP2 =
  82. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  83. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
  84. OMAP_DSS_COLOR_UYVY,
  85. OMAP_DSS_COLOR_GFX_OMAP3 =
  86. OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  87. OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  88. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
  89. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  90. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
  91. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
  92. OMAP_DSS_COLOR_VID1_OMAP3 =
  93. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
  94. OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
  95. OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
  96. OMAP_DSS_COLOR_VID2_OMAP3 =
  97. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
  98. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  99. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
  100. OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
  101. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
  102. };
  103. enum omap_lcd_display_type {
  104. OMAP_DSS_LCD_DISPLAY_STN,
  105. OMAP_DSS_LCD_DISPLAY_TFT,
  106. };
  107. enum omap_dss_load_mode {
  108. OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
  109. OMAP_DSS_LOAD_CLUT_ONLY = 1,
  110. OMAP_DSS_LOAD_FRAME_ONLY = 2,
  111. OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
  112. };
  113. enum omap_dss_trans_key_type {
  114. OMAP_DSS_COLOR_KEY_GFX_DST = 0,
  115. OMAP_DSS_COLOR_KEY_VID_SRC = 1,
  116. };
  117. enum omap_rfbi_te_mode {
  118. OMAP_DSS_RFBI_TE_MODE_1 = 1,
  119. OMAP_DSS_RFBI_TE_MODE_2 = 2,
  120. };
  121. enum omap_panel_config {
  122. OMAP_DSS_LCD_IVS = 1<<0,
  123. OMAP_DSS_LCD_IHS = 1<<1,
  124. OMAP_DSS_LCD_IPC = 1<<2,
  125. OMAP_DSS_LCD_IEO = 1<<3,
  126. OMAP_DSS_LCD_RF = 1<<4,
  127. OMAP_DSS_LCD_ONOFF = 1<<5,
  128. OMAP_DSS_LCD_TFT = 1<<20,
  129. };
  130. enum omap_dss_venc_type {
  131. OMAP_DSS_VENC_TYPE_COMPOSITE,
  132. OMAP_DSS_VENC_TYPE_SVIDEO,
  133. };
  134. enum omap_display_caps {
  135. OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
  136. OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
  137. };
  138. enum omap_dss_update_mode {
  139. OMAP_DSS_UPDATE_DISABLED = 0,
  140. OMAP_DSS_UPDATE_AUTO,
  141. OMAP_DSS_UPDATE_MANUAL,
  142. };
  143. enum omap_dss_display_state {
  144. OMAP_DSS_DISPLAY_DISABLED = 0,
  145. OMAP_DSS_DISPLAY_ACTIVE,
  146. OMAP_DSS_DISPLAY_SUSPENDED,
  147. };
  148. /* XXX perhaps this should be removed */
  149. enum omap_dss_overlay_managers {
  150. OMAP_DSS_OVL_MGR_LCD,
  151. OMAP_DSS_OVL_MGR_TV,
  152. };
  153. enum omap_dss_rotation_type {
  154. OMAP_DSS_ROT_DMA = 0,
  155. OMAP_DSS_ROT_VRFB = 1,
  156. };
  157. /* clockwise rotation angle */
  158. enum omap_dss_rotation_angle {
  159. OMAP_DSS_ROT_0 = 0,
  160. OMAP_DSS_ROT_90 = 1,
  161. OMAP_DSS_ROT_180 = 2,
  162. OMAP_DSS_ROT_270 = 3,
  163. };
  164. enum omap_overlay_caps {
  165. OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
  166. OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
  167. };
  168. enum omap_overlay_manager_caps {
  169. OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
  170. };
  171. /* RFBI */
  172. struct rfbi_timings {
  173. int cs_on_time;
  174. int cs_off_time;
  175. int we_on_time;
  176. int we_off_time;
  177. int re_on_time;
  178. int re_off_time;
  179. int we_cycle_time;
  180. int re_cycle_time;
  181. int cs_pulse_width;
  182. int access_time;
  183. int clk_div;
  184. u32 tim[5]; /* set by rfbi_convert_timings() */
  185. int converted;
  186. };
  187. void omap_rfbi_write_command(const void *buf, u32 len);
  188. void omap_rfbi_read_data(void *buf, u32 len);
  189. void omap_rfbi_write_data(const void *buf, u32 len);
  190. void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
  191. u16 x, u16 y,
  192. u16 w, u16 h);
  193. int omap_rfbi_enable_te(bool enable, unsigned line);
  194. int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
  195. unsigned hs_pulse_time, unsigned vs_pulse_time,
  196. int hs_pol_inv, int vs_pol_inv, int extif_div);
  197. /* DSI */
  198. void dsi_bus_lock(void);
  199. void dsi_bus_unlock(void);
  200. int dsi_vc_dcs_write(int channel, u8 *data, int len);
  201. int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
  202. int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
  203. int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
  204. int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
  205. int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
  206. int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2);
  207. int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
  208. int dsi_vc_send_null(int channel);
  209. int dsi_vc_send_bta_sync(int channel);
  210. /* Board specific data */
  211. struct omap_dss_board_info {
  212. int (*get_last_off_on_transaction_id)(struct device *dev);
  213. int num_devices;
  214. struct omap_dss_device **devices;
  215. struct omap_dss_device *default_device;
  216. };
  217. struct omap_video_timings {
  218. /* Unit: pixels */
  219. u16 x_res;
  220. /* Unit: pixels */
  221. u16 y_res;
  222. /* Unit: KHz */
  223. u32 pixel_clock;
  224. /* Unit: pixel clocks */
  225. u16 hsw; /* Horizontal synchronization pulse width */
  226. /* Unit: pixel clocks */
  227. u16 hfp; /* Horizontal front porch */
  228. /* Unit: pixel clocks */
  229. u16 hbp; /* Horizontal back porch */
  230. /* Unit: line clocks */
  231. u16 vsw; /* Vertical synchronization pulse width */
  232. /* Unit: line clocks */
  233. u16 vfp; /* Vertical front porch */
  234. /* Unit: line clocks */
  235. u16 vbp; /* Vertical back porch */
  236. };
  237. #ifdef CONFIG_OMAP2_DSS_VENC
  238. /* Hardcoded timings for tv modes. Venc only uses these to
  239. * identify the mode, and does not actually use the configs
  240. * itself. However, the configs should be something that
  241. * a normal monitor can also show */
  242. extern const struct omap_video_timings omap_dss_pal_timings;
  243. extern const struct omap_video_timings omap_dss_ntsc_timings;
  244. #endif
  245. struct omap_overlay_info {
  246. bool enabled;
  247. u32 paddr;
  248. void __iomem *vaddr;
  249. u16 screen_width;
  250. u16 width;
  251. u16 height;
  252. enum omap_color_mode color_mode;
  253. u8 rotation;
  254. enum omap_dss_rotation_type rotation_type;
  255. bool mirror;
  256. u16 pos_x;
  257. u16 pos_y;
  258. u16 out_width; /* if 0, out_width == width */
  259. u16 out_height; /* if 0, out_height == height */
  260. u8 global_alpha;
  261. };
  262. struct omap_overlay {
  263. struct kobject kobj;
  264. struct list_head list;
  265. /* static fields */
  266. const char *name;
  267. int id;
  268. enum omap_color_mode supported_modes;
  269. enum omap_overlay_caps caps;
  270. /* dynamic fields */
  271. struct omap_overlay_manager *manager;
  272. struct omap_overlay_info info;
  273. /* if true, info has been changed, but not applied() yet */
  274. bool info_dirty;
  275. int (*set_manager)(struct omap_overlay *ovl,
  276. struct omap_overlay_manager *mgr);
  277. int (*unset_manager)(struct omap_overlay *ovl);
  278. int (*set_overlay_info)(struct omap_overlay *ovl,
  279. struct omap_overlay_info *info);
  280. void (*get_overlay_info)(struct omap_overlay *ovl,
  281. struct omap_overlay_info *info);
  282. int (*wait_for_go)(struct omap_overlay *ovl);
  283. };
  284. struct omap_overlay_manager_info {
  285. u32 default_color;
  286. enum omap_dss_trans_key_type trans_key_type;
  287. u32 trans_key;
  288. bool trans_enabled;
  289. bool alpha_enabled;
  290. };
  291. struct omap_overlay_manager {
  292. struct kobject kobj;
  293. struct list_head list;
  294. /* static fields */
  295. const char *name;
  296. int id;
  297. enum omap_overlay_manager_caps caps;
  298. int num_overlays;
  299. struct omap_overlay **overlays;
  300. enum omap_display_type supported_displays;
  301. /* dynamic fields */
  302. struct omap_dss_device *device;
  303. struct omap_overlay_manager_info info;
  304. bool device_changed;
  305. /* if true, info has been changed but not applied() yet */
  306. bool info_dirty;
  307. int (*set_device)(struct omap_overlay_manager *mgr,
  308. struct omap_dss_device *dssdev);
  309. int (*unset_device)(struct omap_overlay_manager *mgr);
  310. int (*set_manager_info)(struct omap_overlay_manager *mgr,
  311. struct omap_overlay_manager_info *info);
  312. void (*get_manager_info)(struct omap_overlay_manager *mgr,
  313. struct omap_overlay_manager_info *info);
  314. int (*apply)(struct omap_overlay_manager *mgr);
  315. int (*wait_for_go)(struct omap_overlay_manager *mgr);
  316. int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
  317. int (*enable)(struct omap_overlay_manager *mgr);
  318. int (*disable)(struct omap_overlay_manager *mgr);
  319. };
  320. struct omap_dss_device {
  321. struct device dev;
  322. enum omap_display_type type;
  323. union {
  324. struct {
  325. u8 data_lines;
  326. } dpi;
  327. struct {
  328. u8 channel;
  329. u8 data_lines;
  330. } rfbi;
  331. struct {
  332. u8 datapairs;
  333. } sdi;
  334. struct {
  335. u8 clk_lane;
  336. u8 clk_pol;
  337. u8 data1_lane;
  338. u8 data1_pol;
  339. u8 data2_lane;
  340. u8 data2_pol;
  341. struct {
  342. u16 regn;
  343. u16 regm;
  344. u16 regm3;
  345. u16 regm4;
  346. u16 lp_clk_div;
  347. u16 lck_div;
  348. u16 pck_div;
  349. } div;
  350. bool ext_te;
  351. u8 ext_te_gpio;
  352. } dsi;
  353. struct {
  354. enum omap_dss_venc_type type;
  355. bool invert_polarity;
  356. } venc;
  357. } phy;
  358. struct {
  359. struct omap_video_timings timings;
  360. int acbi; /* ac-bias pin transitions per interrupt */
  361. /* Unit: line clocks */
  362. int acb; /* ac-bias pin frequency */
  363. enum omap_panel_config config;
  364. } panel;
  365. struct {
  366. u8 pixel_size;
  367. struct rfbi_timings rfbi_timings;
  368. } ctrl;
  369. int reset_gpio;
  370. int max_backlight_level;
  371. const char *name;
  372. /* used to match device to driver */
  373. const char *driver_name;
  374. void *data;
  375. struct omap_dss_driver *driver;
  376. /* helper variable for driver suspend/resume */
  377. bool activate_after_resume;
  378. enum omap_display_caps caps;
  379. struct omap_overlay_manager *manager;
  380. enum omap_dss_display_state state;
  381. /* platform specific */
  382. int (*platform_enable)(struct omap_dss_device *dssdev);
  383. void (*platform_disable)(struct omap_dss_device *dssdev);
  384. int (*set_backlight)(struct omap_dss_device *dssdev, int level);
  385. int (*get_backlight)(struct omap_dss_device *dssdev);
  386. };
  387. struct omap_dss_driver {
  388. struct device_driver driver;
  389. int (*probe)(struct omap_dss_device *);
  390. void (*remove)(struct omap_dss_device *);
  391. int (*enable)(struct omap_dss_device *display);
  392. void (*disable)(struct omap_dss_device *display);
  393. int (*suspend)(struct omap_dss_device *display);
  394. int (*resume)(struct omap_dss_device *display);
  395. int (*run_test)(struct omap_dss_device *display, int test);
  396. int (*set_update_mode)(struct omap_dss_device *dssdev,
  397. enum omap_dss_update_mode);
  398. enum omap_dss_update_mode (*get_update_mode)(
  399. struct omap_dss_device *dssdev);
  400. int (*update)(struct omap_dss_device *dssdev,
  401. u16 x, u16 y, u16 w, u16 h);
  402. int (*sync)(struct omap_dss_device *dssdev);
  403. int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
  404. int (*get_te)(struct omap_dss_device *dssdev);
  405. u8 (*get_rotate)(struct omap_dss_device *dssdev);
  406. int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
  407. bool (*get_mirror)(struct omap_dss_device *dssdev);
  408. int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
  409. int (*memory_read)(struct omap_dss_device *dssdev,
  410. void *buf, size_t size,
  411. u16 x, u16 y, u16 w, u16 h);
  412. void (*get_resolution)(struct omap_dss_device *dssdev,
  413. u16 *xres, u16 *yres);
  414. int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
  415. int (*check_timings)(struct omap_dss_device *dssdev,
  416. struct omap_video_timings *timings);
  417. void (*set_timings)(struct omap_dss_device *dssdev,
  418. struct omap_video_timings *timings);
  419. void (*get_timings)(struct omap_dss_device *dssdev,
  420. struct omap_video_timings *timings);
  421. int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
  422. u32 (*get_wss)(struct omap_dss_device *dssdev);
  423. };
  424. int omap_dss_register_driver(struct omap_dss_driver *);
  425. void omap_dss_unregister_driver(struct omap_dss_driver *);
  426. int omap_dss_register_device(struct omap_dss_device *);
  427. void omap_dss_unregister_device(struct omap_dss_device *);
  428. void omap_dss_get_device(struct omap_dss_device *dssdev);
  429. void omap_dss_put_device(struct omap_dss_device *dssdev);
  430. #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
  431. struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
  432. struct omap_dss_device *omap_dss_find_device(void *data,
  433. int (*match)(struct omap_dss_device *dssdev, void *data));
  434. int omap_dss_start_device(struct omap_dss_device *dssdev);
  435. void omap_dss_stop_device(struct omap_dss_device *dssdev);
  436. int omap_dss_get_num_overlay_managers(void);
  437. struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
  438. int omap_dss_get_num_overlays(void);
  439. struct omap_overlay *omap_dss_get_overlay(int num);
  440. void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
  441. u16 *xres, u16 *yres);
  442. int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
  443. typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
  444. int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
  445. int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
  446. int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
  447. int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
  448. unsigned long timeout);
  449. #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
  450. #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
  451. void omapdss_dsi_vc_enable_hs(int channel, bool enable);
  452. int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
  453. int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
  454. u16 *x, u16 *y, u16 *w, u16 *h,
  455. bool enlarge_update_area);
  456. int omap_dsi_update(struct omap_dss_device *dssdev,
  457. int channel,
  458. u16 x, u16 y, u16 w, u16 h,
  459. void (*callback)(int, void *), void *data);
  460. int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
  461. void omapdss_dsi_display_disable(struct omap_dss_device *dssdev);
  462. int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
  463. void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
  464. void dpi_set_timings(struct omap_dss_device *dssdev,
  465. struct omap_video_timings *timings);
  466. int dpi_check_timings(struct omap_dss_device *dssdev,
  467. struct omap_video_timings *timings);
  468. int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
  469. void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
  470. int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
  471. void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
  472. int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
  473. u16 *x, u16 *y, u16 *w, u16 *h);
  474. int omap_rfbi_update(struct omap_dss_device *dssdev,
  475. u16 x, u16 y, u16 w, u16 h,
  476. void (*callback)(void *), void *data);
  477. #endif