pinctrl.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675
  1. /*
  2. * SuperH Pin Function Controller pinmux support.
  3. *
  4. * Copyright (C) 2012 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #define DRV_NAME "sh-pfc"
  11. #include <linux/device.h>
  12. #include <linux/err.h>
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/pinctrl/machine.h>
  18. #include <linux/pinctrl/pinconf.h>
  19. #include <linux/pinctrl/pinconf-generic.h>
  20. #include <linux/pinctrl/pinctrl.h>
  21. #include <linux/pinctrl/pinmux.h>
  22. #include <linux/slab.h>
  23. #include <linux/spinlock.h>
  24. #include "core.h"
  25. #include "../core.h"
  26. #include "../pinconf.h"
  27. struct sh_pfc_pin_config {
  28. u32 type;
  29. };
  30. struct sh_pfc_pinctrl {
  31. struct pinctrl_dev *pctl;
  32. struct pinctrl_desc pctl_desc;
  33. struct sh_pfc *pfc;
  34. struct pinctrl_pin_desc *pins;
  35. struct sh_pfc_pin_config *configs;
  36. };
  37. static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
  38. {
  39. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  40. return pmx->pfc->info->nr_groups;
  41. }
  42. static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
  43. unsigned selector)
  44. {
  45. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  46. return pmx->pfc->info->groups[selector].name;
  47. }
  48. static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  49. const unsigned **pins, unsigned *num_pins)
  50. {
  51. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  52. *pins = pmx->pfc->info->groups[selector].pins;
  53. *num_pins = pmx->pfc->info->groups[selector].nr_pins;
  54. return 0;
  55. }
  56. static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  57. unsigned offset)
  58. {
  59. seq_printf(s, "%s", DRV_NAME);
  60. }
  61. static int sh_pfc_map_add_config(struct pinctrl_map *map,
  62. const char *group_or_pin,
  63. enum pinctrl_map_type type,
  64. unsigned long *configs,
  65. unsigned int num_configs)
  66. {
  67. unsigned long *cfgs;
  68. cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
  69. GFP_KERNEL);
  70. if (cfgs == NULL)
  71. return -ENOMEM;
  72. map->type = type;
  73. map->data.configs.group_or_pin = group_or_pin;
  74. map->data.configs.configs = cfgs;
  75. map->data.configs.num_configs = num_configs;
  76. return 0;
  77. }
  78. static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
  79. struct pinctrl_map **map,
  80. unsigned int *num_maps, unsigned int *index)
  81. {
  82. struct pinctrl_map *maps = *map;
  83. unsigned int nmaps = *num_maps;
  84. unsigned int idx = *index;
  85. unsigned int num_configs;
  86. const char *function = NULL;
  87. unsigned long *configs;
  88. struct property *prop;
  89. unsigned int num_groups;
  90. unsigned int num_pins;
  91. const char *group;
  92. const char *pin;
  93. int ret;
  94. /* Parse the function and configuration properties. At least a function
  95. * or one configuration must be specified.
  96. */
  97. ret = of_property_read_string(np, "renesas,function", &function);
  98. if (ret < 0 && ret != -EINVAL) {
  99. dev_err(dev, "Invalid function in DT\n");
  100. return ret;
  101. }
  102. ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
  103. if (ret < 0)
  104. return ret;
  105. if (!function && num_configs == 0) {
  106. dev_err(dev,
  107. "DT node must contain at least a function or config\n");
  108. goto done;
  109. }
  110. /* Count the number of pins and groups and reallocate mappings. */
  111. ret = of_property_count_strings(np, "renesas,pins");
  112. if (ret == -EINVAL) {
  113. num_pins = 0;
  114. } else if (ret < 0) {
  115. dev_err(dev, "Invalid pins list in DT\n");
  116. goto done;
  117. } else {
  118. num_pins = ret;
  119. }
  120. ret = of_property_count_strings(np, "renesas,groups");
  121. if (ret == -EINVAL) {
  122. num_groups = 0;
  123. } else if (ret < 0) {
  124. dev_err(dev, "Invalid pin groups list in DT\n");
  125. goto done;
  126. } else {
  127. num_groups = ret;
  128. }
  129. if (!num_pins && !num_groups) {
  130. dev_err(dev, "No pin or group provided in DT node\n");
  131. ret = -ENODEV;
  132. goto done;
  133. }
  134. if (function)
  135. nmaps += num_groups;
  136. if (configs)
  137. nmaps += num_pins + num_groups;
  138. maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
  139. if (maps == NULL) {
  140. ret = -ENOMEM;
  141. goto done;
  142. }
  143. *map = maps;
  144. *num_maps = nmaps;
  145. /* Iterate over pins and groups and create the mappings. */
  146. of_property_for_each_string(np, "renesas,groups", prop, group) {
  147. if (function) {
  148. maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
  149. maps[idx].data.mux.group = group;
  150. maps[idx].data.mux.function = function;
  151. idx++;
  152. }
  153. if (configs) {
  154. ret = sh_pfc_map_add_config(&maps[idx], group,
  155. PIN_MAP_TYPE_CONFIGS_GROUP,
  156. configs, num_configs);
  157. if (ret < 0)
  158. goto done;
  159. idx++;
  160. }
  161. }
  162. if (!configs) {
  163. ret = 0;
  164. goto done;
  165. }
  166. of_property_for_each_string(np, "renesas,pins", prop, pin) {
  167. ret = sh_pfc_map_add_config(&maps[idx], pin,
  168. PIN_MAP_TYPE_CONFIGS_PIN,
  169. configs, num_configs);
  170. if (ret < 0)
  171. goto done;
  172. idx++;
  173. }
  174. done:
  175. *index = idx;
  176. kfree(configs);
  177. return ret;
  178. }
  179. static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
  180. struct pinctrl_map *map, unsigned num_maps)
  181. {
  182. unsigned int i;
  183. if (map == NULL)
  184. return;
  185. for (i = 0; i < num_maps; ++i) {
  186. if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
  187. map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
  188. kfree(map[i].data.configs.configs);
  189. }
  190. kfree(map);
  191. }
  192. static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
  193. struct device_node *np,
  194. struct pinctrl_map **map, unsigned *num_maps)
  195. {
  196. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  197. struct device *dev = pmx->pfc->dev;
  198. struct device_node *child;
  199. unsigned int index;
  200. int ret;
  201. *map = NULL;
  202. *num_maps = 0;
  203. index = 0;
  204. for_each_child_of_node(np, child) {
  205. ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps,
  206. &index);
  207. if (ret < 0)
  208. goto done;
  209. }
  210. /* If no mapping has been found in child nodes try the config node. */
  211. if (*num_maps == 0) {
  212. ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index);
  213. if (ret < 0)
  214. goto done;
  215. }
  216. if (*num_maps)
  217. return 0;
  218. dev_err(dev, "no mapping found in node %s\n", np->full_name);
  219. ret = -EINVAL;
  220. done:
  221. if (ret < 0)
  222. sh_pfc_dt_free_map(pctldev, *map, *num_maps);
  223. return ret;
  224. }
  225. static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
  226. .get_groups_count = sh_pfc_get_groups_count,
  227. .get_group_name = sh_pfc_get_group_name,
  228. .get_group_pins = sh_pfc_get_group_pins,
  229. .pin_dbg_show = sh_pfc_pin_dbg_show,
  230. .dt_node_to_map = sh_pfc_dt_node_to_map,
  231. .dt_free_map = sh_pfc_dt_free_map,
  232. };
  233. static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
  234. {
  235. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  236. return pmx->pfc->info->nr_functions;
  237. }
  238. static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
  239. unsigned selector)
  240. {
  241. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  242. return pmx->pfc->info->functions[selector].name;
  243. }
  244. static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
  245. unsigned selector,
  246. const char * const **groups,
  247. unsigned * const num_groups)
  248. {
  249. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  250. *groups = pmx->pfc->info->functions[selector].groups;
  251. *num_groups = pmx->pfc->info->functions[selector].nr_groups;
  252. return 0;
  253. }
  254. static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
  255. unsigned group)
  256. {
  257. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  258. struct sh_pfc *pfc = pmx->pfc;
  259. const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
  260. unsigned long flags;
  261. unsigned int i;
  262. int ret = 0;
  263. spin_lock_irqsave(&pfc->lock, flags);
  264. for (i = 0; i < grp->nr_pins; ++i) {
  265. int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
  266. struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
  267. if (cfg->type != PINMUX_TYPE_NONE) {
  268. ret = -EBUSY;
  269. goto done;
  270. }
  271. }
  272. for (i = 0; i < grp->nr_pins; ++i) {
  273. ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
  274. if (ret < 0)
  275. break;
  276. }
  277. done:
  278. spin_unlock_irqrestore(&pfc->lock, flags);
  279. return ret;
  280. }
  281. static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
  282. unsigned group)
  283. {
  284. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  285. struct sh_pfc *pfc = pmx->pfc;
  286. const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
  287. unsigned long flags;
  288. unsigned int i;
  289. spin_lock_irqsave(&pfc->lock, flags);
  290. for (i = 0; i < grp->nr_pins; ++i) {
  291. int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
  292. struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
  293. cfg->type = PINMUX_TYPE_NONE;
  294. }
  295. spin_unlock_irqrestore(&pfc->lock, flags);
  296. }
  297. static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
  298. struct pinctrl_gpio_range *range,
  299. unsigned offset)
  300. {
  301. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  302. struct sh_pfc *pfc = pmx->pfc;
  303. int idx = sh_pfc_get_pin_index(pfc, offset);
  304. struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
  305. unsigned long flags;
  306. int ret;
  307. spin_lock_irqsave(&pfc->lock, flags);
  308. if (cfg->type != PINMUX_TYPE_NONE) {
  309. dev_err(pfc->dev,
  310. "Pin %u is busy, can't configure it as GPIO.\n",
  311. offset);
  312. ret = -EBUSY;
  313. goto done;
  314. }
  315. if (!pfc->gpio) {
  316. /* If GPIOs are handled externally the pin mux type need to be
  317. * set to GPIO here.
  318. */
  319. const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
  320. ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
  321. if (ret < 0)
  322. goto done;
  323. }
  324. cfg->type = PINMUX_TYPE_GPIO;
  325. ret = 0;
  326. done:
  327. spin_unlock_irqrestore(&pfc->lock, flags);
  328. return ret;
  329. }
  330. static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
  331. struct pinctrl_gpio_range *range,
  332. unsigned offset)
  333. {
  334. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  335. struct sh_pfc *pfc = pmx->pfc;
  336. int idx = sh_pfc_get_pin_index(pfc, offset);
  337. struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
  338. unsigned long flags;
  339. spin_lock_irqsave(&pfc->lock, flags);
  340. cfg->type = PINMUX_TYPE_NONE;
  341. spin_unlock_irqrestore(&pfc->lock, flags);
  342. }
  343. static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
  344. struct pinctrl_gpio_range *range,
  345. unsigned offset, bool input)
  346. {
  347. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  348. struct sh_pfc *pfc = pmx->pfc;
  349. int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
  350. int idx = sh_pfc_get_pin_index(pfc, offset);
  351. const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
  352. struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
  353. unsigned long flags;
  354. unsigned int dir;
  355. int ret;
  356. /* Check if the requested direction is supported by the pin. Not all SoC
  357. * provide pin config data, so perform the check conditionally.
  358. */
  359. if (pin->configs) {
  360. dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
  361. if (!(pin->configs & dir))
  362. return -EINVAL;
  363. }
  364. spin_lock_irqsave(&pfc->lock, flags);
  365. ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
  366. if (ret < 0)
  367. goto done;
  368. cfg->type = new_type;
  369. done:
  370. spin_unlock_irqrestore(&pfc->lock, flags);
  371. return ret;
  372. }
  373. static const struct pinmux_ops sh_pfc_pinmux_ops = {
  374. .get_functions_count = sh_pfc_get_functions_count,
  375. .get_function_name = sh_pfc_get_function_name,
  376. .get_function_groups = sh_pfc_get_function_groups,
  377. .enable = sh_pfc_func_enable,
  378. .disable = sh_pfc_func_disable,
  379. .gpio_request_enable = sh_pfc_gpio_request_enable,
  380. .gpio_disable_free = sh_pfc_gpio_disable_free,
  381. .gpio_set_direction = sh_pfc_gpio_set_direction,
  382. };
  383. /* Check whether the requested parameter is supported for a pin. */
  384. static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
  385. enum pin_config_param param)
  386. {
  387. int idx = sh_pfc_get_pin_index(pfc, _pin);
  388. const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
  389. switch (param) {
  390. case PIN_CONFIG_BIAS_DISABLE:
  391. return true;
  392. case PIN_CONFIG_BIAS_PULL_UP:
  393. return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
  394. case PIN_CONFIG_BIAS_PULL_DOWN:
  395. return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
  396. default:
  397. return false;
  398. }
  399. }
  400. static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
  401. unsigned long *config)
  402. {
  403. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  404. struct sh_pfc *pfc = pmx->pfc;
  405. enum pin_config_param param = pinconf_to_config_param(*config);
  406. unsigned long flags;
  407. unsigned int bias;
  408. if (!sh_pfc_pinconf_validate(pfc, _pin, param))
  409. return -ENOTSUPP;
  410. switch (param) {
  411. case PIN_CONFIG_BIAS_DISABLE:
  412. case PIN_CONFIG_BIAS_PULL_UP:
  413. case PIN_CONFIG_BIAS_PULL_DOWN:
  414. if (!pfc->info->ops || !pfc->info->ops->get_bias)
  415. return -ENOTSUPP;
  416. spin_lock_irqsave(&pfc->lock, flags);
  417. bias = pfc->info->ops->get_bias(pfc, _pin);
  418. spin_unlock_irqrestore(&pfc->lock, flags);
  419. if (bias != param)
  420. return -EINVAL;
  421. *config = 0;
  422. break;
  423. default:
  424. return -ENOTSUPP;
  425. }
  426. return 0;
  427. }
  428. static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
  429. unsigned long config)
  430. {
  431. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  432. struct sh_pfc *pfc = pmx->pfc;
  433. enum pin_config_param param = pinconf_to_config_param(config);
  434. unsigned long flags;
  435. if (!sh_pfc_pinconf_validate(pfc, _pin, param))
  436. return -ENOTSUPP;
  437. switch (param) {
  438. case PIN_CONFIG_BIAS_PULL_UP:
  439. case PIN_CONFIG_BIAS_PULL_DOWN:
  440. case PIN_CONFIG_BIAS_DISABLE:
  441. if (!pfc->info->ops || !pfc->info->ops->set_bias)
  442. return -ENOTSUPP;
  443. spin_lock_irqsave(&pfc->lock, flags);
  444. pfc->info->ops->set_bias(pfc, _pin, param);
  445. spin_unlock_irqrestore(&pfc->lock, flags);
  446. break;
  447. default:
  448. return -ENOTSUPP;
  449. }
  450. return 0;
  451. }
  452. static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
  453. unsigned long config)
  454. {
  455. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  456. const unsigned int *pins;
  457. unsigned int num_pins;
  458. unsigned int i;
  459. pins = pmx->pfc->info->groups[group].pins;
  460. num_pins = pmx->pfc->info->groups[group].nr_pins;
  461. for (i = 0; i < num_pins; ++i)
  462. sh_pfc_pinconf_set(pctldev, pins[i], config);
  463. return 0;
  464. }
  465. static const struct pinconf_ops sh_pfc_pinconf_ops = {
  466. .is_generic = true,
  467. .pin_config_get = sh_pfc_pinconf_get,
  468. .pin_config_set = sh_pfc_pinconf_set,
  469. .pin_config_group_set = sh_pfc_pinconf_group_set,
  470. .pin_config_config_dbg_show = pinconf_generic_dump_config,
  471. };
  472. /* PFC ranges -> pinctrl pin descs */
  473. static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
  474. {
  475. const struct pinmux_range *ranges;
  476. struct pinmux_range def_range;
  477. unsigned int nr_ranges;
  478. unsigned int nr_pins;
  479. unsigned int i;
  480. if (pfc->info->ranges == NULL) {
  481. def_range.begin = 0;
  482. def_range.end = pfc->info->nr_pins - 1;
  483. ranges = &def_range;
  484. nr_ranges = 1;
  485. } else {
  486. ranges = pfc->info->ranges;
  487. nr_ranges = pfc->info->nr_ranges;
  488. }
  489. pmx->pins = devm_kzalloc(pfc->dev,
  490. sizeof(*pmx->pins) * pfc->info->nr_pins,
  491. GFP_KERNEL);
  492. if (unlikely(!pmx->pins))
  493. return -ENOMEM;
  494. pmx->configs = devm_kzalloc(pfc->dev,
  495. sizeof(*pmx->configs) * pfc->info->nr_pins,
  496. GFP_KERNEL);
  497. if (unlikely(!pmx->configs))
  498. return -ENOMEM;
  499. for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
  500. const struct pinmux_range *range = &ranges[i];
  501. unsigned int number;
  502. for (number = range->begin; number <= range->end;
  503. number++, nr_pins++) {
  504. struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
  505. struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
  506. const struct sh_pfc_pin *info =
  507. &pfc->info->pins[nr_pins];
  508. pin->number = number;
  509. pin->name = info->name;
  510. cfg->type = PINMUX_TYPE_NONE;
  511. }
  512. }
  513. pfc->nr_pins = ranges[nr_ranges-1].end + 1;
  514. return nr_ranges;
  515. }
  516. int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
  517. {
  518. struct sh_pfc_pinctrl *pmx;
  519. int nr_ranges;
  520. pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
  521. if (unlikely(!pmx))
  522. return -ENOMEM;
  523. pmx->pfc = pfc;
  524. pfc->pinctrl = pmx;
  525. nr_ranges = sh_pfc_map_pins(pfc, pmx);
  526. if (unlikely(nr_ranges < 0))
  527. return nr_ranges;
  528. pmx->pctl_desc.name = DRV_NAME;
  529. pmx->pctl_desc.owner = THIS_MODULE;
  530. pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
  531. pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
  532. pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
  533. pmx->pctl_desc.pins = pmx->pins;
  534. pmx->pctl_desc.npins = pfc->info->nr_pins;
  535. pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
  536. if (pmx->pctl == NULL)
  537. return -EINVAL;
  538. return 0;
  539. }
  540. int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
  541. {
  542. struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
  543. pinctrl_unregister(pmx->pctl);
  544. pfc->pinctrl = NULL;
  545. return 0;
  546. }