tifm_sd.c 26 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/tifm.h>
  12. #include <linux/mmc/protocol.h>
  13. #include <linux/mmc/host.h>
  14. #include <linux/highmem.h>
  15. #include <asm/io.h>
  16. #define DRIVER_NAME "tifm_sd"
  17. #define DRIVER_VERSION "0.7"
  18. static int no_dma = 0;
  19. static int fixed_timeout = 0;
  20. module_param(no_dma, bool, 0644);
  21. module_param(fixed_timeout, bool, 0644);
  22. /* Constants here are mostly from OMAP5912 datasheet */
  23. #define TIFM_MMCSD_RESET 0x0002
  24. #define TIFM_MMCSD_CLKMASK 0x03ff
  25. #define TIFM_MMCSD_POWER 0x0800
  26. #define TIFM_MMCSD_4BBUS 0x8000
  27. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  28. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  29. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  30. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  31. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  32. #define TIFM_MMCSD_READ 0x8000
  33. #define TIFM_MMCSD_DATAMASK 0x001d /* set bits: EOFB, BRS, CB, EOC */
  34. #define TIFM_MMCSD_ERRMASK 0x41e0 /* set bits: CERR, CCRC, CTO, DCRC, DTO */
  35. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  36. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  37. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  38. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  39. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  40. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  41. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  42. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  43. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  44. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  45. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  46. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  47. #define TIFM_MMCSD_RSP_R0 0x0000
  48. #define TIFM_MMCSD_RSP_R1 0x0100
  49. #define TIFM_MMCSD_RSP_R2 0x0200
  50. #define TIFM_MMCSD_RSP_R3 0x0300
  51. #define TIFM_MMCSD_RSP_R4 0x0400
  52. #define TIFM_MMCSD_RSP_R5 0x0500
  53. #define TIFM_MMCSD_RSP_R6 0x0600
  54. #define TIFM_MMCSD_RSP_BUSY 0x0800
  55. #define TIFM_MMCSD_CMD_BC 0x0000
  56. #define TIFM_MMCSD_CMD_BCR 0x1000
  57. #define TIFM_MMCSD_CMD_AC 0x2000
  58. #define TIFM_MMCSD_CMD_ADTC 0x3000
  59. typedef enum {
  60. IDLE = 0,
  61. CMD, /* main command ended */
  62. BRS, /* block transfer finished */
  63. SCMD, /* stop command ended */
  64. CARD, /* card left busy state */
  65. FIFO, /* FIFO operation completed (uncertain) */
  66. READY
  67. } card_state_t;
  68. enum {
  69. FIFO_RDY = 0x0001, /* hardware dependent value */
  70. HOST_REG = 0x0002,
  71. EJECT = 0x0004,
  72. EJECT_DONE = 0x0008,
  73. CARD_BUSY = 0x0010,
  74. OPENDRAIN = 0x0040, /* hardware dependent value */
  75. CARD_EVENT = 0x0100, /* hardware dependent value */
  76. CARD_RO = 0x0200, /* hardware dependent value */
  77. FIFO_EVENT = 0x10000 }; /* hardware dependent value */
  78. struct tifm_sd {
  79. struct tifm_dev *dev;
  80. unsigned int flags;
  81. card_state_t state;
  82. unsigned int clk_freq;
  83. unsigned int clk_div;
  84. unsigned long timeout_jiffies; // software timeout - 2 sec
  85. struct mmc_request *req;
  86. struct work_struct cmd_handler;
  87. struct delayed_work abort_handler;
  88. wait_queue_head_t can_eject;
  89. size_t written_blocks;
  90. char *buffer;
  91. size_t buffer_size;
  92. size_t buffer_pos;
  93. };
  94. static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
  95. unsigned int host_status)
  96. {
  97. struct mmc_command *cmd = host->req->cmd;
  98. unsigned int t_val = 0, cnt = 0;
  99. if (host_status & TIFM_MMCSD_BRS) {
  100. /* in non-dma rx mode BRS fires when fifo is still not empty */
  101. if (host->buffer && (cmd->data->flags & MMC_DATA_READ)) {
  102. while (host->buffer_size > host->buffer_pos) {
  103. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  104. host->buffer[host->buffer_pos++] = t_val & 0xff;
  105. host->buffer[host->buffer_pos++] =
  106. (t_val >> 8) & 0xff;
  107. }
  108. }
  109. return 1;
  110. } else if (host->buffer) {
  111. if ((cmd->data->flags & MMC_DATA_READ) &&
  112. (host_status & TIFM_MMCSD_AF)) {
  113. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  114. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  115. if (host->buffer_size > host->buffer_pos) {
  116. host->buffer[host->buffer_pos++] =
  117. t_val & 0xff;
  118. host->buffer[host->buffer_pos++] =
  119. (t_val >> 8) & 0xff;
  120. }
  121. }
  122. } else if ((cmd->data->flags & MMC_DATA_WRITE)
  123. && (host_status & TIFM_MMCSD_AE)) {
  124. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  125. if (host->buffer_size > host->buffer_pos) {
  126. t_val = host->buffer[host->buffer_pos++] & 0x00ff;
  127. t_val |= ((host->buffer[host->buffer_pos++]) << 8)
  128. & 0xff00;
  129. writel(t_val,
  130. sock->addr + SOCK_MMCSD_DATA);
  131. }
  132. }
  133. }
  134. }
  135. return 0;
  136. }
  137. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  138. {
  139. unsigned int rc = 0;
  140. switch (mmc_resp_type(cmd)) {
  141. case MMC_RSP_NONE:
  142. rc |= TIFM_MMCSD_RSP_R0;
  143. break;
  144. case MMC_RSP_R1B:
  145. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  146. case MMC_RSP_R1:
  147. rc |= TIFM_MMCSD_RSP_R1;
  148. break;
  149. case MMC_RSP_R2:
  150. rc |= TIFM_MMCSD_RSP_R2;
  151. break;
  152. case MMC_RSP_R3:
  153. rc |= TIFM_MMCSD_RSP_R3;
  154. break;
  155. default:
  156. BUG();
  157. }
  158. switch (mmc_cmd_type(cmd)) {
  159. case MMC_CMD_BC:
  160. rc |= TIFM_MMCSD_CMD_BC;
  161. break;
  162. case MMC_CMD_BCR:
  163. rc |= TIFM_MMCSD_CMD_BCR;
  164. break;
  165. case MMC_CMD_AC:
  166. rc |= TIFM_MMCSD_CMD_AC;
  167. break;
  168. case MMC_CMD_ADTC:
  169. rc |= TIFM_MMCSD_CMD_ADTC;
  170. break;
  171. default:
  172. BUG();
  173. }
  174. return rc;
  175. }
  176. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  177. {
  178. struct tifm_dev *sock = host->dev;
  179. unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
  180. (host->flags & OPENDRAIN);
  181. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  182. cmd_mask |= TIFM_MMCSD_READ;
  183. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  184. cmd->opcode, cmd->arg, cmd_mask);
  185. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  186. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  187. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  188. }
  189. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  190. {
  191. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  192. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  193. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  194. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  195. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  196. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  197. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  198. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  199. }
  200. static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
  201. unsigned int host_status)
  202. {
  203. struct mmc_command *cmd = host->req->cmd;
  204. change_state:
  205. switch (host->state) {
  206. case IDLE:
  207. return;
  208. case CMD:
  209. if (host_status & TIFM_MMCSD_EOC) {
  210. tifm_sd_fetch_resp(cmd, sock);
  211. if (cmd->data) {
  212. host->state = BRS;
  213. } else {
  214. host->state = READY;
  215. }
  216. goto change_state;
  217. }
  218. break;
  219. case BRS:
  220. if (tifm_sd_transfer_data(sock, host, host_status)) {
  221. if (cmd->data->flags & MMC_DATA_WRITE) {
  222. host->state = CARD;
  223. } else {
  224. if (no_dma) {
  225. if (host->req->stop) {
  226. tifm_sd_exec(host, host->req->stop);
  227. host->state = SCMD;
  228. } else {
  229. host->state = READY;
  230. }
  231. } else {
  232. host->state = FIFO;
  233. }
  234. }
  235. goto change_state;
  236. }
  237. break;
  238. case SCMD:
  239. if (host_status & TIFM_MMCSD_EOC) {
  240. tifm_sd_fetch_resp(host->req->stop, sock);
  241. host->state = READY;
  242. goto change_state;
  243. }
  244. break;
  245. case CARD:
  246. dev_dbg(&sock->dev, "waiting for CARD, have %zd blocks\n",
  247. host->written_blocks);
  248. if (!(host->flags & CARD_BUSY)
  249. && (host->written_blocks == cmd->data->blocks)) {
  250. if (no_dma) {
  251. if (host->req->stop) {
  252. tifm_sd_exec(host, host->req->stop);
  253. host->state = SCMD;
  254. } else {
  255. host->state = READY;
  256. }
  257. } else {
  258. host->state = FIFO;
  259. }
  260. goto change_state;
  261. }
  262. break;
  263. case FIFO:
  264. if (host->flags & FIFO_RDY) {
  265. host->flags &= ~FIFO_RDY;
  266. if (host->req->stop) {
  267. tifm_sd_exec(host, host->req->stop);
  268. host->state = SCMD;
  269. } else {
  270. host->state = READY;
  271. }
  272. goto change_state;
  273. }
  274. break;
  275. case READY:
  276. queue_work(sock->wq, &host->cmd_handler);
  277. return;
  278. }
  279. queue_delayed_work(sock->wq, &host->abort_handler,
  280. host->timeout_jiffies);
  281. }
  282. /* Called from interrupt handler */
  283. static unsigned int tifm_sd_signal_irq(struct tifm_dev *sock,
  284. unsigned int sock_irq_status)
  285. {
  286. struct tifm_sd *host;
  287. unsigned int host_status = 0, fifo_status = 0;
  288. int error_code = 0;
  289. spin_lock(&sock->lock);
  290. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  291. cancel_delayed_work(&host->abort_handler);
  292. if (sock_irq_status & FIFO_EVENT) {
  293. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  294. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  295. host->flags |= fifo_status & FIFO_RDY;
  296. }
  297. if (sock_irq_status & CARD_EVENT) {
  298. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  299. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  300. if (!(host->flags & HOST_REG))
  301. queue_work(sock->wq, &host->cmd_handler);
  302. if (!host->req)
  303. goto done;
  304. if (host_status & TIFM_MMCSD_ERRMASK) {
  305. if (host_status & TIFM_MMCSD_CERR)
  306. error_code = MMC_ERR_FAILED;
  307. else if (host_status &
  308. (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
  309. error_code = MMC_ERR_TIMEOUT;
  310. else if (host_status &
  311. (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
  312. error_code = MMC_ERR_BADCRC;
  313. writel(TIFM_FIFO_INT_SETALL,
  314. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  315. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  316. if (host->req->stop) {
  317. if (host->state == SCMD) {
  318. host->req->stop->error = error_code;
  319. } else if (host->state == BRS
  320. || host->state == CARD
  321. || host->state == FIFO) {
  322. host->req->cmd->error = error_code;
  323. tifm_sd_exec(host, host->req->stop);
  324. queue_delayed_work(sock->wq,
  325. &host->abort_handler,
  326. host->timeout_jiffies);
  327. host->state = SCMD;
  328. goto done;
  329. } else {
  330. host->req->cmd->error = error_code;
  331. }
  332. } else {
  333. host->req->cmd->error = error_code;
  334. }
  335. host->state = READY;
  336. }
  337. if (host_status & TIFM_MMCSD_CB)
  338. host->flags |= CARD_BUSY;
  339. if ((host_status & TIFM_MMCSD_EOFB) &&
  340. (host->flags & CARD_BUSY)) {
  341. host->written_blocks++;
  342. host->flags &= ~CARD_BUSY;
  343. }
  344. }
  345. if (host->req)
  346. tifm_sd_process_cmd(sock, host, host_status);
  347. done:
  348. dev_dbg(&sock->dev, "host_status %x, fifo_status %x\n",
  349. host_status, fifo_status);
  350. spin_unlock(&sock->lock);
  351. return sock_irq_status;
  352. }
  353. static void tifm_sd_prepare_data(struct tifm_sd *card, struct mmc_command *cmd)
  354. {
  355. struct tifm_dev *sock = card->dev;
  356. unsigned int dest_cnt;
  357. /* DMA style IO */
  358. writel(TIFM_FIFO_INT_SETALL,
  359. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  360. writel(ilog2(cmd->data->blksz) - 2,
  361. sock->addr + SOCK_FIFO_PAGE_SIZE);
  362. writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
  363. writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  364. dest_cnt = (cmd->data->blocks) << 8;
  365. writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
  366. writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  367. writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  368. if (cmd->data->flags & MMC_DATA_WRITE) {
  369. writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  370. writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
  371. sock->addr + SOCK_DMA_CONTROL);
  372. } else {
  373. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  374. writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
  375. }
  376. }
  377. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  378. struct mmc_data *data)
  379. {
  380. struct tifm_dev *sock = host->dev;
  381. unsigned int data_timeout = data->timeout_clks;
  382. if (fixed_timeout)
  383. return;
  384. data_timeout += data->timeout_ns /
  385. ((1000000000 / host->clk_freq) * host->clk_div);
  386. data_timeout *= 10; // call it fudge factor for now
  387. if (data_timeout < 0xffff) {
  388. writel((~TIFM_MMCSD_DPE) &
  389. readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  390. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  391. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  392. } else {
  393. writel(TIFM_MMCSD_DPE |
  394. readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  395. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  396. data_timeout = (data_timeout >> 10) + 1;
  397. if(data_timeout > 0xffff)
  398. data_timeout = 0; /* set to unlimited */
  399. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  400. }
  401. }
  402. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  403. {
  404. struct tifm_sd *host = mmc_priv(mmc);
  405. struct tifm_dev *sock = host->dev;
  406. unsigned long flags;
  407. int sg_count = 0;
  408. struct mmc_data *r_data = mrq->cmd->data;
  409. spin_lock_irqsave(&sock->lock, flags);
  410. if (host->flags & EJECT) {
  411. spin_unlock_irqrestore(&sock->lock, flags);
  412. goto err_out;
  413. }
  414. if (host->req) {
  415. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  416. spin_unlock_irqrestore(&sock->lock, flags);
  417. goto err_out;
  418. }
  419. if (r_data) {
  420. tifm_sd_set_data_timeout(host, r_data);
  421. sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
  422. mrq->cmd->flags & MMC_DATA_WRITE
  423. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  424. if (sg_count != 1) {
  425. printk(KERN_ERR DRIVER_NAME
  426. ": scatterlist map failed\n");
  427. spin_unlock_irqrestore(&sock->lock, flags);
  428. goto err_out;
  429. }
  430. host->written_blocks = 0;
  431. host->flags &= ~CARD_BUSY;
  432. tifm_sd_prepare_data(host, mrq->cmd);
  433. }
  434. host->req = mrq;
  435. host->state = CMD;
  436. queue_delayed_work(sock->wq, &host->abort_handler,
  437. host->timeout_jiffies);
  438. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  439. sock->addr + SOCK_CONTROL);
  440. tifm_sd_exec(host, mrq->cmd);
  441. spin_unlock_irqrestore(&sock->lock, flags);
  442. return;
  443. err_out:
  444. if (sg_count > 0)
  445. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  446. (r_data->flags & MMC_DATA_WRITE)
  447. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  448. mrq->cmd->error = MMC_ERR_TIMEOUT;
  449. mmc_request_done(mmc, mrq);
  450. }
  451. static void tifm_sd_end_cmd(struct work_struct *work)
  452. {
  453. struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
  454. struct tifm_dev *sock = host->dev;
  455. struct mmc_host *mmc = tifm_get_drvdata(sock);
  456. struct mmc_request *mrq;
  457. struct mmc_data *r_data = NULL;
  458. unsigned long flags;
  459. spin_lock_irqsave(&sock->lock, flags);
  460. mrq = host->req;
  461. host->req = NULL;
  462. host->state = IDLE;
  463. if (!mrq) {
  464. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  465. spin_unlock_irqrestore(&sock->lock, flags);
  466. return;
  467. }
  468. r_data = mrq->cmd->data;
  469. if (r_data) {
  470. if (r_data->flags & MMC_DATA_WRITE) {
  471. r_data->bytes_xfered = host->written_blocks *
  472. r_data->blksz;
  473. } else {
  474. r_data->bytes_xfered = r_data->blocks -
  475. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  476. r_data->bytes_xfered *= r_data->blksz;
  477. r_data->bytes_xfered += r_data->blksz -
  478. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  479. }
  480. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  481. (r_data->flags & MMC_DATA_WRITE)
  482. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  483. }
  484. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  485. sock->addr + SOCK_CONTROL);
  486. spin_unlock_irqrestore(&sock->lock, flags);
  487. mmc_request_done(mmc, mrq);
  488. }
  489. static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
  490. {
  491. struct tifm_sd *host = mmc_priv(mmc);
  492. struct tifm_dev *sock = host->dev;
  493. unsigned long flags;
  494. struct mmc_data *r_data = mrq->cmd->data;
  495. char *t_buffer = NULL;
  496. if (r_data) {
  497. t_buffer = kmap(r_data->sg->page);
  498. if (!t_buffer) {
  499. printk(KERN_ERR DRIVER_NAME ": kmap failed\n");
  500. goto err_out;
  501. }
  502. }
  503. spin_lock_irqsave(&sock->lock, flags);
  504. if (host->flags & EJECT) {
  505. spin_unlock_irqrestore(&sock->lock, flags);
  506. goto err_out;
  507. }
  508. if (host->req) {
  509. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  510. spin_unlock_irqrestore(&sock->lock, flags);
  511. goto err_out;
  512. }
  513. if (r_data) {
  514. tifm_sd_set_data_timeout(host, r_data);
  515. host->buffer = t_buffer + r_data->sg->offset;
  516. host->buffer_size = mrq->cmd->data->blocks *
  517. mrq->cmd->data->blksz;
  518. writel(TIFM_MMCSD_BUFINT |
  519. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  520. sock->addr + SOCK_MMCSD_INT_ENABLE);
  521. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8) |
  522. (TIFM_MMCSD_FIFO_SIZE - 1),
  523. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  524. host->written_blocks = 0;
  525. host->flags &= ~CARD_BUSY;
  526. host->buffer_pos = 0;
  527. writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  528. writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  529. }
  530. host->req = mrq;
  531. host->state = CMD;
  532. queue_delayed_work(sock->wq, &host->abort_handler,
  533. host->timeout_jiffies);
  534. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  535. sock->addr + SOCK_CONTROL);
  536. tifm_sd_exec(host, mrq->cmd);
  537. spin_unlock_irqrestore(&sock->lock, flags);
  538. return;
  539. err_out:
  540. if (t_buffer)
  541. kunmap(r_data->sg->page);
  542. mrq->cmd->error = MMC_ERR_TIMEOUT;
  543. mmc_request_done(mmc, mrq);
  544. }
  545. static void tifm_sd_end_cmd_nodma(struct work_struct *work)
  546. {
  547. struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
  548. struct tifm_dev *sock = host->dev;
  549. struct mmc_host *mmc = tifm_get_drvdata(sock);
  550. struct mmc_request *mrq;
  551. struct mmc_data *r_data = NULL;
  552. unsigned long flags;
  553. spin_lock_irqsave(&sock->lock, flags);
  554. mrq = host->req;
  555. host->req = NULL;
  556. host->state = IDLE;
  557. if (!mrq) {
  558. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  559. spin_unlock_irqrestore(&sock->lock, flags);
  560. return;
  561. }
  562. r_data = mrq->cmd->data;
  563. if (r_data) {
  564. writel((~TIFM_MMCSD_BUFINT) &
  565. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  566. sock->addr + SOCK_MMCSD_INT_ENABLE);
  567. if (r_data->flags & MMC_DATA_WRITE) {
  568. r_data->bytes_xfered = host->written_blocks *
  569. r_data->blksz;
  570. } else {
  571. r_data->bytes_xfered = r_data->blocks -
  572. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  573. r_data->bytes_xfered *= r_data->blksz;
  574. r_data->bytes_xfered += r_data->blksz -
  575. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  576. }
  577. host->buffer = NULL;
  578. host->buffer_pos = 0;
  579. host->buffer_size = 0;
  580. }
  581. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  582. sock->addr + SOCK_CONTROL);
  583. spin_unlock_irqrestore(&sock->lock, flags);
  584. if (r_data)
  585. kunmap(r_data->sg->page);
  586. mmc_request_done(mmc, mrq);
  587. }
  588. static void tifm_sd_abort(struct work_struct *work)
  589. {
  590. struct tifm_sd *host =
  591. container_of(work, struct tifm_sd, abort_handler.work);
  592. printk(KERN_ERR DRIVER_NAME
  593. ": card failed to respond for a long period of time");
  594. tifm_eject(host->dev);
  595. }
  596. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  597. {
  598. struct tifm_sd *host = mmc_priv(mmc);
  599. struct tifm_dev *sock = host->dev;
  600. unsigned int clk_div1, clk_div2;
  601. unsigned long flags;
  602. spin_lock_irqsave(&sock->lock, flags);
  603. dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
  604. ios->power_mode);
  605. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  606. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  607. sock->addr + SOCK_MMCSD_CONFIG);
  608. } else {
  609. writel((~TIFM_MMCSD_4BBUS) &
  610. readl(sock->addr + SOCK_MMCSD_CONFIG),
  611. sock->addr + SOCK_MMCSD_CONFIG);
  612. }
  613. if (ios->clock) {
  614. clk_div1 = 20000000 / ios->clock;
  615. if (!clk_div1)
  616. clk_div1 = 1;
  617. clk_div2 = 24000000 / ios->clock;
  618. if (!clk_div2)
  619. clk_div2 = 1;
  620. if ((20000000 / clk_div1) > ios->clock)
  621. clk_div1++;
  622. if ((24000000 / clk_div2) > ios->clock)
  623. clk_div2++;
  624. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  625. host->clk_freq = 20000000;
  626. host->clk_div = clk_div1;
  627. writel((~TIFM_CTRL_FAST_CLK) &
  628. readl(sock->addr + SOCK_CONTROL),
  629. sock->addr + SOCK_CONTROL);
  630. } else {
  631. host->clk_freq = 24000000;
  632. host->clk_div = clk_div2;
  633. writel(TIFM_CTRL_FAST_CLK |
  634. readl(sock->addr + SOCK_CONTROL),
  635. sock->addr + SOCK_CONTROL);
  636. }
  637. } else {
  638. host->clk_div = 0;
  639. }
  640. host->clk_div &= TIFM_MMCSD_CLKMASK;
  641. writel(host->clk_div | ((~TIFM_MMCSD_CLKMASK) &
  642. readl(sock->addr + SOCK_MMCSD_CONFIG)),
  643. sock->addr + SOCK_MMCSD_CONFIG);
  644. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  645. host->flags |= OPENDRAIN;
  646. else
  647. host->flags &= ~OPENDRAIN;
  648. /* chip_select : maybe later */
  649. //vdd
  650. //power is set before probe / after remove
  651. //I believe, power_off when already marked for eject is sufficient to
  652. // allow removal.
  653. if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
  654. host->flags |= EJECT_DONE;
  655. wake_up_all(&host->can_eject);
  656. }
  657. spin_unlock_irqrestore(&sock->lock, flags);
  658. }
  659. static int tifm_sd_ro(struct mmc_host *mmc)
  660. {
  661. int rc;
  662. struct tifm_sd *host = mmc_priv(mmc);
  663. struct tifm_dev *sock = host->dev;
  664. unsigned long flags;
  665. spin_lock_irqsave(&sock->lock, flags);
  666. host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
  667. rc = (host->flags & CARD_RO) ? 1 : 0;
  668. spin_unlock_irqrestore(&sock->lock, flags);
  669. return rc;
  670. }
  671. static struct mmc_host_ops tifm_sd_ops = {
  672. .request = tifm_sd_request,
  673. .set_ios = tifm_sd_ios,
  674. .get_ro = tifm_sd_ro
  675. };
  676. static void tifm_sd_register_host(struct work_struct *work)
  677. {
  678. struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
  679. struct tifm_dev *sock = host->dev;
  680. struct mmc_host *mmc = tifm_get_drvdata(sock);
  681. unsigned long flags;
  682. spin_lock_irqsave(&sock->lock, flags);
  683. host->flags |= HOST_REG;
  684. PREPARE_WORK(&host->cmd_handler,
  685. no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd);
  686. spin_unlock_irqrestore(&sock->lock, flags);
  687. dev_dbg(&sock->dev, "adding host\n");
  688. mmc_add_host(mmc);
  689. }
  690. static int tifm_sd_probe(struct tifm_dev *sock)
  691. {
  692. struct mmc_host *mmc;
  693. struct tifm_sd *host;
  694. int rc = -EIO;
  695. if (!(TIFM_SOCK_STATE_OCCUPIED &
  696. readl(sock->addr + SOCK_PRESENT_STATE))) {
  697. printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
  698. return rc;
  699. }
  700. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  701. if (!mmc)
  702. return -ENOMEM;
  703. host = mmc_priv(mmc);
  704. host->dev = sock;
  705. host->clk_div = 61;
  706. init_waitqueue_head(&host->can_eject);
  707. INIT_WORK(&host->cmd_handler, tifm_sd_register_host);
  708. INIT_DELAYED_WORK(&host->abort_handler, tifm_sd_abort);
  709. tifm_set_drvdata(sock, mmc);
  710. sock->signal_irq = tifm_sd_signal_irq;
  711. host->clk_freq = 20000000;
  712. host->timeout_jiffies = msecs_to_jiffies(1000);
  713. tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
  714. mmc->ops = &tifm_sd_ops;
  715. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  716. mmc->caps = MMC_CAP_4_BIT_DATA;
  717. mmc->f_min = 20000000 / 60;
  718. mmc->f_max = 24000000;
  719. mmc->max_hw_segs = 1;
  720. mmc->max_phys_segs = 1;
  721. mmc->max_sectors = 127;
  722. mmc->max_seg_size = mmc->max_sectors << 11; //2k maximum hw block length
  723. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  724. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  725. writel(host->clk_div | TIFM_MMCSD_POWER,
  726. sock->addr + SOCK_MMCSD_CONFIG);
  727. for (rc = 0; rc < 50; rc++) {
  728. /* Wait for reset ack */
  729. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  730. rc = 0;
  731. break;
  732. }
  733. msleep(10);
  734. }
  735. if (rc) {
  736. printk(KERN_ERR DRIVER_NAME
  737. ": card not ready - probe failed\n");
  738. mmc_free_host(mmc);
  739. return -ENODEV;
  740. }
  741. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  742. writel(host->clk_div | TIFM_MMCSD_POWER,
  743. sock->addr + SOCK_MMCSD_CONFIG);
  744. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  745. writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
  746. sock->addr + SOCK_MMCSD_INT_ENABLE);
  747. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO); // command timeout 64 clocks for now
  748. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  749. writel(host->clk_div | TIFM_MMCSD_POWER,
  750. sock->addr + SOCK_MMCSD_CONFIG);
  751. queue_delayed_work(sock->wq, &host->abort_handler,
  752. host->timeout_jiffies);
  753. return 0;
  754. }
  755. static int tifm_sd_host_is_down(struct tifm_dev *sock)
  756. {
  757. struct mmc_host *mmc = tifm_get_drvdata(sock);
  758. struct tifm_sd *host = mmc_priv(mmc);
  759. unsigned long flags;
  760. int rc = 0;
  761. spin_lock_irqsave(&sock->lock, flags);
  762. rc = (host->flags & EJECT_DONE);
  763. spin_unlock_irqrestore(&sock->lock, flags);
  764. return rc;
  765. }
  766. static void tifm_sd_remove(struct tifm_dev *sock)
  767. {
  768. struct mmc_host *mmc = tifm_get_drvdata(sock);
  769. struct tifm_sd *host = mmc_priv(mmc);
  770. unsigned long flags;
  771. spin_lock_irqsave(&sock->lock, flags);
  772. host->flags |= EJECT;
  773. if (host->req)
  774. queue_work(sock->wq, &host->cmd_handler);
  775. spin_unlock_irqrestore(&sock->lock, flags);
  776. wait_event_timeout(host->can_eject, tifm_sd_host_is_down(sock),
  777. host->timeout_jiffies);
  778. if (host->flags & HOST_REG)
  779. mmc_remove_host(mmc);
  780. /* The meaning of the bit majority in this constant is unknown. */
  781. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  782. sock->addr + SOCK_CONTROL);
  783. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  784. writel(TIFM_FIFO_INT_SETALL,
  785. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  786. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  787. tifm_set_drvdata(sock, NULL);
  788. mmc_free_host(mmc);
  789. }
  790. static tifm_media_id tifm_sd_id_tbl[] = {
  791. FM_SD, 0
  792. };
  793. static struct tifm_driver tifm_sd_driver = {
  794. .driver = {
  795. .name = DRIVER_NAME,
  796. .owner = THIS_MODULE
  797. },
  798. .id_table = tifm_sd_id_tbl,
  799. .probe = tifm_sd_probe,
  800. .remove = tifm_sd_remove
  801. };
  802. static int __init tifm_sd_init(void)
  803. {
  804. return tifm_register_driver(&tifm_sd_driver);
  805. }
  806. static void __exit tifm_sd_exit(void)
  807. {
  808. tifm_unregister_driver(&tifm_sd_driver);
  809. }
  810. MODULE_AUTHOR("Alex Dubov");
  811. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  812. MODULE_LICENSE("GPL");
  813. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  814. MODULE_VERSION(DRIVER_VERSION);
  815. module_init(tifm_sd_init);
  816. module_exit(tifm_sd_exit);