v2m.c 16 KB

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  1. /*
  2. * Versatile Express V2M Motherboard Support
  3. */
  4. #include <linux/device.h>
  5. #include <linux/amba/bus.h>
  6. #include <linux/amba/mmci.h>
  7. #include <linux/io.h>
  8. #include <linux/init.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_fdt.h>
  11. #include <linux/of_irq.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/ata_platform.h>
  15. #include <linux/smsc911x.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/device.h>
  18. #include <linux/usb/isp1760.h>
  19. #include <linux/clkdev.h>
  20. #include <linux/mtd/physmap.h>
  21. #include <asm/arch_timer.h>
  22. #include <asm/mach-types.h>
  23. #include <asm/sizes.h>
  24. #include <asm/smp_twd.h>
  25. #include <asm/mach/arch.h>
  26. #include <asm/mach/map.h>
  27. #include <asm/mach/time.h>
  28. #include <asm/hardware/arm_timer.h>
  29. #include <asm/hardware/cache-l2x0.h>
  30. #include <asm/hardware/gic.h>
  31. #include <asm/hardware/timer-sp.h>
  32. #include <asm/hardware/sp810.h>
  33. #include <asm/hardware/gic.h>
  34. #include <mach/ct-ca9x4.h>
  35. #include <mach/motherboard.h>
  36. #include <plat/sched_clock.h>
  37. #include "core.h"
  38. #define V2M_PA_CS0 0x40000000
  39. #define V2M_PA_CS1 0x44000000
  40. #define V2M_PA_CS2 0x48000000
  41. #define V2M_PA_CS3 0x4c000000
  42. #define V2M_PA_CS7 0x10000000
  43. static struct map_desc v2m_io_desc[] __initdata = {
  44. {
  45. .virtual = V2M_PERIPH,
  46. .pfn = __phys_to_pfn(V2M_PA_CS7),
  47. .length = SZ_128K,
  48. .type = MT_DEVICE,
  49. },
  50. };
  51. static void __iomem *v2m_sysreg_base;
  52. static void __init v2m_sysctl_init(void __iomem *base)
  53. {
  54. u32 scctrl;
  55. if (WARN_ON(!base))
  56. return;
  57. /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
  58. scctrl = readl(base + SCCTRL);
  59. scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
  60. scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
  61. writel(scctrl, base + SCCTRL);
  62. }
  63. static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
  64. {
  65. if (WARN_ON(!base || irq == NO_IRQ))
  66. return;
  67. writel(0, base + TIMER_1_BASE + TIMER_CTRL);
  68. writel(0, base + TIMER_2_BASE + TIMER_CTRL);
  69. sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
  70. sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
  71. }
  72. static void __init v2m_timer_init(void)
  73. {
  74. v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
  75. v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
  76. }
  77. static struct sys_timer v2m_timer = {
  78. .init = v2m_timer_init,
  79. };
  80. static DEFINE_SPINLOCK(v2m_cfg_lock);
  81. int v2m_cfg_write(u32 devfn, u32 data)
  82. {
  83. /* Configuration interface broken? */
  84. u32 val;
  85. printk("%s: writing %08x to %08x\n", __func__, data, devfn);
  86. devfn |= SYS_CFG_START | SYS_CFG_WRITE;
  87. spin_lock(&v2m_cfg_lock);
  88. val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
  89. writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
  90. writel(data, v2m_sysreg_base + V2M_SYS_CFGDATA);
  91. writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
  92. do {
  93. val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
  94. } while (val == 0);
  95. spin_unlock(&v2m_cfg_lock);
  96. return !!(val & SYS_CFG_ERR);
  97. }
  98. int v2m_cfg_read(u32 devfn, u32 *data)
  99. {
  100. u32 val;
  101. devfn |= SYS_CFG_START;
  102. spin_lock(&v2m_cfg_lock);
  103. writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
  104. writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
  105. mb();
  106. do {
  107. cpu_relax();
  108. val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
  109. } while (val == 0);
  110. *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
  111. spin_unlock(&v2m_cfg_lock);
  112. return !!(val & SYS_CFG_ERR);
  113. }
  114. void __init v2m_flags_set(u32 data)
  115. {
  116. writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
  117. writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
  118. }
  119. static struct resource v2m_pcie_i2c_resource = {
  120. .start = V2M_SERIAL_BUS_PCI,
  121. .end = V2M_SERIAL_BUS_PCI + SZ_4K - 1,
  122. .flags = IORESOURCE_MEM,
  123. };
  124. static struct platform_device v2m_pcie_i2c_device = {
  125. .name = "versatile-i2c",
  126. .id = 0,
  127. .num_resources = 1,
  128. .resource = &v2m_pcie_i2c_resource,
  129. };
  130. static struct resource v2m_ddc_i2c_resource = {
  131. .start = V2M_SERIAL_BUS_DVI,
  132. .end = V2M_SERIAL_BUS_DVI + SZ_4K - 1,
  133. .flags = IORESOURCE_MEM,
  134. };
  135. static struct platform_device v2m_ddc_i2c_device = {
  136. .name = "versatile-i2c",
  137. .id = 1,
  138. .num_resources = 1,
  139. .resource = &v2m_ddc_i2c_resource,
  140. };
  141. static struct resource v2m_eth_resources[] = {
  142. {
  143. .start = V2M_LAN9118,
  144. .end = V2M_LAN9118 + SZ_64K - 1,
  145. .flags = IORESOURCE_MEM,
  146. }, {
  147. .start = IRQ_V2M_LAN9118,
  148. .end = IRQ_V2M_LAN9118,
  149. .flags = IORESOURCE_IRQ,
  150. },
  151. };
  152. static struct smsc911x_platform_config v2m_eth_config = {
  153. .flags = SMSC911X_USE_32BIT,
  154. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
  155. .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
  156. .phy_interface = PHY_INTERFACE_MODE_MII,
  157. };
  158. static struct platform_device v2m_eth_device = {
  159. .name = "smsc911x",
  160. .id = -1,
  161. .resource = v2m_eth_resources,
  162. .num_resources = ARRAY_SIZE(v2m_eth_resources),
  163. .dev.platform_data = &v2m_eth_config,
  164. };
  165. static struct resource v2m_usb_resources[] = {
  166. {
  167. .start = V2M_ISP1761,
  168. .end = V2M_ISP1761 + SZ_128K - 1,
  169. .flags = IORESOURCE_MEM,
  170. }, {
  171. .start = IRQ_V2M_ISP1761,
  172. .end = IRQ_V2M_ISP1761,
  173. .flags = IORESOURCE_IRQ,
  174. },
  175. };
  176. static struct isp1760_platform_data v2m_usb_config = {
  177. .is_isp1761 = true,
  178. .bus_width_16 = false,
  179. .port1_otg = true,
  180. .analog_oc = false,
  181. .dack_polarity_high = false,
  182. .dreq_polarity_high = false,
  183. };
  184. static struct platform_device v2m_usb_device = {
  185. .name = "isp1760",
  186. .id = -1,
  187. .resource = v2m_usb_resources,
  188. .num_resources = ARRAY_SIZE(v2m_usb_resources),
  189. .dev.platform_data = &v2m_usb_config,
  190. };
  191. static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
  192. {
  193. writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
  194. }
  195. static struct physmap_flash_data v2m_flash_data = {
  196. .width = 4,
  197. .set_vpp = v2m_flash_set_vpp,
  198. };
  199. static struct resource v2m_flash_resources[] = {
  200. {
  201. .start = V2M_NOR0,
  202. .end = V2M_NOR0 + SZ_64M - 1,
  203. .flags = IORESOURCE_MEM,
  204. }, {
  205. .start = V2M_NOR1,
  206. .end = V2M_NOR1 + SZ_64M - 1,
  207. .flags = IORESOURCE_MEM,
  208. },
  209. };
  210. static struct platform_device v2m_flash_device = {
  211. .name = "physmap-flash",
  212. .id = -1,
  213. .resource = v2m_flash_resources,
  214. .num_resources = ARRAY_SIZE(v2m_flash_resources),
  215. .dev.platform_data = &v2m_flash_data,
  216. };
  217. static struct pata_platform_info v2m_pata_data = {
  218. .ioport_shift = 2,
  219. };
  220. static struct resource v2m_pata_resources[] = {
  221. {
  222. .start = V2M_CF,
  223. .end = V2M_CF + 0xff,
  224. .flags = IORESOURCE_MEM,
  225. }, {
  226. .start = V2M_CF + 0x100,
  227. .end = V2M_CF + SZ_4K - 1,
  228. .flags = IORESOURCE_MEM,
  229. },
  230. };
  231. static struct platform_device v2m_cf_device = {
  232. .name = "pata_platform",
  233. .id = -1,
  234. .resource = v2m_pata_resources,
  235. .num_resources = ARRAY_SIZE(v2m_pata_resources),
  236. .dev.platform_data = &v2m_pata_data,
  237. };
  238. static unsigned int v2m_mmci_status(struct device *dev)
  239. {
  240. return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
  241. }
  242. static struct mmci_platform_data v2m_mmci_data = {
  243. .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
  244. .status = v2m_mmci_status,
  245. };
  246. static AMBA_APB_DEVICE(aaci, "mb:aaci", 0, V2M_AACI, IRQ_V2M_AACI, NULL);
  247. static AMBA_APB_DEVICE(mmci, "mb:mmci", 0, V2M_MMCI, IRQ_V2M_MMCI, &v2m_mmci_data);
  248. static AMBA_APB_DEVICE(kmi0, "mb:kmi0", 0, V2M_KMI0, IRQ_V2M_KMI0, NULL);
  249. static AMBA_APB_DEVICE(kmi1, "mb:kmi1", 0, V2M_KMI1, IRQ_V2M_KMI1, NULL);
  250. static AMBA_APB_DEVICE(uart0, "mb:uart0", 0, V2M_UART0, IRQ_V2M_UART0, NULL);
  251. static AMBA_APB_DEVICE(uart1, "mb:uart1", 0, V2M_UART1, IRQ_V2M_UART1, NULL);
  252. static AMBA_APB_DEVICE(uart2, "mb:uart2", 0, V2M_UART2, IRQ_V2M_UART2, NULL);
  253. static AMBA_APB_DEVICE(uart3, "mb:uart3", 0, V2M_UART3, IRQ_V2M_UART3, NULL);
  254. static AMBA_APB_DEVICE(wdt, "mb:wdt", 0, V2M_WDT, IRQ_V2M_WDT, NULL);
  255. static AMBA_APB_DEVICE(rtc, "mb:rtc", 0, V2M_RTC, IRQ_V2M_RTC, NULL);
  256. static struct amba_device *v2m_amba_devs[] __initdata = {
  257. &aaci_device,
  258. &mmci_device,
  259. &kmi0_device,
  260. &kmi1_device,
  261. &uart0_device,
  262. &uart1_device,
  263. &uart2_device,
  264. &uart3_device,
  265. &wdt_device,
  266. &rtc_device,
  267. };
  268. static long v2m_osc_round(struct clk *clk, unsigned long rate)
  269. {
  270. return rate;
  271. }
  272. static int v2m_osc1_set(struct clk *clk, unsigned long rate)
  273. {
  274. return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate);
  275. }
  276. static const struct clk_ops osc1_clk_ops = {
  277. .round = v2m_osc_round,
  278. .set = v2m_osc1_set,
  279. };
  280. static struct clk osc1_clk = {
  281. .ops = &osc1_clk_ops,
  282. .rate = 24000000,
  283. };
  284. static struct clk osc2_clk = {
  285. .rate = 24000000,
  286. };
  287. static struct clk v2m_sp804_clk = {
  288. .rate = 1000000,
  289. };
  290. static struct clk v2m_ref_clk = {
  291. .rate = 32768,
  292. };
  293. static struct clk dummy_apb_pclk;
  294. static struct clk_lookup v2m_lookups[] = {
  295. { /* AMBA bus clock */
  296. .con_id = "apb_pclk",
  297. .clk = &dummy_apb_pclk,
  298. }, { /* UART0 */
  299. .dev_id = "mb:uart0",
  300. .clk = &osc2_clk,
  301. }, { /* UART1 */
  302. .dev_id = "mb:uart1",
  303. .clk = &osc2_clk,
  304. }, { /* UART2 */
  305. .dev_id = "mb:uart2",
  306. .clk = &osc2_clk,
  307. }, { /* UART3 */
  308. .dev_id = "mb:uart3",
  309. .clk = &osc2_clk,
  310. }, { /* KMI0 */
  311. .dev_id = "mb:kmi0",
  312. .clk = &osc2_clk,
  313. }, { /* KMI1 */
  314. .dev_id = "mb:kmi1",
  315. .clk = &osc2_clk,
  316. }, { /* MMC0 */
  317. .dev_id = "mb:mmci",
  318. .clk = &osc2_clk,
  319. }, { /* CLCD */
  320. .dev_id = "mb:clcd",
  321. .clk = &osc1_clk,
  322. }, { /* SP805 WDT */
  323. .dev_id = "mb:wdt",
  324. .clk = &v2m_ref_clk,
  325. }, { /* SP804 timers */
  326. .dev_id = "sp804",
  327. .con_id = "v2m-timer0",
  328. .clk = &v2m_sp804_clk,
  329. }, { /* SP804 timers */
  330. .dev_id = "sp804",
  331. .con_id = "v2m-timer1",
  332. .clk = &v2m_sp804_clk,
  333. },
  334. };
  335. static void __init v2m_init_early(void)
  336. {
  337. ct_desc->init_early();
  338. clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
  339. versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
  340. }
  341. static void v2m_power_off(void)
  342. {
  343. if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0))
  344. printk(KERN_EMERG "Unable to shutdown\n");
  345. }
  346. static void v2m_restart(char str, const char *cmd)
  347. {
  348. if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
  349. printk(KERN_EMERG "Unable to reboot\n");
  350. }
  351. struct ct_desc *ct_desc;
  352. static struct ct_desc *ct_descs[] __initdata = {
  353. #ifdef CONFIG_ARCH_VEXPRESS_CA9X4
  354. &ct_ca9x4_desc,
  355. #endif
  356. };
  357. static void __init v2m_populate_ct_desc(void)
  358. {
  359. int i;
  360. u32 current_tile_id;
  361. ct_desc = NULL;
  362. current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
  363. & V2M_CT_ID_MASK;
  364. for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
  365. if (ct_descs[i]->id == current_tile_id)
  366. ct_desc = ct_descs[i];
  367. if (!ct_desc)
  368. panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
  369. "You may need a device tree blob or a different kernel to boot on this board.\n",
  370. current_tile_id);
  371. }
  372. static void __init v2m_map_io(void)
  373. {
  374. iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
  375. v2m_sysreg_base = ioremap(V2M_SYSREGS, SZ_4K);
  376. v2m_populate_ct_desc();
  377. ct_desc->map_io();
  378. }
  379. static void __init v2m_init_irq(void)
  380. {
  381. ct_desc->init_irq();
  382. }
  383. static void __init v2m_init(void)
  384. {
  385. int i;
  386. platform_device_register(&v2m_pcie_i2c_device);
  387. platform_device_register(&v2m_ddc_i2c_device);
  388. platform_device_register(&v2m_flash_device);
  389. platform_device_register(&v2m_cf_device);
  390. platform_device_register(&v2m_eth_device);
  391. platform_device_register(&v2m_usb_device);
  392. for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
  393. amba_device_register(v2m_amba_devs[i], &iomem_resource);
  394. pm_power_off = v2m_power_off;
  395. ct_desc->init_tile();
  396. }
  397. MACHINE_START(VEXPRESS, "ARM-Versatile Express")
  398. .atag_offset = 0x100,
  399. .map_io = v2m_map_io,
  400. .init_early = v2m_init_early,
  401. .init_irq = v2m_init_irq,
  402. .timer = &v2m_timer,
  403. .handle_irq = gic_handle_irq,
  404. .init_machine = v2m_init,
  405. .restart = v2m_restart,
  406. MACHINE_END
  407. #if defined(CONFIG_ARCH_VEXPRESS_DT)
  408. static struct map_desc v2m_rs1_io_desc __initdata = {
  409. .virtual = V2M_PERIPH,
  410. .pfn = __phys_to_pfn(0x1c000000),
  411. .length = SZ_2M,
  412. .type = MT_DEVICE,
  413. };
  414. static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
  415. int depth, void *data)
  416. {
  417. const char **map = data;
  418. if (strcmp(uname, "motherboard") != 0)
  419. return 0;
  420. *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
  421. return 1;
  422. }
  423. void __init v2m_dt_map_io(void)
  424. {
  425. const char *map = NULL;
  426. of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
  427. if (map && strcmp(map, "rs1") == 0)
  428. iotable_init(&v2m_rs1_io_desc, 1);
  429. else
  430. iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
  431. #if defined(CONFIG_SMP)
  432. vexpress_dt_smp_map_io();
  433. #endif
  434. }
  435. static struct clk_lookup v2m_dt_lookups[] = {
  436. { /* AMBA bus clock */
  437. .con_id = "apb_pclk",
  438. .clk = &dummy_apb_pclk,
  439. }, { /* SP804 timers */
  440. .dev_id = "sp804",
  441. .con_id = "v2m-timer0",
  442. .clk = &v2m_sp804_clk,
  443. }, { /* SP804 timers */
  444. .dev_id = "sp804",
  445. .con_id = "v2m-timer1",
  446. .clk = &v2m_sp804_clk,
  447. }, { /* PL180 MMCI */
  448. .dev_id = "mb:mmci", /* 10005000.mmci */
  449. .clk = &osc2_clk,
  450. }, { /* PL050 KMI0 */
  451. .dev_id = "10006000.kmi",
  452. .clk = &osc2_clk,
  453. }, { /* PL050 KMI1 */
  454. .dev_id = "10007000.kmi",
  455. .clk = &osc2_clk,
  456. }, { /* PL011 UART0 */
  457. .dev_id = "10009000.uart",
  458. .clk = &osc2_clk,
  459. }, { /* PL011 UART1 */
  460. .dev_id = "1000a000.uart",
  461. .clk = &osc2_clk,
  462. }, { /* PL011 UART2 */
  463. .dev_id = "1000b000.uart",
  464. .clk = &osc2_clk,
  465. }, { /* PL011 UART3 */
  466. .dev_id = "1000c000.uart",
  467. .clk = &osc2_clk,
  468. }, { /* SP805 WDT */
  469. .dev_id = "1000f000.wdt",
  470. .clk = &v2m_ref_clk,
  471. }, { /* PL111 CLCD */
  472. .dev_id = "1001f000.clcd",
  473. .clk = &osc1_clk,
  474. },
  475. /* RS1 memory map */
  476. { /* PL180 MMCI */
  477. .dev_id = "mb:mmci", /* 1c050000.mmci */
  478. .clk = &osc2_clk,
  479. }, { /* PL050 KMI0 */
  480. .dev_id = "1c060000.kmi",
  481. .clk = &osc2_clk,
  482. }, { /* PL050 KMI1 */
  483. .dev_id = "1c070000.kmi",
  484. .clk = &osc2_clk,
  485. }, { /* PL011 UART0 */
  486. .dev_id = "1c090000.uart",
  487. .clk = &osc2_clk,
  488. }, { /* PL011 UART1 */
  489. .dev_id = "1c0a0000.uart",
  490. .clk = &osc2_clk,
  491. }, { /* PL011 UART2 */
  492. .dev_id = "1c0b0000.uart",
  493. .clk = &osc2_clk,
  494. }, { /* PL011 UART3 */
  495. .dev_id = "1c0c0000.uart",
  496. .clk = &osc2_clk,
  497. }, { /* SP805 WDT */
  498. .dev_id = "1c0f0000.wdt",
  499. .clk = &v2m_ref_clk,
  500. }, { /* PL111 CLCD */
  501. .dev_id = "1c1f0000.clcd",
  502. .clk = &osc1_clk,
  503. },
  504. };
  505. void __init v2m_dt_init_early(void)
  506. {
  507. struct device_node *node;
  508. u32 dt_hbi;
  509. node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
  510. v2m_sysreg_base = of_iomap(node, 0);
  511. if (WARN_ON(!v2m_sysreg_base))
  512. return;
  513. /* Confirm board type against DT property, if available */
  514. if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
  515. u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
  516. u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
  517. V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
  518. u32 hbi = id & SYS_PROCIDx_HBI_MASK;
  519. if (WARN_ON(dt_hbi != hbi))
  520. pr_warning("vexpress: DT HBI (%x) is not matching "
  521. "hardware (%x)!\n", dt_hbi, hbi);
  522. }
  523. clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
  524. }
  525. static struct of_device_id vexpress_irq_match[] __initdata = {
  526. { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
  527. {}
  528. };
  529. static void __init v2m_dt_init_irq(void)
  530. {
  531. of_irq_init(vexpress_irq_match);
  532. }
  533. static void __init v2m_dt_timer_init(void)
  534. {
  535. struct device_node *node;
  536. const char *path;
  537. int err;
  538. node = of_find_compatible_node(NULL, NULL, "arm,sp810");
  539. v2m_sysctl_init(of_iomap(node, 0));
  540. err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
  541. if (WARN_ON(err))
  542. return;
  543. node = of_find_node_by_path(path);
  544. v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
  545. if (arch_timer_of_register() != 0)
  546. twd_local_timer_of_register();
  547. if (arch_timer_sched_clock_init() != 0)
  548. versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
  549. }
  550. static struct sys_timer v2m_dt_timer = {
  551. .init = v2m_dt_timer_init,
  552. };
  553. static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
  554. OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
  555. &v2m_flash_data),
  556. OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
  557. /* RS1 memory map */
  558. OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
  559. &v2m_flash_data),
  560. OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
  561. {}
  562. };
  563. static void __init v2m_dt_init(void)
  564. {
  565. l2x0_of_init(0x00400000, 0xfe0fffff);
  566. of_platform_populate(NULL, of_default_bus_match_table,
  567. v2m_dt_auxdata_lookup, NULL);
  568. pm_power_off = v2m_power_off;
  569. }
  570. const static char *v2m_dt_match[] __initconst = {
  571. "arm,vexpress",
  572. NULL,
  573. };
  574. DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
  575. .dt_compat = v2m_dt_match,
  576. .map_io = v2m_dt_map_io,
  577. .init_early = v2m_dt_init_early,
  578. .init_irq = v2m_dt_init_irq,
  579. .timer = &v2m_dt_timer,
  580. .init_machine = v2m_dt_init,
  581. .handle_irq = gic_handle_irq,
  582. .restart = v2m_restart,
  583. MACHINE_END
  584. #endif