smp.c 27 KB

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  1. /* SMP support routines.
  2. *
  3. * Copyright (C) 2006-2008 Panasonic Corporation
  4. * All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/interrupt.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/init.h>
  18. #include <linux/jiffies.h>
  19. #include <linux/cpumask.h>
  20. #include <linux/err.h>
  21. #include <linux/kernel.h>
  22. #include <linux/delay.h>
  23. #include <linux/sched.h>
  24. #include <linux/profile.h>
  25. #include <linux/smp.h>
  26. #include <asm/tlbflush.h>
  27. #include <asm/system.h>
  28. #include <asm/bitops.h>
  29. #include <asm/processor.h>
  30. #include <asm/bug.h>
  31. #include <asm/exceptions.h>
  32. #include <asm/hardirq.h>
  33. #include <asm/fpu.h>
  34. #include <asm/mmu_context.h>
  35. #include <asm/thread_info.h>
  36. #include <asm/cpu-regs.h>
  37. #include <asm/intctl-regs.h>
  38. #include "internal.h"
  39. #ifdef CONFIG_HOTPLUG_CPU
  40. #include <linux/cpu.h>
  41. #include <asm/cacheflush.h>
  42. static unsigned long sleep_mode[NR_CPUS];
  43. static void run_sleep_cpu(unsigned int cpu);
  44. static void run_wakeup_cpu(unsigned int cpu);
  45. #endif /* CONFIG_HOTPLUG_CPU */
  46. /*
  47. * Debug Message function
  48. */
  49. #undef DEBUG_SMP
  50. #ifdef DEBUG_SMP
  51. #define Dprintk(fmt, ...) printk(KERN_DEBUG fmt, ##__VA_ARGS__)
  52. #else
  53. #define Dprintk(fmt, ...) no_printk(KERN_DEBUG fmt, ##__VA_ARGS__)
  54. #endif
  55. /* timeout value in msec for smp_nmi_call_function. zero is no timeout. */
  56. #define CALL_FUNCTION_NMI_IPI_TIMEOUT 0
  57. /*
  58. * Structure and data for smp_nmi_call_function().
  59. */
  60. struct nmi_call_data_struct {
  61. smp_call_func_t func;
  62. void *info;
  63. cpumask_t started;
  64. cpumask_t finished;
  65. int wait;
  66. char size_alignment[0]
  67. __attribute__ ((__aligned__(SMP_CACHE_BYTES)));
  68. } __attribute__ ((__aligned__(SMP_CACHE_BYTES)));
  69. static DEFINE_SPINLOCK(smp_nmi_call_lock);
  70. static struct nmi_call_data_struct *nmi_call_data;
  71. /*
  72. * Data structures and variables
  73. */
  74. static cpumask_t cpu_callin_map; /* Bitmask of callin CPUs */
  75. static cpumask_t cpu_callout_map; /* Bitmask of callout CPUs */
  76. cpumask_t cpu_boot_map; /* Bitmask of boot APs */
  77. unsigned long start_stack[NR_CPUS - 1];
  78. /*
  79. * Per CPU parameters
  80. */
  81. struct mn10300_cpuinfo cpu_data[NR_CPUS] __cacheline_aligned;
  82. static int cpucount; /* The count of boot CPUs */
  83. static cpumask_t smp_commenced_mask;
  84. cpumask_t cpu_initialized __initdata = CPU_MASK_NONE;
  85. /*
  86. * Function Prototypes
  87. */
  88. static int do_boot_cpu(int);
  89. static void smp_show_cpu_info(int cpu_id);
  90. static void smp_callin(void);
  91. static void smp_online(void);
  92. static void smp_store_cpu_info(int);
  93. static void smp_cpu_init(void);
  94. static void smp_tune_scheduling(void);
  95. static void send_IPI_mask(const cpumask_t *cpumask, int irq);
  96. static void init_ipi(void);
  97. /*
  98. * IPI Initialization interrupt definitions
  99. */
  100. static void mn10300_ipi_disable(unsigned int irq);
  101. static void mn10300_ipi_enable(unsigned int irq);
  102. static void mn10300_ipi_chip_disable(struct irq_data *d);
  103. static void mn10300_ipi_chip_enable(struct irq_data *d);
  104. static void mn10300_ipi_ack(struct irq_data *d);
  105. static void mn10300_ipi_nop(struct irq_data *d);
  106. static struct irq_chip mn10300_ipi_type = {
  107. .name = "cpu_ipi",
  108. .irq_disable = mn10300_ipi_chip_disable,
  109. .irq_enable = mn10300_ipi_chip_enable,
  110. .irq_ack = mn10300_ipi_ack,
  111. .irq_eoi = mn10300_ipi_nop
  112. };
  113. static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id);
  114. static irqreturn_t smp_call_function_interrupt(int irq, void *dev_id);
  115. static struct irqaction reschedule_ipi = {
  116. .handler = smp_reschedule_interrupt,
  117. .name = "smp reschedule IPI"
  118. };
  119. static struct irqaction call_function_ipi = {
  120. .handler = smp_call_function_interrupt,
  121. .name = "smp call function IPI"
  122. };
  123. #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
  124. static irqreturn_t smp_ipi_timer_interrupt(int irq, void *dev_id);
  125. static struct irqaction local_timer_ipi = {
  126. .handler = smp_ipi_timer_interrupt,
  127. .flags = IRQF_DISABLED,
  128. .name = "smp local timer IPI"
  129. };
  130. #endif
  131. /**
  132. * init_ipi - Initialise the IPI mechanism
  133. */
  134. static void init_ipi(void)
  135. {
  136. unsigned long flags;
  137. u16 tmp16;
  138. /* set up the reschedule IPI */
  139. set_irq_chip_and_handler(RESCHEDULE_IPI,
  140. &mn10300_ipi_type, handle_percpu_irq);
  141. setup_irq(RESCHEDULE_IPI, &reschedule_ipi);
  142. set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV);
  143. mn10300_ipi_enable(RESCHEDULE_IPI);
  144. /* set up the call function IPI */
  145. set_irq_chip_and_handler(CALL_FUNC_SINGLE_IPI,
  146. &mn10300_ipi_type, handle_percpu_irq);
  147. setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi);
  148. set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV);
  149. mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI);
  150. /* set up the local timer IPI */
  151. #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \
  152. defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
  153. set_irq_chip_and_handler(LOCAL_TIMER_IPI,
  154. &mn10300_ipi_type, handle_percpu_irq);
  155. setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi);
  156. set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV);
  157. mn10300_ipi_enable(LOCAL_TIMER_IPI);
  158. #endif
  159. #ifdef CONFIG_MN10300_CACHE_ENABLED
  160. /* set up the cache flush IPI */
  161. flags = arch_local_cli_save();
  162. __set_intr_stub(NUM2EXCEP_IRQ_LEVEL(FLUSH_CACHE_GxICR_LV),
  163. mn10300_low_ipi_handler);
  164. GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT;
  165. mn10300_ipi_enable(FLUSH_CACHE_IPI);
  166. arch_local_irq_restore(flags);
  167. #endif
  168. /* set up the NMI call function IPI */
  169. flags = arch_local_cli_save();
  170. GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT;
  171. tmp16 = GxICR(CALL_FUNCTION_NMI_IPI);
  172. arch_local_irq_restore(flags);
  173. /* set up the SMP boot IPI */
  174. flags = arch_local_cli_save();
  175. __set_intr_stub(NUM2EXCEP_IRQ_LEVEL(SMP_BOOT_GxICR_LV),
  176. mn10300_low_ipi_handler);
  177. arch_local_irq_restore(flags);
  178. }
  179. /**
  180. * mn10300_ipi_shutdown - Shut down handling of an IPI
  181. * @irq: The IPI to be shut down.
  182. */
  183. static void mn10300_ipi_shutdown(unsigned int irq)
  184. {
  185. unsigned long flags;
  186. u16 tmp;
  187. flags = arch_local_cli_save();
  188. tmp = GxICR(irq);
  189. GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
  190. tmp = GxICR(irq);
  191. arch_local_irq_restore(flags);
  192. }
  193. /**
  194. * mn10300_ipi_enable - Enable an IPI
  195. * @irq: The IPI to be enabled.
  196. */
  197. static void mn10300_ipi_enable(unsigned int irq)
  198. {
  199. unsigned long flags;
  200. u16 tmp;
  201. flags = arch_local_cli_save();
  202. tmp = GxICR(irq);
  203. GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE;
  204. tmp = GxICR(irq);
  205. arch_local_irq_restore(flags);
  206. }
  207. static void mn10300_ipi_chip_enable(struct irq_data *d)
  208. {
  209. mn10300_ipi_enable(d->irq);
  210. }
  211. /**
  212. * mn10300_ipi_disable - Disable an IPI
  213. * @irq: The IPI to be disabled.
  214. */
  215. static void mn10300_ipi_disable(unsigned int irq)
  216. {
  217. unsigned long flags;
  218. u16 tmp;
  219. flags = arch_local_cli_save();
  220. tmp = GxICR(irq);
  221. GxICR(irq) = tmp & GxICR_LEVEL;
  222. tmp = GxICR(irq);
  223. arch_local_irq_restore(flags);
  224. }
  225. static void mn10300_ipi_chip_disable(struct irq_data *d)
  226. {
  227. mn10300_ipi_disable(d->irq);
  228. }
  229. /**
  230. * mn10300_ipi_ack - Acknowledge an IPI interrupt in the PIC
  231. * @irq: The IPI to be acknowledged.
  232. *
  233. * Clear the interrupt detection flag for the IPI on the appropriate interrupt
  234. * channel in the PIC.
  235. */
  236. static void mn10300_ipi_ack(struct irq_data *d)
  237. {
  238. unsigned int irq = d->irq;
  239. unsigned long flags;
  240. u16 tmp;
  241. flags = arch_local_cli_save();
  242. GxICR_u8(irq) = GxICR_DETECT;
  243. tmp = GxICR(irq);
  244. arch_local_irq_restore(flags);
  245. }
  246. /**
  247. * mn10300_ipi_nop - Dummy IPI action
  248. * @irq: The IPI to be acted upon.
  249. */
  250. static void mn10300_ipi_nop(struct irq_data *d)
  251. {
  252. }
  253. /**
  254. * send_IPI_mask - Send IPIs to all CPUs in list
  255. * @cpumask: The list of CPUs to target.
  256. * @irq: The IPI request to be sent.
  257. *
  258. * Send the specified IPI to all the CPUs in the list, not waiting for them to
  259. * finish before returning. The caller is responsible for synchronisation if
  260. * that is needed.
  261. */
  262. static void send_IPI_mask(const cpumask_t *cpumask, int irq)
  263. {
  264. int i;
  265. u16 tmp;
  266. for (i = 0; i < NR_CPUS; i++) {
  267. if (cpu_isset(i, *cpumask)) {
  268. /* send IPI */
  269. tmp = CROSS_GxICR(irq, i);
  270. CROSS_GxICR(irq, i) =
  271. tmp | GxICR_REQUEST | GxICR_DETECT;
  272. tmp = CROSS_GxICR(irq, i); /* flush write buffer */
  273. }
  274. }
  275. }
  276. /**
  277. * send_IPI_self - Send an IPI to this CPU.
  278. * @irq: The IPI request to be sent.
  279. *
  280. * Send the specified IPI to the current CPU.
  281. */
  282. void send_IPI_self(int irq)
  283. {
  284. send_IPI_mask(cpumask_of(smp_processor_id()), irq);
  285. }
  286. /**
  287. * send_IPI_allbutself - Send IPIs to all the other CPUs.
  288. * @irq: The IPI request to be sent.
  289. *
  290. * Send the specified IPI to all CPUs in the system barring the current one,
  291. * not waiting for them to finish before returning. The caller is responsible
  292. * for synchronisation if that is needed.
  293. */
  294. void send_IPI_allbutself(int irq)
  295. {
  296. cpumask_t cpumask;
  297. cpumask = cpu_online_map;
  298. cpu_clear(smp_processor_id(), cpumask);
  299. send_IPI_mask(&cpumask, irq);
  300. }
  301. void arch_send_call_function_ipi_mask(const struct cpumask *mask)
  302. {
  303. BUG();
  304. /*send_IPI_mask(mask, CALL_FUNCTION_IPI);*/
  305. }
  306. void arch_send_call_function_single_ipi(int cpu)
  307. {
  308. send_IPI_mask(cpumask_of(cpu), CALL_FUNC_SINGLE_IPI);
  309. }
  310. /**
  311. * smp_send_reschedule - Send reschedule IPI to a CPU
  312. * @cpu: The CPU to target.
  313. */
  314. void smp_send_reschedule(int cpu)
  315. {
  316. send_IPI_mask(cpumask_of(cpu), RESCHEDULE_IPI);
  317. }
  318. /**
  319. * smp_nmi_call_function - Send a call function NMI IPI to all CPUs
  320. * @func: The function to ask to be run.
  321. * @info: The context data to pass to that function.
  322. * @wait: If true, wait (atomically) until function is run on all CPUs.
  323. *
  324. * Send a non-maskable request to all CPUs in the system, requesting them to
  325. * run the specified function with the given context data, and, potentially, to
  326. * wait for completion of that function on all CPUs.
  327. *
  328. * Returns 0 if successful, -ETIMEDOUT if we were asked to wait, but hit the
  329. * timeout.
  330. */
  331. int smp_nmi_call_function(smp_call_func_t func, void *info, int wait)
  332. {
  333. struct nmi_call_data_struct data;
  334. unsigned long flags;
  335. unsigned int cnt;
  336. int cpus, ret = 0;
  337. cpus = num_online_cpus() - 1;
  338. if (cpus < 1)
  339. return 0;
  340. data.func = func;
  341. data.info = info;
  342. data.started = cpu_online_map;
  343. cpu_clear(smp_processor_id(), data.started);
  344. data.wait = wait;
  345. if (wait)
  346. data.finished = data.started;
  347. spin_lock_irqsave(&smp_nmi_call_lock, flags);
  348. nmi_call_data = &data;
  349. smp_mb();
  350. /* Send a message to all other CPUs and wait for them to respond */
  351. send_IPI_allbutself(CALL_FUNCTION_NMI_IPI);
  352. /* Wait for response */
  353. if (CALL_FUNCTION_NMI_IPI_TIMEOUT > 0) {
  354. for (cnt = 0;
  355. cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT &&
  356. !cpus_empty(data.started);
  357. cnt++)
  358. mdelay(1);
  359. if (wait && cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT) {
  360. for (cnt = 0;
  361. cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT &&
  362. !cpus_empty(data.finished);
  363. cnt++)
  364. mdelay(1);
  365. }
  366. if (cnt >= CALL_FUNCTION_NMI_IPI_TIMEOUT)
  367. ret = -ETIMEDOUT;
  368. } else {
  369. /* If timeout value is zero, wait until cpumask has been
  370. * cleared */
  371. while (!cpus_empty(data.started))
  372. barrier();
  373. if (wait)
  374. while (!cpus_empty(data.finished))
  375. barrier();
  376. }
  377. spin_unlock_irqrestore(&smp_nmi_call_lock, flags);
  378. return ret;
  379. }
  380. /**
  381. * stop_this_cpu - Callback to stop a CPU.
  382. * @unused: Callback context (ignored).
  383. */
  384. void stop_this_cpu(void *unused)
  385. {
  386. static volatile int stopflag;
  387. unsigned long flags;
  388. #ifdef CONFIG_GDBSTUB
  389. /* In case of single stepping smp_send_stop by other CPU,
  390. * clear procindebug to avoid deadlock.
  391. */
  392. atomic_set(&procindebug[smp_processor_id()], 0);
  393. #endif /* CONFIG_GDBSTUB */
  394. flags = arch_local_cli_save();
  395. cpu_clear(smp_processor_id(), cpu_online_map);
  396. while (!stopflag)
  397. cpu_relax();
  398. cpu_set(smp_processor_id(), cpu_online_map);
  399. arch_local_irq_restore(flags);
  400. }
  401. /**
  402. * smp_send_stop - Send a stop request to all CPUs.
  403. */
  404. void smp_send_stop(void)
  405. {
  406. smp_nmi_call_function(stop_this_cpu, NULL, 0);
  407. }
  408. /**
  409. * smp_reschedule_interrupt - Reschedule IPI handler
  410. * @irq: The interrupt number.
  411. * @dev_id: The device ID.
  412. *
  413. * We need do nothing here, since the scheduling will be effected on our way
  414. * back through entry.S.
  415. *
  416. * Returns IRQ_HANDLED to indicate we handled the interrupt successfully.
  417. */
  418. static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id)
  419. {
  420. /* do nothing */
  421. return IRQ_HANDLED;
  422. }
  423. /**
  424. * smp_call_function_interrupt - Call function IPI handler
  425. * @irq: The interrupt number.
  426. * @dev_id: The device ID.
  427. *
  428. * Returns IRQ_HANDLED to indicate we handled the interrupt successfully.
  429. */
  430. static irqreturn_t smp_call_function_interrupt(int irq, void *dev_id)
  431. {
  432. /* generic_smp_call_function_interrupt(); */
  433. generic_smp_call_function_single_interrupt();
  434. return IRQ_HANDLED;
  435. }
  436. /**
  437. * smp_nmi_call_function_interrupt - Non-maskable call function IPI handler
  438. */
  439. void smp_nmi_call_function_interrupt(void)
  440. {
  441. smp_call_func_t func = nmi_call_data->func;
  442. void *info = nmi_call_data->info;
  443. int wait = nmi_call_data->wait;
  444. /* Notify the initiating CPU that I've grabbed the data and am about to
  445. * execute the function
  446. */
  447. smp_mb();
  448. cpu_clear(smp_processor_id(), nmi_call_data->started);
  449. (*func)(info);
  450. if (wait) {
  451. smp_mb();
  452. cpu_clear(smp_processor_id(), nmi_call_data->finished);
  453. }
  454. }
  455. #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \
  456. defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
  457. /**
  458. * smp_ipi_timer_interrupt - Local timer IPI handler
  459. * @irq: The interrupt number.
  460. * @dev_id: The device ID.
  461. *
  462. * Returns IRQ_HANDLED to indicate we handled the interrupt successfully.
  463. */
  464. static irqreturn_t smp_ipi_timer_interrupt(int irq, void *dev_id)
  465. {
  466. return local_timer_interrupt();
  467. }
  468. #endif
  469. void __init smp_init_cpus(void)
  470. {
  471. int i;
  472. for (i = 0; i < NR_CPUS; i++) {
  473. set_cpu_possible(i, true);
  474. set_cpu_present(i, true);
  475. }
  476. }
  477. /**
  478. * smp_cpu_init - Initialise AP in start_secondary.
  479. *
  480. * For this Application Processor, set up init_mm, initialise FPU and set
  481. * interrupt level 0-6 setting.
  482. */
  483. static void __init smp_cpu_init(void)
  484. {
  485. unsigned long flags;
  486. int cpu_id = smp_processor_id();
  487. u16 tmp16;
  488. if (test_and_set_bit(cpu_id, &cpu_initialized)) {
  489. printk(KERN_WARNING "CPU#%d already initialized!\n", cpu_id);
  490. for (;;)
  491. local_irq_enable();
  492. }
  493. printk(KERN_INFO "Initializing CPU#%d\n", cpu_id);
  494. atomic_inc(&init_mm.mm_count);
  495. current->active_mm = &init_mm;
  496. BUG_ON(current->mm);
  497. enter_lazy_tlb(&init_mm, current);
  498. /* Force FPU initialization */
  499. clear_using_fpu(current);
  500. GxICR(CALL_FUNC_SINGLE_IPI) = CALL_FUNCTION_GxICR_LV | GxICR_DETECT;
  501. mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI);
  502. GxICR(LOCAL_TIMER_IPI) = LOCAL_TIMER_GxICR_LV | GxICR_DETECT;
  503. mn10300_ipi_enable(LOCAL_TIMER_IPI);
  504. GxICR(RESCHEDULE_IPI) = RESCHEDULE_GxICR_LV | GxICR_DETECT;
  505. mn10300_ipi_enable(RESCHEDULE_IPI);
  506. #ifdef CONFIG_MN10300_CACHE_ENABLED
  507. GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT;
  508. mn10300_ipi_enable(FLUSH_CACHE_IPI);
  509. #endif
  510. mn10300_ipi_shutdown(SMP_BOOT_IRQ);
  511. /* Set up the non-maskable call function IPI */
  512. flags = arch_local_cli_save();
  513. GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT;
  514. tmp16 = GxICR(CALL_FUNCTION_NMI_IPI);
  515. arch_local_irq_restore(flags);
  516. }
  517. /**
  518. * smp_prepare_cpu_init - Initialise CPU in startup_secondary
  519. *
  520. * Set interrupt level 0-6 setting and init ICR of gdbstub.
  521. */
  522. void smp_prepare_cpu_init(void)
  523. {
  524. int loop;
  525. /* Set the interrupt vector registers */
  526. IVAR0 = EXCEP_IRQ_LEVEL0;
  527. IVAR1 = EXCEP_IRQ_LEVEL1;
  528. IVAR2 = EXCEP_IRQ_LEVEL2;
  529. IVAR3 = EXCEP_IRQ_LEVEL3;
  530. IVAR4 = EXCEP_IRQ_LEVEL4;
  531. IVAR5 = EXCEP_IRQ_LEVEL5;
  532. IVAR6 = EXCEP_IRQ_LEVEL6;
  533. /* Disable all interrupts and set to priority 6 (lowest) */
  534. for (loop = 0; loop < GxICR_NUM_IRQS; loop++)
  535. GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
  536. #ifdef CONFIG_GDBSTUB
  537. /* initialise GDB-stub */
  538. do {
  539. unsigned long flags;
  540. u16 tmp16;
  541. flags = arch_local_cli_save();
  542. GxICR(GDB_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT;
  543. tmp16 = GxICR(GDB_NMI_IPI);
  544. arch_local_irq_restore(flags);
  545. } while (0);
  546. #endif
  547. }
  548. /**
  549. * start_secondary - Activate a secondary CPU (AP)
  550. * @unused: Thread parameter (ignored).
  551. */
  552. int __init start_secondary(void *unused)
  553. {
  554. smp_cpu_init();
  555. smp_callin();
  556. while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
  557. cpu_relax();
  558. local_flush_tlb();
  559. preempt_disable();
  560. smp_online();
  561. #ifdef CONFIG_GENERIC_CLOCKEVENTS
  562. init_clockevents();
  563. #endif
  564. cpu_idle();
  565. return 0;
  566. }
  567. /**
  568. * smp_prepare_cpus - Boot up secondary CPUs (APs)
  569. * @max_cpus: Maximum number of CPUs to boot.
  570. *
  571. * Call do_boot_cpu, and boot up APs.
  572. */
  573. void __init smp_prepare_cpus(unsigned int max_cpus)
  574. {
  575. int phy_id;
  576. /* Setup boot CPU information */
  577. smp_store_cpu_info(0);
  578. smp_tune_scheduling();
  579. init_ipi();
  580. /* If SMP should be disabled, then finish */
  581. if (max_cpus == 0) {
  582. printk(KERN_INFO "SMP mode deactivated.\n");
  583. goto smp_done;
  584. }
  585. /* Boot secondary CPUs (for which phy_id > 0) */
  586. for (phy_id = 0; phy_id < NR_CPUS; phy_id++) {
  587. /* Don't boot primary CPU */
  588. if (max_cpus <= cpucount + 1)
  589. continue;
  590. if (phy_id != 0)
  591. do_boot_cpu(phy_id);
  592. set_cpu_possible(phy_id, true);
  593. smp_show_cpu_info(phy_id);
  594. }
  595. smp_done:
  596. Dprintk("Boot done.\n");
  597. }
  598. /**
  599. * smp_store_cpu_info - Save a CPU's information
  600. * @cpu: The CPU to save for.
  601. *
  602. * Save boot_cpu_data and jiffy for the specified CPU.
  603. */
  604. static void __init smp_store_cpu_info(int cpu)
  605. {
  606. struct mn10300_cpuinfo *ci = &cpu_data[cpu];
  607. *ci = boot_cpu_data;
  608. ci->loops_per_jiffy = loops_per_jiffy;
  609. ci->type = CPUREV;
  610. }
  611. /**
  612. * smp_tune_scheduling - Set time slice value
  613. *
  614. * Nothing to do here.
  615. */
  616. static void __init smp_tune_scheduling(void)
  617. {
  618. }
  619. /**
  620. * do_boot_cpu: Boot up one CPU
  621. * @phy_id: Physical ID of CPU to boot.
  622. *
  623. * Send an IPI to a secondary CPU to boot it. Returns 0 on success, 1
  624. * otherwise.
  625. */
  626. static int __init do_boot_cpu(int phy_id)
  627. {
  628. struct task_struct *idle;
  629. unsigned long send_status, callin_status;
  630. int timeout, cpu_id;
  631. send_status = GxICR_REQUEST;
  632. callin_status = 0;
  633. timeout = 0;
  634. cpu_id = phy_id;
  635. cpucount++;
  636. /* Create idle thread for this CPU */
  637. idle = fork_idle(cpu_id);
  638. if (IS_ERR(idle))
  639. panic("Failed fork for CPU#%d.", cpu_id);
  640. idle->thread.pc = (unsigned long)start_secondary;
  641. printk(KERN_NOTICE "Booting CPU#%d\n", cpu_id);
  642. start_stack[cpu_id - 1] = idle->thread.sp;
  643. task_thread_info(idle)->cpu = cpu_id;
  644. /* Send boot IPI to AP */
  645. send_IPI_mask(cpumask_of(phy_id), SMP_BOOT_IRQ);
  646. Dprintk("Waiting for send to finish...\n");
  647. /* Wait for AP's IPI receive in 100[ms] */
  648. do {
  649. udelay(1000);
  650. send_status =
  651. CROSS_GxICR(SMP_BOOT_IRQ, phy_id) & GxICR_REQUEST;
  652. } while (send_status == GxICR_REQUEST && timeout++ < 100);
  653. Dprintk("Waiting for cpu_callin_map.\n");
  654. if (send_status == 0) {
  655. /* Allow AP to start initializing */
  656. cpu_set(cpu_id, cpu_callout_map);
  657. /* Wait for setting cpu_callin_map */
  658. timeout = 0;
  659. do {
  660. udelay(1000);
  661. callin_status = cpu_isset(cpu_id, cpu_callin_map);
  662. } while (callin_status == 0 && timeout++ < 5000);
  663. if (callin_status == 0)
  664. Dprintk("Not responding.\n");
  665. } else {
  666. printk(KERN_WARNING "IPI not delivered.\n");
  667. }
  668. if (send_status == GxICR_REQUEST || callin_status == 0) {
  669. cpu_clear(cpu_id, cpu_callout_map);
  670. cpu_clear(cpu_id, cpu_callin_map);
  671. cpu_clear(cpu_id, cpu_initialized);
  672. cpucount--;
  673. return 1;
  674. }
  675. return 0;
  676. }
  677. /**
  678. * smp_show_cpu_info - Show SMP CPU information
  679. * @cpu: The CPU of interest.
  680. */
  681. static void __init smp_show_cpu_info(int cpu)
  682. {
  683. struct mn10300_cpuinfo *ci = &cpu_data[cpu];
  684. printk(KERN_INFO
  685. "CPU#%d : ioclk speed: %lu.%02luMHz : bogomips : %lu.%02lu\n",
  686. cpu,
  687. MN10300_IOCLK / 1000000,
  688. (MN10300_IOCLK / 10000) % 100,
  689. ci->loops_per_jiffy / (500000 / HZ),
  690. (ci->loops_per_jiffy / (5000 / HZ)) % 100);
  691. }
  692. /**
  693. * smp_callin - Set cpu_callin_map of the current CPU ID
  694. */
  695. static void __init smp_callin(void)
  696. {
  697. unsigned long timeout;
  698. int cpu;
  699. cpu = smp_processor_id();
  700. timeout = jiffies + (2 * HZ);
  701. if (cpu_isset(cpu, cpu_callin_map)) {
  702. printk(KERN_ERR "CPU#%d already present.\n", cpu);
  703. BUG();
  704. }
  705. Dprintk("CPU#%d waiting for CALLOUT\n", cpu);
  706. /* Wait for AP startup 2s total */
  707. while (time_before(jiffies, timeout)) {
  708. if (cpu_isset(cpu, cpu_callout_map))
  709. break;
  710. cpu_relax();
  711. }
  712. if (!time_before(jiffies, timeout)) {
  713. printk(KERN_ERR
  714. "BUG: CPU#%d started up but did not get a callout!\n",
  715. cpu);
  716. BUG();
  717. }
  718. #ifdef CONFIG_CALIBRATE_DELAY
  719. calibrate_delay(); /* Get our bogomips */
  720. #endif
  721. /* Save our processor parameters */
  722. smp_store_cpu_info(cpu);
  723. /* Allow the boot processor to continue */
  724. cpu_set(cpu, cpu_callin_map);
  725. }
  726. /**
  727. * smp_online - Set cpu_online_map
  728. */
  729. static void __init smp_online(void)
  730. {
  731. int cpu;
  732. cpu = smp_processor_id();
  733. local_irq_enable();
  734. cpu_set(cpu, cpu_online_map);
  735. smp_wmb();
  736. }
  737. /**
  738. * smp_cpus_done -
  739. * @max_cpus: Maximum CPU count.
  740. *
  741. * Do nothing.
  742. */
  743. void __init smp_cpus_done(unsigned int max_cpus)
  744. {
  745. }
  746. /*
  747. * smp_prepare_boot_cpu - Set up stuff for the boot processor.
  748. *
  749. * Set up the cpu_online_map, cpu_callout_map and cpu_callin_map of the boot
  750. * processor (CPU 0).
  751. */
  752. void __devinit smp_prepare_boot_cpu(void)
  753. {
  754. cpu_set(0, cpu_callout_map);
  755. cpu_set(0, cpu_callin_map);
  756. current_thread_info()->cpu = 0;
  757. }
  758. /*
  759. * initialize_secondary - Initialise a secondary CPU (Application Processor).
  760. *
  761. * Set SP register and jump to thread's PC address.
  762. */
  763. void initialize_secondary(void)
  764. {
  765. asm volatile (
  766. "mov %0,sp \n"
  767. "jmp (%1) \n"
  768. :
  769. : "a"(current->thread.sp), "a"(current->thread.pc));
  770. }
  771. /**
  772. * __cpu_up - Set smp_commenced_mask for the nominated CPU
  773. * @cpu: The target CPU.
  774. */
  775. int __devinit __cpu_up(unsigned int cpu)
  776. {
  777. int timeout;
  778. #ifdef CONFIG_HOTPLUG_CPU
  779. if (num_online_cpus() == 1)
  780. disable_hlt();
  781. if (sleep_mode[cpu])
  782. run_wakeup_cpu(cpu);
  783. #endif /* CONFIG_HOTPLUG_CPU */
  784. cpu_set(cpu, smp_commenced_mask);
  785. /* Wait 5s total for a response */
  786. for (timeout = 0 ; timeout < 5000 ; timeout++) {
  787. if (cpu_isset(cpu, cpu_online_map))
  788. break;
  789. udelay(1000);
  790. }
  791. BUG_ON(!cpu_isset(cpu, cpu_online_map));
  792. return 0;
  793. }
  794. /**
  795. * setup_profiling_timer - Set up the profiling timer
  796. * @multiplier - The frequency multiplier to use
  797. *
  798. * The frequency of the profiling timer can be changed by writing a multiplier
  799. * value into /proc/profile.
  800. */
  801. int setup_profiling_timer(unsigned int multiplier)
  802. {
  803. return -EINVAL;
  804. }
  805. /*
  806. * CPU hotplug routines
  807. */
  808. #ifdef CONFIG_HOTPLUG_CPU
  809. static DEFINE_PER_CPU(struct cpu, cpu_devices);
  810. static int __init topology_init(void)
  811. {
  812. int cpu, ret;
  813. for_each_cpu(cpu) {
  814. ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu, NULL);
  815. if (ret)
  816. printk(KERN_WARNING
  817. "topology_init: register_cpu %d failed (%d)\n",
  818. cpu, ret);
  819. }
  820. return 0;
  821. }
  822. subsys_initcall(topology_init);
  823. int __cpu_disable(void)
  824. {
  825. int cpu = smp_processor_id();
  826. if (cpu == 0)
  827. return -EBUSY;
  828. migrate_irqs();
  829. cpu_clear(cpu, current->active_mm->cpu_vm_mask);
  830. return 0;
  831. }
  832. void __cpu_die(unsigned int cpu)
  833. {
  834. run_sleep_cpu(cpu);
  835. if (num_online_cpus() == 1)
  836. enable_hlt();
  837. }
  838. #ifdef CONFIG_MN10300_CACHE_ENABLED
  839. static inline void hotplug_cpu_disable_cache(void)
  840. {
  841. int tmp;
  842. asm volatile(
  843. " movhu (%1),%0 \n"
  844. " and %2,%0 \n"
  845. " movhu %0,(%1) \n"
  846. "1: movhu (%1),%0 \n"
  847. " btst %3,%0 \n"
  848. " bne 1b \n"
  849. : "=&r"(tmp)
  850. : "a"(&CHCTR),
  851. "i"(~(CHCTR_ICEN | CHCTR_DCEN)),
  852. "i"(CHCTR_ICBUSY | CHCTR_DCBUSY)
  853. : "memory", "cc");
  854. }
  855. static inline void hotplug_cpu_enable_cache(void)
  856. {
  857. int tmp;
  858. asm volatile(
  859. "movhu (%1),%0 \n"
  860. "or %2,%0 \n"
  861. "movhu %0,(%1) \n"
  862. : "=&r"(tmp)
  863. : "a"(&CHCTR),
  864. "i"(CHCTR_ICEN | CHCTR_DCEN)
  865. : "memory", "cc");
  866. }
  867. static inline void hotplug_cpu_invalidate_cache(void)
  868. {
  869. int tmp;
  870. asm volatile (
  871. "movhu (%1),%0 \n"
  872. "or %2,%0 \n"
  873. "movhu %0,(%1) \n"
  874. : "=&r"(tmp)
  875. : "a"(&CHCTR),
  876. "i"(CHCTR_ICINV | CHCTR_DCINV)
  877. : "cc");
  878. }
  879. #else /* CONFIG_MN10300_CACHE_ENABLED */
  880. #define hotplug_cpu_disable_cache() do {} while (0)
  881. #define hotplug_cpu_enable_cache() do {} while (0)
  882. #define hotplug_cpu_invalidate_cache() do {} while (0)
  883. #endif /* CONFIG_MN10300_CACHE_ENABLED */
  884. /**
  885. * hotplug_cpu_nmi_call_function - Call a function on other CPUs for hotplug
  886. * @cpumask: List of target CPUs.
  887. * @func: The function to call on those CPUs.
  888. * @info: The context data for the function to be called.
  889. * @wait: Whether to wait for the calls to complete.
  890. *
  891. * Non-maskably call a function on another CPU for hotplug purposes.
  892. *
  893. * This function must be called with maskable interrupts disabled.
  894. */
  895. static int hotplug_cpu_nmi_call_function(cpumask_t cpumask,
  896. smp_call_func_t func, void *info,
  897. int wait)
  898. {
  899. /*
  900. * The address and the size of nmi_call_func_mask_data
  901. * need to be aligned on L1_CACHE_BYTES.
  902. */
  903. static struct nmi_call_data_struct nmi_call_func_mask_data
  904. __cacheline_aligned;
  905. unsigned long start, end;
  906. start = (unsigned long)&nmi_call_func_mask_data;
  907. end = start + sizeof(struct nmi_call_data_struct);
  908. nmi_call_func_mask_data.func = func;
  909. nmi_call_func_mask_data.info = info;
  910. nmi_call_func_mask_data.started = cpumask;
  911. nmi_call_func_mask_data.wait = wait;
  912. if (wait)
  913. nmi_call_func_mask_data.finished = cpumask;
  914. spin_lock(&smp_nmi_call_lock);
  915. nmi_call_data = &nmi_call_func_mask_data;
  916. mn10300_local_dcache_flush_range(start, end);
  917. smp_wmb();
  918. send_IPI_mask(cpumask, CALL_FUNCTION_NMI_IPI);
  919. do {
  920. mn10300_local_dcache_inv_range(start, end);
  921. barrier();
  922. } while (!cpus_empty(nmi_call_func_mask_data.started));
  923. if (wait) {
  924. do {
  925. mn10300_local_dcache_inv_range(start, end);
  926. barrier();
  927. } while (!cpus_empty(nmi_call_func_mask_data.finished));
  928. }
  929. spin_unlock(&smp_nmi_call_lock);
  930. return 0;
  931. }
  932. static void restart_wakeup_cpu(void)
  933. {
  934. unsigned int cpu = smp_processor_id();
  935. cpu_set(cpu, cpu_callin_map);
  936. local_flush_tlb();
  937. cpu_set(cpu, cpu_online_map);
  938. smp_wmb();
  939. }
  940. static void prepare_sleep_cpu(void *unused)
  941. {
  942. sleep_mode[smp_processor_id()] = 1;
  943. smp_mb();
  944. mn10300_local_dcache_flush_inv();
  945. hotplug_cpu_disable_cache();
  946. hotplug_cpu_invalidate_cache();
  947. }
  948. /* when this function called, IE=0, NMID=0. */
  949. static void sleep_cpu(void *unused)
  950. {
  951. unsigned int cpu_id = smp_processor_id();
  952. /*
  953. * CALL_FUNCTION_NMI_IPI for wakeup_cpu() shall not be requested,
  954. * before this cpu goes in SLEEP mode.
  955. */
  956. do {
  957. smp_mb();
  958. __sleep_cpu();
  959. } while (sleep_mode[cpu_id]);
  960. restart_wakeup_cpu();
  961. }
  962. static void run_sleep_cpu(unsigned int cpu)
  963. {
  964. unsigned long flags;
  965. cpumask_t cpumask = cpumask_of(cpu);
  966. flags = arch_local_cli_save();
  967. hotplug_cpu_nmi_call_function(cpumask, prepare_sleep_cpu, NULL, 1);
  968. hotplug_cpu_nmi_call_function(cpumask, sleep_cpu, NULL, 0);
  969. udelay(1); /* delay for the cpu to sleep. */
  970. arch_local_irq_restore(flags);
  971. }
  972. static void wakeup_cpu(void)
  973. {
  974. hotplug_cpu_invalidate_cache();
  975. hotplug_cpu_enable_cache();
  976. smp_mb();
  977. sleep_mode[smp_processor_id()] = 0;
  978. }
  979. static void run_wakeup_cpu(unsigned int cpu)
  980. {
  981. unsigned long flags;
  982. flags = arch_local_cli_save();
  983. #if NR_CPUS == 2
  984. mn10300_local_dcache_flush_inv();
  985. #else
  986. /*
  987. * Before waking up the cpu,
  988. * all online cpus should stop and flush D-Cache for global data.
  989. */
  990. #error not support NR_CPUS > 2, when CONFIG_HOTPLUG_CPU=y.
  991. #endif
  992. hotplug_cpu_nmi_call_function(cpumask_of(cpu), wakeup_cpu, NULL, 1);
  993. arch_local_irq_restore(flags);
  994. }
  995. #endif /* CONFIG_HOTPLUG_CPU */