mpparse.c 27 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086
  1. /*
  2. 2 * Intel Multiprocessor Specification 1.1 and 1.4
  3. * compliant MP-table parsing routines.
  4. *
  5. * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
  6. * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
  7. * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de>
  8. */
  9. #include <linux/mm.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/bootmem.h>
  13. #include <linux/kernel_stat.h>
  14. #include <linux/mc146818rtc.h>
  15. #include <linux/bitops.h>
  16. #include <linux/acpi.h>
  17. #include <linux/module.h>
  18. #include <asm/smp.h>
  19. #include <asm/mtrr.h>
  20. #include <asm/mpspec.h>
  21. #include <asm/pgalloc.h>
  22. #include <asm/io_apic.h>
  23. #include <asm/proto.h>
  24. #include <asm/acpi.h>
  25. #include <asm/bios_ebda.h>
  26. #include <mach_apic.h>
  27. #ifdef CONFIG_X86_32
  28. #include <mach_apicdef.h>
  29. #include <mach_mpparse.h>
  30. #endif
  31. /* Have we found an MP table */
  32. int smp_found_config;
  33. /*
  34. * Various Linux-internal data structures created from the
  35. * MP-table.
  36. */
  37. #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  38. int mp_bus_id_to_type[MAX_MP_BUSSES];
  39. #endif
  40. DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  41. int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
  42. static int mp_current_pci_id;
  43. int pic_mode;
  44. /*
  45. * Intel MP BIOS table parsing routines:
  46. */
  47. /*
  48. * Checksum an MP configuration block.
  49. */
  50. static int __init mpf_checksum(unsigned char *mp, int len)
  51. {
  52. int sum = 0;
  53. while (len--)
  54. sum += *mp++;
  55. return sum & 0xFF;
  56. }
  57. #ifdef CONFIG_X86_NUMAQ
  58. /*
  59. * Have to match translation table entries to main table entries by counter
  60. * hence the mpc_record variable .... can't see a less disgusting way of
  61. * doing this ....
  62. */
  63. static int mpc_record;
  64. static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY]
  65. __cpuinitdata;
  66. #endif
  67. static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
  68. {
  69. int apicid;
  70. char *bootup_cpu = "";
  71. if (!(m->mpc_cpuflag & CPU_ENABLED)) {
  72. disabled_cpus++;
  73. return;
  74. }
  75. #ifdef CONFIG_X86_NUMAQ
  76. apicid = mpc_apic_id(m, translation_table[mpc_record]);
  77. #else
  78. apicid = m->mpc_apicid;
  79. #endif
  80. if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
  81. bootup_cpu = " (Bootup-CPU)";
  82. boot_cpu_physical_apicid = m->mpc_apicid;
  83. }
  84. printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
  85. generic_processor_info(apicid, m->mpc_apicver);
  86. }
  87. static void __init MP_bus_info(struct mpc_config_bus *m)
  88. {
  89. char str[7];
  90. memcpy(str, m->mpc_bustype, 6);
  91. str[6] = 0;
  92. #ifdef CONFIG_X86_NUMAQ
  93. mpc_oem_bus_info(m, str, translation_table[mpc_record]);
  94. #else
  95. printk(KERN_INFO "Bus #%d is %s\n", m->mpc_busid, str);
  96. #endif
  97. #if MAX_MP_BUSSES < 256
  98. if (m->mpc_busid >= MAX_MP_BUSSES) {
  99. printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
  100. " is too large, max. supported is %d\n",
  101. m->mpc_busid, str, MAX_MP_BUSSES - 1);
  102. return;
  103. }
  104. #endif
  105. if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) {
  106. set_bit(m->mpc_busid, mp_bus_not_pci);
  107. #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
  108. mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
  109. #endif
  110. } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
  111. #ifdef CONFIG_X86_NUMAQ
  112. mpc_oem_pci_bus(m, translation_table[mpc_record]);
  113. #endif
  114. clear_bit(m->mpc_busid, mp_bus_not_pci);
  115. mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
  116. mp_current_pci_id++;
  117. #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
  118. mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
  119. } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
  120. mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
  121. } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) {
  122. mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
  123. #endif
  124. } else
  125. printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
  126. }
  127. #ifdef CONFIG_X86_IO_APIC
  128. static int bad_ioapic(unsigned long address)
  129. {
  130. if (nr_ioapics >= MAX_IO_APICS) {
  131. printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
  132. "(found %d)\n", MAX_IO_APICS, nr_ioapics);
  133. panic("Recompile kernel with bigger MAX_IO_APICS!\n");
  134. }
  135. if (!address) {
  136. printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
  137. " found in table, skipping!\n");
  138. return 1;
  139. }
  140. return 0;
  141. }
  142. static void __init MP_ioapic_info(struct mpc_config_ioapic *m)
  143. {
  144. if (!(m->mpc_flags & MPC_APIC_USABLE))
  145. return;
  146. printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
  147. m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
  148. if (bad_ioapic(m->mpc_apicaddr))
  149. return;
  150. mp_ioapics[nr_ioapics] = *m;
  151. nr_ioapics++;
  152. }
  153. static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
  154. {
  155. mp_irqs[mp_irq_entries] = *m;
  156. printk(KERN_INFO "Int: type %d, pol %d, trig %d, bus %02x,"
  157. " IRQ %02x, APIC ID %x, APIC INT %02x\n",
  158. m->mpc_irqtype, m->mpc_irqflag & 3,
  159. (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
  160. m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
  161. if (++mp_irq_entries == MAX_IRQ_SOURCES)
  162. panic("Max # of irq sources exceeded!!\n");
  163. }
  164. #endif
  165. static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m)
  166. {
  167. printk(KERN_INFO "Lint: type %d, pol %d, trig %d, bus %02x,"
  168. " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
  169. m->mpc_irqtype, m->mpc_irqflag & 3,
  170. (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid,
  171. m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
  172. }
  173. #ifdef CONFIG_X86_NUMAQ
  174. static void __init MP_translation_info(struct mpc_config_translation *m)
  175. {
  176. printk(KERN_INFO
  177. "Translation: record %d, type %d, quad %d, global %d, local %d\n",
  178. mpc_record, m->trans_type, m->trans_quad, m->trans_global,
  179. m->trans_local);
  180. if (mpc_record >= MAX_MPC_ENTRY)
  181. printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
  182. else
  183. translation_table[mpc_record] = m; /* stash this for later */
  184. if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
  185. node_set_online(m->trans_quad);
  186. }
  187. /*
  188. * Read/parse the MPC oem tables
  189. */
  190. static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable,
  191. unsigned short oemsize)
  192. {
  193. int count = sizeof(*oemtable); /* the header size */
  194. unsigned char *oemptr = ((unsigned char *)oemtable) + count;
  195. mpc_record = 0;
  196. printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n",
  197. oemtable);
  198. if (memcmp(oemtable->oem_signature, MPC_OEM_SIGNATURE, 4)) {
  199. printk(KERN_WARNING
  200. "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
  201. oemtable->oem_signature[0], oemtable->oem_signature[1],
  202. oemtable->oem_signature[2], oemtable->oem_signature[3]);
  203. return;
  204. }
  205. if (mpf_checksum((unsigned char *)oemtable, oemtable->oem_length)) {
  206. printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
  207. return;
  208. }
  209. while (count < oemtable->oem_length) {
  210. switch (*oemptr) {
  211. case MP_TRANSLATION:
  212. {
  213. struct mpc_config_translation *m =
  214. (struct mpc_config_translation *)oemptr;
  215. MP_translation_info(m);
  216. oemptr += sizeof(*m);
  217. count += sizeof(*m);
  218. ++mpc_record;
  219. break;
  220. }
  221. default:
  222. {
  223. printk(KERN_WARNING
  224. "Unrecognised OEM table entry type! - %d\n",
  225. (int)*oemptr);
  226. return;
  227. }
  228. }
  229. }
  230. }
  231. static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
  232. char *productid)
  233. {
  234. if (strncmp(oem, "IBM NUMA", 8))
  235. printk("Warning! May not be a NUMA-Q system!\n");
  236. if (mpc->mpc_oemptr)
  237. smp_read_mpc_oem((struct mp_config_oemtable *)mpc->mpc_oemptr,
  238. mpc->mpc_oemsize);
  239. }
  240. #endif /* CONFIG_X86_NUMAQ */
  241. /*
  242. * Read/parse the MPC
  243. */
  244. static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
  245. {
  246. char str[16];
  247. char oem[10];
  248. int count = sizeof(*mpc);
  249. unsigned char *mpt = ((unsigned char *)mpc) + count;
  250. if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) {
  251. printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n",
  252. mpc->mpc_signature[0], mpc->mpc_signature[1],
  253. mpc->mpc_signature[2], mpc->mpc_signature[3]);
  254. return 0;
  255. }
  256. if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) {
  257. printk(KERN_ERR "MPTABLE: checksum error!\n");
  258. return 0;
  259. }
  260. if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) {
  261. printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
  262. mpc->mpc_spec);
  263. return 0;
  264. }
  265. if (!mpc->mpc_lapic) {
  266. printk(KERN_ERR "MPTABLE: null local APIC address!\n");
  267. return 0;
  268. }
  269. memcpy(oem, mpc->mpc_oem, 8);
  270. oem[8] = 0;
  271. printk(KERN_INFO "MPTABLE: OEM ID: %s\n", oem);
  272. memcpy(str, mpc->mpc_productid, 12);
  273. str[12] = 0;
  274. #ifdef CONFIG_X86_32
  275. mps_oem_check(mpc, oem, str);
  276. #endif
  277. printk(KERN_INFO "MPTABLE: Product ID: %s\n", str);
  278. printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic);
  279. /* save the local APIC address, it might be non-default */
  280. if (!acpi_lapic)
  281. mp_lapic_addr = mpc->mpc_lapic;
  282. if (early)
  283. return 1;
  284. /*
  285. * Now process the configuration blocks.
  286. */
  287. #ifdef CONFIG_X86_NUMAQ
  288. mpc_record = 0;
  289. #endif
  290. while (count < mpc->mpc_length) {
  291. switch (*mpt) {
  292. case MP_PROCESSOR:
  293. {
  294. struct mpc_config_processor *m =
  295. (struct mpc_config_processor *)mpt;
  296. /* ACPI may have already provided this data */
  297. if (!acpi_lapic)
  298. MP_processor_info(m);
  299. mpt += sizeof(*m);
  300. count += sizeof(*m);
  301. break;
  302. }
  303. case MP_BUS:
  304. {
  305. struct mpc_config_bus *m =
  306. (struct mpc_config_bus *)mpt;
  307. MP_bus_info(m);
  308. mpt += sizeof(*m);
  309. count += sizeof(*m);
  310. break;
  311. }
  312. case MP_IOAPIC:
  313. {
  314. #ifdef CONFIG_X86_IO_APIC
  315. struct mpc_config_ioapic *m =
  316. (struct mpc_config_ioapic *)mpt;
  317. MP_ioapic_info(m);
  318. #endif
  319. mpt += sizeof(struct mpc_config_ioapic);
  320. count += sizeof(struct mpc_config_ioapic);
  321. break;
  322. }
  323. case MP_INTSRC:
  324. {
  325. #ifdef CONFIG_X86_IO_APIC
  326. struct mpc_config_intsrc *m =
  327. (struct mpc_config_intsrc *)mpt;
  328. MP_intsrc_info(m);
  329. #endif
  330. mpt += sizeof(struct mpc_config_intsrc);
  331. count += sizeof(struct mpc_config_intsrc);
  332. break;
  333. }
  334. case MP_LINTSRC:
  335. {
  336. struct mpc_config_lintsrc *m =
  337. (struct mpc_config_lintsrc *)mpt;
  338. MP_lintsrc_info(m);
  339. mpt += sizeof(*m);
  340. count += sizeof(*m);
  341. break;
  342. }
  343. default:
  344. /* wrong mptable */
  345. printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n");
  346. printk(KERN_ERR "type %x\n", *mpt);
  347. print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16,
  348. 1, mpc, mpc->mpc_length, 1);
  349. count = mpc->mpc_length;
  350. break;
  351. }
  352. #ifdef CONFIG_X86_NUMAQ
  353. ++mpc_record;
  354. #endif
  355. }
  356. setup_apic_routing();
  357. if (!num_processors)
  358. printk(KERN_ERR "MPTABLE: no processors registered!\n");
  359. return num_processors;
  360. }
  361. #ifdef CONFIG_X86_IO_APIC
  362. static int __init ELCR_trigger(unsigned int irq)
  363. {
  364. unsigned int port;
  365. port = 0x4d0 + (irq >> 3);
  366. return (inb(port) >> (irq & 7)) & 1;
  367. }
  368. static void __init construct_default_ioirq_mptable(int mpc_default_type)
  369. {
  370. struct mpc_config_intsrc intsrc;
  371. int i;
  372. int ELCR_fallback = 0;
  373. intsrc.mpc_type = MP_INTSRC;
  374. intsrc.mpc_irqflag = 0; /* conforming */
  375. intsrc.mpc_srcbus = 0;
  376. intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
  377. intsrc.mpc_irqtype = mp_INT;
  378. /*
  379. * If true, we have an ISA/PCI system with no IRQ entries
  380. * in the MP table. To prevent the PCI interrupts from being set up
  381. * incorrectly, we try to use the ELCR. The sanity check to see if
  382. * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
  383. * never be level sensitive, so we simply see if the ELCR agrees.
  384. * If it does, we assume it's valid.
  385. */
  386. if (mpc_default_type == 5) {
  387. printk(KERN_INFO "ISA/PCI bus type with no IRQ information... "
  388. "falling back to ELCR\n");
  389. if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
  390. ELCR_trigger(13))
  391. printk(KERN_ERR "ELCR contains invalid data... "
  392. "not using ELCR\n");
  393. else {
  394. printk(KERN_INFO
  395. "Using ELCR to identify PCI interrupts\n");
  396. ELCR_fallback = 1;
  397. }
  398. }
  399. for (i = 0; i < 16; i++) {
  400. switch (mpc_default_type) {
  401. case 2:
  402. if (i == 0 || i == 13)
  403. continue; /* IRQ0 & IRQ13 not connected */
  404. /* fall through */
  405. default:
  406. if (i == 2)
  407. continue; /* IRQ2 is never connected */
  408. }
  409. if (ELCR_fallback) {
  410. /*
  411. * If the ELCR indicates a level-sensitive interrupt, we
  412. * copy that information over to the MP table in the
  413. * irqflag field (level sensitive, active high polarity).
  414. */
  415. if (ELCR_trigger(i))
  416. intsrc.mpc_irqflag = 13;
  417. else
  418. intsrc.mpc_irqflag = 0;
  419. }
  420. intsrc.mpc_srcbusirq = i;
  421. intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
  422. MP_intsrc_info(&intsrc);
  423. }
  424. intsrc.mpc_irqtype = mp_ExtINT;
  425. intsrc.mpc_srcbusirq = 0;
  426. intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
  427. MP_intsrc_info(&intsrc);
  428. }
  429. #endif
  430. static inline void __init construct_default_ISA_mptable(int mpc_default_type)
  431. {
  432. struct mpc_config_processor processor;
  433. struct mpc_config_bus bus;
  434. #ifdef CONFIG_X86_IO_APIC
  435. struct mpc_config_ioapic ioapic;
  436. #endif
  437. struct mpc_config_lintsrc lintsrc;
  438. int linttypes[2] = { mp_ExtINT, mp_NMI };
  439. int i;
  440. /*
  441. * local APIC has default address
  442. */
  443. mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
  444. /*
  445. * 2 CPUs, numbered 0 & 1.
  446. */
  447. processor.mpc_type = MP_PROCESSOR;
  448. /* Either an integrated APIC or a discrete 82489DX. */
  449. processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
  450. processor.mpc_cpuflag = CPU_ENABLED;
  451. processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
  452. (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
  453. processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
  454. processor.mpc_reserved[0] = 0;
  455. processor.mpc_reserved[1] = 0;
  456. for (i = 0; i < 2; i++) {
  457. processor.mpc_apicid = i;
  458. MP_processor_info(&processor);
  459. }
  460. bus.mpc_type = MP_BUS;
  461. bus.mpc_busid = 0;
  462. switch (mpc_default_type) {
  463. default:
  464. printk(KERN_ERR "???\nUnknown standard configuration %d\n",
  465. mpc_default_type);
  466. /* fall through */
  467. case 1:
  468. case 5:
  469. memcpy(bus.mpc_bustype, "ISA ", 6);
  470. break;
  471. case 2:
  472. case 6:
  473. case 3:
  474. memcpy(bus.mpc_bustype, "EISA ", 6);
  475. break;
  476. case 4:
  477. case 7:
  478. memcpy(bus.mpc_bustype, "MCA ", 6);
  479. }
  480. MP_bus_info(&bus);
  481. if (mpc_default_type > 4) {
  482. bus.mpc_busid = 1;
  483. memcpy(bus.mpc_bustype, "PCI ", 6);
  484. MP_bus_info(&bus);
  485. }
  486. #ifdef CONFIG_X86_IO_APIC
  487. ioapic.mpc_type = MP_IOAPIC;
  488. ioapic.mpc_apicid = 2;
  489. ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
  490. ioapic.mpc_flags = MPC_APIC_USABLE;
  491. ioapic.mpc_apicaddr = 0xFEC00000;
  492. MP_ioapic_info(&ioapic);
  493. /*
  494. * We set up most of the low 16 IO-APIC pins according to MPS rules.
  495. */
  496. construct_default_ioirq_mptable(mpc_default_type);
  497. #endif
  498. lintsrc.mpc_type = MP_LINTSRC;
  499. lintsrc.mpc_irqflag = 0; /* conforming */
  500. lintsrc.mpc_srcbusid = 0;
  501. lintsrc.mpc_srcbusirq = 0;
  502. lintsrc.mpc_destapic = MP_APIC_ALL;
  503. for (i = 0; i < 2; i++) {
  504. lintsrc.mpc_irqtype = linttypes[i];
  505. lintsrc.mpc_destapiclint = i;
  506. MP_lintsrc_info(&lintsrc);
  507. }
  508. }
  509. static struct intel_mp_floating *mpf_found;
  510. /*
  511. * Scan the memory blocks for an SMP configuration block.
  512. */
  513. static void __init __get_smp_config(unsigned early)
  514. {
  515. struct intel_mp_floating *mpf = mpf_found;
  516. if (acpi_lapic && early)
  517. return;
  518. /*
  519. * ACPI supports both logical (e.g. Hyper-Threading) and physical
  520. * processors, where MPS only supports physical.
  521. */
  522. if (acpi_lapic && acpi_ioapic) {
  523. printk(KERN_INFO "Using ACPI (MADT) for SMP configuration "
  524. "information\n");
  525. return;
  526. } else if (acpi_lapic)
  527. printk(KERN_INFO "Using ACPI for processor (LAPIC) "
  528. "configuration information\n");
  529. printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
  530. mpf->mpf_specification);
  531. #ifdef CONFIG_X86_32
  532. if (mpf->mpf_feature2 & (1 << 7)) {
  533. printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
  534. pic_mode = 1;
  535. } else {
  536. printk(KERN_INFO " Virtual Wire compatibility mode.\n");
  537. pic_mode = 0;
  538. }
  539. #endif
  540. /*
  541. * Now see if we need to read further.
  542. */
  543. if (mpf->mpf_feature1 != 0) {
  544. if (early) {
  545. /*
  546. * local APIC has default address
  547. */
  548. mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
  549. return;
  550. }
  551. printk(KERN_INFO "Default MP configuration #%d\n",
  552. mpf->mpf_feature1);
  553. construct_default_ISA_mptable(mpf->mpf_feature1);
  554. } else if (mpf->mpf_physptr) {
  555. /*
  556. * Read the physical hardware table. Anything here will
  557. * override the defaults.
  558. */
  559. if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) {
  560. smp_found_config = 0;
  561. printk(KERN_ERR
  562. "BIOS bug, MP table errors detected!...\n");
  563. printk(KERN_ERR "... disabling SMP support. "
  564. "(tell your hw vendor)\n");
  565. return;
  566. }
  567. if (early)
  568. return;
  569. #ifdef CONFIG_X86_IO_APIC
  570. /*
  571. * If there are no explicit MP IRQ entries, then we are
  572. * broken. We set up most of the low 16 IO-APIC pins to
  573. * ISA defaults and hope it will work.
  574. */
  575. if (!mp_irq_entries) {
  576. struct mpc_config_bus bus;
  577. printk(KERN_ERR "BIOS bug, no explicit IRQ entries, "
  578. "using default mptable. "
  579. "(tell your hw vendor)\n");
  580. bus.mpc_type = MP_BUS;
  581. bus.mpc_busid = 0;
  582. memcpy(bus.mpc_bustype, "ISA ", 6);
  583. MP_bus_info(&bus);
  584. construct_default_ioirq_mptable(0);
  585. }
  586. #endif
  587. } else
  588. BUG();
  589. if (!early)
  590. printk(KERN_INFO "Processors: %d\n", num_processors);
  591. /*
  592. * Only use the first configuration found.
  593. */
  594. }
  595. void __init early_get_smp_config(void)
  596. {
  597. __get_smp_config(1);
  598. }
  599. void __init get_smp_config(void)
  600. {
  601. __get_smp_config(0);
  602. }
  603. static int __init smp_scan_config(unsigned long base, unsigned long length,
  604. unsigned reserve)
  605. {
  606. unsigned int *bp = phys_to_virt(base);
  607. struct intel_mp_floating *mpf;
  608. printk(KERN_DEBUG "Scan SMP from %p for %ld bytes.\n", bp, length);
  609. BUILD_BUG_ON(sizeof(*mpf) != 16);
  610. while (length > 0) {
  611. mpf = (struct intel_mp_floating *)bp;
  612. if ((*bp == SMP_MAGIC_IDENT) &&
  613. (mpf->mpf_length == 1) &&
  614. !mpf_checksum((unsigned char *)bp, 16) &&
  615. ((mpf->mpf_specification == 1)
  616. || (mpf->mpf_specification == 4))) {
  617. smp_found_config = 1;
  618. mpf_found = mpf;
  619. #ifdef CONFIG_X86_32
  620. printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
  621. mpf, virt_to_phys(mpf));
  622. reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
  623. BOOTMEM_DEFAULT);
  624. if (mpf->mpf_physptr) {
  625. /*
  626. * We cannot access to MPC table to compute
  627. * table size yet, as only few megabytes from
  628. * the bottom is mapped now.
  629. * PC-9800's MPC table places on the very last
  630. * of physical memory; so that simply reserving
  631. * PAGE_SIZE from mpg->mpf_physptr yields BUG()
  632. * in reserve_bootmem.
  633. */
  634. unsigned long size = PAGE_SIZE;
  635. unsigned long end = max_low_pfn * PAGE_SIZE;
  636. if (mpf->mpf_physptr + size > end)
  637. size = end - mpf->mpf_physptr;
  638. reserve_bootmem(mpf->mpf_physptr, size,
  639. BOOTMEM_DEFAULT);
  640. }
  641. #else
  642. if (!reserve)
  643. return 1;
  644. reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
  645. if (mpf->mpf_physptr)
  646. reserve_bootmem_generic(mpf->mpf_physptr,
  647. PAGE_SIZE);
  648. #endif
  649. return 1;
  650. }
  651. bp += 4;
  652. length -= 16;
  653. }
  654. return 0;
  655. }
  656. static void __init __find_smp_config(unsigned reserve)
  657. {
  658. unsigned int address;
  659. /*
  660. * FIXME: Linux assumes you have 640K of base ram..
  661. * this continues the error...
  662. *
  663. * 1) Scan the bottom 1K for a signature
  664. * 2) Scan the top 1K of base RAM
  665. * 3) Scan the 64K of bios
  666. */
  667. if (smp_scan_config(0x0, 0x400, reserve) ||
  668. smp_scan_config(639 * 0x400, 0x400, reserve) ||
  669. smp_scan_config(0xF0000, 0x10000, reserve))
  670. return;
  671. /*
  672. * If it is an SMP machine we should know now, unless the
  673. * configuration is in an EISA/MCA bus machine with an
  674. * extended bios data area.
  675. *
  676. * there is a real-mode segmented pointer pointing to the
  677. * 4K EBDA area at 0x40E, calculate and scan it here.
  678. *
  679. * NOTE! There are Linux loaders that will corrupt the EBDA
  680. * area, and as such this kind of SMP config may be less
  681. * trustworthy, simply because the SMP table may have been
  682. * stomped on during early boot. These loaders are buggy and
  683. * should be fixed.
  684. *
  685. * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
  686. */
  687. address = get_bios_ebda();
  688. if (address)
  689. smp_scan_config(address, 0x400, reserve);
  690. }
  691. void __init early_find_smp_config(void)
  692. {
  693. __find_smp_config(0);
  694. }
  695. void __init find_smp_config(void)
  696. {
  697. __find_smp_config(1);
  698. }
  699. /* --------------------------------------------------------------------------
  700. ACPI-based MP Configuration
  701. -------------------------------------------------------------------------- */
  702. /*
  703. * Keep this outside and initialized to 0, for !CONFIG_ACPI builds:
  704. */
  705. int es7000_plat;
  706. #ifdef CONFIG_ACPI
  707. #ifdef CONFIG_X86_IO_APIC
  708. #define MP_ISA_BUS 0
  709. static struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
  710. static int mp_find_ioapic(int gsi)
  711. {
  712. int i = 0;
  713. /* Find the IOAPIC that manages this GSI. */
  714. for (i = 0; i < nr_ioapics; i++) {
  715. if ((gsi >= mp_ioapic_routing[i].gsi_base)
  716. && (gsi <= mp_ioapic_routing[i].gsi_end))
  717. return i;
  718. }
  719. printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
  720. return -1;
  721. }
  722. static u8 __init uniq_ioapic_id(u8 id)
  723. {
  724. #ifdef CONFIG_X86_32
  725. if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
  726. !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
  727. return io_apic_get_unique_id(nr_ioapics, id);
  728. else
  729. return id;
  730. #else
  731. int i;
  732. DECLARE_BITMAP(used, 256);
  733. bitmap_zero(used, 256);
  734. for (i = 0; i < nr_ioapics; i++) {
  735. struct mpc_config_ioapic *ia = &mp_ioapics[i];
  736. __set_bit(ia->mpc_apicid, used);
  737. }
  738. if (!test_bit(id, used))
  739. return id;
  740. return find_first_zero_bit(used, 256);
  741. #endif
  742. }
  743. void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
  744. {
  745. int idx = 0;
  746. if (bad_ioapic(address))
  747. return;
  748. idx = nr_ioapics;
  749. mp_ioapics[idx].mpc_type = MP_IOAPIC;
  750. mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
  751. mp_ioapics[idx].mpc_apicaddr = address;
  752. set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
  753. mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
  754. #ifdef CONFIG_X86_32
  755. mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
  756. #else
  757. mp_ioapics[idx].mpc_apicver = 0;
  758. #endif
  759. /*
  760. * Build basic GSI lookup table to facilitate gsi->io_apic lookups
  761. * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
  762. */
  763. mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
  764. mp_ioapic_routing[idx].gsi_base = gsi_base;
  765. mp_ioapic_routing[idx].gsi_end = gsi_base +
  766. io_apic_get_redir_entries(idx);
  767. printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
  768. "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
  769. mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
  770. mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
  771. nr_ioapics++;
  772. }
  773. void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
  774. {
  775. struct mpc_config_intsrc intsrc;
  776. int ioapic = -1;
  777. int pin = -1;
  778. /*
  779. * Convert 'gsi' to 'ioapic.pin'.
  780. */
  781. ioapic = mp_find_ioapic(gsi);
  782. if (ioapic < 0)
  783. return;
  784. pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
  785. /*
  786. * TBD: This check is for faulty timer entries, where the override
  787. * erroneously sets the trigger to level, resulting in a HUGE
  788. * increase of timer interrupts!
  789. */
  790. if ((bus_irq == 0) && (trigger == 3))
  791. trigger = 1;
  792. intsrc.mpc_type = MP_INTSRC;
  793. intsrc.mpc_irqtype = mp_INT;
  794. intsrc.mpc_irqflag = (trigger << 2) | polarity;
  795. intsrc.mpc_srcbus = MP_ISA_BUS;
  796. intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
  797. intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
  798. intsrc.mpc_dstirq = pin; /* INTIN# */
  799. MP_intsrc_info(&intsrc);
  800. }
  801. void __init mp_config_acpi_legacy_irqs(void)
  802. {
  803. struct mpc_config_intsrc intsrc;
  804. int i = 0;
  805. int ioapic = -1;
  806. #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  807. /*
  808. * Fabricate the legacy ISA bus (bus #31).
  809. */
  810. mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
  811. #endif
  812. set_bit(MP_ISA_BUS, mp_bus_not_pci);
  813. Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
  814. /*
  815. * Older generations of ES7000 have no legacy identity mappings
  816. */
  817. if (es7000_plat == 1)
  818. return;
  819. /*
  820. * Locate the IOAPIC that manages the ISA IRQs (0-15).
  821. */
  822. ioapic = mp_find_ioapic(0);
  823. if (ioapic < 0)
  824. return;
  825. intsrc.mpc_type = MP_INTSRC;
  826. intsrc.mpc_irqflag = 0; /* Conforming */
  827. intsrc.mpc_srcbus = MP_ISA_BUS;
  828. #ifdef CONFIG_X86_IO_APIC
  829. intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
  830. #endif
  831. /*
  832. * Use the default configuration for the IRQs 0-15. Unless
  833. * overridden by (MADT) interrupt source override entries.
  834. */
  835. for (i = 0; i < 16; i++) {
  836. int idx;
  837. for (idx = 0; idx < mp_irq_entries; idx++) {
  838. struct mpc_config_intsrc *irq = mp_irqs + idx;
  839. /* Do we already have a mapping for this ISA IRQ? */
  840. if (irq->mpc_srcbus == MP_ISA_BUS
  841. && irq->mpc_srcbusirq == i)
  842. break;
  843. /* Do we already have a mapping for this IOAPIC pin */
  844. if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
  845. (irq->mpc_dstirq == i))
  846. break;
  847. }
  848. if (idx != mp_irq_entries) {
  849. printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
  850. continue; /* IRQ already used */
  851. }
  852. intsrc.mpc_irqtype = mp_INT;
  853. intsrc.mpc_srcbusirq = i; /* Identity mapped */
  854. intsrc.mpc_dstirq = i;
  855. MP_intsrc_info(&intsrc);
  856. }
  857. }
  858. int mp_register_gsi(u32 gsi, int triggering, int polarity)
  859. {
  860. int ioapic;
  861. int ioapic_pin;
  862. #ifdef CONFIG_X86_32
  863. #define MAX_GSI_NUM 4096
  864. #define IRQ_COMPRESSION_START 64
  865. static int pci_irq = IRQ_COMPRESSION_START;
  866. /*
  867. * Mapping between Global System Interrupts, which
  868. * represent all possible interrupts, and IRQs
  869. * assigned to actual devices.
  870. */
  871. static int gsi_to_irq[MAX_GSI_NUM];
  872. #else
  873. if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
  874. return gsi;
  875. #endif
  876. /* Don't set up the ACPI SCI because it's already set up */
  877. if (acpi_gbl_FADT.sci_interrupt == gsi)
  878. return gsi;
  879. ioapic = mp_find_ioapic(gsi);
  880. if (ioapic < 0) {
  881. printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
  882. return gsi;
  883. }
  884. ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
  885. #ifdef CONFIG_X86_32
  886. if (ioapic_renumber_irq)
  887. gsi = ioapic_renumber_irq(ioapic, gsi);
  888. #endif
  889. /*
  890. * Avoid pin reprogramming. PRTs typically include entries
  891. * with redundant pin->gsi mappings (but unique PCI devices);
  892. * we only program the IOAPIC on the first.
  893. */
  894. if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
  895. printk(KERN_ERR "Invalid reference to IOAPIC pin "
  896. "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
  897. ioapic_pin);
  898. return gsi;
  899. }
  900. if (test_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed)) {
  901. Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
  902. mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
  903. #ifdef CONFIG_X86_32
  904. return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
  905. #else
  906. return gsi;
  907. #endif
  908. }
  909. set_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed);
  910. #ifdef CONFIG_X86_32
  911. /*
  912. * For GSI >= 64, use IRQ compression
  913. */
  914. if ((gsi >= IRQ_COMPRESSION_START)
  915. && (triggering == ACPI_LEVEL_SENSITIVE)) {
  916. /*
  917. * For PCI devices assign IRQs in order, avoiding gaps
  918. * due to unused I/O APIC pins.
  919. */
  920. int irq = gsi;
  921. if (gsi < MAX_GSI_NUM) {
  922. /*
  923. * Retain the VIA chipset work-around (gsi > 15), but
  924. * avoid a problem where the 8254 timer (IRQ0) is setup
  925. * via an override (so it's not on pin 0 of the ioapic),
  926. * and at the same time, the pin 0 interrupt is a PCI
  927. * type. The gsi > 15 test could cause these two pins
  928. * to be shared as IRQ0, and they are not shareable.
  929. * So test for this condition, and if necessary, avoid
  930. * the pin collision.
  931. */
  932. gsi = pci_irq++;
  933. /*
  934. * Don't assign IRQ used by ACPI SCI
  935. */
  936. if (gsi == acpi_gbl_FADT.sci_interrupt)
  937. gsi = pci_irq++;
  938. gsi_to_irq[irq] = gsi;
  939. } else {
  940. printk(KERN_ERR "GSI %u is too high\n", gsi);
  941. return gsi;
  942. }
  943. }
  944. #endif
  945. io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
  946. triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
  947. polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
  948. return gsi;
  949. }
  950. #endif /* CONFIG_X86_IO_APIC */
  951. #endif /* CONFIG_ACPI */